1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Ingenic SoCs pinctrl driver
4 *
5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
6 * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
7 * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk>
8 */
9
10 #include <linux/compiler.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/of_device.h>
16 #include <linux/of_irq.h>
17 #include <linux/of_platform.h>
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinmux.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
25
26 #include "core.h"
27 #include "pinconf.h"
28 #include "pinmux.h"
29
30 #define GPIO_PIN 0x00
31 #define GPIO_MSK 0x20
32
33 #define JZ4740_GPIO_DATA 0x10
34 #define JZ4740_GPIO_PULL_DIS 0x30
35 #define JZ4740_GPIO_FUNC 0x40
36 #define JZ4740_GPIO_SELECT 0x50
37 #define JZ4740_GPIO_DIR 0x60
38 #define JZ4740_GPIO_TRIG 0x70
39 #define JZ4740_GPIO_FLAG 0x80
40
41 #define JZ4760_GPIO_INT 0x10
42 #define JZ4760_GPIO_PAT1 0x30
43 #define JZ4760_GPIO_PAT0 0x40
44 #define JZ4760_GPIO_FLAG 0x50
45 #define JZ4760_GPIO_PEN 0x70
46
47 #define X1830_GPIO_PEL 0x110
48 #define X1830_GPIO_PEH 0x120
49
50 #define REG_SET(x) ((x) + 0x4)
51 #define REG_CLEAR(x) ((x) + 0x8)
52
53 #define REG_PZ_BASE(x) ((x) * 7)
54 #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0)
55
56 #define GPIO_PULL_DIS 0
57 #define GPIO_PULL_UP 1
58 #define GPIO_PULL_DOWN 2
59
60 #define PINS_PER_GPIO_CHIP 32
61
62 enum jz_version {
63 ID_JZ4740,
64 ID_JZ4725B,
65 ID_JZ4760,
66 ID_JZ4770,
67 ID_JZ4780,
68 ID_X1000,
69 ID_X1500,
70 ID_X1830,
71 };
72
73 struct ingenic_chip_info {
74 unsigned int num_chips;
75 unsigned int reg_offset;
76 enum jz_version version;
77
78 const struct group_desc *groups;
79 unsigned int num_groups;
80
81 const struct function_desc *functions;
82 unsigned int num_functions;
83
84 const u32 *pull_ups, *pull_downs;
85 };
86
87 struct ingenic_pinctrl {
88 struct device *dev;
89 struct regmap *map;
90 struct pinctrl_dev *pctl;
91 struct pinctrl_pin_desc *pdesc;
92
93 const struct ingenic_chip_info *info;
94 };
95
96 struct ingenic_gpio_chip {
97 struct ingenic_pinctrl *jzpc;
98 struct gpio_chip gc;
99 struct irq_chip irq_chip;
100 unsigned int irq, reg_base;
101 };
102
103 static const u32 jz4740_pull_ups[4] = {
104 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
105 };
106
107 static const u32 jz4740_pull_downs[4] = {
108 0x00000000, 0x00000000, 0x00000000, 0x00000000,
109 };
110
111 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };
112 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
113 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
114 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
115 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
116 static int jz4740_lcd_8bit_pins[] = {
117 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54,
118 };
119 static int jz4740_lcd_16bit_pins[] = {
120 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55,
121 };
122 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
123 static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, };
124 static int jz4740_nand_cs1_pins[] = { 0x39, };
125 static int jz4740_nand_cs2_pins[] = { 0x3a, };
126 static int jz4740_nand_cs3_pins[] = { 0x3b, };
127 static int jz4740_nand_cs4_pins[] = { 0x3c, };
128 static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
129 static int jz4740_pwm_pwm0_pins[] = { 0x77, };
130 static int jz4740_pwm_pwm1_pins[] = { 0x78, };
131 static int jz4740_pwm_pwm2_pins[] = { 0x79, };
132 static int jz4740_pwm_pwm3_pins[] = { 0x7a, };
133 static int jz4740_pwm_pwm4_pins[] = { 0x7b, };
134 static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
135 static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
136 static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
137
138 static int jz4740_mmc_1bit_funcs[] = { 0, 0, 0, };
139 static int jz4740_mmc_4bit_funcs[] = { 0, 0, 0, };
140 static int jz4740_uart0_data_funcs[] = { 1, 1, };
141 static int jz4740_uart0_hwflow_funcs[] = { 1, 1, };
142 static int jz4740_uart1_data_funcs[] = { 2, 2, };
143 static int jz4740_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
144 static int jz4740_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, };
145 static int jz4740_lcd_18bit_funcs[] = { 0, 0, };
146 static int jz4740_lcd_18bit_tft_funcs[] = { 0, 0, 0, 0, };
147 static int jz4740_nand_cs1_funcs[] = { 0, };
148 static int jz4740_nand_cs2_funcs[] = { 0, };
149 static int jz4740_nand_cs3_funcs[] = { 0, };
150 static int jz4740_nand_cs4_funcs[] = { 0, };
151 static int jz4740_nand_fre_fwe_funcs[] = { 0, 0, };
152 static int jz4740_pwm_pwm0_funcs[] = { 0, };
153 static int jz4740_pwm_pwm1_funcs[] = { 0, };
154 static int jz4740_pwm_pwm2_funcs[] = { 0, };
155 static int jz4740_pwm_pwm3_funcs[] = { 0, };
156 static int jz4740_pwm_pwm4_funcs[] = { 0, };
157 static int jz4740_pwm_pwm5_funcs[] = { 0, };
158 static int jz4740_pwm_pwm6_funcs[] = { 0, };
159 static int jz4740_pwm_pwm7_funcs[] = { 0, };
160
161 #define INGENIC_PIN_GROUP(name, id) \
162 { \
163 name, \
164 id##_pins, \
165 ARRAY_SIZE(id##_pins), \
166 id##_funcs, \
167 }
168
169 static const struct group_desc jz4740_groups[] = {
170 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit),
171 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit),
172 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data),
173 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow),
174 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data),
175 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit),
176 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit),
177 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit),
178 INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft),
179 { "lcd-no-pins", },
180 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1),
181 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2),
182 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3),
183 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4),
184 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe),
185 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0),
186 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1),
187 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2),
188 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3),
189 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4),
190 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5),
191 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6),
192 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7),
193 };
194
195 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
196 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
197 static const char *jz4740_uart1_groups[] = { "uart1-data", };
198 static const char *jz4740_lcd_groups[] = {
199 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins",
200 };
201 static const char *jz4740_nand_groups[] = {
202 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
203 };
204 static const char *jz4740_pwm0_groups[] = { "pwm0", };
205 static const char *jz4740_pwm1_groups[] = { "pwm1", };
206 static const char *jz4740_pwm2_groups[] = { "pwm2", };
207 static const char *jz4740_pwm3_groups[] = { "pwm3", };
208 static const char *jz4740_pwm4_groups[] = { "pwm4", };
209 static const char *jz4740_pwm5_groups[] = { "pwm5", };
210 static const char *jz4740_pwm6_groups[] = { "pwm6", };
211 static const char *jz4740_pwm7_groups[] = { "pwm7", };
212
213 static const struct function_desc jz4740_functions[] = {
214 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
215 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), },
216 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), },
217 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), },
218 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), },
219 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), },
220 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), },
221 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), },
222 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), },
223 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), },
224 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), },
225 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), },
226 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), },
227 };
228
229 static const struct ingenic_chip_info jz4740_chip_info = {
230 .num_chips = 4,
231 .reg_offset = 0x100,
232 .version = ID_JZ4740,
233 .groups = jz4740_groups,
234 .num_groups = ARRAY_SIZE(jz4740_groups),
235 .functions = jz4740_functions,
236 .num_functions = ARRAY_SIZE(jz4740_functions),
237 .pull_ups = jz4740_pull_ups,
238 .pull_downs = jz4740_pull_downs,
239 };
240
241 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, };
242 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, };
243 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, };
244 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, };
245 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, };
246 static int jz4725b_nand_cs1_pins[] = { 0x55, };
247 static int jz4725b_nand_cs2_pins[] = { 0x56, };
248 static int jz4725b_nand_cs3_pins[] = { 0x57, };
249 static int jz4725b_nand_cs4_pins[] = { 0x58, };
250 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 };
251 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d };
252 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, };
253 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, };
254 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, };
255 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, };
256 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, };
257 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, };
258 static int jz4725b_lcd_8bit_pins[] = {
259 0x72, 0x73, 0x74,
260 0x60, 0x61, 0x62, 0x63,
261 0x64, 0x65, 0x66, 0x67,
262 };
263 static int jz4725b_lcd_16bit_pins[] = {
264 0x68, 0x69, 0x6a, 0x6b,
265 0x6c, 0x6d, 0x6e, 0x6f,
266 };
267 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, };
268 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, };
269 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
270 static int jz4725b_lcd_generic_pins[] = { 0x75, };
271
272 static int jz4725b_mmc0_1bit_funcs[] = { 1, 1, 1, };
273 static int jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
274 static int jz4725b_mmc1_1bit_funcs[] = { 0, 0, 0, };
275 static int jz4725b_mmc1_4bit_funcs[] = { 0, 0, 0, };
276 static int jz4725b_uart_data_funcs[] = { 1, 1, };
277 static int jz4725b_nand_cs1_funcs[] = { 0, };
278 static int jz4725b_nand_cs2_funcs[] = { 0, };
279 static int jz4725b_nand_cs3_funcs[] = { 0, };
280 static int jz4725b_nand_cs4_funcs[] = { 0, };
281 static int jz4725b_nand_cle_ale_funcs[] = { 0, 0, };
282 static int jz4725b_nand_fre_fwe_funcs[] = { 0, 0, };
283 static int jz4725b_pwm_pwm0_funcs[] = { 0, };
284 static int jz4725b_pwm_pwm1_funcs[] = { 0, };
285 static int jz4725b_pwm_pwm2_funcs[] = { 0, };
286 static int jz4725b_pwm_pwm3_funcs[] = { 0, };
287 static int jz4725b_pwm_pwm4_funcs[] = { 0, };
288 static int jz4725b_pwm_pwm5_funcs[] = { 0, };
289 static int jz4725b_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
290 static int jz4725b_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
291 static int jz4725b_lcd_18bit_funcs[] = { 0, 0, };
292 static int jz4725b_lcd_24bit_funcs[] = { 1, 1, 1, 1, };
293 static int jz4725b_lcd_special_funcs[] = { 0, 0, 0, 0, };
294 static int jz4725b_lcd_generic_funcs[] = { 0, };
295
296 static const struct group_desc jz4725b_groups[] = {
297 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit),
298 INGENIC_PIN_GROUP("mmc0-4bit", jz4725b_mmc0_4bit),
299 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit),
300 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit),
301 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data),
302 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1),
303 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2),
304 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3),
305 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4),
306 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale),
307 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe),
308 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0),
309 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1),
310 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2),
311 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3),
312 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4),
313 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5),
314 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit),
315 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit),
316 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit),
317 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit),
318 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special),
319 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic),
320 };
321
322 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
323 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
324 static const char *jz4725b_uart_groups[] = { "uart-data", };
325 static const char *jz4725b_nand_groups[] = {
326 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
327 "nand-cle-ale", "nand-fre-fwe",
328 };
329 static const char *jz4725b_pwm0_groups[] = { "pwm0", };
330 static const char *jz4725b_pwm1_groups[] = { "pwm1", };
331 static const char *jz4725b_pwm2_groups[] = { "pwm2", };
332 static const char *jz4725b_pwm3_groups[] = { "pwm3", };
333 static const char *jz4725b_pwm4_groups[] = { "pwm4", };
334 static const char *jz4725b_pwm5_groups[] = { "pwm5", };
335 static const char *jz4725b_lcd_groups[] = {
336 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
337 "lcd-special", "lcd-generic",
338 };
339
340 static const struct function_desc jz4725b_functions[] = {
341 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
342 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), },
343 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), },
344 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), },
345 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), },
346 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), },
347 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), },
348 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), },
349 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), },
350 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), },
351 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), },
352 };
353
354 static const struct ingenic_chip_info jz4725b_chip_info = {
355 .num_chips = 4,
356 .reg_offset = 0x100,
357 .version = ID_JZ4725B,
358 .groups = jz4725b_groups,
359 .num_groups = ARRAY_SIZE(jz4725b_groups),
360 .functions = jz4725b_functions,
361 .num_functions = ARRAY_SIZE(jz4725b_functions),
362 .pull_ups = jz4740_pull_ups,
363 .pull_downs = jz4740_pull_downs,
364 };
365
366 static const u32 jz4760_pull_ups[6] = {
367 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0x0000000f,
368 };
369
370 static const u32 jz4760_pull_downs[6] = {
371 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0,
372 };
373
374 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, };
375 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
376 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, };
377 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
378 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };
379 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
380 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };
381 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };
382 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
383 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
384 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
385 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
386 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
387 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
388 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
389 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
390 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
391 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
392 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
393 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
394 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
395 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
396 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
397 static int jz4760_nemc_8bit_data_pins[] = {
398 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
399 };
400 static int jz4760_nemc_16bit_data_pins[] = {
401 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
402 };
403 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, };
404 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
405 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, };
406 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
407 static int jz4760_nemc_wait_pins[] = { 0x1b, };
408 static int jz4760_nemc_cs1_pins[] = { 0x15, };
409 static int jz4760_nemc_cs2_pins[] = { 0x16, };
410 static int jz4760_nemc_cs3_pins[] = { 0x17, };
411 static int jz4760_nemc_cs4_pins[] = { 0x18, };
412 static int jz4760_nemc_cs5_pins[] = { 0x19, };
413 static int jz4760_nemc_cs6_pins[] = { 0x1a, };
414 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, };
415 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, };
416 static int jz4760_cim_pins[] = {
417 0x26, 0x27, 0x28, 0x29,
418 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
419 };
420 static int jz4760_lcd_24bit_pins[] = {
421 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
422 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
423 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
424 0x58, 0x59, 0x5a, 0x5b,
425 };
426 static int jz4760_pwm_pwm0_pins[] = { 0x80, };
427 static int jz4760_pwm_pwm1_pins[] = { 0x81, };
428 static int jz4760_pwm_pwm2_pins[] = { 0x82, };
429 static int jz4760_pwm_pwm3_pins[] = { 0x83, };
430 static int jz4760_pwm_pwm4_pins[] = { 0x84, };
431 static int jz4760_pwm_pwm5_pins[] = { 0x85, };
432 static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
433 static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
434
435 static int jz4760_uart0_data_funcs[] = { 0, 0, };
436 static int jz4760_uart0_hwflow_funcs[] = { 0, 0, };
437 static int jz4760_uart1_data_funcs[] = { 0, 0, };
438 static int jz4760_uart1_hwflow_funcs[] = { 0, 0, };
439 static int jz4760_uart2_data_funcs[] = { 0, 0, };
440 static int jz4760_uart2_hwflow_funcs[] = { 0, 0, };
441 static int jz4760_uart3_data_funcs[] = { 0, 1, };
442 static int jz4760_uart3_hwflow_funcs[] = { 0, 0, };
443 static int jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
444 static int jz4760_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
445 static int jz4760_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
446 static int jz4760_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
447 static int jz4760_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
448 static int jz4760_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
449 static int jz4760_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
450 static int jz4760_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
451 static int jz4760_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
452 static int jz4760_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
453 static int jz4760_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
454 static int jz4760_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
455 static int jz4760_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
456 static int jz4760_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
457 static int jz4760_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
458 static int jz4760_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
459 static int jz4760_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
460 static int jz4760_nemc_cle_ale_funcs[] = { 0, 0, };
461 static int jz4760_nemc_addr_funcs[] = { 0, 0, 0, 0, };
462 static int jz4760_nemc_rd_we_funcs[] = { 0, 0, };
463 static int jz4760_nemc_frd_fwe_funcs[] = { 0, 0, };
464 static int jz4760_nemc_wait_funcs[] = { 0, };
465 static int jz4760_nemc_cs1_funcs[] = { 0, };
466 static int jz4760_nemc_cs2_funcs[] = { 0, };
467 static int jz4760_nemc_cs3_funcs[] = { 0, };
468 static int jz4760_nemc_cs4_funcs[] = { 0, };
469 static int jz4760_nemc_cs5_funcs[] = { 0, };
470 static int jz4760_nemc_cs6_funcs[] = { 0, };
471 static int jz4760_i2c0_funcs[] = { 0, 0, };
472 static int jz4760_i2c1_funcs[] = { 0, 0, };
473 static int jz4760_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
474 static int jz4760_lcd_24bit_funcs[] = {
475 0, 0, 0, 0, 0, 0, 0, 0,
476 0, 0, 0, 0, 0, 0, 0, 0,
477 0, 0, 0, 0, 0, 0, 0, 0,
478 0, 0, 0, 0,
479 };
480 static int jz4760_pwm_pwm0_funcs[] = { 0, };
481 static int jz4760_pwm_pwm1_funcs[] = { 0, };
482 static int jz4760_pwm_pwm2_funcs[] = { 0, };
483 static int jz4760_pwm_pwm3_funcs[] = { 0, };
484 static int jz4760_pwm_pwm4_funcs[] = { 0, };
485 static int jz4760_pwm_pwm5_funcs[] = { 0, };
486 static int jz4760_pwm_pwm6_funcs[] = { 0, };
487 static int jz4760_pwm_pwm7_funcs[] = { 0, };
488
489 static const struct group_desc jz4760_groups[] = {
490 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data),
491 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow),
492 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data),
493 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow),
494 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data),
495 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow),
496 INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data),
497 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow),
498 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a),
499 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a),
500 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e),
501 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e),
502 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e),
503 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d),
504 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d),
505 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e),
506 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e),
507 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e),
508 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b),
509 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b),
510 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e),
511 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e),
512 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e),
513 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data),
514 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data),
515 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale),
516 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr),
517 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we),
518 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe),
519 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait),
520 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1),
521 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2),
522 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3),
523 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4),
524 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5),
525 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6),
526 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0),
527 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1),
528 INGENIC_PIN_GROUP("cim-data", jz4760_cim),
529 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit),
530 { "lcd-no-pins", },
531 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0),
532 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1),
533 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2),
534 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3),
535 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4),
536 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5),
537 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6),
538 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7),
539 };
540
541 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
542 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
543 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
544 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
545 static const char *jz4760_mmc0_groups[] = {
546 "mmc0-1bit-a", "mmc0-4bit-a",
547 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
548 };
549 static const char *jz4760_mmc1_groups[] = {
550 "mmc1-1bit-d", "mmc1-4bit-d",
551 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
552 };
553 static const char *jz4760_mmc2_groups[] = {
554 "mmc2-1bit-b", "mmc2-4bit-b",
555 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
556 };
557 static const char *jz4760_nemc_groups[] = {
558 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
559 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
560 };
561 static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
562 static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
563 static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
564 static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
565 static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
566 static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
567 static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
568 static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
569 static const char *jz4760_cim_groups[] = { "cim-data", };
570 static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
571 static const char *jz4760_pwm0_groups[] = { "pwm0", };
572 static const char *jz4760_pwm1_groups[] = { "pwm1", };
573 static const char *jz4760_pwm2_groups[] = { "pwm2", };
574 static const char *jz4760_pwm3_groups[] = { "pwm3", };
575 static const char *jz4760_pwm4_groups[] = { "pwm4", };
576 static const char *jz4760_pwm5_groups[] = { "pwm5", };
577 static const char *jz4760_pwm6_groups[] = { "pwm6", };
578 static const char *jz4760_pwm7_groups[] = { "pwm7", };
579
580 static const struct function_desc jz4760_functions[] = {
581 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
582 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), },
583 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), },
584 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), },
585 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), },
586 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), },
587 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), },
588 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), },
589 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
590 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
591 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
592 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
593 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
594 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
595 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), },
596 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), },
597 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), },
598 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), },
599 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), },
600 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), },
601 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), },
602 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), },
603 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), },
604 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
605 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
606 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
607 };
608
609 static const struct ingenic_chip_info jz4760_chip_info = {
610 .num_chips = 6,
611 .reg_offset = 0x100,
612 .version = ID_JZ4760,
613 .groups = jz4760_groups,
614 .num_groups = ARRAY_SIZE(jz4760_groups),
615 .functions = jz4760_functions,
616 .num_functions = ARRAY_SIZE(jz4760_functions),
617 .pull_ups = jz4760_pull_ups,
618 .pull_downs = jz4760_pull_downs,
619 };
620
621 static const u32 jz4770_pull_ups[6] = {
622 0x3fffffff, 0xfff0f3fc, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0x0024f00f,
623 };
624
625 static const u32 jz4770_pull_downs[6] = {
626 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x005b0ff0,
627 };
628
629 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
630 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
631 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
632 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
633 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
634 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
635 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
636 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
637 static int jz4770_ssi0_dt_a_pins[] = { 0x15, };
638 static int jz4770_ssi0_dt_b_pins[] = { 0x35, };
639 static int jz4770_ssi0_dt_d_pins[] = { 0x75, };
640 static int jz4770_ssi0_dt_e_pins[] = { 0x91, };
641 static int jz4770_ssi0_dr_a_pins[] = { 0x14, };
642 static int jz4770_ssi0_dr_b_pins[] = { 0x34, };
643 static int jz4770_ssi0_dr_d_pins[] = { 0x74, };
644 static int jz4770_ssi0_dr_e_pins[] = { 0x8e, };
645 static int jz4770_ssi0_clk_a_pins[] = { 0x12, };
646 static int jz4770_ssi0_clk_b_pins[] = { 0x3c, };
647 static int jz4770_ssi0_clk_d_pins[] = { 0x78, };
648 static int jz4770_ssi0_clk_e_pins[] = { 0x8f, };
649 static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, };
650 static int jz4770_ssi0_gpc_d_pins[] = { 0x76, };
651 static int jz4770_ssi0_gpc_e_pins[] = { 0x93, };
652 static int jz4770_ssi0_ce0_a_pins[] = { 0x13, };
653 static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, };
654 static int jz4770_ssi0_ce0_d_pins[] = { 0x79, };
655 static int jz4770_ssi0_ce0_e_pins[] = { 0x90, };
656 static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, };
657 static int jz4770_ssi0_ce1_d_pins[] = { 0x77, };
658 static int jz4770_ssi0_ce1_e_pins[] = { 0x92, };
659 static int jz4770_ssi1_dt_b_pins[] = { 0x35, };
660 static int jz4770_ssi1_dt_d_pins[] = { 0x75, };
661 static int jz4770_ssi1_dt_e_pins[] = { 0x91, };
662 static int jz4770_ssi1_dr_b_pins[] = { 0x34, };
663 static int jz4770_ssi1_dr_d_pins[] = { 0x74, };
664 static int jz4770_ssi1_dr_e_pins[] = { 0x8e, };
665 static int jz4770_ssi1_clk_b_pins[] = { 0x3c, };
666 static int jz4770_ssi1_clk_d_pins[] = { 0x78, };
667 static int jz4770_ssi1_clk_e_pins[] = { 0x8f, };
668 static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, };
669 static int jz4770_ssi1_gpc_d_pins[] = { 0x76, };
670 static int jz4770_ssi1_gpc_e_pins[] = { 0x93, };
671 static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, };
672 static int jz4770_ssi1_ce0_d_pins[] = { 0x79, };
673 static int jz4770_ssi1_ce0_e_pins[] = { 0x90, };
674 static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, };
675 static int jz4770_ssi1_ce1_d_pins[] = { 0x77, };
676 static int jz4770_ssi1_ce1_e_pins[] = { 0x92, };
677 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
678 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
679 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
680 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
681 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
682 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
683 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
684 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
685 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
686 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
687 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
688 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
689 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
690 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
691 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
692 static int jz4770_nemc_8bit_data_pins[] = {
693 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
694 };
695 static int jz4770_nemc_16bit_data_pins[] = {
696 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
697 };
698 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
699 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
700 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
701 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
702 static int jz4770_nemc_wait_pins[] = { 0x1b, };
703 static int jz4770_nemc_cs1_pins[] = { 0x15, };
704 static int jz4770_nemc_cs2_pins[] = { 0x16, };
705 static int jz4770_nemc_cs3_pins[] = { 0x17, };
706 static int jz4770_nemc_cs4_pins[] = { 0x18, };
707 static int jz4770_nemc_cs5_pins[] = { 0x19, };
708 static int jz4770_nemc_cs6_pins[] = { 0x1a, };
709 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
710 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
711 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
712 static int jz4770_cim_8bit_pins[] = {
713 0x26, 0x27, 0x28, 0x29,
714 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
715 };
716 static int jz4770_cim_12bit_pins[] = {
717 0x32, 0x33, 0xb0, 0xb1,
718 };
719 static int jz4770_lcd_24bit_pins[] = {
720 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
721 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
722 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
723 0x58, 0x59, 0x5a, 0x5b,
724 };
725 static int jz4770_pwm_pwm0_pins[] = { 0x80, };
726 static int jz4770_pwm_pwm1_pins[] = { 0x81, };
727 static int jz4770_pwm_pwm2_pins[] = { 0x82, };
728 static int jz4770_pwm_pwm3_pins[] = { 0x83, };
729 static int jz4770_pwm_pwm4_pins[] = { 0x84, };
730 static int jz4770_pwm_pwm5_pins[] = { 0x85, };
731 static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
732 static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
733 static int jz4770_mac_rmii_pins[] = {
734 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
735 };
736 static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
737 static int jz4770_otg_pins[] = { 0x8a, };
738
739 static int jz4770_uart0_data_funcs[] = { 0, 0, };
740 static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
741 static int jz4770_uart1_data_funcs[] = { 0, 0, };
742 static int jz4770_uart1_hwflow_funcs[] = { 0, 0, };
743 static int jz4770_uart2_data_funcs[] = { 0, 0, };
744 static int jz4770_uart2_hwflow_funcs[] = { 0, 0, };
745 static int jz4770_uart3_data_funcs[] = { 0, 1, };
746 static int jz4770_uart3_hwflow_funcs[] = { 0, 0, };
747 static int jz4770_ssi0_dt_a_funcs[] = { 2, };
748 static int jz4770_ssi0_dt_b_funcs[] = { 1, };
749 static int jz4770_ssi0_dt_d_funcs[] = { 1, };
750 static int jz4770_ssi0_dt_e_funcs[] = { 0, };
751 static int jz4770_ssi0_dr_a_funcs[] = { 1, };
752 static int jz4770_ssi0_dr_b_funcs[] = { 1, };
753 static int jz4770_ssi0_dr_d_funcs[] = { 1, };
754 static int jz4770_ssi0_dr_e_funcs[] = { 0, };
755 static int jz4770_ssi0_clk_a_funcs[] = { 2, };
756 static int jz4770_ssi0_clk_b_funcs[] = { 1, };
757 static int jz4770_ssi0_clk_d_funcs[] = { 1, };
758 static int jz4770_ssi0_clk_e_funcs[] = { 0, };
759 static int jz4770_ssi0_gpc_b_funcs[] = { 1, };
760 static int jz4770_ssi0_gpc_d_funcs[] = { 1, };
761 static int jz4770_ssi0_gpc_e_funcs[] = { 0, };
762 static int jz4770_ssi0_ce0_a_funcs[] = { 2, };
763 static int jz4770_ssi0_ce0_b_funcs[] = { 1, };
764 static int jz4770_ssi0_ce0_d_funcs[] = { 1, };
765 static int jz4770_ssi0_ce0_e_funcs[] = { 0, };
766 static int jz4770_ssi0_ce1_b_funcs[] = { 1, };
767 static int jz4770_ssi0_ce1_d_funcs[] = { 1, };
768 static int jz4770_ssi0_ce1_e_funcs[] = { 0, };
769 static int jz4770_ssi1_dt_b_funcs[] = { 2, };
770 static int jz4770_ssi1_dt_d_funcs[] = { 2, };
771 static int jz4770_ssi1_dt_e_funcs[] = { 1, };
772 static int jz4770_ssi1_dr_b_funcs[] = { 2, };
773 static int jz4770_ssi1_dr_d_funcs[] = { 2, };
774 static int jz4770_ssi1_dr_e_funcs[] = { 1, };
775 static int jz4770_ssi1_clk_b_funcs[] = { 2, };
776 static int jz4770_ssi1_clk_d_funcs[] = { 2, };
777 static int jz4770_ssi1_clk_e_funcs[] = { 1, };
778 static int jz4770_ssi1_gpc_b_funcs[] = { 2, };
779 static int jz4770_ssi1_gpc_d_funcs[] = { 2, };
780 static int jz4770_ssi1_gpc_e_funcs[] = { 1, };
781 static int jz4770_ssi1_ce0_b_funcs[] = { 2, };
782 static int jz4770_ssi1_ce0_d_funcs[] = { 2, };
783 static int jz4770_ssi1_ce0_e_funcs[] = { 1, };
784 static int jz4770_ssi1_ce1_b_funcs[] = { 2, };
785 static int jz4770_ssi1_ce1_d_funcs[] = { 2, };
786 static int jz4770_ssi1_ce1_e_funcs[] = { 1, };
787 static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
788 static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
789 static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
790 static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, };
791 static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, };
792 static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, };
793 static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, };
794 static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, };
795 static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, };
796 static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, };
797 static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, };
798 static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, };
799 static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, };
800 static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, };
801 static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, };
802 static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
803 static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
804 static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, };
805 static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, };
806 static int jz4770_nemc_rd_we_funcs[] = { 0, 0, };
807 static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, };
808 static int jz4770_nemc_wait_funcs[] = { 0, };
809 static int jz4770_nemc_cs1_funcs[] = { 0, };
810 static int jz4770_nemc_cs2_funcs[] = { 0, };
811 static int jz4770_nemc_cs3_funcs[] = { 0, };
812 static int jz4770_nemc_cs4_funcs[] = { 0, };
813 static int jz4770_nemc_cs5_funcs[] = { 0, };
814 static int jz4770_nemc_cs6_funcs[] = { 0, };
815 static int jz4770_i2c0_funcs[] = { 0, 0, };
816 static int jz4770_i2c1_funcs[] = { 0, 0, };
817 static int jz4770_i2c2_funcs[] = { 2, 2, };
818 static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
819 static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, };
820 static int jz4770_lcd_24bit_funcs[] = {
821 0, 0, 0, 0, 0, 0, 0, 0,
822 0, 0, 0, 0, 0, 0, 0, 0,
823 0, 0, 0, 0, 0, 0, 0, 0,
824 0, 0, 0, 0,
825 };
826 static int jz4770_pwm_pwm0_funcs[] = { 0, };
827 static int jz4770_pwm_pwm1_funcs[] = { 0, };
828 static int jz4770_pwm_pwm2_funcs[] = { 0, };
829 static int jz4770_pwm_pwm3_funcs[] = { 0, };
830 static int jz4770_pwm_pwm4_funcs[] = { 0, };
831 static int jz4770_pwm_pwm5_funcs[] = { 0, };
832 static int jz4770_pwm_pwm6_funcs[] = { 0, };
833 static int jz4770_pwm_pwm7_funcs[] = { 0, };
834 static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
835 static int jz4770_mac_mii_funcs[] = { 0, 0, };
836 static int jz4770_otg_funcs[] = { 0, };
837
838 static const struct group_desc jz4770_groups[] = {
839 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
840 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
841 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
842 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
843 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data),
844 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow),
845 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
846 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
847 INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a),
848 INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b),
849 INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d),
850 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e),
851 INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a),
852 INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b),
853 INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d),
854 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e),
855 INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a),
856 INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b),
857 INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d),
858 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e),
859 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b),
860 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d),
861 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e),
862 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a),
863 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b),
864 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d),
865 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e),
866 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b),
867 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d),
868 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e),
869 INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b),
870 INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d),
871 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e),
872 INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b),
873 INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d),
874 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e),
875 INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b),
876 INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d),
877 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e),
878 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b),
879 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d),
880 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e),
881 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b),
882 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d),
883 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e),
884 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b),
885 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d),
886 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e),
887 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
888 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
889 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
890 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
891 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e),
892 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
893 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
894 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
895 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
896 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e),
897 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
898 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
899 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
900 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
901 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e),
902 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data),
903 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data),
904 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
905 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
906 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
907 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
908 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
909 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
910 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
911 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
912 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
913 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
914 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
915 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
916 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
917 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
918 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit),
919 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit),
920 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
921 { "lcd-no-pins", },
922 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
923 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
924 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
925 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
926 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
927 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
928 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
929 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
930 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii),
931 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii),
932 INGENIC_PIN_GROUP("otg-vbus", jz4770_otg),
933 };
934
935 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
936 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
937 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
938 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
939 static const char *jz4770_ssi0_groups[] = {
940 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
941 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
942 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
943 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
944 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
945 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
946 };
947 static const char *jz4770_ssi1_groups[] = {
948 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
949 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
950 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
951 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
952 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
953 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
954 };
955 static const char *jz4770_mmc0_groups[] = {
956 "mmc0-1bit-a", "mmc0-4bit-a",
957 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
958 };
959 static const char *jz4770_mmc1_groups[] = {
960 "mmc1-1bit-d", "mmc1-4bit-d",
961 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
962 };
963 static const char *jz4770_mmc2_groups[] = {
964 "mmc2-1bit-b", "mmc2-4bit-b",
965 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
966 };
967 static const char *jz4770_nemc_groups[] = {
968 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
969 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
970 };
971 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
972 static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
973 static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
974 static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
975 static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
976 static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
977 static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
978 static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
979 static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
980 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
981 static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", };
982 static const char *jz4770_pwm0_groups[] = { "pwm0", };
983 static const char *jz4770_pwm1_groups[] = { "pwm1", };
984 static const char *jz4770_pwm2_groups[] = { "pwm2", };
985 static const char *jz4770_pwm3_groups[] = { "pwm3", };
986 static const char *jz4770_pwm4_groups[] = { "pwm4", };
987 static const char *jz4770_pwm5_groups[] = { "pwm5", };
988 static const char *jz4770_pwm6_groups[] = { "pwm6", };
989 static const char *jz4770_pwm7_groups[] = { "pwm7", };
990 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
991 static const char *jz4770_otg_groups[] = { "otg-vbus", };
992
993 static const struct function_desc jz4770_functions[] = {
994 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
995 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
996 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
997 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
998 { "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), },
999 { "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), },
1000 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
1001 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
1002 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
1003 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
1004 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1005 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1006 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1007 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1008 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1009 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1010 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
1011 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
1012 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
1013 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
1014 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
1015 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
1016 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
1017 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
1018 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
1019 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
1020 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
1021 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
1022 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
1023 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
1024 { "otg", jz4770_otg_groups, ARRAY_SIZE(jz4770_otg_groups), },
1025 };
1026
1027 static const struct ingenic_chip_info jz4770_chip_info = {
1028 .num_chips = 6,
1029 .reg_offset = 0x100,
1030 .version = ID_JZ4770,
1031 .groups = jz4770_groups,
1032 .num_groups = ARRAY_SIZE(jz4770_groups),
1033 .functions = jz4770_functions,
1034 .num_functions = ARRAY_SIZE(jz4770_functions),
1035 .pull_ups = jz4770_pull_ups,
1036 .pull_downs = jz4770_pull_downs,
1037 };
1038
1039 static const u32 jz4780_pull_ups[6] = {
1040 0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f,
1041 };
1042
1043 static const u32 jz4780_pull_downs[6] = {
1044 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
1045 };
1046
1047 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
1048 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
1049 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
1050 static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, };
1051 static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, };
1052 static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, };
1053 static int jz4780_ssi0_dt_b_pins[] = { 0x3d, };
1054 static int jz4780_ssi0_dt_d_pins[] = { 0x79, };
1055 static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, };
1056 static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, };
1057 static int jz4780_ssi0_dr_b_pins[] = { 0x34, };
1058 static int jz4780_ssi0_dr_d_pins[] = { 0x74, };
1059 static int jz4780_ssi0_clk_a_pins[] = { 0x12, };
1060 static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, };
1061 static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, };
1062 static int jz4780_ssi0_clk_d_pins[] = { 0x78, };
1063 static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, };
1064 static int jz4780_ssi0_gpc_d_pins[] = { 0x76, };
1065 static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, };
1066 static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, };
1067 static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, };
1068 static int jz4780_ssi0_ce0_d_pins[] = { 0x77, };
1069 static int jz4780_ssi0_ce1_b_pins[] = { 0x35, };
1070 static int jz4780_ssi0_ce1_d_pins[] = { 0x75, };
1071 static int jz4780_ssi1_dt_b_pins[] = { 0x3d, };
1072 static int jz4780_ssi1_dt_d_pins[] = { 0x79, };
1073 static int jz4780_ssi1_dr_b_pins[] = { 0x34, };
1074 static int jz4780_ssi1_dr_d_pins[] = { 0x74, };
1075 static int jz4780_ssi1_clk_b_pins[] = { 0x3c, };
1076 static int jz4780_ssi1_clk_d_pins[] = { 0x78, };
1077 static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, };
1078 static int jz4780_ssi1_gpc_d_pins[] = { 0x76, };
1079 static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, };
1080 static int jz4780_ssi1_ce0_d_pins[] = { 0x77, };
1081 static int jz4780_ssi1_ce1_b_pins[] = { 0x35, };
1082 static int jz4780_ssi1_ce1_d_pins[] = { 0x75, };
1083 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
1084 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
1085 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
1086 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
1087 static int jz4780_i2s_data_tx_pins[] = { 0x87, };
1088 static int jz4780_i2s_data_rx_pins[] = { 0x86, };
1089 static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, };
1090 static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, };
1091 static int jz4780_i2s_sysclk_pins[] = { 0x85, };
1092 static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, };
1093
1094 static int jz4780_uart2_data_funcs[] = { 1, 1, };
1095 static int jz4780_uart2_hwflow_funcs[] = { 1, 1, };
1096 static int jz4780_uart4_data_funcs[] = { 2, 2, };
1097 static int jz4780_ssi0_dt_a_19_funcs[] = { 2, };
1098 static int jz4780_ssi0_dt_a_21_funcs[] = { 2, };
1099 static int jz4780_ssi0_dt_a_28_funcs[] = { 2, };
1100 static int jz4780_ssi0_dt_b_funcs[] = { 1, };
1101 static int jz4780_ssi0_dt_d_funcs[] = { 1, };
1102 static int jz4780_ssi0_dr_a_20_funcs[] = { 2, };
1103 static int jz4780_ssi0_dr_a_27_funcs[] = { 2, };
1104 static int jz4780_ssi0_dr_b_funcs[] = { 1, };
1105 static int jz4780_ssi0_dr_d_funcs[] = { 1, };
1106 static int jz4780_ssi0_clk_a_funcs[] = { 2, };
1107 static int jz4780_ssi0_clk_b_5_funcs[] = { 1, };
1108 static int jz4780_ssi0_clk_b_28_funcs[] = { 1, };
1109 static int jz4780_ssi0_clk_d_funcs[] = { 1, };
1110 static int jz4780_ssi0_gpc_b_funcs[] = { 1, };
1111 static int jz4780_ssi0_gpc_d_funcs[] = { 1, };
1112 static int jz4780_ssi0_ce0_a_23_funcs[] = { 2, };
1113 static int jz4780_ssi0_ce0_a_25_funcs[] = { 2, };
1114 static int jz4780_ssi0_ce0_b_funcs[] = { 1, };
1115 static int jz4780_ssi0_ce0_d_funcs[] = { 1, };
1116 static int jz4780_ssi0_ce1_b_funcs[] = { 1, };
1117 static int jz4780_ssi0_ce1_d_funcs[] = { 1, };
1118 static int jz4780_ssi1_dt_b_funcs[] = { 2, };
1119 static int jz4780_ssi1_dt_d_funcs[] = { 2, };
1120 static int jz4780_ssi1_dr_b_funcs[] = { 2, };
1121 static int jz4780_ssi1_dr_d_funcs[] = { 2, };
1122 static int jz4780_ssi1_clk_b_funcs[] = { 2, };
1123 static int jz4780_ssi1_clk_d_funcs[] = { 2, };
1124 static int jz4780_ssi1_gpc_b_funcs[] = { 2, };
1125 static int jz4780_ssi1_gpc_d_funcs[] = { 2, };
1126 static int jz4780_ssi1_ce0_b_funcs[] = { 2, };
1127 static int jz4780_ssi1_ce0_d_funcs[] = { 2, };
1128 static int jz4780_ssi1_ce1_b_funcs[] = { 2, };
1129 static int jz4780_ssi1_ce1_d_funcs[] = { 2, };
1130 static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, };
1131 static int jz4780_i2c3_funcs[] = { 1, 1, };
1132 static int jz4780_i2c4_e_funcs[] = { 1, 1, };
1133 static int jz4780_i2c4_f_funcs[] = { 1, 1, };
1134 static int jz4780_i2s_data_tx_funcs[] = { 0, };
1135 static int jz4780_i2s_data_rx_funcs[] = { 0, };
1136 static int jz4780_i2s_clk_txrx_funcs[] = { 1, 0, };
1137 static int jz4780_i2s_clk_rx_funcs[] = { 1, 1, };
1138 static int jz4780_i2s_sysclk_funcs[] = { 2, };
1139 static int jz4780_hdmi_ddc_funcs[] = { 0, 0, };
1140
1141 static const struct group_desc jz4780_groups[] = {
1142 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
1143 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow),
1144 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data),
1145 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow),
1146 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data),
1147 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow),
1148 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
1149 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
1150 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data),
1151 INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19),
1152 INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21),
1153 INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28),
1154 INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b),
1155 INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d),
1156 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e),
1157 INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20),
1158 INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27),
1159 INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b),
1160 INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d),
1161 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e),
1162 INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a),
1163 INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5),
1164 INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28),
1165 INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d),
1166 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e),
1167 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b),
1168 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d),
1169 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e),
1170 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23),
1171 INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25),
1172 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b),
1173 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d),
1174 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e),
1175 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b),
1176 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d),
1177 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e),
1178 INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b),
1179 INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d),
1180 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e),
1181 INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b),
1182 INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d),
1183 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e),
1184 INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b),
1185 INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d),
1186 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e),
1187 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b),
1188 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d),
1189 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e),
1190 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b),
1191 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d),
1192 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e),
1193 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b),
1194 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d),
1195 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e),
1196 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a),
1197 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a),
1198 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a),
1199 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e),
1200 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e),
1201 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d),
1202 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d),
1203 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e),
1204 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e),
1205 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b),
1206 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b),
1207 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e),
1208 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e),
1209 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data),
1210 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale),
1211 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr),
1212 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we),
1213 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe),
1214 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait),
1215 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1),
1216 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2),
1217 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3),
1218 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4),
1219 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5),
1220 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6),
1221 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0),
1222 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1),
1223 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2),
1224 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3),
1225 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e),
1226 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f),
1227 INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx),
1228 INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx),
1229 INGENIC_PIN_GROUP("i2s-clk-txrx", jz4780_i2s_clk_txrx),
1230 INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx),
1231 INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk),
1232 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc),
1233 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit),
1234 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit),
1235 { "lcd-no-pins", },
1236 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0),
1237 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1),
1238 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2),
1239 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3),
1240 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4),
1241 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5),
1242 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6),
1243 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
1244 };
1245
1246 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1247 static const char *jz4780_uart4_groups[] = { "uart4-data", };
1248 static const char *jz4780_ssi0_groups[] = {
1249 "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1250 "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1251 "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",
1252 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1253 "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1254 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1255 };
1256 static const char *jz4780_ssi1_groups[] = {
1257 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1258 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1259 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1260 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1261 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1262 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1263 };
1264 static const char *jz4780_mmc0_groups[] = {
1265 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1266 "mmc0-1bit-e", "mmc0-4bit-e",
1267 };
1268 static const char *jz4780_mmc1_groups[] = {
1269 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
1270 };
1271 static const char *jz4780_mmc2_groups[] = {
1272 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
1273 };
1274 static const char *jz4780_nemc_groups[] = {
1275 "nemc-data", "nemc-cle-ale", "nemc-addr",
1276 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1277 };
1278 static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
1279 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
1280 static const char *jz4780_i2s_groups[] = {
1281 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1282 };
1283 static const char *jz4780_cim_groups[] = { "cim-data", };
1284 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
1285
1286 static const struct function_desc jz4780_functions[] = {
1287 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
1288 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
1289 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
1290 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
1291 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
1292 { "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), },
1293 { "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), },
1294 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
1295 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
1296 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
1297 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
1298 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1299 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1300 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1301 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1302 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1303 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1304 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
1305 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
1306 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
1307 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
1308 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
1309 { "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), },
1310 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
1311 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
1312 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
1313 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
1314 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
1315 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
1316 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
1317 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
1318 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
1319 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
1320 { "hdmi-ddc", jz4780_hdmi_ddc_groups,
1321 ARRAY_SIZE(jz4780_hdmi_ddc_groups), },
1322 };
1323
1324 static const struct ingenic_chip_info jz4780_chip_info = {
1325 .num_chips = 6,
1326 .reg_offset = 0x100,
1327 .version = ID_JZ4780,
1328 .groups = jz4780_groups,
1329 .num_groups = ARRAY_SIZE(jz4780_groups),
1330 .functions = jz4780_functions,
1331 .num_functions = ARRAY_SIZE(jz4780_functions),
1332 .pull_ups = jz4780_pull_ups,
1333 .pull_downs = jz4780_pull_downs,
1334 };
1335
1336 static const u32 x1000_pull_ups[4] = {
1337 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f,
1338 };
1339
1340 static const u32 x1000_pull_downs[4] = {
1341 0x00000000, 0x02000000, 0x02000000, 0x00000000,
1342 };
1343
1344 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };
1345 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
1346 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
1347 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
1348 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, };
1349 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
1350 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
1351 static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, };
1352 static int x1000_ssi_dt_a_22_pins[] = { 0x16, };
1353 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, };
1354 static int x1000_ssi_dt_d_pins[] = { 0x62, };
1355 static int x1000_ssi_dr_a_23_pins[] = { 0x17, };
1356 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, };
1357 static int x1000_ssi_dr_d_pins[] = { 0x63, };
1358 static int x1000_ssi_clk_a_24_pins[] = { 0x18, };
1359 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, };
1360 static int x1000_ssi_clk_d_pins[] = { 0x60, };
1361 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, };
1362 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, };
1363 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, };
1364 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, };
1365 static int x1000_ssi_ce0_d_pins[] = { 0x61, };
1366 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, };
1367 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, };
1368 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
1369 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
1370 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
1371 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
1372 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
1373 static int x1000_emc_8bit_data_pins[] = {
1374 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1375 };
1376 static int x1000_emc_16bit_data_pins[] = {
1377 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1378 };
1379 static int x1000_emc_addr_pins[] = {
1380 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
1381 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
1382 };
1383 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, };
1384 static int x1000_emc_wait_pins[] = { 0x34, };
1385 static int x1000_emc_cs1_pins[] = { 0x32, };
1386 static int x1000_emc_cs2_pins[] = { 0x33, };
1387 static int x1000_i2c0_pins[] = { 0x38, 0x37, };
1388 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
1389 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
1390 static int x1000_i2c2_pins[] = { 0x61, 0x60, };
1391 static int x1000_i2s_data_tx_pins[] = { 0x24, };
1392 static int x1000_i2s_data_rx_pins[] = { 0x23, };
1393 static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
1394 static int x1000_i2s_sysclk_pins[] = { 0x20, };
1395 static int x1000_cim_pins[] = {
1396 0x08, 0x09, 0x0a, 0x0b,
1397 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
1398 };
1399 static int x1000_lcd_8bit_pins[] = {
1400 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1401 0x30, 0x31, 0x32, 0x33, 0x34,
1402 };
1403 static int x1000_lcd_16bit_pins[] = {
1404 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1405 };
1406 static int x1000_pwm_pwm0_pins[] = { 0x59, };
1407 static int x1000_pwm_pwm1_pins[] = { 0x5a, };
1408 static int x1000_pwm_pwm2_pins[] = { 0x5b, };
1409 static int x1000_pwm_pwm3_pins[] = { 0x26, };
1410 static int x1000_pwm_pwm4_pins[] = { 0x58, };
1411 static int x1000_mac_pins[] = {
1412 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
1413 };
1414
1415 static int x1000_uart0_data_funcs[] = { 0, 0, };
1416 static int x1000_uart0_hwflow_funcs[] = { 0, 0, };
1417 static int x1000_uart1_data_a_funcs[] = { 2, 2, };
1418 static int x1000_uart1_data_d_funcs[] = { 1, 1, };
1419 static int x1000_uart1_hwflow_funcs[] = { 1, 1, };
1420 static int x1000_uart2_data_a_funcs[] = { 2, 2, };
1421 static int x1000_uart2_data_d_funcs[] = { 0, 0, };
1422 static int x1000_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, };
1423 static int x1000_ssi_dt_a_22_funcs[] = { 2, };
1424 static int x1000_ssi_dt_a_29_funcs[] = { 2, };
1425 static int x1000_ssi_dt_d_funcs[] = { 0, };
1426 static int x1000_ssi_dr_a_23_funcs[] = { 2, };
1427 static int x1000_ssi_dr_a_28_funcs[] = { 2, };
1428 static int x1000_ssi_dr_d_funcs[] = { 0, };
1429 static int x1000_ssi_clk_a_24_funcs[] = { 2, };
1430 static int x1000_ssi_clk_a_26_funcs[] = { 2, };
1431 static int x1000_ssi_clk_d_funcs[] = { 0, };
1432 static int x1000_ssi_gpc_a_20_funcs[] = { 2, };
1433 static int x1000_ssi_gpc_a_31_funcs[] = { 2, };
1434 static int x1000_ssi_ce0_a_25_funcs[] = { 2, };
1435 static int x1000_ssi_ce0_a_27_funcs[] = { 2, };
1436 static int x1000_ssi_ce0_d_funcs[] = { 0, };
1437 static int x1000_ssi_ce1_a_21_funcs[] = { 2, };
1438 static int x1000_ssi_ce1_a_30_funcs[] = { 2, };
1439 static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, };
1440 static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, };
1441 static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, };
1442 static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, };
1443 static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, };
1444 static int x1000_emc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
1445 static int x1000_emc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
1446 static int x1000_emc_addr_funcs[] = {
1447 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1448 };
1449 static int x1000_emc_rd_we_funcs[] = { 0, 0, };
1450 static int x1000_emc_wait_funcs[] = { 0, };
1451 static int x1000_emc_cs1_funcs[] = { 0, };
1452 static int x1000_emc_cs2_funcs[] = { 0, };
1453 static int x1000_i2c0_funcs[] = { 0, 0, };
1454 static int x1000_i2c1_a_funcs[] = { 2, 2, };
1455 static int x1000_i2c1_c_funcs[] = { 0, 0, };
1456 static int x1000_i2c2_funcs[] = { 1, 1, };
1457 static int x1000_i2s_data_tx_funcs[] = { 1, };
1458 static int x1000_i2s_data_rx_funcs[] = { 1, };
1459 static int x1000_i2s_clk_txrx_funcs[] = { 1, 1, };
1460 static int x1000_i2s_sysclk_funcs[] = { 1, };
1461 static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
1462 static int x1000_lcd_8bit_funcs[] = {
1463 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1464 };
1465 static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
1466 static int x1000_pwm_pwm0_funcs[] = { 0, };
1467 static int x1000_pwm_pwm1_funcs[] = { 1, };
1468 static int x1000_pwm_pwm2_funcs[] = { 1, };
1469 static int x1000_pwm_pwm3_funcs[] = { 2, };
1470 static int x1000_pwm_pwm4_funcs[] = { 0, };
1471 static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
1472
1473 static const struct group_desc x1000_groups[] = {
1474 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data),
1475 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow),
1476 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a),
1477 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d),
1478 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow),
1479 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a),
1480 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d),
1481 INGENIC_PIN_GROUP("sfc", x1000_sfc),
1482 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22),
1483 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29),
1484 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d),
1485 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23),
1486 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28),
1487 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d),
1488 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24),
1489 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26),
1490 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d),
1491 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20),
1492 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31),
1493 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25),
1494 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27),
1495 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d),
1496 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21),
1497 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30),
1498 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit),
1499 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit),
1500 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit),
1501 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit),
1502 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit),
1503 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data),
1504 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data),
1505 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr),
1506 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we),
1507 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait),
1508 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1),
1509 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2),
1510 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0),
1511 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a),
1512 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c),
1513 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2),
1514 INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx),
1515 INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx),
1516 INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx),
1517 INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk),
1518 INGENIC_PIN_GROUP("cim-data", x1000_cim),
1519 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit),
1520 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit),
1521 { "lcd-no-pins", },
1522 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0),
1523 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1),
1524 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2),
1525 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3),
1526 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4),
1527 INGENIC_PIN_GROUP("mac", x1000_mac),
1528 };
1529
1530 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1531 static const char *x1000_uart1_groups[] = {
1532 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
1533 };
1534 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
1535 static const char *x1000_sfc_groups[] = { "sfc", };
1536 static const char *x1000_ssi_groups[] = {
1537 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
1538 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
1539 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
1540 "ssi-gpc-a-20", "ssi-gpc-a-31",
1541 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
1542 "ssi-ce1-a-21", "ssi-ce1-a-30",
1543 };
1544 static const char *x1000_mmc0_groups[] = {
1545 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
1546 };
1547 static const char *x1000_mmc1_groups[] = {
1548 "mmc1-1bit", "mmc1-4bit",
1549 };
1550 static const char *x1000_emc_groups[] = {
1551 "emc-8bit-data", "emc-16bit-data",
1552 "emc-addr", "emc-rd-we", "emc-wait",
1553 };
1554 static const char *x1000_cs1_groups[] = { "emc-cs1", };
1555 static const char *x1000_cs2_groups[] = { "emc-cs2", };
1556 static const char *x1000_i2c0_groups[] = { "i2c0-data", };
1557 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
1558 static const char *x1000_i2c2_groups[] = { "i2c2-data", };
1559 static const char *x1000_i2s_groups[] = {
1560 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1561 };
1562 static const char *x1000_cim_groups[] = { "cim-data", };
1563 static const char *x1000_lcd_groups[] = {
1564 "lcd-8bit", "lcd-16bit", "lcd-no-pins",
1565 };
1566 static const char *x1000_pwm0_groups[] = { "pwm0", };
1567 static const char *x1000_pwm1_groups[] = { "pwm1", };
1568 static const char *x1000_pwm2_groups[] = { "pwm2", };
1569 static const char *x1000_pwm3_groups[] = { "pwm3", };
1570 static const char *x1000_pwm4_groups[] = { "pwm4", };
1571 static const char *x1000_mac_groups[] = { "mac", };
1572
1573 static const struct function_desc x1000_functions[] = {
1574 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
1575 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
1576 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
1577 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
1578 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), },
1579 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
1580 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
1581 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), },
1582 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
1583 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
1584 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
1585 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
1586 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
1587 { "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), },
1588 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
1589 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
1590 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
1591 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), },
1592 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), },
1593 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), },
1594 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), },
1595 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
1596 };
1597
1598 static const struct ingenic_chip_info x1000_chip_info = {
1599 .num_chips = 4,
1600 .reg_offset = 0x100,
1601 .version = ID_X1000,
1602 .groups = x1000_groups,
1603 .num_groups = ARRAY_SIZE(x1000_groups),
1604 .functions = x1000_functions,
1605 .num_functions = ARRAY_SIZE(x1000_functions),
1606 .pull_ups = x1000_pull_ups,
1607 .pull_downs = x1000_pull_downs,
1608 };
1609
1610 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
1611 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
1612 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };
1613 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };
1614 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, };
1615 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };
1616 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };
1617 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, };
1618 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, };
1619 static int x1500_i2c0_pins[] = { 0x38, 0x37, };
1620 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
1621 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
1622 static int x1500_i2c2_pins[] = { 0x61, 0x60, };
1623 static int x1500_i2s_data_tx_pins[] = { 0x24, };
1624 static int x1500_i2s_data_rx_pins[] = { 0x23, };
1625 static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
1626 static int x1500_i2s_sysclk_pins[] = { 0x20, };
1627 static int x1500_cim_pins[] = {
1628 0x08, 0x09, 0x0a, 0x0b,
1629 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
1630 };
1631 static int x1500_pwm_pwm0_pins[] = { 0x59, };
1632 static int x1500_pwm_pwm1_pins[] = { 0x5a, };
1633 static int x1500_pwm_pwm2_pins[] = { 0x5b, };
1634 static int x1500_pwm_pwm3_pins[] = { 0x26, };
1635 static int x1500_pwm_pwm4_pins[] = { 0x58, };
1636
1637 static int x1500_uart0_data_funcs[] = { 0, 0, };
1638 static int x1500_uart0_hwflow_funcs[] = { 0, 0, };
1639 static int x1500_uart1_data_a_funcs[] = { 2, 2, };
1640 static int x1500_uart1_data_d_funcs[] = { 1, 1, };
1641 static int x1500_uart1_hwflow_funcs[] = { 1, 1, };
1642 static int x1500_uart2_data_a_funcs[] = { 2, 2, };
1643 static int x1500_uart2_data_d_funcs[] = { 0, 0, };
1644 static int x1500_mmc_1bit_funcs[] = { 1, 1, 1, };
1645 static int x1500_mmc_4bit_funcs[] = { 1, 1, 1, };
1646 static int x1500_i2c0_funcs[] = { 0, 0, };
1647 static int x1500_i2c1_a_funcs[] = { 2, 2, };
1648 static int x1500_i2c1_c_funcs[] = { 0, 0, };
1649 static int x1500_i2c2_funcs[] = { 1, 1, };
1650 static int x1500_i2s_data_tx_funcs[] = { 1, };
1651 static int x1500_i2s_data_rx_funcs[] = { 1, };
1652 static int x1500_i2s_clk_txrx_funcs[] = { 1, 1, };
1653 static int x1500_i2s_sysclk_funcs[] = { 1, };
1654 static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
1655 static int x1500_pwm_pwm0_funcs[] = { 0, };
1656 static int x1500_pwm_pwm1_funcs[] = { 1, };
1657 static int x1500_pwm_pwm2_funcs[] = { 1, };
1658 static int x1500_pwm_pwm3_funcs[] = { 2, };
1659 static int x1500_pwm_pwm4_funcs[] = { 0, };
1660
1661 static const struct group_desc x1500_groups[] = {
1662 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data),
1663 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow),
1664 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a),
1665 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d),
1666 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow),
1667 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a),
1668 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d),
1669 INGENIC_PIN_GROUP("sfc", x1000_sfc),
1670 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit),
1671 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit),
1672 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0),
1673 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a),
1674 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c),
1675 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2),
1676 INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx),
1677 INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx),
1678 INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx),
1679 INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk),
1680 INGENIC_PIN_GROUP("cim-data", x1500_cim),
1681 { "lcd-no-pins", },
1682 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0),
1683 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1),
1684 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2),
1685 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3),
1686 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4),
1687 };
1688
1689 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1690 static const char *x1500_uart1_groups[] = {
1691 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
1692 };
1693 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
1694 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
1695 static const char *x1500_i2c0_groups[] = { "i2c0-data", };
1696 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
1697 static const char *x1500_i2c2_groups[] = { "i2c2-data", };
1698 static const char *x1500_i2s_groups[] = {
1699 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1700 };
1701 static const char *x1500_cim_groups[] = { "cim-data", };
1702 static const char *x1500_lcd_groups[] = { "lcd-no-pins", };
1703 static const char *x1500_pwm0_groups[] = { "pwm0", };
1704 static const char *x1500_pwm1_groups[] = { "pwm1", };
1705 static const char *x1500_pwm2_groups[] = { "pwm2", };
1706 static const char *x1500_pwm3_groups[] = { "pwm3", };
1707 static const char *x1500_pwm4_groups[] = { "pwm4", };
1708
1709 static const struct function_desc x1500_functions[] = {
1710 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },
1711 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },
1712 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },
1713 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
1714 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), },
1715 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
1716 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
1717 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
1718 { "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), },
1719 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), },
1720 { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), },
1721 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), },
1722 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), },
1723 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), },
1724 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), },
1725 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), },
1726 };
1727
1728 static const struct ingenic_chip_info x1500_chip_info = {
1729 .num_chips = 4,
1730 .reg_offset = 0x100,
1731 .version = ID_X1500,
1732 .groups = x1500_groups,
1733 .num_groups = ARRAY_SIZE(x1500_groups),
1734 .functions = x1500_functions,
1735 .num_functions = ARRAY_SIZE(x1500_functions),
1736 .pull_ups = x1000_pull_ups,
1737 .pull_downs = x1000_pull_downs,
1738 };
1739
1740 static const u32 x1830_pull_ups[4] = {
1741 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
1742 };
1743
1744 static const u32 x1830_pull_downs[4] = {
1745 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
1746 };
1747
1748 static int x1830_uart0_data_pins[] = { 0x33, 0x36, };
1749 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, };
1750 static int x1830_uart1_data_pins[] = { 0x38, 0x37, };
1751 static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, };
1752 static int x1830_ssi0_dt_pins[] = { 0x4c, };
1753 static int x1830_ssi0_dr_pins[] = { 0x4b, };
1754 static int x1830_ssi0_clk_pins[] = { 0x4f, };
1755 static int x1830_ssi0_gpc_pins[] = { 0x4d, };
1756 static int x1830_ssi0_ce0_pins[] = { 0x50, };
1757 static int x1830_ssi0_ce1_pins[] = { 0x4e, };
1758 static int x1830_ssi1_dt_c_pins[] = { 0x53, };
1759 static int x1830_ssi1_dr_c_pins[] = { 0x54, };
1760 static int x1830_ssi1_clk_c_pins[] = { 0x57, };
1761 static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
1762 static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
1763 static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
1764 static int x1830_ssi1_dt_d_pins[] = { 0x62, };
1765 static int x1830_ssi1_dr_d_pins[] = { 0x63, };
1766 static int x1830_ssi1_clk_d_pins[] = { 0x66, };
1767 static int x1830_ssi1_gpc_d_pins[] = { 0x64, };
1768 static int x1830_ssi1_ce0_d_pins[] = { 0x67, };
1769 static int x1830_ssi1_ce1_d_pins[] = { 0x65, };
1770 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, };
1771 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };
1772 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, };
1773 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, };
1774 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, };
1775 static int x1830_i2c1_pins[] = { 0x39, 0x3a, };
1776 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, };
1777 static int x1830_i2s_data_tx_pins[] = { 0x53, };
1778 static int x1830_i2s_data_rx_pins[] = { 0x54, };
1779 static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, };
1780 static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, };
1781 static int x1830_i2s_sysclk_pins[] = { 0x57, };
1782 static int x1830_lcd_rgb_18bit_pins[] = {
1783 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
1784 0x68, 0x69, 0x6c, 0x6d, 0x6e, 0x6f,
1785 0x70, 0x71, 0x72, 0x73, 0x76, 0x77,
1786 0x78, 0x79, 0x7a, 0x7b,
1787 };
1788 static int x1830_lcd_slcd_8bit_pins[] = {
1789 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d,
1790 0x69, 0x72, 0x73, 0x7b, 0x7a,
1791 };
1792 static int x1830_lcd_slcd_16bit_pins[] = {
1793 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79,
1794 };
1795 static int x1830_pwm_pwm0_b_pins[] = { 0x31, };
1796 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, };
1797 static int x1830_pwm_pwm1_b_pins[] = { 0x32, };
1798 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, };
1799 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, };
1800 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, };
1801 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, };
1802 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, };
1803 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, };
1804 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, };
1805 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, };
1806 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, };
1807 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, };
1808 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, };
1809 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, };
1810 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, };
1811 static int x1830_mac_pins[] = {
1812 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27,
1813 };
1814
1815 static int x1830_uart0_data_funcs[] = { 0, 0, };
1816 static int x1830_uart0_hwflow_funcs[] = { 0, 0, };
1817 static int x1830_uart1_data_funcs[] = { 0, 0, };
1818 static int x1830_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, };
1819 static int x1830_ssi0_dt_funcs[] = { 0, };
1820 static int x1830_ssi0_dr_funcs[] = { 0, };
1821 static int x1830_ssi0_clk_funcs[] = { 0, };
1822 static int x1830_ssi0_gpc_funcs[] = { 0, };
1823 static int x1830_ssi0_ce0_funcs[] = { 0, };
1824 static int x1830_ssi0_ce1_funcs[] = { 0, };
1825 static int x1830_ssi1_dt_c_funcs[] = { 1, };
1826 static int x1830_ssi1_dr_c_funcs[] = { 1, };
1827 static int x1830_ssi1_clk_c_funcs[] = { 1, };
1828 static int x1830_ssi1_gpc_c_funcs[] = { 1, };
1829 static int x1830_ssi1_ce0_c_funcs[] = { 1, };
1830 static int x1830_ssi1_ce1_c_funcs[] = { 1, };
1831 static int x1830_ssi1_dt_d_funcs[] = { 2, };
1832 static int x1830_ssi1_dr_d_funcs[] = { 2, };
1833 static int x1830_ssi1_clk_d_funcs[] = { 2, };
1834 static int x1830_ssi1_gpc_d_funcs[] = { 2, };
1835 static int x1830_ssi1_ce0_d_funcs[] = { 2, };
1836 static int x1830_ssi1_ce1_d_funcs[] = { 2, };
1837 static int x1830_mmc0_1bit_funcs[] = { 0, 0, 0, };
1838 static int x1830_mmc0_4bit_funcs[] = { 0, 0, 0, };
1839 static int x1830_mmc1_1bit_funcs[] = { 0, 0, 0, };
1840 static int x1830_mmc1_4bit_funcs[] = { 0, 0, 0, };
1841 static int x1830_i2c0_funcs[] = { 1, 1, };
1842 static int x1830_i2c1_funcs[] = { 0, 0, };
1843 static int x1830_i2c2_funcs[] = { 1, 1, };
1844 static int x1830_i2s_data_tx_funcs[] = { 0, };
1845 static int x1830_i2s_data_rx_funcs[] = { 0, };
1846 static int x1830_i2s_clk_txrx_funcs[] = { 0, 0, };
1847 static int x1830_i2s_clk_rx_funcs[] = { 0, 0, };
1848 static int x1830_i2s_sysclk_funcs[] = { 0, };
1849 static int x1830_lcd_rgb_18bit_funcs[] = {
1850 0, 0, 0, 0, 0, 0,
1851 0, 0, 0, 0, 0, 0,
1852 0, 0, 0, 0, 0, 0,
1853 0, 0, 0, 0,
1854 };
1855 static int x1830_lcd_slcd_8bit_funcs[] = {
1856 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1857 };
1858 static int x1830_lcd_slcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
1859 static int x1830_pwm_pwm0_b_funcs[] = { 0, };
1860 static int x1830_pwm_pwm0_c_funcs[] = { 1, };
1861 static int x1830_pwm_pwm1_b_funcs[] = { 0, };
1862 static int x1830_pwm_pwm1_c_funcs[] = { 1, };
1863 static int x1830_pwm_pwm2_c_8_funcs[] = { 0, };
1864 static int x1830_pwm_pwm2_c_13_funcs[] = { 1, };
1865 static int x1830_pwm_pwm3_c_9_funcs[] = { 0, };
1866 static int x1830_pwm_pwm3_c_14_funcs[] = { 1, };
1867 static int x1830_pwm_pwm4_c_15_funcs[] = { 1, };
1868 static int x1830_pwm_pwm4_c_25_funcs[] = { 0, };
1869 static int x1830_pwm_pwm5_c_16_funcs[] = { 1, };
1870 static int x1830_pwm_pwm5_c_26_funcs[] = { 0, };
1871 static int x1830_pwm_pwm6_c_17_funcs[] = { 1, };
1872 static int x1830_pwm_pwm6_c_27_funcs[] = { 0, };
1873 static int x1830_pwm_pwm7_c_18_funcs[] = { 1, };
1874 static int x1830_pwm_pwm7_c_28_funcs[] = { 0, };
1875 static int x1830_mac_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
1876
1877 static const struct group_desc x1830_groups[] = {
1878 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data),
1879 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow),
1880 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data),
1881 INGENIC_PIN_GROUP("sfc", x1830_sfc),
1882 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt),
1883 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr),
1884 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk),
1885 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc),
1886 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0),
1887 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1),
1888 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c),
1889 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c),
1890 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c),
1891 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c),
1892 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c),
1893 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c),
1894 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d),
1895 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d),
1896 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d),
1897 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d),
1898 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d),
1899 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d),
1900 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit),
1901 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit),
1902 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit),
1903 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit),
1904 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0),
1905 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1),
1906 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2),
1907 INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx),
1908 INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx),
1909 INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx),
1910 INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx),
1911 INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk),
1912 INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit),
1913 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit),
1914 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit),
1915 { "lcd-no-pins", },
1916 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b),
1917 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c),
1918 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b),
1919 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c),
1920 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8),
1921 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13),
1922 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9),
1923 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14),
1924 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15),
1925 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25),
1926 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16),
1927 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26),
1928 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17),
1929 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27),
1930 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18),
1931 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28),
1932 INGENIC_PIN_GROUP("mac", x1830_mac),
1933 };
1934
1935 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1936 static const char *x1830_uart1_groups[] = { "uart1-data", };
1937 static const char *x1830_sfc_groups[] = { "sfc", };
1938 static const char *x1830_ssi0_groups[] = {
1939 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
1940 };
1941 static const char *x1830_ssi1_groups[] = {
1942 "ssi1-dt-c", "ssi1-dt-d",
1943 "ssi1-dr-c", "ssi1-dr-d",
1944 "ssi1-clk-c", "ssi1-clk-d",
1945 "ssi1-gpc-c", "ssi1-gpc-d",
1946 "ssi1-ce0-c", "ssi1-ce0-d",
1947 "ssi1-ce1-c", "ssi1-ce1-d",
1948 };
1949 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
1950 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
1951 static const char *x1830_i2c0_groups[] = { "i2c0-data", };
1952 static const char *x1830_i2c1_groups[] = { "i2c1-data", };
1953 static const char *x1830_i2c2_groups[] = { "i2c2-data", };
1954 static const char *x1830_i2s_groups[] = {
1955 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1956 };
1957 static const char *x1830_lcd_groups[] = {
1958 "lcd-rgb-18bit", "lcd-slcd-8bit", "lcd-slcd-16bit", "lcd-no-pins",
1959 };
1960 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
1961 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
1962 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
1963 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
1964 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
1965 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
1966 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
1967 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
1968 static const char *x1830_mac_groups[] = { "mac", };
1969
1970 static const struct function_desc x1830_functions[] = {
1971 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), },
1972 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), },
1973 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), },
1974 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), },
1975 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), },
1976 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), },
1977 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), },
1978 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), },
1979 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), },
1980 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), },
1981 { "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), },
1982 { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), },
1983 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), },
1984 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), },
1985 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), },
1986 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), },
1987 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1988 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1989 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1990 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), },
1991 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), },
1992 };
1993
1994 static const struct ingenic_chip_info x1830_chip_info = {
1995 .num_chips = 4,
1996 .reg_offset = 0x1000,
1997 .version = ID_X1830,
1998 .groups = x1830_groups,
1999 .num_groups = ARRAY_SIZE(x1830_groups),
2000 .functions = x1830_functions,
2001 .num_functions = ARRAY_SIZE(x1830_functions),
2002 .pull_ups = x1830_pull_ups,
2003 .pull_downs = x1830_pull_downs,
2004 };
2005
ingenic_gpio_read_reg(struct ingenic_gpio_chip * jzgc,u8 reg)2006 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
2007 {
2008 unsigned int val;
2009
2010 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
2011
2012 return (u32) val;
2013 }
2014
ingenic_gpio_set_bit(struct ingenic_gpio_chip * jzgc,u8 reg,u8 offset,bool set)2015 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
2016 u8 reg, u8 offset, bool set)
2017 {
2018 if (set)
2019 reg = REG_SET(reg);
2020 else
2021 reg = REG_CLEAR(reg);
2022
2023 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
2024 }
2025
ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip * jzgc,u8 reg,u8 offset,bool set)2026 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
2027 u8 reg, u8 offset, bool set)
2028 {
2029 if (set)
2030 reg = REG_SET(reg);
2031 else
2032 reg = REG_CLEAR(reg);
2033
2034 regmap_write(jzgc->jzpc->map, REG_PZ_BASE(
2035 jzgc->jzpc->info->reg_offset) + reg, BIT(offset));
2036 }
2037
ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip * jzgc)2038 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
2039 {
2040 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(
2041 jzgc->jzpc->info->reg_offset),
2042 jzgc->gc.base / PINS_PER_GPIO_CHIP);
2043 }
2044
ingenic_gpio_get_value(struct ingenic_gpio_chip * jzgc,u8 offset)2045 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
2046 u8 offset)
2047 {
2048 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
2049
2050 return !!(val & BIT(offset));
2051 }
2052
ingenic_gpio_set_value(struct ingenic_gpio_chip * jzgc,u8 offset,int value)2053 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
2054 u8 offset, int value)
2055 {
2056 if (jzgc->jzpc->info->version >= ID_JZ4770)
2057 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value);
2058 else
2059 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
2060 }
2061
irq_set_type(struct ingenic_gpio_chip * jzgc,u8 offset,unsigned int type)2062 static void irq_set_type(struct ingenic_gpio_chip *jzgc,
2063 u8 offset, unsigned int type)
2064 {
2065 u8 reg1, reg2;
2066 bool val1, val2;
2067
2068 switch (type) {
2069 case IRQ_TYPE_EDGE_RISING:
2070 val1 = val2 = true;
2071 break;
2072 case IRQ_TYPE_EDGE_FALLING:
2073 val1 = false;
2074 val2 = true;
2075 break;
2076 case IRQ_TYPE_LEVEL_HIGH:
2077 val1 = true;
2078 val2 = false;
2079 break;
2080 case IRQ_TYPE_LEVEL_LOW:
2081 default:
2082 val1 = val2 = false;
2083 break;
2084 }
2085
2086 if (jzgc->jzpc->info->version >= ID_JZ4770) {
2087 reg1 = JZ4760_GPIO_PAT1;
2088 reg2 = JZ4760_GPIO_PAT0;
2089 } else {
2090 reg1 = JZ4740_GPIO_TRIG;
2091 reg2 = JZ4740_GPIO_DIR;
2092 }
2093
2094 if (jzgc->jzpc->info->version >= ID_X1000) {
2095 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
2096 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
2097 ingenic_gpio_shadow_set_bit_load(jzgc);
2098 } else {
2099 ingenic_gpio_set_bit(jzgc, reg2, offset, val1);
2100 ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
2101 }
2102 }
2103
ingenic_gpio_irq_mask(struct irq_data * irqd)2104 static void ingenic_gpio_irq_mask(struct irq_data *irqd)
2105 {
2106 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
2107 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2108
2109 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true);
2110 }
2111
ingenic_gpio_irq_unmask(struct irq_data * irqd)2112 static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
2113 {
2114 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
2115 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2116
2117 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false);
2118 }
2119
ingenic_gpio_irq_enable(struct irq_data * irqd)2120 static void ingenic_gpio_irq_enable(struct irq_data *irqd)
2121 {
2122 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
2123 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2124 int irq = irqd->hwirq;
2125
2126 if (jzgc->jzpc->info->version >= ID_JZ4770)
2127 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true);
2128 else
2129 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
2130
2131 ingenic_gpio_irq_unmask(irqd);
2132 }
2133
ingenic_gpio_irq_disable(struct irq_data * irqd)2134 static void ingenic_gpio_irq_disable(struct irq_data *irqd)
2135 {
2136 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
2137 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2138 int irq = irqd->hwirq;
2139
2140 ingenic_gpio_irq_mask(irqd);
2141
2142 if (jzgc->jzpc->info->version >= ID_JZ4770)
2143 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false);
2144 else
2145 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
2146 }
2147
ingenic_gpio_irq_ack(struct irq_data * irqd)2148 static void ingenic_gpio_irq_ack(struct irq_data *irqd)
2149 {
2150 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
2151 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2152 int irq = irqd->hwirq;
2153 bool high;
2154
2155 if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) {
2156 /*
2157 * Switch to an interrupt for the opposite edge to the one that
2158 * triggered the interrupt being ACKed.
2159 */
2160 high = ingenic_gpio_get_value(jzgc, irq);
2161 if (high)
2162 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW);
2163 else
2164 irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH);
2165 }
2166
2167 if (jzgc->jzpc->info->version >= ID_JZ4770)
2168 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false);
2169 else
2170 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
2171 }
2172
ingenic_gpio_irq_set_type(struct irq_data * irqd,unsigned int type)2173 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
2174 {
2175 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
2176 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2177
2178 switch (type) {
2179 case IRQ_TYPE_EDGE_BOTH:
2180 case IRQ_TYPE_EDGE_RISING:
2181 case IRQ_TYPE_EDGE_FALLING:
2182 irq_set_handler_locked(irqd, handle_edge_irq);
2183 break;
2184 case IRQ_TYPE_LEVEL_HIGH:
2185 case IRQ_TYPE_LEVEL_LOW:
2186 irq_set_handler_locked(irqd, handle_level_irq);
2187 break;
2188 default:
2189 irq_set_handler_locked(irqd, handle_bad_irq);
2190 }
2191
2192 if (type == IRQ_TYPE_EDGE_BOTH) {
2193 /*
2194 * The hardware does not support interrupts on both edges. The
2195 * best we can do is to set up a single-edge interrupt and then
2196 * switch to the opposing edge when ACKing the interrupt.
2197 */
2198 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq);
2199
2200 type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH;
2201 }
2202
2203 irq_set_type(jzgc, irqd->hwirq, type);
2204 return 0;
2205 }
2206
ingenic_gpio_irq_set_wake(struct irq_data * irqd,unsigned int on)2207 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
2208 {
2209 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
2210 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2211
2212 return irq_set_irq_wake(jzgc->irq, on);
2213 }
2214
ingenic_gpio_irq_handler(struct irq_desc * desc)2215 static void ingenic_gpio_irq_handler(struct irq_desc *desc)
2216 {
2217 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
2218 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2219 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
2220 unsigned long flag, i;
2221
2222 chained_irq_enter(irq_chip, desc);
2223
2224 if (jzgc->jzpc->info->version >= ID_JZ4770)
2225 flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG);
2226 else
2227 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
2228
2229 for_each_set_bit(i, &flag, 32)
2230 generic_handle_irq(irq_linear_revmap(gc->irq.domain, i));
2231 chained_irq_exit(irq_chip, desc);
2232 }
2233
ingenic_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)2234 static void ingenic_gpio_set(struct gpio_chip *gc,
2235 unsigned int offset, int value)
2236 {
2237 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2238
2239 ingenic_gpio_set_value(jzgc, offset, value);
2240 }
2241
ingenic_gpio_get(struct gpio_chip * gc,unsigned int offset)2242 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
2243 {
2244 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2245
2246 return (int) ingenic_gpio_get_value(jzgc, offset);
2247 }
2248
ingenic_gpio_direction_input(struct gpio_chip * gc,unsigned int offset)2249 static int ingenic_gpio_direction_input(struct gpio_chip *gc,
2250 unsigned int offset)
2251 {
2252 return pinctrl_gpio_direction_input(gc->base + offset);
2253 }
2254
ingenic_gpio_direction_output(struct gpio_chip * gc,unsigned int offset,int value)2255 static int ingenic_gpio_direction_output(struct gpio_chip *gc,
2256 unsigned int offset, int value)
2257 {
2258 ingenic_gpio_set(gc, offset, value);
2259 return pinctrl_gpio_direction_output(gc->base + offset);
2260 }
2261
ingenic_config_pin(struct ingenic_pinctrl * jzpc,unsigned int pin,u8 reg,bool set)2262 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
2263 unsigned int pin, u8 reg, bool set)
2264 {
2265 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2266 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2267
2268 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2269 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
2270 }
2271
ingenic_shadow_config_pin(struct ingenic_pinctrl * jzpc,unsigned int pin,u8 reg,bool set)2272 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,
2273 unsigned int pin, u8 reg, bool set)
2274 {
2275 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2276
2277 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +
2278 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
2279 }
2280
ingenic_shadow_config_pin_load(struct ingenic_pinctrl * jzpc,unsigned int pin)2281 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
2282 unsigned int pin)
2283 {
2284 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),
2285 pin / PINS_PER_GPIO_CHIP);
2286 }
2287
ingenic_get_pin_config(struct ingenic_pinctrl * jzpc,unsigned int pin,u8 reg)2288 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
2289 unsigned int pin, u8 reg)
2290 {
2291 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2292 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2293 unsigned int val;
2294
2295 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);
2296
2297 return val & BIT(idx);
2298 }
2299
ingenic_gpio_get_direction(struct gpio_chip * gc,unsigned int offset)2300 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
2301 {
2302 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
2303 struct ingenic_pinctrl *jzpc = jzgc->jzpc;
2304 unsigned int pin = gc->base + offset;
2305
2306 if (jzpc->info->version >= ID_JZ4770) {
2307 if (ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_INT) ||
2308 ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1))
2309 return GPIO_LINE_DIRECTION_IN;
2310 return GPIO_LINE_DIRECTION_OUT;
2311 }
2312
2313 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
2314 return GPIO_LINE_DIRECTION_IN;
2315
2316 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR))
2317 return GPIO_LINE_DIRECTION_OUT;
2318
2319 return GPIO_LINE_DIRECTION_IN;
2320 }
2321
2322 static const struct pinctrl_ops ingenic_pctlops = {
2323 .get_groups_count = pinctrl_generic_get_group_count,
2324 .get_group_name = pinctrl_generic_get_group_name,
2325 .get_group_pins = pinctrl_generic_get_group_pins,
2326 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
2327 .dt_free_map = pinconf_generic_dt_free_map,
2328 };
2329
ingenic_gpio_irq_request(struct irq_data * data)2330 static int ingenic_gpio_irq_request(struct irq_data *data)
2331 {
2332 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
2333 int ret;
2334
2335 ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq);
2336 if (ret)
2337 return ret;
2338
2339 return gpiochip_reqres_irq(gpio_chip, data->hwirq);
2340 }
2341
ingenic_gpio_irq_release(struct irq_data * data)2342 static void ingenic_gpio_irq_release(struct irq_data *data)
2343 {
2344 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
2345
2346 return gpiochip_relres_irq(gpio_chip, data->hwirq);
2347 }
2348
ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl * jzpc,int pin,int func)2349 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
2350 int pin, int func)
2351 {
2352 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2353 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2354
2355 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
2356 'A' + offt, idx, func);
2357
2358 if (jzpc->info->version >= ID_X1000) {
2359 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
2360 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
2361 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
2362 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);
2363 ingenic_shadow_config_pin_load(jzpc, pin);
2364 } else if (jzpc->info->version >= ID_JZ4770) {
2365 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
2366 ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
2367 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2);
2368 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1);
2369 } else {
2370 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
2371 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
2372 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1);
2373 }
2374
2375 return 0;
2376 }
2377
ingenic_pinmux_set_mux(struct pinctrl_dev * pctldev,unsigned int selector,unsigned int group)2378 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
2379 unsigned int selector, unsigned int group)
2380 {
2381 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2382 struct function_desc *func;
2383 struct group_desc *grp;
2384 unsigned int i;
2385
2386 func = pinmux_generic_get_function(pctldev, selector);
2387 if (!func)
2388 return -EINVAL;
2389
2390 grp = pinctrl_generic_get_group(pctldev, group);
2391 if (!grp)
2392 return -EINVAL;
2393
2394 dev_dbg(pctldev->dev, "enable function %s group %s\n",
2395 func->name, grp->name);
2396
2397 for (i = 0; i < grp->num_pins; i++) {
2398 int *pin_modes = grp->data;
2399
2400 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
2401 }
2402
2403 return 0;
2404 }
2405
ingenic_pinmux_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int pin,bool input)2406 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
2407 struct pinctrl_gpio_range *range,
2408 unsigned int pin, bool input)
2409 {
2410 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2411 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2412 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2413
2414 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
2415 'A' + offt, idx, input ? "in" : "out");
2416
2417 if (jzpc->info->version >= ID_X1000) {
2418 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
2419 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
2420 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
2421 ingenic_shadow_config_pin_load(jzpc, pin);
2422 } else if (jzpc->info->version >= ID_JZ4770) {
2423 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false);
2424 ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
2425 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input);
2426 } else {
2427 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
2428 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
2429 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
2430 }
2431
2432 return 0;
2433 }
2434
2435 static const struct pinmux_ops ingenic_pmxops = {
2436 .get_functions_count = pinmux_generic_get_function_count,
2437 .get_function_name = pinmux_generic_get_function_name,
2438 .get_function_groups = pinmux_generic_get_function_groups,
2439 .set_mux = ingenic_pinmux_set_mux,
2440 .gpio_set_direction = ingenic_pinmux_gpio_set_direction,
2441 };
2442
ingenic_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)2443 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
2444 unsigned int pin, unsigned long *config)
2445 {
2446 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2447 enum pin_config_param param = pinconf_to_config_param(*config);
2448 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2449 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2450 bool pull;
2451
2452 if (jzpc->info->version >= ID_JZ4770)
2453 pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN);
2454 else
2455 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
2456
2457 switch (param) {
2458 case PIN_CONFIG_BIAS_DISABLE:
2459 if (pull)
2460 return -EINVAL;
2461 break;
2462
2463 case PIN_CONFIG_BIAS_PULL_UP:
2464 if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx)))
2465 return -EINVAL;
2466 break;
2467
2468 case PIN_CONFIG_BIAS_PULL_DOWN:
2469 if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx)))
2470 return -EINVAL;
2471 break;
2472
2473 default:
2474 return -ENOTSUPP;
2475 }
2476
2477 *config = pinconf_to_config_packed(param, 1);
2478 return 0;
2479 }
2480
ingenic_set_bias(struct ingenic_pinctrl * jzpc,unsigned int pin,unsigned int bias)2481 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
2482 unsigned int pin, unsigned int bias)
2483 {
2484 if (jzpc->info->version >= ID_X1830) {
2485 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2486 unsigned int half = PINS_PER_GPIO_CHIP / 2;
2487 unsigned int idxh = pin % half * 2;
2488 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2489
2490 if (idx < half) {
2491 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2492 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh);
2493 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2494 REG_SET(X1830_GPIO_PEL), bias << idxh);
2495 } else {
2496 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2497 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh);
2498 regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
2499 REG_SET(X1830_GPIO_PEH), bias << idxh);
2500 }
2501
2502 } else if (jzpc->info->version >= ID_JZ4770) {
2503 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !bias);
2504 } else {
2505 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias);
2506 }
2507 }
2508
ingenic_set_output_level(struct ingenic_pinctrl * jzpc,unsigned int pin,bool high)2509 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
2510 unsigned int pin, bool high)
2511 {
2512 if (jzpc->info->version >= ID_JZ4770)
2513 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, high);
2514 else
2515 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);
2516 }
2517
ingenic_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)2518 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2519 unsigned long *configs, unsigned int num_configs)
2520 {
2521 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
2522 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
2523 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
2524 unsigned int cfg, arg;
2525 int ret;
2526
2527 for (cfg = 0; cfg < num_configs; cfg++) {
2528 switch (pinconf_to_config_param(configs[cfg])) {
2529 case PIN_CONFIG_BIAS_DISABLE:
2530 case PIN_CONFIG_BIAS_PULL_UP:
2531 case PIN_CONFIG_BIAS_PULL_DOWN:
2532 case PIN_CONFIG_OUTPUT:
2533 continue;
2534 default:
2535 return -ENOTSUPP;
2536 }
2537 }
2538
2539 for (cfg = 0; cfg < num_configs; cfg++) {
2540 arg = pinconf_to_config_argument(configs[cfg]);
2541
2542 switch (pinconf_to_config_param(configs[cfg])) {
2543 case PIN_CONFIG_BIAS_DISABLE:
2544 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
2545 'A' + offt, idx);
2546 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS);
2547 break;
2548
2549 case PIN_CONFIG_BIAS_PULL_UP:
2550 if (!(jzpc->info->pull_ups[offt] & BIT(idx)))
2551 return -EINVAL;
2552 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
2553 'A' + offt, idx);
2554 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP);
2555 break;
2556
2557 case PIN_CONFIG_BIAS_PULL_DOWN:
2558 if (!(jzpc->info->pull_downs[offt] & BIT(idx)))
2559 return -EINVAL;
2560 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
2561 'A' + offt, idx);
2562 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN);
2563 break;
2564
2565 case PIN_CONFIG_OUTPUT:
2566 ret = pinctrl_gpio_direction_output(pin);
2567 if (ret)
2568 return ret;
2569
2570 ingenic_set_output_level(jzpc, pin, arg);
2571 break;
2572
2573 default:
2574 /* unreachable */
2575 break;
2576 }
2577 }
2578
2579 return 0;
2580 }
2581
ingenic_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)2582 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
2583 unsigned int group, unsigned long *config)
2584 {
2585 const unsigned int *pins;
2586 unsigned int i, npins, old = 0;
2587 int ret;
2588
2589 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
2590 if (ret)
2591 return ret;
2592
2593 for (i = 0; i < npins; i++) {
2594 if (ingenic_pinconf_get(pctldev, pins[i], config))
2595 return -ENOTSUPP;
2596
2597 /* configs do not match between two pins */
2598 if (i && (old != *config))
2599 return -ENOTSUPP;
2600
2601 old = *config;
2602 }
2603
2604 return 0;
2605 }
2606
ingenic_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * configs,unsigned int num_configs)2607 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
2608 unsigned int group, unsigned long *configs,
2609 unsigned int num_configs)
2610 {
2611 const unsigned int *pins;
2612 unsigned int i, npins;
2613 int ret;
2614
2615 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
2616 if (ret)
2617 return ret;
2618
2619 for (i = 0; i < npins; i++) {
2620 ret = ingenic_pinconf_set(pctldev,
2621 pins[i], configs, num_configs);
2622 if (ret)
2623 return ret;
2624 }
2625
2626 return 0;
2627 }
2628
2629 static const struct pinconf_ops ingenic_confops = {
2630 .is_generic = true,
2631 .pin_config_get = ingenic_pinconf_get,
2632 .pin_config_set = ingenic_pinconf_set,
2633 .pin_config_group_get = ingenic_pinconf_group_get,
2634 .pin_config_group_set = ingenic_pinconf_group_set,
2635 };
2636
2637 static const struct regmap_config ingenic_pinctrl_regmap_config = {
2638 .reg_bits = 32,
2639 .val_bits = 32,
2640 .reg_stride = 4,
2641 };
2642
2643 static const struct of_device_id ingenic_gpio_of_match[] __initconst = {
2644 { .compatible = "ingenic,jz4740-gpio", },
2645 { .compatible = "ingenic,jz4725b-gpio", },
2646 { .compatible = "ingenic,jz4760-gpio", },
2647 { .compatible = "ingenic,jz4770-gpio", },
2648 { .compatible = "ingenic,jz4780-gpio", },
2649 { .compatible = "ingenic,x1000-gpio", },
2650 { .compatible = "ingenic,x1830-gpio", },
2651 {},
2652 };
2653
ingenic_gpio_probe(struct ingenic_pinctrl * jzpc,struct device_node * node)2654 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
2655 struct device_node *node)
2656 {
2657 struct ingenic_gpio_chip *jzgc;
2658 struct device *dev = jzpc->dev;
2659 struct gpio_irq_chip *girq;
2660 unsigned int bank;
2661 int err;
2662
2663 err = of_property_read_u32(node, "reg", &bank);
2664 if (err) {
2665 dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
2666 return err;
2667 }
2668
2669 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
2670 if (!jzgc)
2671 return -ENOMEM;
2672
2673 jzgc->jzpc = jzpc;
2674 jzgc->reg_base = bank * jzpc->info->reg_offset;
2675
2676 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
2677 if (!jzgc->gc.label)
2678 return -ENOMEM;
2679
2680 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
2681 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
2682 * <linux/gpio/consumer.h> INSTEAD.
2683 */
2684 jzgc->gc.base = bank * 32;
2685
2686 jzgc->gc.ngpio = 32;
2687 jzgc->gc.parent = dev;
2688 jzgc->gc.of_node = node;
2689 jzgc->gc.owner = THIS_MODULE;
2690
2691 jzgc->gc.set = ingenic_gpio_set;
2692 jzgc->gc.get = ingenic_gpio_get;
2693 jzgc->gc.direction_input = ingenic_gpio_direction_input;
2694 jzgc->gc.direction_output = ingenic_gpio_direction_output;
2695 jzgc->gc.get_direction = ingenic_gpio_get_direction;
2696 jzgc->gc.request = gpiochip_generic_request;
2697 jzgc->gc.free = gpiochip_generic_free;
2698
2699 jzgc->irq = irq_of_parse_and_map(node, 0);
2700 if (!jzgc->irq)
2701 return -EINVAL;
2702
2703 jzgc->irq_chip.name = jzgc->gc.label;
2704 jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable;
2705 jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable;
2706 jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask;
2707 jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask;
2708 jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack;
2709 jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type;
2710 jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;
2711 jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request;
2712 jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release;
2713 jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
2714
2715 girq = &jzgc->gc.irq;
2716 girq->chip = &jzgc->irq_chip;
2717 girq->parent_handler = ingenic_gpio_irq_handler;
2718 girq->num_parents = 1;
2719 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
2720 GFP_KERNEL);
2721 if (!girq->parents)
2722 return -ENOMEM;
2723 girq->parents[0] = jzgc->irq;
2724 girq->default_type = IRQ_TYPE_NONE;
2725 girq->handler = handle_level_irq;
2726
2727 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
2728 if (err)
2729 return err;
2730
2731 return 0;
2732 }
2733
ingenic_pinctrl_probe(struct platform_device * pdev)2734 static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
2735 {
2736 struct device *dev = &pdev->dev;
2737 struct ingenic_pinctrl *jzpc;
2738 struct pinctrl_desc *pctl_desc;
2739 void __iomem *base;
2740 const struct ingenic_chip_info *chip_info;
2741 struct device_node *node;
2742 unsigned int i;
2743 int err;
2744
2745 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
2746 if (!jzpc)
2747 return -ENOMEM;
2748
2749 base = devm_platform_ioremap_resource(pdev, 0);
2750 if (IS_ERR(base))
2751 return PTR_ERR(base);
2752
2753 jzpc->map = devm_regmap_init_mmio(dev, base,
2754 &ingenic_pinctrl_regmap_config);
2755 if (IS_ERR(jzpc->map)) {
2756 dev_err(dev, "Failed to create regmap\n");
2757 return PTR_ERR(jzpc->map);
2758 }
2759
2760 jzpc->dev = dev;
2761 jzpc->info = chip_info = of_device_get_match_data(dev);
2762
2763 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
2764 if (!pctl_desc)
2765 return -ENOMEM;
2766
2767 /* fill in pinctrl_desc structure */
2768 pctl_desc->name = dev_name(dev);
2769 pctl_desc->owner = THIS_MODULE;
2770 pctl_desc->pctlops = &ingenic_pctlops;
2771 pctl_desc->pmxops = &ingenic_pmxops;
2772 pctl_desc->confops = &ingenic_confops;
2773 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;
2774 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,
2775 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);
2776 if (!jzpc->pdesc)
2777 return -ENOMEM;
2778
2779 for (i = 0; i < pctl_desc->npins; i++) {
2780 jzpc->pdesc[i].number = i;
2781 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
2782 'A' + (i / PINS_PER_GPIO_CHIP),
2783 i % PINS_PER_GPIO_CHIP);
2784 }
2785
2786 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);
2787 if (IS_ERR(jzpc->pctl)) {
2788 dev_err(dev, "Failed to register pinctrl\n");
2789 return PTR_ERR(jzpc->pctl);
2790 }
2791
2792 for (i = 0; i < chip_info->num_groups; i++) {
2793 const struct group_desc *group = &chip_info->groups[i];
2794
2795 err = pinctrl_generic_add_group(jzpc->pctl, group->name,
2796 group->pins, group->num_pins, group->data);
2797 if (err < 0) {
2798 dev_err(dev, "Failed to register group %s\n",
2799 group->name);
2800 return err;
2801 }
2802 }
2803
2804 for (i = 0; i < chip_info->num_functions; i++) {
2805 const struct function_desc *func = &chip_info->functions[i];
2806
2807 err = pinmux_generic_add_function(jzpc->pctl, func->name,
2808 func->group_names, func->num_group_names,
2809 func->data);
2810 if (err < 0) {
2811 dev_err(dev, "Failed to register function %s\n",
2812 func->name);
2813 return err;
2814 }
2815 }
2816
2817 dev_set_drvdata(dev, jzpc->map);
2818
2819 for_each_child_of_node(dev->of_node, node) {
2820 if (of_match_node(ingenic_gpio_of_match, node)) {
2821 err = ingenic_gpio_probe(jzpc, node);
2822 if (err)
2823 return err;
2824 }
2825 }
2826
2827 return 0;
2828 }
2829
2830 #define IF_ENABLED(cfg, ptr) PTR_IF(IS_ENABLED(cfg), (ptr))
2831
2832 static const struct of_device_id ingenic_pinctrl_of_match[] = {
2833 { .compatible = "ingenic,jz4740-pinctrl", .data = &jz4740_chip_info },
2834 { .compatible = "ingenic,jz4725b-pinctrl", .data = &jz4725b_chip_info },
2835 { .compatible = "ingenic,jz4760-pinctrl", .data = &jz4760_chip_info },
2836 { .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760_chip_info },
2837 { .compatible = "ingenic,jz4770-pinctrl", .data = &jz4770_chip_info },
2838 { .compatible = "ingenic,jz4780-pinctrl", .data = &jz4780_chip_info },
2839 { .compatible = "ingenic,x1000-pinctrl", .data = &x1000_chip_info },
2840 { .compatible = "ingenic,x1000e-pinctrl", .data = &x1000_chip_info },
2841 { .compatible = "ingenic,x1500-pinctrl", .data = &x1500_chip_info },
2842 { .compatible = "ingenic,x1830-pinctrl", .data = &x1830_chip_info },
2843 {},
2844 };
2845
2846 static struct platform_driver ingenic_pinctrl_driver = {
2847 .driver = {
2848 .name = "pinctrl-ingenic",
2849 .of_match_table = ingenic_pinctrl_of_match,
2850 },
2851 };
2852
ingenic_pinctrl_drv_register(void)2853 static int __init ingenic_pinctrl_drv_register(void)
2854 {
2855 return platform_driver_probe(&ingenic_pinctrl_driver,
2856 ingenic_pinctrl_probe);
2857 }
2858 subsys_initcall(ingenic_pinctrl_drv_register);
2859