1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #ifndef __HCLGE_CMD_H
5 #define __HCLGE_CMD_H
6 #include <linux/types.h>
7 #include <linux/io.h>
8 #include <linux/etherdevice.h>
9 #include "hnae3.h"
10
11 #define HCLGE_CMDQ_TX_TIMEOUT 30000
12 #define HCLGE_CMDQ_CLEAR_WAIT_TIME 200
13 #define HCLGE_DESC_DATA_LEN 6
14
15 struct hclge_dev;
16 struct hclge_desc {
17 __le16 opcode;
18
19 #define HCLGE_CMDQ_RX_INVLD_B 0
20 #define HCLGE_CMDQ_RX_OUTVLD_B 1
21
22 __le16 flag;
23 __le16 retval;
24 __le16 rsv;
25 __le32 data[HCLGE_DESC_DATA_LEN];
26 };
27
28 struct hclge_cmq_ring {
29 dma_addr_t desc_dma_addr;
30 struct hclge_desc *desc;
31 struct hclge_dev *dev;
32 u32 head;
33 u32 tail;
34
35 u16 buf_size;
36 u16 desc_num;
37 int next_to_use;
38 int next_to_clean;
39 u8 ring_type; /* cmq ring type */
40 spinlock_t lock; /* Command queue lock */
41 };
42
43 enum hclge_cmd_return_status {
44 HCLGE_CMD_EXEC_SUCCESS = 0,
45 HCLGE_CMD_NO_AUTH = 1,
46 HCLGE_CMD_NOT_SUPPORTED = 2,
47 HCLGE_CMD_QUEUE_FULL = 3,
48 HCLGE_CMD_NEXT_ERR = 4,
49 HCLGE_CMD_UNEXE_ERR = 5,
50 HCLGE_CMD_PARA_ERR = 6,
51 HCLGE_CMD_RESULT_ERR = 7,
52 HCLGE_CMD_TIMEOUT = 8,
53 HCLGE_CMD_HILINK_ERR = 9,
54 HCLGE_CMD_QUEUE_ILLEGAL = 10,
55 HCLGE_CMD_INVALID = 11,
56 };
57
58 enum hclge_cmd_status {
59 HCLGE_STATUS_SUCCESS = 0,
60 HCLGE_ERR_CSQ_FULL = -1,
61 HCLGE_ERR_CSQ_TIMEOUT = -2,
62 HCLGE_ERR_CSQ_ERROR = -3,
63 };
64
65 struct hclge_misc_vector {
66 u8 __iomem *addr;
67 int vector_irq;
68 char name[HNAE3_INT_NAME_LEN];
69 };
70
71 struct hclge_cmq {
72 struct hclge_cmq_ring csq;
73 struct hclge_cmq_ring crq;
74 u16 tx_timeout;
75 enum hclge_cmd_status last_status;
76 };
77
78 #define HCLGE_CMD_FLAG_IN BIT(0)
79 #define HCLGE_CMD_FLAG_OUT BIT(1)
80 #define HCLGE_CMD_FLAG_NEXT BIT(2)
81 #define HCLGE_CMD_FLAG_WR BIT(3)
82 #define HCLGE_CMD_FLAG_NO_INTR BIT(4)
83 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
84
85 enum hclge_opcode_type {
86 /* Generic commands */
87 HCLGE_OPC_QUERY_FW_VER = 0x0001,
88 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020,
89 HCLGE_OPC_GBL_RST_STATUS = 0x0021,
90 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022,
91 HCLGE_OPC_QUERY_PF_RSRC = 0x0023,
92 HCLGE_OPC_QUERY_VF_RSRC = 0x0024,
93 HCLGE_OPC_GET_CFG_PARAM = 0x0025,
94 HCLGE_OPC_PF_RST_DONE = 0x0026,
95 HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027,
96
97 HCLGE_OPC_STATS_64_BIT = 0x0030,
98 HCLGE_OPC_STATS_32_BIT = 0x0031,
99 HCLGE_OPC_STATS_MAC = 0x0032,
100 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033,
101 HCLGE_OPC_STATS_MAC_ALL = 0x0034,
102
103 HCLGE_OPC_QUERY_REG_NUM = 0x0040,
104 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041,
105 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042,
106 HCLGE_OPC_DFX_BD_NUM = 0x0043,
107 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044,
108 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045,
109 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046,
110 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047,
111 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048,
112 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049,
113 HCLGE_OPC_DFX_NCSI_REG = 0x004A,
114 HCLGE_OPC_DFX_RTC_REG = 0x004B,
115 HCLGE_OPC_DFX_PPP_REG = 0x004C,
116 HCLGE_OPC_DFX_RCB_REG = 0x004D,
117 HCLGE_OPC_DFX_TQP_REG = 0x004E,
118 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F,
119
120 HCLGE_OPC_QUERY_DEV_SPECS = 0x0050,
121
122 /* MAC command */
123 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301,
124 HCLGE_OPC_CONFIG_AN_MODE = 0x0304,
125 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307,
126 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
127 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309,
128 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310,
129 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311,
130 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312,
131 HCLGE_OPC_SERDES_LOOPBACK = 0x0315,
132 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A,
133
134 /* PFC/Pause commands */
135 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701,
136 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702,
137 HCLGE_OPC_CFG_MAC_PARA = 0x0703,
138 HCLGE_OPC_CFG_PFC_PARA = 0x0704,
139 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
140 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
141 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
142 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
143 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709,
144 HCLGE_OPC_QOS_MAP = 0x070A,
145
146 /* ETS/scheduler commands */
147 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804,
148 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805,
149 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806,
150 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807,
151 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808,
152 HCLGE_OPC_TM_PG_WEIGHT = 0x0809,
153 HCLGE_OPC_TM_QS_WEIGHT = 0x080A,
154 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B,
155 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C,
156 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D,
157 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E,
158 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F,
159 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810,
160 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
161 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
162 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
163 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
164 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843,
165 HCLGE_OPC_QSET_DFX_STS = 0x0844,
166 HCLGE_OPC_PRI_DFX_STS = 0x0845,
167 HCLGE_OPC_PG_DFX_STS = 0x0846,
168 HCLGE_OPC_PORT_DFX_STS = 0x0847,
169 HCLGE_OPC_SCH_NQ_CNT = 0x0848,
170 HCLGE_OPC_SCH_RQ_CNT = 0x0849,
171 HCLGE_OPC_TM_INTERNAL_STS = 0x0850,
172 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851,
173 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852,
174
175 /* Packet buffer allocate commands */
176 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901,
177 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
178 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903,
179 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904,
180 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905,
181 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906,
182
183 /* TQP management command */
184 HCLGE_OPC_SET_TQP_MAP = 0x0A01,
185
186 /* TQP commands */
187 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01,
188 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02,
189 HCLGE_OPC_QUERY_TX_STATS = 0x0B03,
190 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04,
191 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11,
192 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12,
193 HCLGE_OPC_QUERY_RX_STATS = 0x0B13,
194 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16,
195 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17,
196 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
197 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22,
198
199 /* PPU commands */
200 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A,
201
202 /* TSO command */
203 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01,
204 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10,
205
206 /* RSS commands */
207 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01,
208 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07,
209 HCLGE_OPC_RSS_TC_MODE = 0x0D08,
210 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02,
211
212 /* Promisuous mode command */
213 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01,
214
215 /* Vlan offload commands */
216 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01,
217 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02,
218
219 /* Interrupts commands */
220 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503,
221 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504,
222
223 /* MAC commands */
224 HCLGE_OPC_MAC_VLAN_ADD = 0x1000,
225 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001,
226 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002,
227 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003,
228 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004,
229 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010,
230 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011,
231
232 /* MAC VLAN commands */
233 HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,
234
235 /* VLAN commands */
236 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100,
237 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101,
238 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102,
239
240 /* Flow Director commands */
241 HCLGE_OPC_FD_MODE_CTRL = 0x1200,
242 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201,
243 HCLGE_OPC_FD_KEY_CONFIG = 0x1202,
244 HCLGE_OPC_FD_TCAM_OP = 0x1203,
245 HCLGE_OPC_FD_AD_OP = 0x1204,
246
247 /* MDIO command */
248 HCLGE_OPC_MDIO_CONFIG = 0x1900,
249
250 /* QCN commands */
251 HCLGE_OPC_QCN_MOD_CFG = 0x1A01,
252 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02,
253 HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03,
254 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04,
255 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05,
256 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06,
257 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07,
258 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08,
259
260 /* Mailbox command */
261 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000,
262
263 /* Led command */
264 HCLGE_OPC_LED_STATUS_CFG = 0xB000,
265
266 /* clear hardware resource command */
267 HCLGE_OPC_CLEAR_HW_RESOURCE = 0x700B,
268
269 /* NCL config command */
270 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011,
271
272 /* M7 stats command */
273 HCLGE_OPC_M7_STATS_BD = 0x7012,
274 HCLGE_OPC_M7_STATS_INFO = 0x7013,
275 HCLGE_OPC_M7_COMPAT_CFG = 0x701A,
276
277 /* SFP command */
278 HCLGE_OPC_GET_SFP_EEPROM = 0x7100,
279 HCLGE_OPC_GET_SFP_EXIST = 0x7101,
280 HCLGE_OPC_GET_SFP_INFO = 0x7104,
281
282 /* Error INT commands */
283 HCLGE_MAC_COMMON_INT_EN = 0x030E,
284 HCLGE_TM_SCH_ECC_INT_EN = 0x0829,
285 HCLGE_SSU_ECC_INT_CMD = 0x0989,
286 HCLGE_SSU_COMMON_INT_CMD = 0x098C,
287 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40,
288 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41,
289 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42,
290 HCLGE_COMMON_ECC_INT_CFG = 0x1505,
291 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
292 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
293 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512,
294 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
295 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
296 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
297 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580,
298 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
299 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584,
300 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585,
301 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586,
302 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803,
303 HCLGE_IGU_COMMON_INT_EN = 0x1806,
304 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14,
305 HCLGE_PPP_CMD0_INT_CMD = 0x2100,
306 HCLGE_PPP_CMD1_INT_CMD = 0x2101,
307 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105,
308 HCLGE_NCSI_INT_EN = 0x2401,
309 };
310
311 #define HCLGE_TQP_REG_OFFSET 0x80000
312 #define HCLGE_TQP_REG_SIZE 0x200
313
314 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10
315 #define HCLGE_RCB_INIT_FLAG_EN_B 0
316 #define HCLGE_RCB_INIT_FLAG_FINI_B 8
317 struct hclge_config_rcb_init_cmd {
318 __le16 rcb_init_flag;
319 u8 rsv[22];
320 };
321
322 struct hclge_tqp_map_cmd {
323 __le16 tqp_id; /* Absolute tqp id for in this pf */
324 u8 tqp_vf; /* VF id */
325 #define HCLGE_TQP_MAP_TYPE_PF 0
326 #define HCLGE_TQP_MAP_TYPE_VF 1
327 #define HCLGE_TQP_MAP_TYPE_B 0
328 #define HCLGE_TQP_MAP_EN_B 1
329 u8 tqp_flag; /* Indicate it's pf or vf tqp */
330 __le16 tqp_vid; /* Virtual id in this pf/vf */
331 u8 rsv[18];
332 };
333
334 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10
335
336 enum hclge_int_type {
337 HCLGE_INT_TX,
338 HCLGE_INT_RX,
339 HCLGE_INT_EVENT,
340 };
341
342 struct hclge_ctrl_vector_chain_cmd {
343 u8 int_vector_id;
344 u8 int_cause_num;
345 #define HCLGE_INT_TYPE_S 0
346 #define HCLGE_INT_TYPE_M GENMASK(1, 0)
347 #define HCLGE_TQP_ID_S 2
348 #define HCLGE_TQP_ID_M GENMASK(12, 2)
349 #define HCLGE_INT_GL_IDX_S 13
350 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13)
351 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
352 u8 vfid;
353 u8 rsv;
354 };
355
356 #define HCLGE_MAX_TC_NUM 8
357 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
358 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
359 struct hclge_tx_buff_alloc_cmd {
360 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];
361 u8 tx_buff_rsv[8];
362 };
363
364 struct hclge_rx_priv_buff_cmd {
365 __le16 buf_num[HCLGE_MAX_TC_NUM];
366 __le16 shared_buf;
367 u8 rsv[6];
368 };
369
370 enum HCLGE_CAP_BITS {
371 HCLGE_CAP_UDP_GSO_B,
372 HCLGE_CAP_QB_B,
373 HCLGE_CAP_FD_FORWARD_TC_B,
374 HCLGE_CAP_PTP_B,
375 HCLGE_CAP_INT_QL_B,
376 HCLGE_CAP_SIMPLE_BD_B,
377 HCLGE_CAP_TX_PUSH_B,
378 HCLGE_CAP_PHY_IMP_B,
379 HCLGE_CAP_TQP_TXRX_INDEP_B,
380 HCLGE_CAP_HW_PAD_B,
381 HCLGE_CAP_STASH_B,
382 };
383
384 #define HCLGE_QUERY_CAP_LENGTH 3
385 struct hclge_query_version_cmd {
386 __le32 firmware;
387 __le32 hardware;
388 __le32 rsv;
389 __le32 caps[HCLGE_QUERY_CAP_LENGTH]; /* capabilities of device */
390 };
391
392 #define HCLGE_RX_PRIV_EN_B 15
393 #define HCLGE_TC_NUM_ONE_DESC 4
394 struct hclge_priv_wl {
395 __le16 high;
396 __le16 low;
397 };
398
399 struct hclge_rx_priv_wl_buf {
400 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
401 };
402
403 struct hclge_rx_com_thrd {
404 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
405 };
406
407 struct hclge_rx_com_wl {
408 struct hclge_priv_wl com_wl;
409 };
410
411 struct hclge_waterline {
412 u32 low;
413 u32 high;
414 };
415
416 struct hclge_tc_thrd {
417 u32 low;
418 u32 high;
419 };
420
421 struct hclge_priv_buf {
422 struct hclge_waterline wl; /* Waterline for low and high*/
423 u32 buf_size; /* TC private buffer size */
424 u32 tx_buf_size;
425 u32 enable; /* Enable TC private buffer or not */
426 };
427
428 struct hclge_shared_buf {
429 struct hclge_waterline self;
430 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
431 u32 buf_size;
432 };
433
434 struct hclge_pkt_buf_alloc {
435 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
436 struct hclge_shared_buf s_buf;
437 };
438
439 #define HCLGE_RX_COM_WL_EN_B 15
440 struct hclge_rx_com_wl_buf_cmd {
441 __le16 high_wl;
442 __le16 low_wl;
443 u8 rsv[20];
444 };
445
446 #define HCLGE_RX_PKT_EN_B 15
447 struct hclge_rx_pkt_buf_cmd {
448 __le16 high_pkt;
449 __le16 low_pkt;
450 u8 rsv[20];
451 };
452
453 #define HCLGE_PF_STATE_DONE_B 0
454 #define HCLGE_PF_STATE_MAIN_B 1
455 #define HCLGE_PF_STATE_BOND_B 2
456 #define HCLGE_PF_STATE_MAC_N_B 6
457 #define HCLGE_PF_MAC_NUM_MASK 0x3
458 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B)
459 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B)
460 #define HCLGE_VF_RST_STATUS_CMD 4
461
462 struct hclge_func_status_cmd {
463 __le32 vf_rst_state[HCLGE_VF_RST_STATUS_CMD];
464 u8 pf_state;
465 u8 mac_id;
466 u8 rsv1;
467 u8 pf_cnt_in_mac;
468 u8 pf_num;
469 u8 vf_num;
470 u8 rsv[2];
471 };
472
473 struct hclge_pf_res_cmd {
474 __le16 tqp_num;
475 __le16 buf_size;
476 __le16 msixcap_localid_ba_nic;
477 __le16 msixcap_localid_ba_rocee;
478 #define HCLGE_MSIX_OFT_ROCEE_S 0
479 #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0)
480 #define HCLGE_PF_VEC_NUM_S 0
481 #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0)
482 __le16 pf_intr_vector_number;
483 __le16 pf_own_fun_number;
484 __le16 tx_buf_size;
485 __le16 dv_buf_size;
486 __le32 rsv[2];
487 };
488
489 #define HCLGE_CFG_OFFSET_S 0
490 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0)
491 #define HCLGE_CFG_RD_LEN_S 24
492 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24)
493 #define HCLGE_CFG_RD_LEN_BYTES 16
494 #define HCLGE_CFG_RD_LEN_UNIT 4
495
496 #define HCLGE_CFG_VMDQ_S 0
497 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0)
498 #define HCLGE_CFG_TC_NUM_S 8
499 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8)
500 #define HCLGE_CFG_TQP_DESC_N_S 16
501 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16)
502 #define HCLGE_CFG_PHY_ADDR_S 0
503 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0)
504 #define HCLGE_CFG_MEDIA_TP_S 8
505 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8)
506 #define HCLGE_CFG_RX_BUF_LEN_S 16
507 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16)
508 #define HCLGE_CFG_MAC_ADDR_H_S 0
509 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0)
510 #define HCLGE_CFG_DEFAULT_SPEED_S 16
511 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
512 #define HCLGE_CFG_RSS_SIZE_S 24
513 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24)
514 #define HCLGE_CFG_SPEED_ABILITY_S 0
515 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0)
516 #define HCLGE_CFG_SPEED_ABILITY_EXT_S 10
517 #define HCLGE_CFG_SPEED_ABILITY_EXT_M GENMASK(15, 10)
518 #define HCLGE_CFG_UMV_TBL_SPACE_S 16
519 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
520
521 #define HCLGE_CFG_CMD_CNT 4
522
523 struct hclge_cfg_param_cmd {
524 __le32 offset;
525 __le32 rsv;
526 __le32 param[HCLGE_CFG_CMD_CNT];
527 };
528
529 #define HCLGE_MAC_MODE 0x0
530 #define HCLGE_DESC_NUM 0x40
531
532 #define HCLGE_ALLOC_VALID_B 0
533 struct hclge_vf_num_cmd {
534 u8 alloc_valid;
535 u8 rsv[23];
536 };
537
538 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4
539 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4
540 #define HCLGE_RSS_HASH_KEY_NUM 16
541 struct hclge_rss_config_cmd {
542 u8 hash_config;
543 u8 rsv[7];
544 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
545 };
546
547 struct hclge_rss_input_tuple_cmd {
548 u8 ipv4_tcp_en;
549 u8 ipv4_udp_en;
550 u8 ipv4_sctp_en;
551 u8 ipv4_fragment_en;
552 u8 ipv6_tcp_en;
553 u8 ipv6_udp_en;
554 u8 ipv6_sctp_en;
555 u8 ipv6_fragment_en;
556 u8 rsv[16];
557 };
558
559 #define HCLGE_RSS_CFG_TBL_SIZE 16
560
561 struct hclge_rss_indirection_table_cmd {
562 __le16 start_table_index;
563 __le16 rss_set_bitmap;
564 u8 rsv[4];
565 u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE];
566 };
567
568 #define HCLGE_RSS_TC_OFFSET_S 0
569 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0)
570 #define HCLGE_RSS_TC_SIZE_S 12
571 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12)
572 #define HCLGE_RSS_TC_VALID_B 15
573 struct hclge_rss_tc_mode_cmd {
574 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
575 u8 rsv[8];
576 };
577
578 #define HCLGE_LINK_STATUS_UP_B 0
579 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B)
580 struct hclge_link_status_cmd {
581 u8 status;
582 u8 rsv[23];
583 };
584
585 struct hclge_promisc_param {
586 u8 vf_id;
587 u8 enable;
588 };
589
590 #define HCLGE_PROMISC_TX_EN_B BIT(4)
591 #define HCLGE_PROMISC_RX_EN_B BIT(5)
592 #define HCLGE_PROMISC_EN_B 1
593 #define HCLGE_PROMISC_EN_ALL 0x7
594 #define HCLGE_PROMISC_EN_UC 0x1
595 #define HCLGE_PROMISC_EN_MC 0x2
596 #define HCLGE_PROMISC_EN_BC 0x4
597 struct hclge_promisc_cfg_cmd {
598 u8 flag;
599 u8 vf_id;
600 __le16 rsv0;
601 u8 rsv1[20];
602 };
603
604 enum hclge_promisc_type {
605 HCLGE_UNICAST = 1,
606 HCLGE_MULTICAST = 2,
607 HCLGE_BROADCAST = 3,
608 };
609
610 #define HCLGE_MAC_TX_EN_B 6
611 #define HCLGE_MAC_RX_EN_B 7
612 #define HCLGE_MAC_PAD_TX_B 11
613 #define HCLGE_MAC_PAD_RX_B 12
614 #define HCLGE_MAC_1588_TX_B 13
615 #define HCLGE_MAC_1588_RX_B 14
616 #define HCLGE_MAC_APP_LP_B 15
617 #define HCLGE_MAC_LINE_LP_B 16
618 #define HCLGE_MAC_FCS_TX_B 17
619 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18
620 #define HCLGE_MAC_RX_FCS_STRIP_B 19
621 #define HCLGE_MAC_RX_FCS_B 20
622 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21
623 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22
624
625 struct hclge_config_mac_mode_cmd {
626 __le32 txrx_pad_fcs_loop_en;
627 u8 rsv[20];
628 };
629
630 struct hclge_pf_rst_sync_cmd {
631 #define HCLGE_PF_RST_ALL_VF_RDY_B 0
632 u8 all_vf_ready;
633 u8 rsv[23];
634 };
635
636 #define HCLGE_CFG_SPEED_S 0
637 #define HCLGE_CFG_SPEED_M GENMASK(5, 0)
638
639 #define HCLGE_CFG_DUPLEX_B 7
640 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B)
641
642 struct hclge_config_mac_speed_dup_cmd {
643 u8 speed_dup;
644
645 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
646 u8 mac_change_fec_en;
647 u8 rsv[22];
648 };
649
650 #define HCLGE_RING_ID_MASK GENMASK(9, 0)
651 #define HCLGE_TQP_ENABLE_B 0
652
653 #define HCLGE_MAC_CFG_AN_EN_B 0
654 #define HCLGE_MAC_CFG_AN_INT_EN_B 1
655 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2
656 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3
657 #define HCLGE_MAC_CFG_AN_RST_B 4
658
659 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B)
660
661 struct hclge_config_auto_neg_cmd {
662 __le32 cfg_an_cmd_flag;
663 u8 rsv[20];
664 };
665
666 struct hclge_sfp_info_cmd {
667 __le32 speed;
668 u8 query_type; /* 0: sfp speed, 1: active speed */
669 u8 active_fec;
670 u8 autoneg; /* autoneg state */
671 u8 autoneg_ability; /* whether support autoneg */
672 __le32 speed_ability; /* speed ability for current media */
673 __le32 module_type;
674 u8 rsv[8];
675 };
676
677 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0
678 #define HCLGE_MAC_CFG_FEC_MODE_S 1
679 #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1)
680 #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0
681 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1
682
683 #define HCLGE_MAC_FEC_OFF 0
684 #define HCLGE_MAC_FEC_BASER 1
685 #define HCLGE_MAC_FEC_RS 2
686 struct hclge_config_fec_cmd {
687 u8 fec_mode;
688 u8 default_config;
689 u8 rsv[22];
690 };
691
692 #define HCLGE_MAC_UPLINK_PORT 0x100
693
694 struct hclge_config_max_frm_size_cmd {
695 __le16 max_frm_size;
696 u8 min_frm_size;
697 u8 rsv[21];
698 };
699
700 enum hclge_mac_vlan_tbl_opcode {
701 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */
702 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */
703 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */
704 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */
705 };
706
707 enum hclge_mac_vlan_add_resp_code {
708 HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */
709 HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
710 };
711
712 #define HCLGE_MAC_VLAN_BIT0_EN_B 0
713 #define HCLGE_MAC_VLAN_BIT1_EN_B 1
714 #define HCLGE_MAC_EPORT_SW_EN_B 12
715 #define HCLGE_MAC_EPORT_TYPE_B 11
716 #define HCLGE_MAC_EPORT_VFID_S 3
717 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3)
718 #define HCLGE_MAC_EPORT_PFID_S 0
719 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0)
720 struct hclge_mac_vlan_tbl_entry_cmd {
721 u8 flags;
722 u8 resp_code;
723 __le16 vlan_tag;
724 __le32 mac_addr_hi32;
725 __le16 mac_addr_lo16;
726 __le16 rsv1;
727 u8 entry_type;
728 u8 mc_mac_en;
729 __le16 egress_port;
730 __le16 egress_queue;
731 u8 rsv2[6];
732 };
733
734 #define HCLGE_UMV_SPC_ALC_B 0
735 struct hclge_umv_spc_alc_cmd {
736 u8 allocate;
737 u8 rsv1[3];
738 __le32 space_size;
739 u8 rsv2[16];
740 };
741
742 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0)
743 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1)
744 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
745
746 struct hclge_mac_mgr_tbl_entry_cmd {
747 u8 flags;
748 u8 resp_code;
749 __le16 vlan_tag;
750 u8 mac_addr[ETH_ALEN];
751 __le16 rsv1;
752 __le16 ethter_type;
753 __le16 egress_port;
754 __le16 egress_queue;
755 u8 sw_port_id_aware;
756 u8 rsv2;
757 u8 i_port_bitmap;
758 u8 i_port_direction;
759 u8 rsv3[2];
760 };
761
762 struct hclge_vlan_filter_ctrl_cmd {
763 u8 vlan_type;
764 u8 vlan_fe;
765 u8 rsv1[2];
766 u8 vf_id;
767 u8 rsv2[19];
768 };
769
770 #define HCLGE_VLAN_ID_OFFSET_STEP 160
771 #define HCLGE_VLAN_BYTE_SIZE 8
772 #define HCLGE_VLAN_OFFSET_BITMAP \
773 (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE)
774
775 struct hclge_vlan_filter_pf_cfg_cmd {
776 u8 vlan_offset;
777 u8 vlan_cfg;
778 u8 rsv[2];
779 u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP];
780 };
781
782 #define HCLGE_MAX_VF_BYTES 16
783
784 struct hclge_vlan_filter_vf_cfg_cmd {
785 __le16 vlan_id;
786 u8 resp_code;
787 u8 rsv;
788 u8 vlan_cfg;
789 u8 rsv1[3];
790 u8 vf_bitmap[HCLGE_MAX_VF_BYTES];
791 };
792
793 #define HCLGE_SWITCH_ANTI_SPOOF_B 0U
794 #define HCLGE_SWITCH_ALW_LPBK_B 1U
795 #define HCLGE_SWITCH_ALW_LCL_LPBK_B 2U
796 #define HCLGE_SWITCH_ALW_DST_OVRD_B 3U
797 #define HCLGE_SWITCH_NO_MASK 0x0
798 #define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE
799 #define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD
800 #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB
801 #define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7
802
803 struct hclge_mac_vlan_switch_cmd {
804 u8 roce_sel;
805 u8 rsv1[3];
806 __le32 func_id;
807 u8 switch_param;
808 u8 rsv2[3];
809 u8 param_mask;
810 u8 rsv3[11];
811 };
812
813 enum hclge_mac_vlan_cfg_sel {
814 HCLGE_MAC_VLAN_NIC_SEL = 0,
815 HCLGE_MAC_VLAN_ROCE_SEL,
816 };
817
818 #define HCLGE_ACCEPT_TAG1_B 0
819 #define HCLGE_ACCEPT_UNTAG1_B 1
820 #define HCLGE_PORT_INS_TAG1_EN_B 2
821 #define HCLGE_PORT_INS_TAG2_EN_B 3
822 #define HCLGE_CFG_NIC_ROCE_SEL_B 4
823 #define HCLGE_ACCEPT_TAG2_B 5
824 #define HCLGE_ACCEPT_UNTAG2_B 6
825 #define HCLGE_VF_NUM_PER_BYTE 8
826
827 struct hclge_vport_vtag_tx_cfg_cmd {
828 u8 vport_vlan_cfg;
829 u8 vf_offset;
830 u8 rsv1[2];
831 __le16 def_vlan_tag1;
832 __le16 def_vlan_tag2;
833 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
834 u8 rsv2[8];
835 };
836
837 #define HCLGE_REM_TAG1_EN_B 0
838 #define HCLGE_REM_TAG2_EN_B 1
839 #define HCLGE_SHOW_TAG1_EN_B 2
840 #define HCLGE_SHOW_TAG2_EN_B 3
841 struct hclge_vport_vtag_rx_cfg_cmd {
842 u8 vport_vlan_cfg;
843 u8 vf_offset;
844 u8 rsv1[6];
845 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
846 u8 rsv2[8];
847 };
848
849 struct hclge_tx_vlan_type_cfg_cmd {
850 __le16 ot_vlan_type;
851 __le16 in_vlan_type;
852 u8 rsv[20];
853 };
854
855 struct hclge_rx_vlan_type_cfg_cmd {
856 __le16 ot_fst_vlan_type;
857 __le16 ot_sec_vlan_type;
858 __le16 in_fst_vlan_type;
859 __le16 in_sec_vlan_type;
860 u8 rsv[16];
861 };
862
863 struct hclge_cfg_com_tqp_queue_cmd {
864 __le16 tqp_id;
865 __le16 stream_id;
866 u8 enable;
867 u8 rsv[19];
868 };
869
870 struct hclge_cfg_tx_queue_pointer_cmd {
871 __le16 tqp_id;
872 __le16 tx_tail;
873 __le16 tx_head;
874 __le16 fbd_num;
875 __le16 ring_offset;
876 u8 rsv[14];
877 };
878
879 #pragma pack(1)
880 struct hclge_mac_ethertype_idx_rd_cmd {
881 u8 flags;
882 u8 resp_code;
883 __le16 vlan_tag;
884 u8 mac_addr[ETH_ALEN];
885 __le16 index;
886 __le16 ethter_type;
887 __le16 egress_port;
888 __le16 egress_queue;
889 __le16 rev0;
890 u8 i_port_bitmap;
891 u8 i_port_direction;
892 u8 rev1[2];
893 };
894
895 #pragma pack()
896
897 #define HCLGE_TSO_MSS_MIN_S 0
898 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0)
899
900 #define HCLGE_TSO_MSS_MAX_S 16
901 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16)
902
903 struct hclge_cfg_tso_status_cmd {
904 __le16 tso_mss_min;
905 __le16 tso_mss_max;
906 u8 rsv[20];
907 };
908
909 #define HCLGE_GRO_EN_B 0
910 struct hclge_cfg_gro_status_cmd {
911 u8 gro_en;
912 u8 rsv[23];
913 };
914
915 #define HCLGE_TSO_MSS_MIN 256
916 #define HCLGE_TSO_MSS_MAX 9668
917
918 #define HCLGE_TQP_RESET_B 0
919 struct hclge_reset_tqp_queue_cmd {
920 __le16 tqp_id;
921 u8 reset_req;
922 u8 ready_to_reset;
923 u8 rsv[20];
924 };
925
926 #define HCLGE_CFG_RESET_MAC_B 3
927 #define HCLGE_CFG_RESET_FUNC_B 7
928 struct hclge_reset_cmd {
929 u8 mac_func_reset;
930 u8 fun_reset_vfid;
931 u8 rsv[22];
932 };
933
934 #define HCLGE_PF_RESET_DONE_BIT BIT(0)
935
936 struct hclge_pf_rst_done_cmd {
937 u8 pf_rst_done;
938 u8 rsv[23];
939 };
940
941 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0)
942 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2)
943 #define HCLGE_CMD_SERDES_DONE_B BIT(0)
944 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1)
945 struct hclge_serdes_lb_cmd {
946 u8 mask;
947 u8 enable;
948 u8 result;
949 u8 rsv[21];
950 };
951
952 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
953 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
954 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */
955 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
956 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */
957
958 #define HCLGE_TYPE_CRQ 0
959 #define HCLGE_TYPE_CSQ 1
960 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000
961 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004
962 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
963 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010
964 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014
965 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018
966 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c
967 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020
968 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024
969 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028
970
971 /* this bit indicates that the driver is ready for hardware reset */
972 #define HCLGE_NIC_SW_RST_RDY_B 16
973 #define HCLGE_NIC_SW_RST_RDY BIT(HCLGE_NIC_SW_RST_RDY_B)
974
975 #define HCLGE_NIC_CMQ_DESC_NUM 1024
976 #define HCLGE_NIC_CMQ_DESC_NUM_S 3
977
978 #define HCLGE_LED_LOCATE_STATE_S 0
979 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0)
980
981 struct hclge_set_led_state_cmd {
982 u8 rsv1[3];
983 u8 locate_led_config;
984 u8 rsv2[20];
985 };
986
987 struct hclge_get_fd_mode_cmd {
988 u8 mode;
989 u8 enable;
990 u8 rsv[22];
991 };
992
993 struct hclge_get_fd_allocation_cmd {
994 __le32 stage1_entry_num;
995 __le32 stage2_entry_num;
996 __le16 stage1_counter_num;
997 __le16 stage2_counter_num;
998 u8 rsv[12];
999 };
1000
1001 struct hclge_set_fd_key_config_cmd {
1002 u8 stage;
1003 u8 key_select;
1004 u8 inner_sipv6_word_en;
1005 u8 inner_dipv6_word_en;
1006 u8 outer_sipv6_word_en;
1007 u8 outer_dipv6_word_en;
1008 u8 rsv1[2];
1009 __le32 tuple_mask;
1010 __le32 meta_data_mask;
1011 u8 rsv2[8];
1012 };
1013
1014 #define HCLGE_FD_EPORT_SW_EN_B 0
1015 struct hclge_fd_tcam_config_1_cmd {
1016 u8 stage;
1017 u8 xy_sel;
1018 u8 port_info;
1019 u8 rsv1[1];
1020 __le32 index;
1021 u8 entry_vld;
1022 u8 rsv2[7];
1023 u8 tcam_data[8];
1024 };
1025
1026 struct hclge_fd_tcam_config_2_cmd {
1027 u8 tcam_data[24];
1028 };
1029
1030 struct hclge_fd_tcam_config_3_cmd {
1031 u8 tcam_data[20];
1032 u8 rsv[4];
1033 };
1034
1035 #define HCLGE_FD_AD_DROP_B 0
1036 #define HCLGE_FD_AD_DIRECT_QID_B 1
1037 #define HCLGE_FD_AD_QID_S 2
1038 #define HCLGE_FD_AD_QID_M GENMASK(11, 2)
1039 #define HCLGE_FD_AD_USE_COUNTER_B 12
1040 #define HCLGE_FD_AD_COUNTER_NUM_S 13
1041 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13)
1042 #define HCLGE_FD_AD_NXT_STEP_B 20
1043 #define HCLGE_FD_AD_NXT_KEY_S 21
1044 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(25, 21)
1045 #define HCLGE_FD_AD_WR_RULE_ID_B 0
1046 #define HCLGE_FD_AD_RULE_ID_S 1
1047 #define HCLGE_FD_AD_RULE_ID_M GENMASK(12, 1)
1048
1049 struct hclge_fd_ad_config_cmd {
1050 u8 stage;
1051 u8 rsv1[3];
1052 __le32 index;
1053 __le64 ad_data;
1054 u8 rsv2[8];
1055 };
1056
1057 struct hclge_get_m7_bd_cmd {
1058 __le32 bd_num;
1059 u8 rsv[20];
1060 };
1061
1062 struct hclge_query_ppu_pf_other_int_dfx_cmd {
1063 __le16 over_8bd_no_fe_qid;
1064 __le16 over_8bd_no_fe_vf_id;
1065 __le16 tso_mss_cmp_min_err_qid;
1066 __le16 tso_mss_cmp_min_err_vf_id;
1067 __le16 tso_mss_cmp_max_err_qid;
1068 __le16 tso_mss_cmp_max_err_vf_id;
1069 __le16 tx_rd_fbd_poison_qid;
1070 __le16 tx_rd_fbd_poison_vf_id;
1071 __le16 rx_rd_fbd_poison_qid;
1072 __le16 rx_rd_fbd_poison_vf_id;
1073 u8 rsv[4];
1074 };
1075
1076 #define HCLGE_LINK_EVENT_REPORT_EN_B 0
1077 #define HCLGE_NCSI_ERROR_REPORT_EN_B 1
1078 struct hclge_firmware_compat_cmd {
1079 __le32 compat;
1080 u8 rsv[20];
1081 };
1082
1083 #define HCLGE_SFP_INFO_CMD_NUM 6
1084 #define HCLGE_SFP_INFO_BD0_LEN 20
1085 #define HCLGE_SFP_INFO_BDX_LEN 24
1086 #define HCLGE_SFP_INFO_MAX_LEN \
1087 (HCLGE_SFP_INFO_BD0_LEN + \
1088 (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN)
1089
1090 struct hclge_sfp_info_bd0_cmd {
1091 __le16 offset;
1092 __le16 read_len;
1093 u8 data[HCLGE_SFP_INFO_BD0_LEN];
1094 };
1095
1096 #define HCLGE_QUERY_DEV_SPECS_BD_NUM 4
1097
1098 struct hclge_dev_specs_0_cmd {
1099 __le32 rsv0;
1100 __le32 mac_entry_num;
1101 __le32 mng_entry_num;
1102 __le16 rss_ind_tbl_size;
1103 __le16 rss_key_size;
1104 __le16 int_ql_max;
1105 u8 max_non_tso_bd_num;
1106 u8 rsv1;
1107 __le32 max_tm_rate;
1108 };
1109
1110 int hclge_cmd_init(struct hclge_dev *hdev);
hclge_write_reg(void __iomem * base,u32 reg,u32 value)1111 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
1112 {
1113 writel(value, base + reg);
1114 }
1115
1116 #define hclge_write_dev(a, reg, value) \
1117 hclge_write_reg((a)->io_base, (reg), (value))
1118 #define hclge_read_dev(a, reg) \
1119 hclge_read_reg((a)->io_base, (reg))
1120
hclge_read_reg(u8 __iomem * base,u32 reg)1121 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
1122 {
1123 u8 __iomem *reg_addr = READ_ONCE(base);
1124
1125 return readl(reg_addr + reg);
1126 }
1127
1128 #define HCLGE_SEND_SYNC(flag) \
1129 ((flag) & HCLGE_CMD_FLAG_NO_INTR)
1130
1131 struct hclge_hw;
1132 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
1133 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
1134 enum hclge_opcode_type opcode, bool is_read);
1135 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
1136
1137 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
1138 struct hclge_desc *desc);
1139 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
1140 struct hclge_desc *desc);
1141
1142 void hclge_cmd_uninit(struct hclge_dev *hdev);
1143 int hclge_cmd_queue_init(struct hclge_dev *hdev);
1144 #endif
1145