1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #ifndef __HCLGE_MAIN_H
5 #define __HCLGE_MAIN_H
6 #include <linux/fs.h>
7 #include <linux/types.h>
8 #include <linux/phy.h>
9 #include <linux/if_vlan.h>
10 #include <linux/kfifo.h>
11
12 #include "hclge_cmd.h"
13 #include "hnae3.h"
14
15 #define HCLGE_MOD_VERSION "1.0"
16 #define HCLGE_DRIVER_NAME "hclge"
17
18 #define HCLGE_MAX_PF_NUM 8
19
20 #define HCLGE_RD_FIRST_STATS_NUM 2
21 #define HCLGE_RD_OTHER_STATS_NUM 4
22
23 #define HCLGE_INVALID_VPORT 0xffff
24
25 #define HCLGE_PF_CFG_BLOCK_SIZE 32
26 #define HCLGE_PF_CFG_DESC_NUM \
27 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
28
29 #define HCLGE_VECTOR_REG_BASE 0x20000
30 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400
31
32 #define HCLGE_VECTOR_REG_OFFSET 0x4
33 #define HCLGE_VECTOR_VF_OFFSET 0x100000
34
35 #define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000
36 #define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004
37 #define HCLGE_CMDQ_TX_DEPTH_REG 0x27008
38 #define HCLGE_CMDQ_TX_TAIL_REG 0x27010
39 #define HCLGE_CMDQ_TX_HEAD_REG 0x27014
40 #define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018
41 #define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C
42 #define HCLGE_CMDQ_RX_DEPTH_REG 0x27020
43 #define HCLGE_CMDQ_RX_TAIL_REG 0x27024
44 #define HCLGE_CMDQ_RX_HEAD_REG 0x27028
45 #define HCLGE_CMDQ_INTR_SRC_REG 0x27100
46 #define HCLGE_CMDQ_INTR_STS_REG 0x27104
47 #define HCLGE_CMDQ_INTR_EN_REG 0x27108
48 #define HCLGE_CMDQ_INTR_GEN_REG 0x2710C
49
50 /* bar registers for common func */
51 #define HCLGE_VECTOR0_OTER_EN_REG 0x20600
52 #define HCLGE_RAS_OTHER_STS_REG 0x20B00
53 #define HCLGE_FUNC_RESET_STS_REG 0x20C00
54 #define HCLGE_GRO_EN_REG 0x28000
55
56 /* bar registers for rcb */
57 #define HCLGE_RING_RX_ADDR_L_REG 0x80000
58 #define HCLGE_RING_RX_ADDR_H_REG 0x80004
59 #define HCLGE_RING_RX_BD_NUM_REG 0x80008
60 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C
61 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014
62 #define HCLGE_RING_RX_TAIL_REG 0x80018
63 #define HCLGE_RING_RX_HEAD_REG 0x8001C
64 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020
65 #define HCLGE_RING_RX_OFFSET_REG 0x80024
66 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028
67 #define HCLGE_RING_RX_STASH_REG 0x80030
68 #define HCLGE_RING_RX_BD_ERR_REG 0x80034
69 #define HCLGE_RING_TX_ADDR_L_REG 0x80040
70 #define HCLGE_RING_TX_ADDR_H_REG 0x80044
71 #define HCLGE_RING_TX_BD_NUM_REG 0x80048
72 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C
73 #define HCLGE_RING_TX_TC_REG 0x80050
74 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054
75 #define HCLGE_RING_TX_TAIL_REG 0x80058
76 #define HCLGE_RING_TX_HEAD_REG 0x8005C
77 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060
78 #define HCLGE_RING_TX_OFFSET_REG 0x80064
79 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068
80 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070
81 #define HCLGE_RING_TX_BD_ERR_REG 0x80074
82 #define HCLGE_RING_EN_REG 0x80090
83
84 /* bar registers for tqp interrupt */
85 #define HCLGE_TQP_INTR_CTRL_REG 0x20000
86 #define HCLGE_TQP_INTR_GL0_REG 0x20100
87 #define HCLGE_TQP_INTR_GL1_REG 0x20200
88 #define HCLGE_TQP_INTR_GL2_REG 0x20300
89 #define HCLGE_TQP_INTR_RL_REG 0x20900
90
91 #define HCLGE_RSS_IND_TBL_SIZE 512
92 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0)
93 #define HCLGE_RSS_KEY_SIZE 40
94 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0
95 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1
96 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2
97 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0)
98 #define HCLGE_RSS_CFG_TBL_NUM \
99 (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE)
100
101 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0)
102 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0)
103 #define HCLGE_D_PORT_BIT BIT(0)
104 #define HCLGE_S_PORT_BIT BIT(1)
105 #define HCLGE_D_IP_BIT BIT(2)
106 #define HCLGE_S_IP_BIT BIT(3)
107 #define HCLGE_V_TAG_BIT BIT(4)
108 #define HCLGE_RSS_INPUT_TUPLE_SCTP_NO_PORT \
109 (HCLGE_D_IP_BIT | HCLGE_S_IP_BIT | HCLGE_V_TAG_BIT)
110
111 #define HCLGE_RSS_TC_SIZE_0 1
112 #define HCLGE_RSS_TC_SIZE_1 2
113 #define HCLGE_RSS_TC_SIZE_2 4
114 #define HCLGE_RSS_TC_SIZE_3 8
115 #define HCLGE_RSS_TC_SIZE_4 16
116 #define HCLGE_RSS_TC_SIZE_5 32
117 #define HCLGE_RSS_TC_SIZE_6 64
118 #define HCLGE_RSS_TC_SIZE_7 128
119
120 #define HCLGE_UMV_TBL_SIZE 3072
121 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \
122 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM)
123
124 #define HCLGE_TQP_RESET_TRY_TIMES 200
125
126 #define HCLGE_PHY_PAGE_MDIX 0
127 #define HCLGE_PHY_PAGE_COPPER 0
128
129 /* Page Selection Reg. */
130 #define HCLGE_PHY_PAGE_REG 22
131
132 /* Copper Specific Control Register */
133 #define HCLGE_PHY_CSC_REG 16
134
135 /* Copper Specific Status Register */
136 #define HCLGE_PHY_CSS_REG 17
137
138 #define HCLGE_PHY_MDIX_CTRL_S 5
139 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
140
141 #define HCLGE_PHY_MDIX_STATUS_B 6
142 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11
143
144 #define HCLGE_GET_DFX_REG_TYPE_CNT 4
145
146 /* Factor used to calculate offset and bitmap of VF num */
147 #define HCLGE_VF_NUM_PER_CMD 64
148
149 enum HLCGE_PORT_TYPE {
150 HOST_PORT,
151 NETWORK_PORT
152 };
153
154 #define PF_VPORT_ID 0
155
156 #define HCLGE_PF_ID_S 0
157 #define HCLGE_PF_ID_M GENMASK(2, 0)
158 #define HCLGE_VF_ID_S 3
159 #define HCLGE_VF_ID_M GENMASK(10, 3)
160 #define HCLGE_PORT_TYPE_B 11
161 #define HCLGE_NETWORK_PORT_ID_S 0
162 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0)
163
164 /* Reset related Registers */
165 #define HCLGE_PF_OTHER_INT_REG 0x20600
166 #define HCLGE_MISC_RESET_STS_REG 0x20700
167 #define HCLGE_MISC_VECTOR_INT_STS 0x20800
168 #define HCLGE_GLOBAL_RESET_REG 0x20A00
169 #define HCLGE_GLOBAL_RESET_BIT 0
170 #define HCLGE_CORE_RESET_BIT 1
171 #define HCLGE_IMP_RESET_BIT 2
172 #define HCLGE_RESET_INT_M GENMASK(7, 5)
173 #define HCLGE_FUN_RST_ING 0x20C00
174 #define HCLGE_FUN_RST_ING_B 0
175
176 /* Vector0 register bits define */
177 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
178 #define HCLGE_VECTOR0_CORERESET_INT_B 6
179 #define HCLGE_VECTOR0_IMPRESET_INT_B 7
180
181 /* Vector0 interrupt CMDQ event source register(RW) */
182 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100
183 /* CMDQ register bits for RX event(=MBX event) */
184 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1
185
186 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1
187 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U
188 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U
189
190 #define HCLGE_MAC_DEFAULT_FRAME \
191 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
192 #define HCLGE_MAC_MIN_FRAME 64
193 #define HCLGE_MAC_MAX_FRAME 9728
194
195 #define HCLGE_SUPPORT_1G_BIT BIT(0)
196 #define HCLGE_SUPPORT_10G_BIT BIT(1)
197 #define HCLGE_SUPPORT_25G_BIT BIT(2)
198 #define HCLGE_SUPPORT_50G_BIT BIT(3)
199 #define HCLGE_SUPPORT_100G_BIT BIT(4)
200 /* to be compatible with exsit board */
201 #define HCLGE_SUPPORT_40G_BIT BIT(5)
202 #define HCLGE_SUPPORT_100M_BIT BIT(6)
203 #define HCLGE_SUPPORT_10M_BIT BIT(7)
204 #define HCLGE_SUPPORT_200G_BIT BIT(8)
205 #define HCLGE_SUPPORT_GE \
206 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT)
207
208 enum HCLGE_DEV_STATE {
209 HCLGE_STATE_REINITING,
210 HCLGE_STATE_DOWN,
211 HCLGE_STATE_DISABLED,
212 HCLGE_STATE_REMOVING,
213 HCLGE_STATE_NIC_REGISTERED,
214 HCLGE_STATE_ROCE_REGISTERED,
215 HCLGE_STATE_SERVICE_INITED,
216 HCLGE_STATE_RST_SERVICE_SCHED,
217 HCLGE_STATE_RST_HANDLING,
218 HCLGE_STATE_MBX_SERVICE_SCHED,
219 HCLGE_STATE_MBX_HANDLING,
220 HCLGE_STATE_STATISTICS_UPDATING,
221 HCLGE_STATE_CMD_DISABLE,
222 HCLGE_STATE_LINK_UPDATING,
223 HCLGE_STATE_PROMISC_CHANGED,
224 HCLGE_STATE_RST_FAIL,
225 HCLGE_STATE_MAX
226 };
227
228 enum hclge_evt_cause {
229 HCLGE_VECTOR0_EVENT_RST,
230 HCLGE_VECTOR0_EVENT_MBX,
231 HCLGE_VECTOR0_EVENT_ERR,
232 HCLGE_VECTOR0_EVENT_OTHER,
233 };
234
235 enum HCLGE_MAC_SPEED {
236 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */
237 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */
238 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */
239 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
240 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
241 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
242 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
243 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
244 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */
245 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */
246 };
247
248 enum HCLGE_MAC_DUPLEX {
249 HCLGE_MAC_HALF,
250 HCLGE_MAC_FULL
251 };
252
253 #define QUERY_SFP_SPEED 0
254 #define QUERY_ACTIVE_SPEED 1
255
256 struct hclge_mac {
257 u8 mac_id;
258 u8 phy_addr;
259 u8 flag;
260 u8 media_type; /* port media type, e.g. fibre/copper/backplane */
261 u8 mac_addr[ETH_ALEN];
262 u8 autoneg;
263 u8 duplex;
264 u8 support_autoneg;
265 u8 speed_type; /* 0: sfp speed, 1: active speed */
266 u32 speed;
267 u32 max_speed;
268 u32 speed_ability; /* speed ability supported by current media */
269 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */
270 u32 fec_mode; /* active fec mode */
271 u32 user_fec_mode;
272 u32 fec_ability;
273 int link; /* store the link status of mac & phy (if phy exists) */
274 struct phy_device *phydev;
275 struct mii_bus *mdio_bus;
276 phy_interface_t phy_if;
277 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
278 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
279 };
280
281 struct hclge_hw {
282 void __iomem *io_base;
283 struct hclge_mac mac;
284 int num_vec;
285 struct hclge_cmq cmq;
286 };
287
288 /* TQP stats */
289 struct hlcge_tqp_stats {
290 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */
291 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
292 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */
293 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
294 };
295
296 struct hclge_tqp {
297 /* copy of device pointer from pci_dev,
298 * used when perform DMA mapping
299 */
300 struct device *dev;
301 struct hnae3_queue q;
302 struct hlcge_tqp_stats tqp_stats;
303 u16 index; /* Global index in a NIC controller */
304
305 bool alloced;
306 };
307
308 enum hclge_fc_mode {
309 HCLGE_FC_NONE,
310 HCLGE_FC_RX_PAUSE,
311 HCLGE_FC_TX_PAUSE,
312 HCLGE_FC_FULL,
313 HCLGE_FC_PFC,
314 HCLGE_FC_DEFAULT
315 };
316
317 enum hclge_link_fail_code {
318 HCLGE_LF_NORMAL,
319 HCLGE_LF_REF_CLOCK_LOST,
320 HCLGE_LF_XSFP_TX_DISABLE,
321 HCLGE_LF_XSFP_ABSENT,
322 };
323
324 #define HCLGE_LINK_STATUS_DOWN 0
325 #define HCLGE_LINK_STATUS_UP 1
326
327 #define HCLGE_PG_NUM 4
328 #define HCLGE_SCH_MODE_SP 0
329 #define HCLGE_SCH_MODE_DWRR 1
330 struct hclge_pg_info {
331 u8 pg_id;
332 u8 pg_sch_mode; /* 0: sp; 1: dwrr */
333 u8 tc_bit_map;
334 u32 bw_limit;
335 u8 tc_dwrr[HNAE3_MAX_TC];
336 };
337
338 struct hclge_tc_info {
339 u8 tc_id;
340 u8 tc_sch_mode; /* 0: sp; 1: dwrr */
341 u8 pgid;
342 u32 bw_limit;
343 };
344
345 struct hclge_cfg {
346 u8 vmdq_vport_num;
347 u8 tc_num;
348 u16 tqp_desc_num;
349 u16 rx_buf_len;
350 u16 rss_size_max;
351 u8 phy_addr;
352 u8 media_type;
353 u8 mac_addr[ETH_ALEN];
354 u8 default_speed;
355 u32 numa_node_map;
356 u16 speed_ability;
357 u16 umv_space;
358 };
359
360 struct hclge_tm_info {
361 u8 num_tc;
362 u8 num_pg; /* It must be 1 if vNET-Base schd */
363 u8 pg_dwrr[HCLGE_PG_NUM];
364 u8 prio_tc[HNAE3_MAX_USER_PRIO];
365 struct hclge_pg_info pg_info[HCLGE_PG_NUM];
366 struct hclge_tc_info tc_info[HNAE3_MAX_TC];
367 enum hclge_fc_mode fc_mode;
368 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
369 u8 pfc_en; /* PFC enabled or not for user priority */
370 };
371
372 struct hclge_comm_stats_str {
373 char desc[ETH_GSTRING_LEN];
374 unsigned long offset;
375 };
376
377 /* mac stats ,opcode id: 0x0032 */
378 struct hclge_mac_stats {
379 u64 mac_tx_mac_pause_num;
380 u64 mac_rx_mac_pause_num;
381 u64 mac_tx_pfc_pri0_pkt_num;
382 u64 mac_tx_pfc_pri1_pkt_num;
383 u64 mac_tx_pfc_pri2_pkt_num;
384 u64 mac_tx_pfc_pri3_pkt_num;
385 u64 mac_tx_pfc_pri4_pkt_num;
386 u64 mac_tx_pfc_pri5_pkt_num;
387 u64 mac_tx_pfc_pri6_pkt_num;
388 u64 mac_tx_pfc_pri7_pkt_num;
389 u64 mac_rx_pfc_pri0_pkt_num;
390 u64 mac_rx_pfc_pri1_pkt_num;
391 u64 mac_rx_pfc_pri2_pkt_num;
392 u64 mac_rx_pfc_pri3_pkt_num;
393 u64 mac_rx_pfc_pri4_pkt_num;
394 u64 mac_rx_pfc_pri5_pkt_num;
395 u64 mac_rx_pfc_pri6_pkt_num;
396 u64 mac_rx_pfc_pri7_pkt_num;
397 u64 mac_tx_total_pkt_num;
398 u64 mac_tx_total_oct_num;
399 u64 mac_tx_good_pkt_num;
400 u64 mac_tx_bad_pkt_num;
401 u64 mac_tx_good_oct_num;
402 u64 mac_tx_bad_oct_num;
403 u64 mac_tx_uni_pkt_num;
404 u64 mac_tx_multi_pkt_num;
405 u64 mac_tx_broad_pkt_num;
406 u64 mac_tx_undersize_pkt_num;
407 u64 mac_tx_oversize_pkt_num;
408 u64 mac_tx_64_oct_pkt_num;
409 u64 mac_tx_65_127_oct_pkt_num;
410 u64 mac_tx_128_255_oct_pkt_num;
411 u64 mac_tx_256_511_oct_pkt_num;
412 u64 mac_tx_512_1023_oct_pkt_num;
413 u64 mac_tx_1024_1518_oct_pkt_num;
414 u64 mac_tx_1519_2047_oct_pkt_num;
415 u64 mac_tx_2048_4095_oct_pkt_num;
416 u64 mac_tx_4096_8191_oct_pkt_num;
417 u64 rsv0;
418 u64 mac_tx_8192_9216_oct_pkt_num;
419 u64 mac_tx_9217_12287_oct_pkt_num;
420 u64 mac_tx_12288_16383_oct_pkt_num;
421 u64 mac_tx_1519_max_good_oct_pkt_num;
422 u64 mac_tx_1519_max_bad_oct_pkt_num;
423
424 u64 mac_rx_total_pkt_num;
425 u64 mac_rx_total_oct_num;
426 u64 mac_rx_good_pkt_num;
427 u64 mac_rx_bad_pkt_num;
428 u64 mac_rx_good_oct_num;
429 u64 mac_rx_bad_oct_num;
430 u64 mac_rx_uni_pkt_num;
431 u64 mac_rx_multi_pkt_num;
432 u64 mac_rx_broad_pkt_num;
433 u64 mac_rx_undersize_pkt_num;
434 u64 mac_rx_oversize_pkt_num;
435 u64 mac_rx_64_oct_pkt_num;
436 u64 mac_rx_65_127_oct_pkt_num;
437 u64 mac_rx_128_255_oct_pkt_num;
438 u64 mac_rx_256_511_oct_pkt_num;
439 u64 mac_rx_512_1023_oct_pkt_num;
440 u64 mac_rx_1024_1518_oct_pkt_num;
441 u64 mac_rx_1519_2047_oct_pkt_num;
442 u64 mac_rx_2048_4095_oct_pkt_num;
443 u64 mac_rx_4096_8191_oct_pkt_num;
444 u64 rsv1;
445 u64 mac_rx_8192_9216_oct_pkt_num;
446 u64 mac_rx_9217_12287_oct_pkt_num;
447 u64 mac_rx_12288_16383_oct_pkt_num;
448 u64 mac_rx_1519_max_good_oct_pkt_num;
449 u64 mac_rx_1519_max_bad_oct_pkt_num;
450
451 u64 mac_tx_fragment_pkt_num;
452 u64 mac_tx_undermin_pkt_num;
453 u64 mac_tx_jabber_pkt_num;
454 u64 mac_tx_err_all_pkt_num;
455 u64 mac_tx_from_app_good_pkt_num;
456 u64 mac_tx_from_app_bad_pkt_num;
457 u64 mac_rx_fragment_pkt_num;
458 u64 mac_rx_undermin_pkt_num;
459 u64 mac_rx_jabber_pkt_num;
460 u64 mac_rx_fcs_err_pkt_num;
461 u64 mac_rx_send_app_good_pkt_num;
462 u64 mac_rx_send_app_bad_pkt_num;
463 u64 mac_tx_pfc_pause_pkt_num;
464 u64 mac_rx_pfc_pause_pkt_num;
465 u64 mac_tx_ctrl_pkt_num;
466 u64 mac_rx_ctrl_pkt_num;
467 };
468
469 #define HCLGE_STATS_TIMER_INTERVAL 300UL
470
471 struct hclge_vlan_type_cfg {
472 u16 rx_ot_fst_vlan_type;
473 u16 rx_ot_sec_vlan_type;
474 u16 rx_in_fst_vlan_type;
475 u16 rx_in_sec_vlan_type;
476 u16 tx_ot_vlan_type;
477 u16 tx_in_vlan_type;
478 };
479
480 enum HCLGE_FD_MODE {
481 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1,
482 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2,
483 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1,
484 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2,
485 };
486
487 enum HCLGE_FD_KEY_TYPE {
488 HCLGE_FD_KEY_BASE_ON_PTYPE,
489 HCLGE_FD_KEY_BASE_ON_TUPLE,
490 };
491
492 enum HCLGE_FD_STAGE {
493 HCLGE_FD_STAGE_1,
494 HCLGE_FD_STAGE_2,
495 MAX_STAGE_NUM,
496 };
497
498 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet
499 * INNER_XXX indicate tuples in tunneled header of tunnel packet or
500 * tuples of non-tunnel packet
501 */
502 enum HCLGE_FD_TUPLE {
503 OUTER_DST_MAC,
504 OUTER_SRC_MAC,
505 OUTER_VLAN_TAG_FST,
506 OUTER_VLAN_TAG_SEC,
507 OUTER_ETH_TYPE,
508 OUTER_L2_RSV,
509 OUTER_IP_TOS,
510 OUTER_IP_PROTO,
511 OUTER_SRC_IP,
512 OUTER_DST_IP,
513 OUTER_L3_RSV,
514 OUTER_SRC_PORT,
515 OUTER_DST_PORT,
516 OUTER_L4_RSV,
517 OUTER_TUN_VNI,
518 OUTER_TUN_FLOW_ID,
519 INNER_DST_MAC,
520 INNER_SRC_MAC,
521 INNER_VLAN_TAG_FST,
522 INNER_VLAN_TAG_SEC,
523 INNER_ETH_TYPE,
524 INNER_L2_RSV,
525 INNER_IP_TOS,
526 INNER_IP_PROTO,
527 INNER_SRC_IP,
528 INNER_DST_IP,
529 INNER_L3_RSV,
530 INNER_SRC_PORT,
531 INNER_DST_PORT,
532 INNER_L4_RSV,
533 MAX_TUPLE,
534 };
535
536 enum HCLGE_FD_META_DATA {
537 PACKET_TYPE_ID,
538 IP_FRAGEMENT,
539 ROCE_TYPE,
540 NEXT_KEY,
541 VLAN_NUMBER,
542 SRC_VPORT,
543 DST_VPORT,
544 TUNNEL_PACKET,
545 MAX_META_DATA,
546 };
547
548 struct key_info {
549 u8 key_type;
550 u8 key_length; /* use bit as unit */
551 };
552
553 #define MAX_KEY_LENGTH 400
554 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4)
555 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4)
556 #define MAX_META_DATA_LENGTH 32
557
558 /* assigned by firmware, the real filter number for each pf may be less */
559 #define MAX_FD_FILTER_NUM 4096
560 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL
561
562 enum HCLGE_FD_ACTIVE_RULE_TYPE {
563 HCLGE_FD_RULE_NONE,
564 HCLGE_FD_ARFS_ACTIVE,
565 HCLGE_FD_EP_ACTIVE,
566 };
567
568 enum HCLGE_FD_PACKET_TYPE {
569 NIC_PACKET,
570 ROCE_PACKET,
571 };
572
573 enum HCLGE_FD_ACTION {
574 HCLGE_FD_ACTION_ACCEPT_PACKET,
575 HCLGE_FD_ACTION_DROP_PACKET,
576 };
577
578 struct hclge_fd_key_cfg {
579 u8 key_sel;
580 u8 inner_sipv6_word_en;
581 u8 inner_dipv6_word_en;
582 u8 outer_sipv6_word_en;
583 u8 outer_dipv6_word_en;
584 u32 tuple_active;
585 u32 meta_data_active;
586 };
587
588 struct hclge_fd_cfg {
589 u8 fd_mode;
590 u16 max_key_length; /* use bit as unit */
591 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */
592 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */
593 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM];
594 };
595
596 #define IPV4_INDEX 3
597 #define IPV6_SIZE 4
598 struct hclge_fd_rule_tuples {
599 u8 src_mac[ETH_ALEN];
600 u8 dst_mac[ETH_ALEN];
601 /* Be compatible for ip address of both ipv4 and ipv6.
602 * For ipv4 address, we store it in src/dst_ip[3].
603 */
604 u32 src_ip[IPV6_SIZE];
605 u32 dst_ip[IPV6_SIZE];
606 u16 src_port;
607 u16 dst_port;
608 u16 vlan_tag1;
609 u16 ether_proto;
610 u8 ip_tos;
611 u8 ip_proto;
612 };
613
614 struct hclge_fd_rule {
615 struct hlist_node rule_node;
616 struct hclge_fd_rule_tuples tuples;
617 struct hclge_fd_rule_tuples tuples_mask;
618 u32 unused_tuple;
619 u32 flow_type;
620 u8 action;
621 u16 vf_id;
622 u16 queue_id;
623 u16 location;
624 u16 flow_id; /* only used for arfs */
625 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type;
626 };
627
628 struct hclge_fd_ad_data {
629 u16 ad_id;
630 u8 drop_packet;
631 u8 forward_to_direct_queue;
632 u16 queue_id;
633 u8 use_counter;
634 u8 counter_id;
635 u8 use_next_stage;
636 u8 write_rule_id_to_bd;
637 u8 next_input_key;
638 u16 rule_id;
639 };
640
641 enum HCLGE_MAC_NODE_STATE {
642 HCLGE_MAC_TO_ADD,
643 HCLGE_MAC_TO_DEL,
644 HCLGE_MAC_ACTIVE
645 };
646
647 struct hclge_mac_node {
648 struct list_head node;
649 enum HCLGE_MAC_NODE_STATE state;
650 u8 mac_addr[ETH_ALEN];
651 };
652
653 enum HCLGE_MAC_ADDR_TYPE {
654 HCLGE_MAC_ADDR_UC,
655 HCLGE_MAC_ADDR_MC
656 };
657
658 struct hclge_vport_vlan_cfg {
659 struct list_head node;
660 int hd_tbl_status;
661 u16 vlan_id;
662 };
663
664 struct hclge_rst_stats {
665 u32 reset_done_cnt; /* the number of reset has completed */
666 u32 hw_reset_done_cnt; /* the number of HW reset has completed */
667 u32 pf_rst_cnt; /* the number of PF reset */
668 u32 flr_rst_cnt; /* the number of FLR */
669 u32 global_rst_cnt; /* the number of GLOBAL */
670 u32 imp_rst_cnt; /* the number of IMP reset */
671 u32 reset_cnt; /* the number of reset */
672 u32 reset_fail_cnt; /* the number of reset fail */
673 };
674
675 /* time and register status when mac tunnel interruption occur */
676 struct hclge_mac_tnl_stats {
677 u64 time;
678 u32 status;
679 };
680
681 #define HCLGE_RESET_INTERVAL (10 * HZ)
682 #define HCLGE_WAIT_RESET_DONE 100
683
684 #pragma pack(1)
685 struct hclge_vf_vlan_cfg {
686 u8 mbx_cmd;
687 u8 subcode;
688 u8 is_kill;
689 u16 vlan;
690 u16 proto;
691 };
692
693 #pragma pack()
694
695 /* For each bit of TCAM entry, it uses a pair of 'x' and
696 * 'y' to indicate which value to match, like below:
697 * ----------------------------------
698 * | bit x | bit y | search value |
699 * ----------------------------------
700 * | 0 | 0 | always hit |
701 * ----------------------------------
702 * | 1 | 0 | match '0' |
703 * ----------------------------------
704 * | 0 | 1 | match '1' |
705 * ----------------------------------
706 * | 1 | 1 | invalid |
707 * ----------------------------------
708 * Then for input key(k) and mask(v), we can calculate the value by
709 * the formulae:
710 * x = (~k) & v
711 * y = (k ^ ~v) & k
712 */
713 #define calc_x(x, k, v) ((x) = (~(k) & (v)))
714 #define calc_y(y, k, v) \
715 do { \
716 const typeof(k) _k_ = (k); \
717 const typeof(v) _v_ = (v); \
718 (y) = (_k_ ^ ~_v_) & (_k_); \
719 } while (0)
720
721 #define HCLGE_MAC_TNL_LOG_SIZE 8
722 #define HCLGE_VPORT_NUM 256
723 struct hclge_dev {
724 struct pci_dev *pdev;
725 struct hnae3_ae_dev *ae_dev;
726 struct hclge_hw hw;
727 struct hclge_misc_vector misc_vector;
728 struct hclge_mac_stats mac_stats;
729 unsigned long state;
730 unsigned long flr_state;
731 unsigned long last_reset_time;
732
733 enum hnae3_reset_type reset_type;
734 enum hnae3_reset_type reset_level;
735 unsigned long default_reset_request;
736 unsigned long reset_request; /* reset has been requested */
737 unsigned long reset_pending; /* client rst is pending to be served */
738 struct hclge_rst_stats rst_stats;
739 struct semaphore reset_sem; /* protect reset process */
740 u32 fw_version;
741 u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */
742 u16 num_tqps; /* Num task queue pairs of this PF */
743 u16 num_req_vfs; /* Num VFs requested for this PF */
744
745 u16 base_tqp_pid; /* Base task tqp physical id of this PF */
746 u16 alloc_rss_size; /* Allocated RSS task queue */
747 u16 rss_size_max; /* HW defined max RSS task queue */
748
749 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */
750 u16 num_alloc_vport; /* Num vports this driver supports */
751 u32 numa_node_mask;
752 u16 rx_buf_len;
753 u16 num_tx_desc; /* desc num of per tx queue */
754 u16 num_rx_desc; /* desc num of per rx queue */
755 u8 hw_tc_map;
756 enum hclge_fc_mode fc_mode_last_time;
757 u8 support_sfp_query;
758
759 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1
760 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2
761 u8 tx_sch_mode;
762 u8 tc_max;
763 u8 pfc_max;
764
765 u8 default_up;
766 u8 dcbx_cap;
767 struct hclge_tm_info tm_info;
768
769 u16 num_msi;
770 u16 num_msi_left;
771 u16 num_msi_used;
772 u16 roce_base_msix_offset;
773 u32 base_msi_vector;
774 u16 *vector_status;
775 int *vector_irq;
776 u16 num_nic_msi; /* Num of nic vectors for this PF */
777 u16 num_roce_msi; /* Num of roce vectors for this PF */
778 int roce_base_vector;
779
780 unsigned long service_timer_period;
781 unsigned long service_timer_previous;
782 struct timer_list reset_timer;
783 struct delayed_work service_task;
784
785 bool cur_promisc;
786 int num_alloc_vfs; /* Actual number of VFs allocated */
787
788 struct hclge_tqp *htqp;
789 struct hclge_vport *vport;
790
791 struct dentry *hclge_dbgfs;
792
793 struct hnae3_client *nic_client;
794 struct hnae3_client *roce_client;
795
796 #define HCLGE_FLAG_MAIN BIT(0)
797 #define HCLGE_FLAG_DCB_CAPABLE BIT(1)
798 #define HCLGE_FLAG_DCB_ENABLE BIT(2)
799 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3)
800 u32 flag;
801
802 u32 pkt_buf_size; /* Total pf buf size for tx/rx */
803 u32 tx_buf_size; /* Tx buffer size for each TC */
804 u32 dv_buf_size; /* Dv buffer size for each TC */
805
806 u32 mps; /* Max packet size */
807 /* vport_lock protect resource shared by vports */
808 struct mutex vport_lock;
809
810 struct hclge_vlan_type_cfg vlan_type_cfg;
811
812 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)];
813 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
814
815 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
816
817 struct hclge_fd_cfg fd_cfg;
818 struct hlist_head fd_rule_list;
819 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */
820 u16 hclge_fd_rule_num;
821 unsigned long serv_processed_cnt;
822 unsigned long last_serv_processed;
823 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)];
824 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type;
825 u8 fd_en;
826
827 u16 wanted_umv_size;
828 /* max available unicast mac vlan space */
829 u16 max_umv_size;
830 /* private unicast mac vlan space, it's same for PF and its VFs */
831 u16 priv_umv_size;
832 /* unicast mac vlan space shared by PF and its VFs */
833 u16 share_umv_size;
834
835 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats,
836 HCLGE_MAC_TNL_LOG_SIZE);
837
838 /* affinity mask and notify for misc interrupt */
839 cpumask_t affinity_mask;
840 struct irq_affinity_notify affinity_notify;
841 };
842
843 /* VPort level vlan tag configuration for TX direction */
844 struct hclge_tx_vtag_cfg {
845 bool accept_tag1; /* Whether accept tag1 packet from host */
846 bool accept_untag1; /* Whether accept untag1 packet from host */
847 bool accept_tag2;
848 bool accept_untag2;
849 bool insert_tag1_en; /* Whether insert inner vlan tag */
850 bool insert_tag2_en; /* Whether insert outer vlan tag */
851 u16 default_tag1; /* The default inner vlan tag to insert */
852 u16 default_tag2; /* The default outer vlan tag to insert */
853 };
854
855 /* VPort level vlan tag configuration for RX direction */
856 struct hclge_rx_vtag_cfg {
857 u8 rx_vlan_offload_en; /* Whether enable rx vlan offload */
858 u8 strip_tag1_en; /* Whether strip inner vlan tag */
859 u8 strip_tag2_en; /* Whether strip outer vlan tag */
860 u8 vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */
861 u8 vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */
862 };
863
864 struct hclge_rss_tuple_cfg {
865 u8 ipv4_tcp_en;
866 u8 ipv4_udp_en;
867 u8 ipv4_sctp_en;
868 u8 ipv4_fragment_en;
869 u8 ipv6_tcp_en;
870 u8 ipv6_udp_en;
871 u8 ipv6_sctp_en;
872 u8 ipv6_fragment_en;
873 };
874
875 enum HCLGE_VPORT_STATE {
876 HCLGE_VPORT_STATE_ALIVE,
877 HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
878 HCLGE_VPORT_STATE_MAX
879 };
880
881 struct hclge_vlan_info {
882 u16 vlan_proto; /* so far support 802.1Q only */
883 u16 qos;
884 u16 vlan_tag;
885 };
886
887 struct hclge_port_base_vlan_config {
888 u16 state;
889 struct hclge_vlan_info vlan_info;
890 };
891
892 struct hclge_vf_info {
893 int link_state;
894 u8 mac[ETH_ALEN];
895 u32 spoofchk;
896 u32 max_tx_rate;
897 u32 trusted;
898 u16 promisc_enable;
899 };
900
901 struct hclge_vport {
902 u16 alloc_tqps; /* Allocated Tx/Rx queues */
903
904 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
905 /* User configured lookup table entries */
906 u8 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE];
907 int rss_algo; /* User configured hash algorithm */
908 /* User configured rss tuple sets */
909 struct hclge_rss_tuple_cfg rss_tuple_sets;
910
911 u16 alloc_rss_size;
912
913 u16 qs_offset;
914 u32 bw_limit; /* VSI BW Limit (0 = disabled) */
915 u8 dwrr;
916
917 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
918 struct hclge_port_base_vlan_config port_base_vlan_cfg;
919 struct hclge_tx_vtag_cfg txvlan_cfg;
920 struct hclge_rx_vtag_cfg rxvlan_cfg;
921
922 u16 used_umv_num;
923
924 u16 vport_id;
925 struct hclge_dev *back; /* Back reference to associated dev */
926 struct hnae3_handle nic;
927 struct hnae3_handle roce;
928
929 unsigned long state;
930 unsigned long last_active_jiffies;
931 u32 mps; /* Max packet size */
932 struct hclge_vf_info vf_info;
933
934 u8 overflow_promisc_flags;
935 u8 last_promisc_flags;
936
937 spinlock_t mac_list_lock; /* protect mac address need to add/detele */
938 struct list_head uc_mac_list; /* Store VF unicast table */
939 struct list_head mc_mac_list; /* Store VF multicast table */
940 struct list_head vlan_list; /* Store VF vlan table */
941 };
942
943 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
944 bool en_mc_pmc, bool en_bc_pmc);
945 int hclge_add_uc_addr_common(struct hclge_vport *vport,
946 const unsigned char *addr);
947 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
948 const unsigned char *addr);
949 int hclge_add_mc_addr_common(struct hclge_vport *vport,
950 const unsigned char *addr);
951 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
952 const unsigned char *addr);
953
954 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
955 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
956 int vector_id, bool en,
957 struct hnae3_ring_chain_node *ring_chain);
958
hclge_get_queue_id(struct hnae3_queue * queue)959 static inline int hclge_get_queue_id(struct hnae3_queue *queue)
960 {
961 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q);
962
963 return tqp->index;
964 }
965
hclge_is_reset_pending(struct hclge_dev * hdev)966 static inline bool hclge_is_reset_pending(struct hclge_dev *hdev)
967 {
968 return !!hdev->reset_pending;
969 }
970
971 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport);
972 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
973 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
974 u16 vlan_id, bool is_kill);
975 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable);
976
977 int hclge_buffer_alloc(struct hclge_dev *hdev);
978 int hclge_rss_init_hw(struct hclge_dev *hdev);
979 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev);
980
981 void hclge_mbx_handler(struct hclge_dev *hdev);
982 int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id);
983 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id);
984 int hclge_cfg_flowctrl(struct hclge_dev *hdev);
985 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id);
986 int hclge_vport_start(struct hclge_vport *vport);
987 void hclge_vport_stop(struct hclge_vport *vport);
988 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu);
989 int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf);
990 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id);
991 int hclge_notify_client(struct hclge_dev *hdev,
992 enum hnae3_reset_notify_type type);
993 int hclge_update_mac_list(struct hclge_vport *vport,
994 enum HCLGE_MAC_NODE_STATE state,
995 enum HCLGE_MAC_ADDR_TYPE mac_type,
996 const unsigned char *addr);
997 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport,
998 const u8 *old_addr, const u8 *new_addr);
999 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list,
1000 enum HCLGE_MAC_ADDR_TYPE mac_type);
1001 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list);
1002 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev);
1003 void hclge_restore_mac_table_common(struct hclge_vport *vport);
1004 void hclge_restore_vport_vlan_table(struct hclge_vport *vport);
1005 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
1006 struct hclge_vlan_info *vlan_info);
1007 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid,
1008 u16 state, u16 vlan_tag, u16 qos,
1009 u16 vlan_proto);
1010 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time);
1011 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev,
1012 struct hclge_desc *desc);
1013 void hclge_report_hw_error(struct hclge_dev *hdev,
1014 enum hnae3_hw_error_type type);
1015 void hclge_inform_vf_promisc_info(struct hclge_vport *vport);
1016 void hclge_dbg_dump_rst_info(struct hclge_dev *hdev);
1017 #endif
1018