1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_AMDGPU_DM_MST_TYPES_H__ 27 #define __DAL_AMDGPU_DM_MST_TYPES_H__ 28 29 #define DP_BRANCH_VENDOR_SPECIFIC_START 0x50C 30 31 /** 32 * Panamera MST Hub detection 33 * Offset DPCD 050Eh == 0x5A indicates cascaded MST hub case 34 * Check from beginning of branch device vendor specific field (050Ch) 35 */ 36 #define IS_SYNAPTICS_PANAMERA(branchDevName) (((int)branchDevName[4] & 0xF0) == 0x50 ? 1 : 0) 37 #define BRANCH_HW_REVISION_PANAMERA_A2 0x10 38 #define SYNAPTICS_CASCADED_HUB_ID 0x5A 39 #define IS_SYNAPTICS_CASCADED_PANAMERA(devName, data) ((IS_SYNAPTICS_PANAMERA(devName) && ((int)data[2] == SYNAPTICS_CASCADED_HUB_ID)) ? 1 : 0) 40 41 struct amdgpu_display_manager; 42 struct amdgpu_dm_connector; 43 44 int dm_mst_get_pbn_divider(struct dc_link *link); 45 46 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, 47 struct amdgpu_dm_connector *aconnector, 48 int link_index); 49 50 void 51 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev); 52 53 #if defined(CONFIG_DRM_AMD_DC_DCN) 54 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, 55 struct dc_state *dc_state); 56 #endif 57 58 #endif 59