1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * QLogic iSCSI HBA Driver
4 * Copyright (c) 2003-2013 QLogic Corporation
5 */
6
7 #ifndef __QL4_DEF_H
8 #define __QL4_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/workqueue.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/mutex.h>
26 #include <linux/aer.h>
27 #include <linux/bsg-lib.h>
28 #include <linux/vmalloc.h>
29
30 #include <net/tcp.h>
31 #include <scsi/scsi.h>
32 #include <scsi/scsi_host.h>
33 #include <scsi/scsi_device.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <scsi/scsi_transport.h>
36 #include <scsi/scsi_transport_iscsi.h>
37 #include <scsi/scsi_bsg_iscsi.h>
38 #include <scsi/scsi_netlink.h>
39 #include <scsi/libiscsi.h>
40
41 #include "ql4_dbg.h"
42 #include "ql4_nx.h"
43 #include "ql4_fw.h"
44 #include "ql4_nvram.h"
45 #include "ql4_83xx.h"
46
47 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
48 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
49 #endif
50
51 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
52 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
53 #endif
54
55 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
56 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
57 #endif
58
59 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
60 #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
61 #endif
62
63 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8324
64 #define PCI_DEVICE_ID_QLOGIC_ISP8324 0x8032
65 #endif
66
67 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8042
68 #define PCI_DEVICE_ID_QLOGIC_ISP8042 0x8042
69 #endif
70
71 #define ISP4XXX_PCI_FN_1 0x1
72 #define ISP4XXX_PCI_FN_2 0x3
73
74 #define QLA_SUCCESS 0
75 #define QLA_ERROR 1
76 #define STATUS(status) status == QLA_ERROR ? "FAILED" : "SUCCEEDED"
77
78 /*
79 * Data bit definitions
80 */
81 #define BIT_0 0x1
82 #define BIT_1 0x2
83 #define BIT_2 0x4
84 #define BIT_3 0x8
85 #define BIT_4 0x10
86 #define BIT_5 0x20
87 #define BIT_6 0x40
88 #define BIT_7 0x80
89 #define BIT_8 0x100
90 #define BIT_9 0x200
91 #define BIT_10 0x400
92 #define BIT_11 0x800
93 #define BIT_12 0x1000
94 #define BIT_13 0x2000
95 #define BIT_14 0x4000
96 #define BIT_15 0x8000
97 #define BIT_16 0x10000
98 #define BIT_17 0x20000
99 #define BIT_18 0x40000
100 #define BIT_19 0x80000
101 #define BIT_20 0x100000
102 #define BIT_21 0x200000
103 #define BIT_22 0x400000
104 #define BIT_23 0x800000
105 #define BIT_24 0x1000000
106 #define BIT_25 0x2000000
107 #define BIT_26 0x4000000
108 #define BIT_27 0x8000000
109 #define BIT_28 0x10000000
110 #define BIT_29 0x20000000
111 #define BIT_30 0x40000000
112 #define BIT_31 0x80000000
113
114 /**
115 * Macros to help code, maintain, etc.
116 **/
117 #define ql4_printk(level, ha, format, arg...) \
118 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
119
120
121 /*
122 * Host adapter default definitions
123 ***********************************/
124 #define MAX_HBAS 16
125 #define MAX_BUSES 1
126 #define MAX_TARGETS MAX_DEV_DB_ENTRIES
127 #define MAX_LUNS 0xffff
128 #define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES
129 #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
130 #define MAX_PDU_ENTRIES 32
131 #define INVALID_ENTRY 0xFFFF
132 #define MAX_CMDS_TO_RISC 1024
133 #define MAX_SRBS MAX_CMDS_TO_RISC
134 #define MBOX_AEN_REG_COUNT 8
135 #define MAX_INIT_RETRIES 5
136
137 /*
138 * Buffer sizes
139 */
140 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
141 #define RESPONSE_QUEUE_DEPTH 64
142 #define QUEUE_SIZE 64
143 #define DMA_BUFFER_SIZE 512
144 #define IOCB_HIWAT_CUSHION 4
145
146 /*
147 * Misc
148 */
149 #define MAC_ADDR_LEN 6 /* in bytes */
150 #define IP_ADDR_LEN 4 /* in bytes */
151 #define IPv6_ADDR_LEN 16 /* IPv6 address size */
152 #define DRIVER_NAME "qla4xxx"
153
154 #define MAX_LINKED_CMDS_PER_LUN 3
155 #define MAX_REQS_SERVICED_PER_INTR 1
156
157 #define ISCSI_IPADDR_SIZE 4 /* IP address size */
158 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */
159 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */
160
161 #define QL4_SESS_RECOVERY_TMO 120 /* iSCSI session */
162 /* recovery timeout */
163
164 #define LSDW(x) ((u32)((u64)(x)))
165 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
166
167 #define DEV_DB_NON_PERSISTENT 0
168 #define DEV_DB_PERSISTENT 1
169
170 #define QL4_ISP_REG_DISCONNECT 0xffffffffU
171
172 #define COPY_ISID(dst_isid, src_isid) { \
173 int i, j; \
174 for (i = 0, j = ISID_SIZE - 1; i < ISID_SIZE;) \
175 dst_isid[i++] = src_isid[j--]; \
176 }
177
178 #define SET_BITVAL(o, n, v) { \
179 if (o) \
180 n |= v; \
181 else \
182 n &= ~v; \
183 }
184
185 #define OP_STATE(o, f, p) { \
186 p = (o & f) ? "enable" : "disable"; \
187 }
188
189 /*
190 * Retry & Timeout Values
191 */
192 #define MBOX_TOV 60
193 #define SOFT_RESET_TOV 30
194 #define RESET_INTR_TOV 3
195 #define SEMAPHORE_TOV 10
196 #define ADAPTER_INIT_TOV 30
197 #define ADAPTER_RESET_TOV 180
198 #define EXTEND_CMD_TOV 60
199 #define WAIT_CMD_TOV 5
200 #define EH_WAIT_CMD_TOV 120
201 #define FIRMWARE_UP_TOV 60
202 #define RESET_FIRMWARE_TOV 30
203 #define LOGOUT_TOV 10
204 #define IOCB_TOV_MARGIN 10
205 #define RELOGIN_TOV 18
206 #define ISNS_DEREG_TOV 5
207 #define HBA_ONLINE_TOV 30
208 #define DISABLE_ACB_TOV 30
209 #define IP_CONFIG_TOV 30
210 #define LOGIN_TOV 12
211 #define BOOT_LOGIN_RESP_TOV 60
212
213 #define MAX_RESET_HA_RETRIES 2
214 #define FW_ALIVE_WAIT_TOV 3
215 #define IDC_EXTEND_TOV 8
216 #define IDC_COMP_TOV 5
217 #define LINK_UP_COMP_TOV 30
218
219 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
220
221 /*
222 * SCSI Request Block structure (srb) that is placed
223 * on cmd->SCp location of every I/O [We have 22 bytes available]
224 */
225 struct srb {
226 struct list_head list; /* (8) */
227 struct scsi_qla_host *ha; /* HA the SP is queued on */
228 struct ddb_entry *ddb;
229 uint16_t flags; /* (1) Status flags. */
230
231 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
232 #define SRB_GOT_SENSE BIT_4 /* sense data received. */
233 uint8_t state; /* (1) Status flags. */
234
235 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
236 #define SRB_FREE_STATE 1
237 #define SRB_ACTIVE_STATE 3
238 #define SRB_ACTIVE_TIMEOUT_STATE 4
239 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
240
241 struct scsi_cmnd *cmd; /* (4) SCSI command block */
242 dma_addr_t dma_handle; /* (4) for unmap of single transfers */
243 struct kref srb_ref; /* reference count for this srb */
244 uint8_t err_id; /* error id */
245 #define SRB_ERR_PORT 1 /* Request failed because "port down" */
246 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
247 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
248 #define SRB_ERR_OTHER 4
249
250 uint16_t reserved;
251 uint16_t iocb_tov;
252 uint16_t iocb_cnt; /* Number of used iocbs */
253 uint16_t cc_stat;
254
255 /* Used for extended sense / status continuation */
256 uint8_t *req_sense_ptr;
257 uint16_t req_sense_len;
258 uint16_t reserved2;
259 };
260
261 /* Mailbox request block structure */
262 struct mrb {
263 struct scsi_qla_host *ha;
264 struct mbox_cmd_iocb *mbox;
265 uint32_t mbox_cmd;
266 uint16_t iocb_cnt; /* Number of used iocbs */
267 uint32_t pid;
268 };
269
270 /*
271 * Asynchronous Event Queue structure
272 */
273 struct aen {
274 uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
275 };
276
277 struct ql4_aen_log {
278 int count;
279 struct aen entry[MAX_AEN_ENTRIES];
280 };
281
282 /*
283 * Device Database (DDB) structure
284 */
285 struct ddb_entry {
286 struct scsi_qla_host *ha;
287 struct iscsi_cls_session *sess;
288 struct iscsi_cls_conn *conn;
289
290 uint16_t fw_ddb_index; /* DDB firmware index */
291 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */
292 uint16_t ddb_type;
293 #define FLASH_DDB 0x01
294
295 struct dev_db_entry fw_ddb_entry;
296 int (*unblock_sess)(struct iscsi_cls_session *cls_session);
297 int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
298 struct ddb_entry *ddb_entry, uint32_t state);
299
300 /* Driver Re-login */
301 unsigned long flags; /* DDB Flags */
302 #define DDB_CONN_CLOSE_FAILURE 0 /* 0x00000001 */
303
304 uint16_t default_relogin_timeout; /* Max time to wait for
305 * relogin to complete */
306 atomic_t retry_relogin_timer; /* Min Time between relogins
307 * (4000 only) */
308 atomic_t relogin_timer; /* Max Time to wait for
309 * relogin to complete */
310 atomic_t relogin_retry_count; /* Num of times relogin has been
311 * retried */
312 uint32_t default_time2wait; /* Default Min time between
313 * relogins (+aens) */
314 uint16_t chap_tbl_idx;
315 };
316
317 struct qla_ddb_index {
318 struct list_head list;
319 uint16_t fw_ddb_idx;
320 uint16_t flash_ddb_idx;
321 struct dev_db_entry fw_ddb;
322 uint8_t flash_isid[6];
323 };
324
325 #define DDB_IPADDR_LEN 64
326
327 struct ql4_tuple_ddb {
328 int port;
329 int tpgt;
330 char ip_addr[DDB_IPADDR_LEN];
331 char iscsi_name[ISCSI_NAME_SIZE];
332 uint16_t options;
333 #define DDB_OPT_IPV6 0x0e0e
334 #define DDB_OPT_IPV4 0x0f0f
335 uint8_t isid[6];
336 };
337
338 /*
339 * DDB states.
340 */
341 #define DDB_STATE_DEAD 0 /* We can no longer talk to
342 * this device */
343 #define DDB_STATE_ONLINE 1 /* Device ready to accept
344 * commands */
345 #define DDB_STATE_MISSING 2 /* Device logged off, trying
346 * to re-login */
347
348 /*
349 * DDB flags.
350 */
351 #define DF_RELOGIN 0 /* Relogin to device */
352 #define DF_BOOT_TGT 1 /* Boot target entry */
353 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
354 #define DF_FO_MASKED 3
355 #define DF_DISABLE_RELOGIN 4 /* Disable relogin to device */
356
357 enum qla4_work_type {
358 QLA4_EVENT_AEN,
359 QLA4_EVENT_PING_STATUS,
360 };
361
362 struct qla4_work_evt {
363 struct list_head list;
364 enum qla4_work_type type;
365 union {
366 struct {
367 enum iscsi_host_event_code code;
368 uint32_t data_size;
369 uint8_t data[0];
370 } aen;
371 struct {
372 uint32_t status;
373 uint32_t pid;
374 uint32_t data_size;
375 uint8_t data[0];
376 } ping;
377 } u;
378 };
379
380 struct ql82xx_hw_data {
381 /* Offsets for flash/nvram access (set to ~0 if not used). */
382 uint32_t flash_conf_off;
383 uint32_t flash_data_off;
384
385 uint32_t fdt_wrt_disable;
386 uint32_t fdt_erase_cmd;
387 uint32_t fdt_block_size;
388 uint32_t fdt_unprotect_sec_cmd;
389 uint32_t fdt_protect_sec_cmd;
390
391 uint32_t flt_region_flt;
392 uint32_t flt_region_fdt;
393 uint32_t flt_region_boot;
394 uint32_t flt_region_bootload;
395 uint32_t flt_region_fw;
396
397 uint32_t flt_iscsi_param;
398 uint32_t flt_region_chap;
399 uint32_t flt_chap_size;
400 uint32_t flt_region_ddb;
401 uint32_t flt_ddb_size;
402 };
403
404 struct qla4_8xxx_legacy_intr_set {
405 uint32_t int_vec_bit;
406 uint32_t tgt_status_reg;
407 uint32_t tgt_mask_reg;
408 uint32_t pci_int_reg;
409 };
410
411 /* MSI-X Support */
412 #define QLA_MSIX_ENTRIES 2
413
414 /*
415 * ISP Operations
416 */
417 struct isp_operations {
418 int (*iospace_config) (struct scsi_qla_host *ha);
419 void (*pci_config) (struct scsi_qla_host *);
420 void (*disable_intrs) (struct scsi_qla_host *);
421 void (*enable_intrs) (struct scsi_qla_host *);
422 int (*start_firmware) (struct scsi_qla_host *);
423 int (*restart_firmware) (struct scsi_qla_host *);
424 irqreturn_t (*intr_handler) (int , void *);
425 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
426 int (*need_reset) (struct scsi_qla_host *);
427 int (*reset_chip) (struct scsi_qla_host *);
428 int (*reset_firmware) (struct scsi_qla_host *);
429 void (*queue_iocb) (struct scsi_qla_host *);
430 void (*complete_iocb) (struct scsi_qla_host *);
431 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
432 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
433 int (*get_sys_info) (struct scsi_qla_host *);
434 uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong);
435 void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t);
436 int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *);
437 int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t);
438 int (*idc_lock) (struct scsi_qla_host *);
439 void (*idc_unlock) (struct scsi_qla_host *);
440 void (*rom_lock_recovery) (struct scsi_qla_host *);
441 void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int);
442 void (*process_mailbox_interrupt) (struct scsi_qla_host *, int);
443 };
444
445 struct ql4_mdump_size_table {
446 uint32_t size;
447 uint32_t size_cmask_02;
448 uint32_t size_cmask_04;
449 uint32_t size_cmask_08;
450 uint32_t size_cmask_10;
451 uint32_t size_cmask_FF;
452 uint32_t version;
453 };
454
455 /*qla4xxx ipaddress configuration details */
456 struct ipaddress_config {
457 uint16_t ipv4_options;
458 uint16_t tcp_options;
459 uint16_t ipv4_vlan_tag;
460 uint8_t ipv4_addr_state;
461 uint8_t ip_address[IP_ADDR_LEN];
462 uint8_t subnet_mask[IP_ADDR_LEN];
463 uint8_t gateway[IP_ADDR_LEN];
464 uint32_t ipv6_options;
465 uint32_t ipv6_addl_options;
466 uint8_t ipv6_link_local_state;
467 uint8_t ipv6_addr0_state;
468 uint8_t ipv6_addr1_state;
469 uint8_t ipv6_default_router_state;
470 uint16_t ipv6_vlan_tag;
471 struct in6_addr ipv6_link_local_addr;
472 struct in6_addr ipv6_addr0;
473 struct in6_addr ipv6_addr1;
474 struct in6_addr ipv6_default_router_addr;
475 uint16_t eth_mtu_size;
476 uint16_t ipv4_port;
477 uint16_t ipv6_port;
478 uint8_t control;
479 uint16_t ipv6_tcp_options;
480 uint8_t tcp_wsf;
481 uint8_t ipv6_tcp_wsf;
482 uint8_t ipv4_tos;
483 uint8_t ipv4_cache_id;
484 uint8_t ipv6_cache_id;
485 uint8_t ipv4_alt_cid_len;
486 uint8_t ipv4_alt_cid[11];
487 uint8_t ipv4_vid_len;
488 uint8_t ipv4_vid[11];
489 uint8_t ipv4_ttl;
490 uint16_t ipv6_flow_lbl;
491 uint8_t ipv6_traffic_class;
492 uint8_t ipv6_hop_limit;
493 uint32_t ipv6_nd_reach_time;
494 uint32_t ipv6_nd_rexmit_timer;
495 uint32_t ipv6_nd_stale_timeout;
496 uint8_t ipv6_dup_addr_detect_count;
497 uint32_t ipv6_gw_advrt_mtu;
498 uint16_t def_timeout;
499 uint8_t abort_timer;
500 uint16_t iscsi_options;
501 uint16_t iscsi_max_pdu_size;
502 uint16_t iscsi_first_burst_len;
503 uint16_t iscsi_max_outstnd_r2t;
504 uint16_t iscsi_max_burst_len;
505 uint8_t iscsi_name[224];
506 };
507
508 #define QL4_CHAP_MAX_NAME_LEN 256
509 #define QL4_CHAP_MAX_SECRET_LEN 100
510 #define LOCAL_CHAP 0
511 #define BIDI_CHAP 1
512
513 struct ql4_chap_format {
514 u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN];
515 u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN];
516 u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN];
517 u8 target_secret[QL4_CHAP_MAX_SECRET_LEN];
518 u16 intr_chap_name_length;
519 u16 intr_secret_length;
520 u16 target_chap_name_length;
521 u16 target_secret_length;
522 };
523
524 struct ip_address_format {
525 u8 ip_type;
526 u8 ip_address[16];
527 };
528
529 struct ql4_conn_info {
530 u16 dest_port;
531 struct ip_address_format dest_ipaddr;
532 struct ql4_chap_format chap;
533 };
534
535 struct ql4_boot_session_info {
536 u8 target_name[224];
537 struct ql4_conn_info conn_list[1];
538 };
539
540 struct ql4_boot_tgt_info {
541 struct ql4_boot_session_info boot_pri_sess;
542 struct ql4_boot_session_info boot_sec_sess;
543 };
544
545 /*
546 * Linux Host Adapter structure
547 */
548 struct scsi_qla_host {
549 /* Linux adapter configuration data */
550 unsigned long flags;
551
552 #define AF_ONLINE 0 /* 0x00000001 */
553 #define AF_INIT_DONE 1 /* 0x00000002 */
554 #define AF_MBOX_COMMAND 2 /* 0x00000004 */
555 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
556 #define AF_ST_DISCOVERY_IN_PROGRESS 4 /* 0x00000010 */
557 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */
558 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
559 #define AF_LINK_UP 8 /* 0x00000100 */
560 #define AF_LOOPBACK 9 /* 0x00000200 */
561 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */
562 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */
563 #define AF_HA_REMOVAL 12 /* 0x00001000 */
564 #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */
565 #define AF_FW_RECOVERY 19 /* 0x00080000 */
566 #define AF_EEH_BUSY 20 /* 0x00100000 */
567 #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */
568 #define AF_BUILD_DDB_LIST 22 /* 0x00400000 */
569 #define AF_82XX_FW_DUMPED 24 /* 0x01000000 */
570 #define AF_8XXX_RST_OWNER 25 /* 0x02000000 */
571 #define AF_82XX_DUMP_READING 26 /* 0x04000000 */
572 #define AF_83XX_IOCB_INTR_ON 28 /* 0x10000000 */
573 #define AF_83XX_MBOX_INTR_ON 29 /* 0x20000000 */
574
575 unsigned long dpc_flags;
576
577 #define DPC_RESET_HA 1 /* 0x00000002 */
578 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
579 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
580 #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */
581 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */
582 #define DPC_ISNS_RESTART 7 /* 0x00000080 */
583 #define DPC_AEN 9 /* 0x00000200 */
584 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
585 #define DPC_LINK_CHANGED 18 /* 0x00040000 */
586 #define DPC_RESET_ACTIVE 20 /* 0x00100000 */
587 #define DPC_HA_UNRECOVERABLE 21 /* 0x00200000 ISP-82xx only*/
588 #define DPC_HA_NEED_QUIESCENT 22 /* 0x00400000 ISP-82xx only*/
589 #define DPC_POST_IDC_ACK 23 /* 0x00800000 */
590 #define DPC_RESTORE_ACB 24 /* 0x01000000 */
591 #define DPC_SYSFS_DDB_EXPORT 25 /* 0x02000000 */
592
593 struct Scsi_Host *host; /* pointer to host data */
594 uint32_t tot_ddbs;
595
596 uint16_t iocb_cnt;
597 uint16_t iocb_hiwat;
598
599 /* SRB cache. */
600 #define SRB_MIN_REQ 128
601 mempool_t *srb_mempool;
602
603 /* pci information */
604 struct pci_dev *pdev;
605
606 struct isp_reg __iomem *reg; /* Base I/O address */
607 unsigned long pio_address;
608 unsigned long pio_length;
609 #define MIN_IOBASE_LEN 0x100
610
611 uint16_t req_q_count;
612
613 unsigned long host_no;
614
615 /* NVRAM registers */
616 struct eeprom_data *nvram;
617 spinlock_t hardware_lock ____cacheline_aligned;
618 uint32_t eeprom_cmd_data;
619
620 /* Counters for general statistics */
621 uint64_t isr_count;
622 uint64_t adapter_error_count;
623 uint64_t device_error_count;
624 uint64_t total_io_count;
625 uint64_t total_mbytes_xferred;
626 uint64_t link_failure_count;
627 uint64_t invalid_crc_count;
628 uint32_t bytes_xfered;
629 uint32_t spurious_int_count;
630 uint32_t aborted_io_count;
631 uint32_t io_timeout_count;
632 uint32_t mailbox_timeout_count;
633 uint32_t seconds_since_last_intr;
634 uint32_t seconds_since_last_heartbeat;
635 uint32_t mac_index;
636
637 /* Info Needed for Management App */
638 /* --- From GetFwVersion --- */
639 uint32_t firmware_version[2];
640 uint32_t patch_number;
641 uint32_t build_number;
642 uint32_t board_id;
643
644 /* --- From Init_FW --- */
645 /* init_cb_t *init_cb; */
646 uint16_t firmware_options;
647 uint8_t alias[32];
648 uint8_t name_string[256];
649 uint8_t heartbeat_interval;
650
651 /* --- From FlashSysInfo --- */
652 uint8_t my_mac[MAC_ADDR_LEN];
653 uint8_t serial_number[16];
654 uint16_t port_num;
655 /* --- From GetFwState --- */
656 uint32_t firmware_state;
657 uint32_t addl_fw_state;
658
659 /* Linux kernel thread */
660 struct workqueue_struct *dpc_thread;
661 struct work_struct dpc_work;
662
663 /* Linux timer thread */
664 struct timer_list timer;
665 uint32_t timer_active;
666
667 /* Recovery Timers */
668 atomic_t check_relogin_timeouts;
669 uint32_t retry_reset_ha_cnt;
670 uint32_t isp_reset_timer; /* reset test timer */
671 uint32_t nic_reset_timer; /* simulated nic reset test timer */
672 int eh_start;
673 struct list_head free_srb_q;
674 uint16_t free_srb_q_count;
675 uint16_t num_srbs_allocated;
676
677 /* DMA Memory Block */
678 void *queues;
679 dma_addr_t queues_dma;
680 unsigned long queues_len;
681
682 #define MEM_ALIGN_VALUE \
683 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
684 sizeof(struct queue_entry))
685 /* request and response queue variables */
686 dma_addr_t request_dma;
687 struct queue_entry *request_ring;
688 struct queue_entry *request_ptr;
689 dma_addr_t response_dma;
690 struct queue_entry *response_ring;
691 struct queue_entry *response_ptr;
692 dma_addr_t shadow_regs_dma;
693 struct shadow_regs *shadow_regs;
694 uint16_t request_in; /* Current indexes. */
695 uint16_t request_out;
696 uint16_t response_in;
697 uint16_t response_out;
698
699 /* aen queue variables */
700 uint16_t aen_q_count; /* Number of available aen_q entries */
701 uint16_t aen_in; /* Current indexes */
702 uint16_t aen_out;
703 struct aen aen_q[MAX_AEN_ENTRIES];
704
705 struct ql4_aen_log aen_log;/* tracks all aens */
706
707 /* This mutex protects several threads to do mailbox commands
708 * concurrently.
709 */
710 struct mutex mbox_sem;
711
712 /* temporary mailbox status registers */
713 volatile uint8_t mbox_status_count;
714 volatile uint32_t mbox_status[MBOX_REG_COUNT];
715
716 /* FW ddb index map */
717 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
718
719 /* Saved srb for status continuation entry processing */
720 struct srb *status_srb;
721
722 uint8_t acb_version;
723
724 /* qla82xx specific fields */
725 struct device_reg_82xx __iomem *qla4_82xx_reg; /* Base I/O address */
726 unsigned long nx_pcibase; /* Base I/O address */
727 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */
728 unsigned long nx_db_wr_ptr; /* Door bell write pointer */
729 unsigned long first_page_group_start;
730 unsigned long first_page_group_end;
731
732 uint32_t crb_win;
733 uint32_t curr_window;
734 uint32_t ddr_mn_window;
735 unsigned long mn_win_crb;
736 unsigned long ms_win_crb;
737 int qdr_sn_window;
738 rwlock_t hw_lock;
739 uint16_t func_num;
740 int link_width;
741
742 struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
743 u32 nx_crb_mask;
744
745 uint8_t revision_id;
746 uint32_t fw_heartbeat_counter;
747
748 struct isp_operations *isp_ops;
749 struct ql82xx_hw_data hw;
750
751 uint32_t nx_dev_init_timeout;
752 uint32_t nx_reset_timeout;
753 void *fw_dump;
754 uint32_t fw_dump_size;
755 uint32_t fw_dump_capture_mask;
756 void *fw_dump_tmplt_hdr;
757 uint32_t fw_dump_tmplt_size;
758 uint32_t fw_dump_skip_size;
759
760 struct completion mbx_intr_comp;
761
762 struct ipaddress_config ip_config;
763 struct iscsi_iface *iface_ipv4;
764 struct iscsi_iface *iface_ipv6_0;
765 struct iscsi_iface *iface_ipv6_1;
766
767 /* --- From About Firmware --- */
768 struct about_fw_info fw_info;
769 uint32_t fw_uptime_secs; /* seconds elapsed since fw bootup */
770 uint32_t fw_uptime_msecs; /* milliseconds beyond elapsed seconds */
771 uint16_t def_timeout; /* Default login timeout */
772
773 uint32_t flash_state;
774 #define QLFLASH_WAITING 0
775 #define QLFLASH_READING 1
776 #define QLFLASH_WRITING 2
777 struct dma_pool *chap_dma_pool;
778 uint8_t *chap_list; /* CHAP table cache */
779 struct mutex chap_sem;
780
781 #define CHAP_DMA_BLOCK_SIZE 512
782 struct workqueue_struct *task_wq;
783 unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG];
784 #define SYSFS_FLAG_FW_SEL_BOOT 2
785 struct iscsi_boot_kset *boot_kset;
786 struct ql4_boot_tgt_info boot_tgt;
787 uint16_t phy_port_num;
788 uint16_t phy_port_cnt;
789 uint16_t iscsi_pci_func_cnt;
790 uint8_t model_name[16];
791 struct completion disable_acb_comp;
792 struct dma_pool *fw_ddb_dma_pool;
793 #define DDB_DMA_BLOCK_SIZE 512
794 uint16_t pri_ddb_idx;
795 uint16_t sec_ddb_idx;
796 int is_reset;
797 uint16_t temperature;
798
799 /* event work list */
800 struct list_head work_list;
801 spinlock_t work_lock;
802
803 /* mbox iocb */
804 #define MAX_MRB 128
805 struct mrb *active_mrb_array[MAX_MRB];
806 uint32_t mrb_index;
807
808 uint32_t *reg_tbl;
809 struct qla4_83xx_reset_template reset_tmplt;
810 struct device_reg_83xx __iomem *qla4_83xx_reg; /* Base I/O address
811 for ISP8324 and
812 and ISP8042 */
813 uint32_t pf_bit;
814 struct qla4_83xx_idc_information idc_info;
815 struct addr_ctrl_blk *saved_acb;
816 int notify_idc_comp;
817 int notify_link_up_comp;
818 int idc_extend_tmo;
819 struct completion idc_comp;
820 struct completion link_up_comp;
821 };
822
823 struct ql4_task_data {
824 struct scsi_qla_host *ha;
825 uint8_t iocb_req_cnt;
826 dma_addr_t data_dma;
827 void *req_buffer;
828 dma_addr_t req_dma;
829 uint32_t req_len;
830 void *resp_buffer;
831 dma_addr_t resp_dma;
832 uint32_t resp_len;
833 struct iscsi_task *task;
834 struct passthru_status sts;
835 struct work_struct task_work;
836 };
837
838 struct qla_endpoint {
839 struct Scsi_Host *host;
840 struct sockaddr_storage dst_addr;
841 };
842
843 struct qla_conn {
844 struct qla_endpoint *qla_ep;
845 };
846
is_ipv4_enabled(struct scsi_qla_host * ha)847 static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
848 {
849 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
850 }
851
is_ipv6_enabled(struct scsi_qla_host * ha)852 static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
853 {
854 return ((ha->ip_config.ipv6_options &
855 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
856 }
857
is_qla4010(struct scsi_qla_host * ha)858 static inline int is_qla4010(struct scsi_qla_host *ha)
859 {
860 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
861 }
862
is_qla4022(struct scsi_qla_host * ha)863 static inline int is_qla4022(struct scsi_qla_host *ha)
864 {
865 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
866 }
867
is_qla4032(struct scsi_qla_host * ha)868 static inline int is_qla4032(struct scsi_qla_host *ha)
869 {
870 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
871 }
872
is_qla40XX(struct scsi_qla_host * ha)873 static inline int is_qla40XX(struct scsi_qla_host *ha)
874 {
875 return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha);
876 }
877
is_qla8022(struct scsi_qla_host * ha)878 static inline int is_qla8022(struct scsi_qla_host *ha)
879 {
880 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
881 }
882
is_qla8032(struct scsi_qla_host * ha)883 static inline int is_qla8032(struct scsi_qla_host *ha)
884 {
885 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324;
886 }
887
is_qla8042(struct scsi_qla_host * ha)888 static inline int is_qla8042(struct scsi_qla_host *ha)
889 {
890 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042;
891 }
892
is_qla80XX(struct scsi_qla_host * ha)893 static inline int is_qla80XX(struct scsi_qla_host *ha)
894 {
895 return is_qla8022(ha) || is_qla8032(ha) || is_qla8042(ha);
896 }
897
is_aer_supported(struct scsi_qla_host * ha)898 static inline int is_aer_supported(struct scsi_qla_host *ha)
899 {
900 return ((ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022) ||
901 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324) ||
902 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042));
903 }
904
adapter_up(struct scsi_qla_host * ha)905 static inline int adapter_up(struct scsi_qla_host *ha)
906 {
907 return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
908 (test_bit(AF_LINK_UP, &ha->flags) != 0) &&
909 (!test_bit(AF_LOOPBACK, &ha->flags));
910 }
911
to_qla_host(struct Scsi_Host * shost)912 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
913 {
914 return (struct scsi_qla_host *)iscsi_host_priv(shost);
915 }
916
isp_semaphore(struct scsi_qla_host * ha)917 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
918 {
919 return (is_qla4010(ha) ?
920 &ha->reg->u1.isp4010.nvram :
921 &ha->reg->u1.isp4022.semaphore);
922 }
923
isp_nvram(struct scsi_qla_host * ha)924 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
925 {
926 return (is_qla4010(ha) ?
927 &ha->reg->u1.isp4010.nvram :
928 &ha->reg->u1.isp4022.nvram);
929 }
930
isp_ext_hw_conf(struct scsi_qla_host * ha)931 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
932 {
933 return (is_qla4010(ha) ?
934 &ha->reg->u2.isp4010.ext_hw_conf :
935 &ha->reg->u2.isp4022.p0.ext_hw_conf);
936 }
937
isp_port_status(struct scsi_qla_host * ha)938 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
939 {
940 return (is_qla4010(ha) ?
941 &ha->reg->u2.isp4010.port_status :
942 &ha->reg->u2.isp4022.p0.port_status);
943 }
944
isp_port_ctrl(struct scsi_qla_host * ha)945 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
946 {
947 return (is_qla4010(ha) ?
948 &ha->reg->u2.isp4010.port_ctrl :
949 &ha->reg->u2.isp4022.p0.port_ctrl);
950 }
951
isp_port_error_status(struct scsi_qla_host * ha)952 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
953 {
954 return (is_qla4010(ha) ?
955 &ha->reg->u2.isp4010.port_err_status :
956 &ha->reg->u2.isp4022.p0.port_err_status);
957 }
958
isp_gp_out(struct scsi_qla_host * ha)959 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
960 {
961 return (is_qla4010(ha) ?
962 &ha->reg->u2.isp4010.gp_out :
963 &ha->reg->u2.isp4022.p0.gp_out);
964 }
965
eeprom_ext_hw_conf_offset(struct scsi_qla_host * ha)966 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
967 {
968 return (is_qla4010(ha) ?
969 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
970 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
971 }
972
973 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
974 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
975 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
976
ql4xxx_lock_flash(struct scsi_qla_host * a)977 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
978 {
979 if (is_qla4010(a))
980 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
981 QL4010_FLASH_SEM_BITS);
982 else
983 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
984 (QL4022_RESOURCE_BITS_BASE_CODE |
985 (a->mac_index)) << 13);
986 }
987
ql4xxx_unlock_flash(struct scsi_qla_host * a)988 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
989 {
990 if (is_qla4010(a))
991 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
992 else
993 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
994 }
995
ql4xxx_lock_nvram(struct scsi_qla_host * a)996 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
997 {
998 if (is_qla4010(a))
999 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
1000 QL4010_NVRAM_SEM_BITS);
1001 else
1002 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
1003 (QL4022_RESOURCE_BITS_BASE_CODE |
1004 (a->mac_index)) << 10);
1005 }
1006
ql4xxx_unlock_nvram(struct scsi_qla_host * a)1007 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
1008 {
1009 if (is_qla4010(a))
1010 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
1011 else
1012 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
1013 }
1014
ql4xxx_lock_drvr(struct scsi_qla_host * a)1015 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
1016 {
1017 if (is_qla4010(a))
1018 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
1019 QL4010_DRVR_SEM_BITS);
1020 else
1021 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
1022 (QL4022_RESOURCE_BITS_BASE_CODE |
1023 (a->mac_index)) << 1);
1024 }
1025
ql4xxx_unlock_drvr(struct scsi_qla_host * a)1026 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
1027 {
1028 if (is_qla4010(a))
1029 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
1030 else
1031 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
1032 }
1033
ql4xxx_reset_active(struct scsi_qla_host * ha)1034 static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
1035 {
1036 return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
1037 test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
1038 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) ||
1039 test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) ||
1040 test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) ||
1041 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
1042
1043 }
1044
qla4_8xxx_rd_direct(struct scsi_qla_host * ha,const uint32_t crb_reg)1045 static inline int qla4_8xxx_rd_direct(struct scsi_qla_host *ha,
1046 const uint32_t crb_reg)
1047 {
1048 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]);
1049 }
1050
qla4_8xxx_wr_direct(struct scsi_qla_host * ha,const uint32_t crb_reg,const uint32_t value)1051 static inline void qla4_8xxx_wr_direct(struct scsi_qla_host *ha,
1052 const uint32_t crb_reg,
1053 const uint32_t value)
1054 {
1055 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value);
1056 }
1057
1058 /*---------------------------------------------------------------------------*/
1059
1060 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
1061
1062 #define INIT_ADAPTER 0
1063 #define RESET_ADAPTER 1
1064
1065 #define PRESERVE_DDB_LIST 0
1066 #define REBUILD_DDB_LIST 1
1067
1068 /* Defines for process_aen() */
1069 #define PROCESS_ALL_AENS 0
1070 #define FLUSH_DDB_CHANGED_AENS 1
1071
1072 /* Defines for udev events */
1073 #define QL4_UEVENT_CODE_FW_DUMP 0
1074
1075 #endif /*_QLA4XXX_H */
1076