1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __AMD_SHARED_H__ 24 #define __AMD_SHARED_H__ 25 26 #include <drm/amd_asic_type.h> 27 28 29 #define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */ 30 31 /* 32 * Chip flags 33 */ 34 enum amd_chip_flags { 35 AMD_ASIC_MASK = 0x0000ffffUL, 36 AMD_FLAGS_MASK = 0xffff0000UL, 37 AMD_IS_MOBILITY = 0x00010000UL, 38 AMD_IS_APU = 0x00020000UL, 39 AMD_IS_PX = 0x00040000UL, 40 AMD_EXP_HW_SUPPORT = 0x00080000UL, 41 }; 42 43 enum amd_apu_flags { 44 AMD_APU_IS_RAVEN = 0x00000001UL, 45 AMD_APU_IS_RAVEN2 = 0x00000002UL, 46 AMD_APU_IS_PICASSO = 0x00000004UL, 47 AMD_APU_IS_RENOIR = 0x00000008UL, 48 AMD_APU_IS_GREEN_SARDINE = 0x00000010UL, 49 }; 50 51 /** 52 * DOC: IP Blocks 53 * 54 * GPUs are composed of IP (intellectual property) blocks. These 55 * IP blocks provide various functionalities: display, graphics, 56 * video decode, etc. The IP blocks that comprise a particular GPU 57 * are listed in the GPU's respective SoC file. amdgpu_device.c 58 * acquires the list of IP blocks for the GPU in use on initialization. 59 * It can then operate on this list to perform standard driver operations 60 * such as: init, fini, suspend, resume, etc. 61 * 62 * 63 * IP block implementations are named using the following convention: 64 * <functionality>_v<version> (E.g.: gfx_v6_0). 65 */ 66 67 /** 68 * enum amd_ip_block_type - Used to classify IP blocks by functionality. 69 * 70 * @AMD_IP_BLOCK_TYPE_COMMON: GPU Family 71 * @AMD_IP_BLOCK_TYPE_GMC: Graphics Memory Controller 72 * @AMD_IP_BLOCK_TYPE_IH: Interrupt Handler 73 * @AMD_IP_BLOCK_TYPE_SMC: System Management Controller 74 * @AMD_IP_BLOCK_TYPE_PSP: Platform Security Processor 75 * @AMD_IP_BLOCK_TYPE_DCE: Display and Compositing Engine 76 * @AMD_IP_BLOCK_TYPE_GFX: Graphics and Compute Engine 77 * @AMD_IP_BLOCK_TYPE_SDMA: System DMA Engine 78 * @AMD_IP_BLOCK_TYPE_UVD: Unified Video Decoder 79 * @AMD_IP_BLOCK_TYPE_VCE: Video Compression Engine 80 * @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor 81 * @AMD_IP_BLOCK_TYPE_VCN: Video Core/Codec Next 82 * @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler 83 * @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine 84 */ 85 enum amd_ip_block_type { 86 AMD_IP_BLOCK_TYPE_COMMON, 87 AMD_IP_BLOCK_TYPE_GMC, 88 AMD_IP_BLOCK_TYPE_IH, 89 AMD_IP_BLOCK_TYPE_SMC, 90 AMD_IP_BLOCK_TYPE_PSP, 91 AMD_IP_BLOCK_TYPE_DCE, 92 AMD_IP_BLOCK_TYPE_GFX, 93 AMD_IP_BLOCK_TYPE_SDMA, 94 AMD_IP_BLOCK_TYPE_UVD, 95 AMD_IP_BLOCK_TYPE_VCE, 96 AMD_IP_BLOCK_TYPE_ACP, 97 AMD_IP_BLOCK_TYPE_VCN, 98 AMD_IP_BLOCK_TYPE_MES, 99 AMD_IP_BLOCK_TYPE_JPEG 100 }; 101 102 enum amd_clockgating_state { 103 AMD_CG_STATE_GATE = 0, 104 AMD_CG_STATE_UNGATE, 105 }; 106 107 108 enum amd_powergating_state { 109 AMD_PG_STATE_GATE = 0, 110 AMD_PG_STATE_UNGATE, 111 }; 112 113 114 /* CG flags */ 115 #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) 116 #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1) 117 #define AMD_CG_SUPPORT_GFX_CGCG (1 << 2) 118 #define AMD_CG_SUPPORT_GFX_CGLS (1 << 3) 119 #define AMD_CG_SUPPORT_GFX_CGTS (1 << 4) 120 #define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 121 #define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6) 122 #define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7) 123 #define AMD_CG_SUPPORT_MC_LS (1 << 8) 124 #define AMD_CG_SUPPORT_MC_MGCG (1 << 9) 125 #define AMD_CG_SUPPORT_SDMA_LS (1 << 10) 126 #define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11) 127 #define AMD_CG_SUPPORT_BIF_LS (1 << 12) 128 #define AMD_CG_SUPPORT_UVD_MGCG (1 << 13) 129 #define AMD_CG_SUPPORT_VCE_MGCG (1 << 14) 130 #define AMD_CG_SUPPORT_HDP_LS (1 << 15) 131 #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16) 132 #define AMD_CG_SUPPORT_ROM_MGCG (1 << 17) 133 #define AMD_CG_SUPPORT_DRM_LS (1 << 18) 134 #define AMD_CG_SUPPORT_BIF_MGCG (1 << 19) 135 #define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20) 136 #define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21) 137 #define AMD_CG_SUPPORT_DRM_MGCG (1 << 22) 138 #define AMD_CG_SUPPORT_DF_MGCG (1 << 23) 139 #define AMD_CG_SUPPORT_VCN_MGCG (1 << 24) 140 #define AMD_CG_SUPPORT_HDP_DS (1 << 25) 141 #define AMD_CG_SUPPORT_HDP_SD (1 << 26) 142 #define AMD_CG_SUPPORT_IH_CG (1 << 27) 143 #define AMD_CG_SUPPORT_ATHUB_LS (1 << 28) 144 #define AMD_CG_SUPPORT_ATHUB_MGCG (1 << 29) 145 #define AMD_CG_SUPPORT_JPEG_MGCG (1 << 30) 146 /* PG flags */ 147 #define AMD_PG_SUPPORT_GFX_PG (1 << 0) 148 #define AMD_PG_SUPPORT_GFX_SMG (1 << 1) 149 #define AMD_PG_SUPPORT_GFX_DMG (1 << 2) 150 #define AMD_PG_SUPPORT_UVD (1 << 3) 151 #define AMD_PG_SUPPORT_VCE (1 << 4) 152 #define AMD_PG_SUPPORT_CP (1 << 5) 153 #define AMD_PG_SUPPORT_GDS (1 << 6) 154 #define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7) 155 #define AMD_PG_SUPPORT_SDMA (1 << 8) 156 #define AMD_PG_SUPPORT_ACP (1 << 9) 157 #define AMD_PG_SUPPORT_SAMU (1 << 10) 158 #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11) 159 #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) 160 #define AMD_PG_SUPPORT_MMHUB (1 << 13) 161 #define AMD_PG_SUPPORT_VCN (1 << 14) 162 #define AMD_PG_SUPPORT_VCN_DPG (1 << 15) 163 #define AMD_PG_SUPPORT_ATHUB (1 << 16) 164 #define AMD_PG_SUPPORT_JPEG (1 << 17) 165 166 /** 167 * enum PP_FEATURE_MASK - Used to mask power play features. 168 * 169 * @PP_SCLK_DPM_MASK: Dynamic adjustment of the system (graphics) clock. 170 * @PP_MCLK_DPM_MASK: Dynamic adjustment of the memory clock. 171 * @PP_PCIE_DPM_MASK: Dynamic adjustment of PCIE clocks and lanes. 172 * @PP_SCLK_DEEP_SLEEP_MASK: System (graphics) clock deep sleep. 173 * @PP_POWER_CONTAINMENT_MASK: Power containment. 174 * @PP_UVD_HANDSHAKE_MASK: Unified video decoder handshake. 175 * @PP_SMC_VOLTAGE_CONTROL_MASK: Dynamic voltage control. 176 * @PP_VBI_TIME_SUPPORT_MASK: Vertical blank interval support. 177 * @PP_ULV_MASK: Ultra low voltage. 178 * @PP_ENABLE_GFX_CG_THRU_SMU: SMU control of GFX engine clockgating. 179 * @PP_CLOCK_STRETCH_MASK: Clock stretching. 180 * @PP_OD_FUZZY_FAN_CONTROL_MASK: Overdrive fuzzy fan control. 181 * @PP_SOCCLK_DPM_MASK: Dynamic adjustment of the SoC clock. 182 * @PP_DCEFCLK_DPM_MASK: Dynamic adjustment of the Display Controller Engine Fabric clock. 183 * @PP_OVERDRIVE_MASK: Over- and under-clocking support. 184 * @PP_GFXOFF_MASK: Dynamic graphics engine power control. 185 * @PP_ACG_MASK: Adaptive clock generator. 186 * @PP_STUTTER_MODE: Stutter mode. 187 * @PP_AVFS_MASK: Adaptive voltage and frequency scaling. 188 * 189 * To override these settings on boot, append amdgpu.ppfeaturemask=<mask> to 190 * the kernel's command line parameters. This is usually done through a system's 191 * boot loader (E.g. GRUB). If manually loading the driver, pass 192 * ppfeaturemask=<mask> as a modprobe parameter. 193 */ 194 enum PP_FEATURE_MASK { 195 PP_SCLK_DPM_MASK = 0x1, 196 PP_MCLK_DPM_MASK = 0x2, 197 PP_PCIE_DPM_MASK = 0x4, 198 PP_SCLK_DEEP_SLEEP_MASK = 0x8, 199 PP_POWER_CONTAINMENT_MASK = 0x10, 200 PP_UVD_HANDSHAKE_MASK = 0x20, 201 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40, 202 PP_VBI_TIME_SUPPORT_MASK = 0x80, 203 PP_ULV_MASK = 0x100, 204 PP_ENABLE_GFX_CG_THRU_SMU = 0x200, 205 PP_CLOCK_STRETCH_MASK = 0x400, 206 PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800, 207 PP_SOCCLK_DPM_MASK = 0x1000, 208 PP_DCEFCLK_DPM_MASK = 0x2000, 209 PP_OVERDRIVE_MASK = 0x4000, 210 PP_GFXOFF_MASK = 0x8000, 211 PP_ACG_MASK = 0x10000, 212 PP_STUTTER_MODE = 0x20000, 213 PP_AVFS_MASK = 0x40000, 214 }; 215 216 enum DC_FEATURE_MASK { 217 DC_FBC_MASK = 0x1, 218 DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2, 219 DC_DISABLE_FRACTIONAL_PWM_MASK = 0x4, 220 DC_PSR_MASK = 0x8, 221 }; 222 223 enum DC_DEBUG_MASK { 224 DC_DISABLE_PIPE_SPLIT = 0x1, 225 DC_DISABLE_STUTTER = 0x2, 226 DC_DISABLE_DSC = 0x4, 227 DC_DISABLE_CLOCK_GATING = 0x8 228 }; 229 230 enum amd_dpm_forced_level; 231 232 /** 233 * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks 234 * @name: Name of IP block 235 * @early_init: sets up early driver state (pre sw_init), 236 * does not configure hw - Optional 237 * @late_init: sets up late driver/hw state (post hw_init) - Optional 238 * @sw_init: sets up driver state, does not configure hw 239 * @sw_fini: tears down driver state, does not configure hw 240 * @hw_init: sets up the hw state 241 * @hw_fini: tears down the hw state 242 * @late_fini: final cleanup 243 * @suspend: handles IP specific hw/sw changes for suspend 244 * @resume: handles IP specific hw/sw changes for resume 245 * @is_idle: returns current IP block idle status 246 * @wait_for_idle: poll for idle 247 * @check_soft_reset: check soft reset the IP block 248 * @pre_soft_reset: pre soft reset the IP block 249 * @soft_reset: soft reset the IP block 250 * @post_soft_reset: post soft reset the IP block 251 * @set_clockgating_state: enable/disable cg for the IP block 252 * @set_powergating_state: enable/disable pg for the IP block 253 * @get_clockgating_state: get current clockgating status 254 * @enable_umd_pstate: enable UMD powerstate 255 * 256 * These hooks provide an interface for controlling the operational state 257 * of IP blocks. After acquiring a list of IP blocks for the GPU in use, 258 * the driver can make chip-wide state changes by walking this list and 259 * making calls to hooks from each IP block. This list is ordered to ensure 260 * that the driver initializes the IP blocks in a safe sequence. 261 */ 262 struct amd_ip_funcs { 263 char *name; 264 int (*early_init)(void *handle); 265 int (*late_init)(void *handle); 266 int (*sw_init)(void *handle); 267 int (*sw_fini)(void *handle); 268 int (*hw_init)(void *handle); 269 int (*hw_fini)(void *handle); 270 void (*late_fini)(void *handle); 271 int (*suspend)(void *handle); 272 int (*resume)(void *handle); 273 bool (*is_idle)(void *handle); 274 int (*wait_for_idle)(void *handle); 275 bool (*check_soft_reset)(void *handle); 276 int (*pre_soft_reset)(void *handle); 277 int (*soft_reset)(void *handle); 278 int (*post_soft_reset)(void *handle); 279 int (*set_clockgating_state)(void *handle, 280 enum amd_clockgating_state state); 281 int (*set_powergating_state)(void *handle, 282 enum amd_powergating_state state); 283 void (*get_clockgating_state)(void *handle, u32 *flags); 284 int (*enable_umd_pstate)(void *handle, enum amd_dpm_forced_level *level); 285 }; 286 287 288 #endif /* __AMD_SHARED_H__ */ 289