1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2017-2020 Broadcom. All Rights Reserved. The term *
5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
7 * EMULEX and SLI are trademarks of Emulex. *
8 * www.broadcom.com *
9 * *
10 * This program is free software; you can redistribute it and/or *
11 * modify it under the terms of version 2 of the GNU General *
12 * Public License as published by the Free Software Foundation. *
13 * This program is distributed in the hope that it will be useful. *
14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18 * TO BE LEGALLY INVALID. See the GNU General Public License for *
19 * more details, a copy of which can be found in the file COPYING *
20 * included with this package. *
21 *******************************************************************/
22
23 #define FDMI_DID 0xfffffaU
24 #define NameServer_DID 0xfffffcU
25 #define Fabric_Cntl_DID 0xfffffdU
26 #define Fabric_DID 0xfffffeU
27 #define Bcast_DID 0xffffffU
28 #define Mask_DID 0xffffffU
29 #define CT_DID_MASK 0xffff00U
30 #define Fabric_DID_MASK 0xfff000U
31 #define WELL_KNOWN_DID_MASK 0xfffff0U
32
33 #define PT2PT_LocalID 1
34 #define PT2PT_RemoteID 2
35
36 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
37 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
38 #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */
39 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
40
41 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
42 0 */
43
44 #define FCELSSIZE 1024 /* maximum ELS transfer size */
45
46 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
47 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
48 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
49
50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
57 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
58 #define SLI2_IOCB_CMD_R3_ENTRIES 0
59 #define SLI2_IOCB_RSP_R3_ENTRIES 0
60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62
63 #define SLI2_IOCB_CMD_SIZE 32
64 #define SLI2_IOCB_RSP_SIZE 32
65 #define SLI3_IOCB_CMD_SIZE 128
66 #define SLI3_IOCB_RSP_SIZE 64
67
68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
70
71 /* vendor ID used in SCSI netlink calls */
72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
73
74 #define FW_REV_STR_SIZE 32
75 /* Common Transport structures and definitions */
76
77 union CtRevisionId {
78 /* Structure is in Big Endian format */
79 struct {
80 uint32_t Revision:8;
81 uint32_t InId:24;
82 } bits;
83 uint32_t word;
84 };
85
86 union CtCommandResponse {
87 /* Structure is in Big Endian format */
88 struct {
89 uint32_t CmdRsp:16;
90 uint32_t Size:16;
91 } bits;
92 uint32_t word;
93 };
94
95 /* FC4 Feature bits for RFF_ID */
96 #define FC4_FEATURE_TARGET 0x1
97 #define FC4_FEATURE_INIT 0x2
98 #define FC4_FEATURE_NVME_DISC 0x4
99
100 struct lpfc_sli_ct_request {
101 /* Structure is in Big Endian format */
102 union CtRevisionId RevisionId;
103 uint8_t FsType;
104 uint8_t FsSubType;
105 uint8_t Options;
106 uint8_t Rsrvd1;
107 union CtCommandResponse CommandResponse;
108 uint8_t Rsrvd2;
109 uint8_t ReasonCode;
110 uint8_t Explanation;
111 uint8_t VendorUnique;
112 #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */
113
114 union {
115 uint32_t PortID;
116 struct gid {
117 uint8_t PortType; /* for GID_PT requests */
118 #define GID_PT_N_PORT 1
119 uint8_t DomainScope;
120 uint8_t AreaScope;
121 uint8_t Fc4Type; /* for GID_FT requests */
122 } gid;
123 struct gid_ff {
124 uint8_t Flags;
125 uint8_t DomainScope;
126 uint8_t AreaScope;
127 uint8_t rsvd1;
128 uint8_t rsvd2;
129 uint8_t rsvd3;
130 uint8_t Fc4FBits;
131 uint8_t Fc4Type;
132 } gid_ff;
133 struct rft {
134 uint32_t PortId; /* For RFT_ID requests */
135
136 #ifdef __BIG_ENDIAN_BITFIELD
137 uint32_t rsvd0:16;
138 uint32_t rsvd1:7;
139 uint32_t fcpReg:1; /* Type 8 */
140 uint32_t rsvd2:2;
141 uint32_t ipReg:1; /* Type 5 */
142 uint32_t rsvd3:5;
143 #else /* __LITTLE_ENDIAN_BITFIELD */
144 uint32_t rsvd0:16;
145 uint32_t fcpReg:1; /* Type 8 */
146 uint32_t rsvd1:7;
147 uint32_t rsvd3:5;
148 uint32_t ipReg:1; /* Type 5 */
149 uint32_t rsvd2:2;
150 #endif
151
152 uint32_t rsvd[7];
153 } rft;
154 struct rnn {
155 uint32_t PortId; /* For RNN_ID requests */
156 uint8_t wwnn[8];
157 } rnn;
158 struct rsnn { /* For RSNN_ID requests */
159 uint8_t wwnn[8];
160 uint8_t len;
161 uint8_t symbname[255];
162 } rsnn;
163 struct da_id { /* For DA_ID requests */
164 uint32_t port_id;
165 } da_id;
166 struct rspn { /* For RSPN_ID requests */
167 uint32_t PortId;
168 uint8_t len;
169 uint8_t symbname[255];
170 } rspn;
171 struct gff {
172 uint32_t PortId;
173 } gff;
174 struct gff_acc {
175 uint8_t fbits[128];
176 } gff_acc;
177 struct gft {
178 uint32_t PortId;
179 } gft;
180 struct gft_acc {
181 uint32_t fc4_types[8];
182 } gft_acc;
183 #define FCP_TYPE_FEATURE_OFFSET 7
184 struct rff {
185 uint32_t PortId;
186 uint8_t reserved[2];
187 uint8_t fbits;
188 uint8_t type_code; /* type=8 for FCP */
189 } rff;
190 } un;
191 };
192
193 #define LPFC_MAX_CT_SIZE (60 * 4096)
194
195 #define SLI_CT_REVISION 1
196 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
197 sizeof(struct gid))
198 #define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
199 sizeof(struct gid_ff))
200 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
201 sizeof(struct gff))
202 #define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
203 sizeof(struct gft))
204 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
205 sizeof(struct rft))
206 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
207 sizeof(struct rff))
208 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
209 sizeof(struct rnn))
210 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
211 sizeof(struct rsnn))
212 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
213 sizeof(struct da_id))
214 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
215 sizeof(struct rspn))
216
217 /*
218 * FsType Definitions
219 */
220
221 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
222 #define SLI_CT_TIME_SERVICE 0xFB
223 #define SLI_CT_DIRECTORY_SERVICE 0xFC
224 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
225
226 /*
227 * Directory Service Subtypes
228 */
229
230 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
231
232 /*
233 * Response Codes
234 */
235
236 #define SLI_CT_RESPONSE_FS_RJT 0x8001
237 #define SLI_CT_RESPONSE_FS_ACC 0x8002
238
239 /*
240 * Reason Codes
241 */
242
243 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
244 #define SLI_CT_INVALID_COMMAND 0x01
245 #define SLI_CT_INVALID_VERSION 0x02
246 #define SLI_CT_LOGICAL_ERROR 0x03
247 #define SLI_CT_INVALID_IU_SIZE 0x04
248 #define SLI_CT_LOGICAL_BUSY 0x05
249 #define SLI_CT_PROTOCOL_ERROR 0x07
250 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
251 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
252 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
253 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
254 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
255 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
256 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
257 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
258 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
259 #define SLI_CT_VENDOR_UNIQUE 0xff
260
261 /*
262 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
263 */
264
265 #define SLI_CT_NO_PORT_ID 0x01
266 #define SLI_CT_NO_PORT_NAME 0x02
267 #define SLI_CT_NO_NODE_NAME 0x03
268 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
269 #define SLI_CT_NO_IP_ADDRESS 0x05
270 #define SLI_CT_NO_IPA 0x06
271 #define SLI_CT_NO_FC4_TYPES 0x07
272 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
273 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
274 #define SLI_CT_NO_PORT_TYPE 0x0A
275 #define SLI_CT_ACCESS_DENIED 0x10
276 #define SLI_CT_INVALID_PORT_ID 0x11
277 #define SLI_CT_DATABASE_EMPTY 0x12
278
279 /*
280 * Name Server Command Codes
281 */
282
283 #define SLI_CTNS_GA_NXT 0x0100
284 #define SLI_CTNS_GPN_ID 0x0112
285 #define SLI_CTNS_GNN_ID 0x0113
286 #define SLI_CTNS_GCS_ID 0x0114
287 #define SLI_CTNS_GFT_ID 0x0117
288 #define SLI_CTNS_GSPN_ID 0x0118
289 #define SLI_CTNS_GPT_ID 0x011A
290 #define SLI_CTNS_GFF_ID 0x011F
291 #define SLI_CTNS_GID_PN 0x0121
292 #define SLI_CTNS_GID_NN 0x0131
293 #define SLI_CTNS_GIP_NN 0x0135
294 #define SLI_CTNS_GIPA_NN 0x0136
295 #define SLI_CTNS_GSNN_NN 0x0139
296 #define SLI_CTNS_GNN_IP 0x0153
297 #define SLI_CTNS_GIPA_IP 0x0156
298 #define SLI_CTNS_GID_FT 0x0171
299 #define SLI_CTNS_GID_FF 0x01F1
300 #define SLI_CTNS_GID_PT 0x01A1
301 #define SLI_CTNS_RPN_ID 0x0212
302 #define SLI_CTNS_RNN_ID 0x0213
303 #define SLI_CTNS_RCS_ID 0x0214
304 #define SLI_CTNS_RFT_ID 0x0217
305 #define SLI_CTNS_RSPN_ID 0x0218
306 #define SLI_CTNS_RPT_ID 0x021A
307 #define SLI_CTNS_RFF_ID 0x021F
308 #define SLI_CTNS_RIP_NN 0x0235
309 #define SLI_CTNS_RIPA_NN 0x0236
310 #define SLI_CTNS_RSNN_NN 0x0239
311 #define SLI_CTNS_DA_ID 0x0300
312
313 /*
314 * Port Types
315 */
316
317 #define SLI_CTPT_N_PORT 0x01
318 #define SLI_CTPT_NL_PORT 0x02
319 #define SLI_CTPT_FNL_PORT 0x03
320 #define SLI_CTPT_IP 0x04
321 #define SLI_CTPT_FCP 0x08
322 #define SLI_CTPT_NVME 0x28
323 #define SLI_CTPT_NX_PORT 0x7F
324 #define SLI_CTPT_F_PORT 0x81
325 #define SLI_CTPT_FL_PORT 0x82
326 #define SLI_CTPT_E_PORT 0x84
327
328 #define SLI_CT_LAST_ENTRY 0x80000000
329
330 /* Fibre Channel Service Parameter definitions */
331
332 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
333 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
334 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
335 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
336
337 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
338 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
339 #define FC_PH3 0x20 /* FC-PH-3 version */
340
341 #define FF_FRAME_SIZE 2048
342
343 struct lpfc_name {
344 union {
345 struct {
346 #ifdef __BIG_ENDIAN_BITFIELD
347 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
348 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
349 8:11 of IEEE ext */
350 #else /* __LITTLE_ENDIAN_BITFIELD */
351 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
352 8:11 of IEEE ext */
353 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
354 #endif
355
356 #define NAME_IEEE 0x1 /* IEEE name - nameType */
357 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
358 #define NAME_FC_TYPE 0x3 /* FC native name type */
359 #define NAME_IP_TYPE 0x4 /* IP address */
360 #define NAME_CCITT_TYPE 0xC
361 #define NAME_CCITT_GR_TYPE 0xE
362 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
363 extended Lsb */
364 uint8_t IEEE[6]; /* FC IEEE address */
365 } s;
366 uint8_t wwn[8];
367 uint64_t name;
368 } u;
369 };
370
371 struct csp {
372 uint8_t fcphHigh; /* FC Word 0, byte 0 */
373 uint8_t fcphLow;
374 uint8_t bbCreditMsb;
375 uint8_t bbCreditLsb; /* FC Word 0, byte 3 */
376
377 /*
378 * Word 1 Bit 31 in common service parameter is overloaded.
379 * Word 1 Bit 31 in FLOGI request is multiple NPort request
380 * Word 1 Bit 31 in FLOGI response is clean address bit
381 */
382 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
383 /*
384 * Word 1 Bit 30 in common service parameter is overloaded.
385 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
386 * Word 1 Bit 30 in PLOGI request is random offset
387 */
388 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */
389 /*
390 * Word 1 Bit 29 in common service parameter is overloaded.
391 * Word 1 Bit 29 in FLOGI response is multiple NPort assignment
392 * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level
393 */
394 #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */
395 #ifdef __BIG_ENDIAN_BITFIELD
396 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
397 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
398 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
399 uint16_t fPort:1; /* FC Word 1, bit 28 */
400 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
401 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
402 uint16_t multicast:1; /* FC Word 1, bit 25 */
403 uint16_t broadcast:1; /* FC Word 1, bit 24 */
404
405 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
406 uint16_t simplex:1; /* FC Word 1, bit 22 */
407 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
408 uint16_t dhd:1; /* FC Word 1, bit 18 */
409 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
410 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
411 #else /* __LITTLE_ENDIAN_BITFIELD */
412 uint16_t broadcast:1; /* FC Word 1, bit 24 */
413 uint16_t multicast:1; /* FC Word 1, bit 25 */
414 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
415 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
416 uint16_t fPort:1; /* FC Word 1, bit 28 */
417 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
418 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
419 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
420
421 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
422 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
423 uint16_t dhd:1; /* FC Word 1, bit 18 */
424 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
425 uint16_t simplex:1; /* FC Word 1, bit 22 */
426 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
427 #endif
428
429 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
430 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
431 union {
432 struct {
433 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
434
435 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
436 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
437
438 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
439 } nPort;
440 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
441 } w2;
442
443 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
444 };
445
446 struct class_parms {
447 #ifdef __BIG_ENDIAN_BITFIELD
448 uint8_t classValid:1; /* FC Word 0, bit 31 */
449 uint8_t intermix:1; /* FC Word 0, bit 30 */
450 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
451 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
452 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
453 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
454 #else /* __LITTLE_ENDIAN_BITFIELD */
455 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
456 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
457 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
458 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
459 uint8_t intermix:1; /* FC Word 0, bit 30 */
460 uint8_t classValid:1; /* FC Word 0, bit 31 */
461
462 #endif
463
464 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
465
466 #ifdef __BIG_ENDIAN_BITFIELD
467 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
468 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
469 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
470 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
471 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
472 #else /* __LITTLE_ENDIAN_BITFIELD */
473 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
474 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
475 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
476 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
477 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
478 #endif
479
480 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
481
482 #ifdef __BIG_ENDIAN_BITFIELD
483 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
484 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
485 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
486 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
487 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
488 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
489 #else /* __LITTLE_ENDIAN_BITFIELD */
490 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
491 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
492 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
493 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
494 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
495 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
496 #endif
497
498 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
499 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
500 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
501
502 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
503 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
504 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
505 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
506
507 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
508 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
509 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
510 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
511 };
512
513 #define FAPWWN_KEY_VENDOR 0x42524344 /*valid vendor version fawwpn key*/
514
515 struct serv_parm { /* Structure is in Big Endian format */
516 struct csp cmn;
517 struct lpfc_name portName;
518 struct lpfc_name nodeName;
519 struct class_parms cls1;
520 struct class_parms cls2;
521 struct class_parms cls3;
522 struct class_parms cls4;
523 union {
524 uint8_t vendorVersion[16];
525 struct {
526 uint32_t vid;
527 #define LPFC_VV_EMLX_ID 0x454d4c58 /* EMLX */
528 uint32_t flags;
529 #define LPFC_VV_SUPPRESS_RSP 1
530 } vv;
531 } un;
532 };
533
534 /*
535 * Virtual Fabric Tagging Header
536 */
537 struct fc_vft_header {
538 uint32_t word0;
539 #define fc_vft_hdr_r_ctl_SHIFT 24
540 #define fc_vft_hdr_r_ctl_MASK 0xFF
541 #define fc_vft_hdr_r_ctl_WORD word0
542 #define fc_vft_hdr_ver_SHIFT 22
543 #define fc_vft_hdr_ver_MASK 0x3
544 #define fc_vft_hdr_ver_WORD word0
545 #define fc_vft_hdr_type_SHIFT 18
546 #define fc_vft_hdr_type_MASK 0xF
547 #define fc_vft_hdr_type_WORD word0
548 #define fc_vft_hdr_e_SHIFT 16
549 #define fc_vft_hdr_e_MASK 0x1
550 #define fc_vft_hdr_e_WORD word0
551 #define fc_vft_hdr_priority_SHIFT 13
552 #define fc_vft_hdr_priority_MASK 0x7
553 #define fc_vft_hdr_priority_WORD word0
554 #define fc_vft_hdr_vf_id_SHIFT 1
555 #define fc_vft_hdr_vf_id_MASK 0xFFF
556 #define fc_vft_hdr_vf_id_WORD word0
557 uint32_t word1;
558 #define fc_vft_hdr_hopct_SHIFT 24
559 #define fc_vft_hdr_hopct_MASK 0xFF
560 #define fc_vft_hdr_hopct_WORD word1
561 };
562
563 #include <uapi/scsi/fc/fc_els.h>
564
565 /*
566 * Extended Link Service LS_COMMAND codes (Payload Word 0)
567 */
568 #ifdef __BIG_ENDIAN_BITFIELD
569 #define ELS_CMD_MASK 0xffff0000
570 #define ELS_RSP_MASK 0xff000000
571 #define ELS_CMD_LS_RJT 0x01000000
572 #define ELS_CMD_ACC 0x02000000
573 #define ELS_CMD_PLOGI 0x03000000
574 #define ELS_CMD_FLOGI 0x04000000
575 #define ELS_CMD_LOGO 0x05000000
576 #define ELS_CMD_ABTX 0x06000000
577 #define ELS_CMD_RCS 0x07000000
578 #define ELS_CMD_RES 0x08000000
579 #define ELS_CMD_RSS 0x09000000
580 #define ELS_CMD_RSI 0x0A000000
581 #define ELS_CMD_ESTS 0x0B000000
582 #define ELS_CMD_ESTC 0x0C000000
583 #define ELS_CMD_ADVC 0x0D000000
584 #define ELS_CMD_RTV 0x0E000000
585 #define ELS_CMD_RLS 0x0F000000
586 #define ELS_CMD_ECHO 0x10000000
587 #define ELS_CMD_TEST 0x11000000
588 #define ELS_CMD_RRQ 0x12000000
589 #define ELS_CMD_REC 0x13000000
590 #define ELS_CMD_RDP 0x18000000
591 #define ELS_CMD_RDF 0x19000000
592 #define ELS_CMD_PRLI 0x20100014
593 #define ELS_CMD_NVMEPRLI 0x20140018
594 #define ELS_CMD_PRLO 0x21100014
595 #define ELS_CMD_PRLO_ACC 0x02100014
596 #define ELS_CMD_PDISC 0x50000000
597 #define ELS_CMD_FDISC 0x51000000
598 #define ELS_CMD_ADISC 0x52000000
599 #define ELS_CMD_FARP 0x54000000
600 #define ELS_CMD_FARPR 0x55000000
601 #define ELS_CMD_RPL 0x57000000
602 #define ELS_CMD_FAN 0x60000000
603 #define ELS_CMD_RSCN 0x61040000
604 #define ELS_CMD_RSCN_XMT 0x61040008
605 #define ELS_CMD_SCR 0x62000000
606 #define ELS_CMD_RNID 0x78000000
607 #define ELS_CMD_LIRR 0x7A000000
608 #define ELS_CMD_LCB 0x81000000
609 #define ELS_CMD_FPIN 0x16000000
610 #else /* __LITTLE_ENDIAN_BITFIELD */
611 #define ELS_CMD_MASK 0xffff
612 #define ELS_RSP_MASK 0xff
613 #define ELS_CMD_LS_RJT 0x01
614 #define ELS_CMD_ACC 0x02
615 #define ELS_CMD_PLOGI 0x03
616 #define ELS_CMD_FLOGI 0x04
617 #define ELS_CMD_LOGO 0x05
618 #define ELS_CMD_ABTX 0x06
619 #define ELS_CMD_RCS 0x07
620 #define ELS_CMD_RES 0x08
621 #define ELS_CMD_RSS 0x09
622 #define ELS_CMD_RSI 0x0A
623 #define ELS_CMD_ESTS 0x0B
624 #define ELS_CMD_ESTC 0x0C
625 #define ELS_CMD_ADVC 0x0D
626 #define ELS_CMD_RTV 0x0E
627 #define ELS_CMD_RLS 0x0F
628 #define ELS_CMD_ECHO 0x10
629 #define ELS_CMD_TEST 0x11
630 #define ELS_CMD_RRQ 0x12
631 #define ELS_CMD_REC 0x13
632 #define ELS_CMD_RDP 0x18
633 #define ELS_CMD_RDF 0x19
634 #define ELS_CMD_PRLI 0x14001020
635 #define ELS_CMD_NVMEPRLI 0x18001420
636 #define ELS_CMD_PRLO 0x14001021
637 #define ELS_CMD_PRLO_ACC 0x14001002
638 #define ELS_CMD_PDISC 0x50
639 #define ELS_CMD_FDISC 0x51
640 #define ELS_CMD_ADISC 0x52
641 #define ELS_CMD_FARP 0x54
642 #define ELS_CMD_FARPR 0x55
643 #define ELS_CMD_RPL 0x57
644 #define ELS_CMD_FAN 0x60
645 #define ELS_CMD_RSCN 0x0461
646 #define ELS_CMD_RSCN_XMT 0x08000461
647 #define ELS_CMD_SCR 0x62
648 #define ELS_CMD_RNID 0x78
649 #define ELS_CMD_LIRR 0x7A
650 #define ELS_CMD_LCB 0x81
651 #define ELS_CMD_FPIN ELS_FPIN
652 #endif
653
654 /*
655 * LS_RJT Payload Definition
656 */
657
658 struct ls_rjt { /* Structure is in Big Endian format */
659 union {
660 uint32_t lsRjtError;
661 struct {
662 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
663
664 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
665 /* LS_RJT reason codes */
666 #define LSRJT_INVALID_CMD 0x01
667 #define LSRJT_LOGICAL_ERR 0x03
668 #define LSRJT_LOGICAL_BSY 0x05
669 #define LSRJT_PROTOCOL_ERR 0x07
670 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
671 #define LSRJT_CMD_UNSUPPORTED 0x0B
672 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
673
674 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
675 /* LS_RJT reason explanation */
676 #define LSEXP_NOTHING_MORE 0x00
677 #define LSEXP_SPARM_OPTIONS 0x01
678 #define LSEXP_SPARM_ICTL 0x03
679 #define LSEXP_SPARM_RCTL 0x05
680 #define LSEXP_SPARM_RCV_SIZE 0x07
681 #define LSEXP_SPARM_CONCUR_SEQ 0x09
682 #define LSEXP_SPARM_CREDIT 0x0B
683 #define LSEXP_INVALID_PNAME 0x0D
684 #define LSEXP_INVALID_NNAME 0x0E
685 #define LSEXP_INVALID_CSP 0x0F
686 #define LSEXP_INVALID_ASSOC_HDR 0x11
687 #define LSEXP_ASSOC_HDR_REQ 0x13
688 #define LSEXP_INVALID_O_SID 0x15
689 #define LSEXP_INVALID_OX_RX 0x17
690 #define LSEXP_CMD_IN_PROGRESS 0x19
691 #define LSEXP_PORT_LOGIN_REQ 0x1E
692 #define LSEXP_INVALID_NPORT_ID 0x1F
693 #define LSEXP_INVALID_SEQ_ID 0x21
694 #define LSEXP_INVALID_XCHG 0x23
695 #define LSEXP_INACTIVE_XCHG 0x25
696 #define LSEXP_RQ_REQUIRED 0x27
697 #define LSEXP_OUT_OF_RESOURCE 0x29
698 #define LSEXP_CANT_GIVE_DATA 0x2A
699 #define LSEXP_REQ_UNSUPPORTED 0x2C
700 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
701 } b;
702 } un;
703 };
704
705 /*
706 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
707 */
708
709 typedef struct _LOGO { /* Structure is in Big Endian format */
710 union {
711 uint32_t nPortId32; /* Access nPortId as a word */
712 struct {
713 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
714 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
715 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
716 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
717 } b;
718 } un;
719 struct lpfc_name portName; /* N_port name field */
720 } LOGO;
721
722 /*
723 * FCP Login (PRLI Request / ACC) Payload Definition
724 */
725
726 #define PRLX_PAGE_LEN 0x10
727 #define TPRLO_PAGE_LEN 0x14
728
729 typedef struct _PRLI { /* Structure is in Big Endian format */
730 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
731
732 #define PRLI_FCP_TYPE 0x08
733 #define PRLI_NVME_TYPE 0x28
734 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
735
736 #ifdef __BIG_ENDIAN_BITFIELD
737 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
738 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
739 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
740
741 /* ACC = imagePairEstablished */
742 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
743 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
744 #else /* __LITTLE_ENDIAN_BITFIELD */
745 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
746 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
747 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
748 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
749 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
750 /* ACC = imagePairEstablished */
751 #endif
752
753 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
754 #define PRLI_NO_RESOURCES 0x2
755 #define PRLI_INIT_INCOMPLETE 0x3
756 #define PRLI_NO_SUCH_PA 0x4
757 #define PRLI_PREDEF_CONFIG 0x5
758 #define PRLI_PARTIAL_SUCCESS 0x6
759 #define PRLI_INVALID_PAGE_CNT 0x7
760 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
761
762 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
763
764 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
765
766 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
767 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
768
769 #ifdef __BIG_ENDIAN_BITFIELD
770 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
771 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
772 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
773 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
774 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
775 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
776 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
777 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
778 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
779 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
780 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
781 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
782 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
783 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
784 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
785 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
786 #else /* __LITTLE_ENDIAN_BITFIELD */
787 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
788 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
789 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
790 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
791 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
792 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
793 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
794 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
795 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
796 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
797 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
798 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
799 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
800 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
801 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
802 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
803 #endif
804 } PRLI;
805
806 /*
807 * FCP Logout (PRLO Request / ACC) Payload Definition
808 */
809
810 typedef struct _PRLO { /* Structure is in Big Endian format */
811 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
812
813 #define PRLO_FCP_TYPE 0x08
814 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
815
816 #ifdef __BIG_ENDIAN_BITFIELD
817 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
818 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
819 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
820 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
821 #else /* __LITTLE_ENDIAN_BITFIELD */
822 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
823 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
824 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
825 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
826 #endif
827
828 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
829 #define PRLO_NO_SUCH_IMAGE 0x4
830 #define PRLO_INVALID_PAGE_CNT 0x7
831
832 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
833
834 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
835
836 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
837
838 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
839 } PRLO;
840
841 typedef struct _ADISC { /* Structure is in Big Endian format */
842 uint32_t hardAL_PA;
843 struct lpfc_name portName;
844 struct lpfc_name nodeName;
845 uint32_t DID;
846 } __packed ADISC;
847
848 typedef struct _FARP { /* Structure is in Big Endian format */
849 uint32_t Mflags:8;
850 uint32_t Odid:24;
851 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
852 action */
853 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
854 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
855 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
856 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
857 supported */
858 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
859 supported */
860 uint32_t Rflags:8;
861 uint32_t Rdid:24;
862 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
863 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
864 struct lpfc_name OportName;
865 struct lpfc_name OnodeName;
866 struct lpfc_name RportName;
867 struct lpfc_name RnodeName;
868 uint8_t Oipaddr[16];
869 uint8_t Ripaddr[16];
870 } FARP;
871
872 typedef struct _FAN { /* Structure is in Big Endian format */
873 uint32_t Fdid;
874 struct lpfc_name FportName;
875 struct lpfc_name FnodeName;
876 } __packed FAN;
877
878 typedef struct _SCR { /* Structure is in Big Endian format */
879 uint8_t resvd1;
880 uint8_t resvd2;
881 uint8_t resvd3;
882 uint8_t Function;
883 #define SCR_FUNC_FABRIC 0x01
884 #define SCR_FUNC_NPORT 0x02
885 #define SCR_FUNC_FULL 0x03
886 #define SCR_CLEAR 0xff
887 } SCR;
888
889 typedef struct _RNID_TOP_DISC {
890 struct lpfc_name portName;
891 uint8_t resvd[8];
892 uint32_t unitType;
893 #define RNID_HBA 0x7
894 #define RNID_HOST 0xa
895 #define RNID_DRIVER 0xd
896 uint32_t physPort;
897 uint32_t attachedNodes;
898 uint16_t ipVersion;
899 #define RNID_IPV4 0x1
900 #define RNID_IPV6 0x2
901 uint16_t UDPport;
902 uint8_t ipAddr[16];
903 uint16_t resvd1;
904 uint16_t flags;
905 #define RNID_TD_SUPPORT 0x1
906 #define RNID_LP_VALID 0x2
907 } RNID_TOP_DISC;
908
909 typedef struct _RNID { /* Structure is in Big Endian format */
910 uint8_t Format;
911 #define RNID_TOPOLOGY_DISC 0xdf
912 uint8_t CommonLen;
913 uint8_t resvd1;
914 uint8_t SpecificLen;
915 struct lpfc_name portName;
916 struct lpfc_name nodeName;
917 union {
918 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
919 } un;
920 } __packed RNID;
921
922 struct RLS { /* Structure is in Big Endian format */
923 uint32_t rls;
924 #define rls_rsvd_SHIFT 24
925 #define rls_rsvd_MASK 0x000000ff
926 #define rls_rsvd_WORD rls
927 #define rls_did_SHIFT 0
928 #define rls_did_MASK 0x00ffffff
929 #define rls_did_WORD rls
930 };
931
932 struct RLS_RSP { /* Structure is in Big Endian format */
933 uint32_t linkFailureCnt;
934 uint32_t lossSyncCnt;
935 uint32_t lossSignalCnt;
936 uint32_t primSeqErrCnt;
937 uint32_t invalidXmitWord;
938 uint32_t crcCnt;
939 };
940
941 struct RRQ { /* Structure is in Big Endian format */
942 uint32_t rrq;
943 #define rrq_rsvd_SHIFT 24
944 #define rrq_rsvd_MASK 0x000000ff
945 #define rrq_rsvd_WORD rrq
946 #define rrq_did_SHIFT 0
947 #define rrq_did_MASK 0x00ffffff
948 #define rrq_did_WORD rrq
949 uint32_t rrq_exchg;
950 #define rrq_oxid_SHIFT 16
951 #define rrq_oxid_MASK 0xffff
952 #define rrq_oxid_WORD rrq_exchg
953 #define rrq_rxid_SHIFT 0
954 #define rrq_rxid_MASK 0xffff
955 #define rrq_rxid_WORD rrq_exchg
956 };
957
958 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */
959 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
960
961 struct RTV_RSP { /* Structure is in Big Endian format */
962 uint32_t ratov;
963 uint32_t edtov;
964 uint32_t qtov;
965 #define qtov_rsvd0_SHIFT 28
966 #define qtov_rsvd0_MASK 0x0000000f
967 #define qtov_rsvd0_WORD qtov /* reserved */
968 #define qtov_edtovres_SHIFT 27
969 #define qtov_edtovres_MASK 0x00000001
970 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
971 #define qtov__rsvd1_SHIFT 19
972 #define qtov_rsvd1_MASK 0x0000003f
973 #define qtov_rsvd1_WORD qtov /* reserved */
974 #define qtov_rttov_SHIFT 18
975 #define qtov_rttov_MASK 0x00000001
976 #define qtov_rttov_WORD qtov /* R_T_TOV value */
977 #define qtov_rsvd2_SHIFT 0
978 #define qtov_rsvd2_MASK 0x0003ffff
979 #define qtov_rsvd2_WORD qtov /* reserved */
980 };
981
982
983 typedef struct _RPL { /* Structure is in Big Endian format */
984 uint32_t maxsize;
985 uint32_t index;
986 } RPL;
987
988 typedef struct _PORT_NUM_BLK {
989 uint32_t portNum;
990 uint32_t portID;
991 struct lpfc_name portName;
992 } PORT_NUM_BLK;
993
994 typedef struct _RPL_RSP { /* Structure is in Big Endian format */
995 uint32_t listLen;
996 uint32_t index;
997 PORT_NUM_BLK port_num_blk;
998 } RPL_RSP;
999
1000 /* This is used for RSCN command */
1001 typedef struct _D_ID { /* Structure is in Big Endian format */
1002 union {
1003 uint32_t word;
1004 struct {
1005 #ifdef __BIG_ENDIAN_BITFIELD
1006 uint8_t resv;
1007 uint8_t domain;
1008 uint8_t area;
1009 uint8_t id;
1010 #else /* __LITTLE_ENDIAN_BITFIELD */
1011 uint8_t id;
1012 uint8_t area;
1013 uint8_t domain;
1014 uint8_t resv;
1015 #endif
1016 } b;
1017 } un;
1018 } D_ID;
1019
1020 #define RSCN_ADDRESS_FORMAT_PORT 0x0
1021 #define RSCN_ADDRESS_FORMAT_AREA 0x1
1022 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
1023 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3
1024 #define RSCN_ADDRESS_FORMAT_MASK 0x3
1025
1026 /*
1027 * Structure to define all ELS Payload types
1028 */
1029
1030 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
1031 uint8_t elsCode; /* FC Word 0, bit 24:31 */
1032 uint8_t elsByte1;
1033 uint8_t elsByte2;
1034 uint8_t elsByte3;
1035 union {
1036 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
1037 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
1038 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
1039 PRLI prli; /* Payload for PRLI/ACC */
1040 PRLO prlo; /* Payload for PRLO/ACC */
1041 ADISC adisc; /* Payload for ADISC/ACC */
1042 FARP farp; /* Payload for FARP/ACC */
1043 FAN fan; /* Payload for FAN */
1044 SCR scr; /* Payload for SCR/ACC */
1045 RNID rnid; /* Payload for RNID */
1046 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
1047 } un;
1048 } ELS_PKT;
1049
1050 /*
1051 * Link Cable Beacon (LCB) ELS Frame
1052 */
1053
1054 struct fc_lcb_request_frame {
1055 uint32_t lcb_command; /* ELS command opcode (0x81) */
1056 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1057 #define LPFC_LCB_ON 0x1
1058 #define LPFC_LCB_OFF 0x2
1059 uint8_t reserved[2];
1060 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */
1061 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1062 #define LPFC_LCB_GREEN 0x1
1063 #define LPFC_LCB_AMBER 0x2
1064 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1065 #define LCB_CAPABILITY_DURATION 1
1066 #define BEACON_VERSION_V1 1
1067 #define BEACON_VERSION_V0 0
1068 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1069 };
1070
1071 /*
1072 * Link Cable Beacon (LCB) ELS Response Frame
1073 */
1074 struct fc_lcb_res_frame {
1075 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */
1076 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1077 uint8_t reserved[2];
1078 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */
1079 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1080 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1081 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1082 };
1083
1084 /*
1085 * Read Diagnostic Parameters (RDP) ELS frame.
1086 */
1087 #define SFF_PG0_IDENT_SFP 0x3
1088
1089 #define SFP_FLAG_PT_OPTICAL 0x0
1090 #define SFP_FLAG_PT_SWLASER 0x01
1091 #define SFP_FLAG_PT_LWLASER_LC1310 0x02
1092 #define SFP_FLAG_PT_LWLASER_LL1550 0x03
1093 #define SFP_FLAG_PT_MASK 0x0F
1094 #define SFP_FLAG_PT_SHIFT 0
1095
1096 #define SFP_FLAG_IS_OPTICAL_PORT 0x01
1097 #define SFP_FLAG_IS_OPTICAL_MASK 0x010
1098 #define SFP_FLAG_IS_OPTICAL_SHIFT 4
1099
1100 #define SFP_FLAG_IS_DESC_VALID 0x01
1101 #define SFP_FLAG_IS_DESC_VALID_MASK 0x020
1102 #define SFP_FLAG_IS_DESC_VALID_SHIFT 5
1103
1104 #define SFP_FLAG_CT_UNKNOWN 0x0
1105 #define SFP_FLAG_CT_SFP_PLUS 0x01
1106 #define SFP_FLAG_CT_MASK 0x3C
1107 #define SFP_FLAG_CT_SHIFT 6
1108
1109 struct fc_rdp_port_name_info {
1110 uint8_t wwnn[8];
1111 uint8_t wwpn[8];
1112 };
1113
1114
1115 /*
1116 * Link Error Status Block Structure (FC-FS-3) for RDP
1117 * This similar to RPS ELS
1118 */
1119 struct fc_link_status {
1120 uint32_t link_failure_cnt;
1121 uint32_t loss_of_synch_cnt;
1122 uint32_t loss_of_signal_cnt;
1123 uint32_t primitive_seq_proto_err;
1124 uint32_t invalid_trans_word;
1125 uint32_t invalid_crc_cnt;
1126
1127 };
1128
1129 #define RDP_PORT_NAMES_DESC_TAG 0x00010003
1130 struct fc_rdp_port_name_desc {
1131 uint32_t tag; /* 0001 0003h */
1132 uint32_t length; /* set to size of payload struct */
1133 struct fc_rdp_port_name_info port_names;
1134 };
1135
1136
1137 struct fc_rdp_fec_info {
1138 uint32_t CorrectedBlocks;
1139 uint32_t UncorrectableBlocks;
1140 };
1141
1142 #define RDP_FEC_DESC_TAG 0x00010005
1143 struct fc_fec_rdp_desc {
1144 uint32_t tag;
1145 uint32_t length;
1146 struct fc_rdp_fec_info info;
1147 };
1148
1149 struct fc_rdp_link_error_status_payload_info {
1150 struct fc_link_status link_status; /* 24 bytes */
1151 uint32_t port_type; /* bits 31-30 only */
1152 };
1153
1154 #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002
1155 struct fc_rdp_link_error_status_desc {
1156 uint32_t tag; /* 0001 0002h */
1157 uint32_t length; /* set to size of payload struct */
1158 struct fc_rdp_link_error_status_payload_info info;
1159 };
1160
1161 #define VN_PT_PHY_UNKNOWN 0x00
1162 #define VN_PT_PHY_PF_PORT 0x01
1163 #define VN_PT_PHY_ETH_MAC 0x10
1164 #define VN_PT_PHY_SHIFT 30
1165
1166 #define RDP_PS_1GB 0x8000
1167 #define RDP_PS_2GB 0x4000
1168 #define RDP_PS_4GB 0x2000
1169 #define RDP_PS_10GB 0x1000
1170 #define RDP_PS_8GB 0x0800
1171 #define RDP_PS_16GB 0x0400
1172 #define RDP_PS_32GB 0x0200
1173 #define RDP_PS_64GB 0x0100
1174 #define RDP_PS_128GB 0x0080
1175 #define RDP_PS_256GB 0x0040
1176
1177 #define RDP_CAP_USER_CONFIGURED 0x0002
1178 #define RDP_CAP_UNKNOWN 0x0001
1179 #define RDP_PS_UNKNOWN 0x0002
1180 #define RDP_PS_NOT_ESTABLISHED 0x0001
1181
1182 struct fc_rdp_port_speed {
1183 uint16_t capabilities;
1184 uint16_t speed;
1185 };
1186
1187 struct fc_rdp_port_speed_info {
1188 struct fc_rdp_port_speed port_speed;
1189 };
1190
1191 #define RDP_PORT_SPEED_DESC_TAG 0x00010001
1192 struct fc_rdp_port_speed_desc {
1193 uint32_t tag; /* 00010001h */
1194 uint32_t length; /* set to size of payload struct */
1195 struct fc_rdp_port_speed_info info;
1196 };
1197
1198 #define RDP_NPORT_ID_SIZE 4
1199 #define RDP_N_PORT_DESC_TAG 0x00000003
1200 struct fc_rdp_nport_desc {
1201 uint32_t tag; /* 0000 0003h, big endian */
1202 uint32_t length; /* size of RDP_N_PORT_ID struct */
1203 uint32_t nport_id : 12;
1204 uint32_t reserved : 8;
1205 };
1206
1207
1208 struct fc_rdp_link_service_info {
1209 uint32_t els_req; /* Request payload word 0 value.*/
1210 };
1211
1212 #define RDP_LINK_SERVICE_DESC_TAG 0x00000001
1213 struct fc_rdp_link_service_desc {
1214 uint32_t tag; /* Descriptor tag 1 */
1215 uint32_t length; /* set to size of payload struct. */
1216 struct fc_rdp_link_service_info payload;
1217 /* must be ELS req Word 0(0x18) */
1218 };
1219
1220 struct fc_rdp_sfp_info {
1221 uint16_t temperature;
1222 uint16_t vcc;
1223 uint16_t tx_bias;
1224 uint16_t tx_power;
1225 uint16_t rx_power;
1226 uint16_t flags;
1227 };
1228
1229 #define RDP_SFP_DESC_TAG 0x00010000
1230 struct fc_rdp_sfp_desc {
1231 uint32_t tag;
1232 uint32_t length; /* set to size of sfp_info struct */
1233 struct fc_rdp_sfp_info sfp_info;
1234 };
1235
1236 /* Buffer Credit Descriptor */
1237 struct fc_rdp_bbc_info {
1238 uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */
1239 uint32_t attached_port_bbc;
1240 uint32_t rtt; /* Round trip time */
1241 };
1242 #define RDP_BBC_DESC_TAG 0x00010006
1243 struct fc_rdp_bbc_desc {
1244 uint32_t tag;
1245 uint32_t length;
1246 struct fc_rdp_bbc_info bbc_info;
1247 };
1248
1249 /* Optical Element Type Transgression Flags */
1250 #define RDP_OET_LOW_WARNING 0x1
1251 #define RDP_OET_HIGH_WARNING 0x2
1252 #define RDP_OET_LOW_ALARM 0x4
1253 #define RDP_OET_HIGH_ALARM 0x8
1254
1255 #define RDP_OED_TEMPERATURE 0x1
1256 #define RDP_OED_VOLTAGE 0x2
1257 #define RDP_OED_TXBIAS 0x3
1258 #define RDP_OED_TXPOWER 0x4
1259 #define RDP_OED_RXPOWER 0x5
1260
1261 #define RDP_OED_TYPE_SHIFT 28
1262 /* Optical Element Data descriptor */
1263 struct fc_rdp_oed_info {
1264 uint16_t hi_alarm;
1265 uint16_t lo_alarm;
1266 uint16_t hi_warning;
1267 uint16_t lo_warning;
1268 uint32_t function_flags;
1269 };
1270 #define RDP_OED_DESC_TAG 0x00010007
1271 struct fc_rdp_oed_sfp_desc {
1272 uint32_t tag;
1273 uint32_t length;
1274 struct fc_rdp_oed_info oed_info;
1275 };
1276
1277 /* Optical Product Data descriptor */
1278 struct fc_rdp_opd_sfp_info {
1279 uint8_t vendor_name[16];
1280 uint8_t model_number[16];
1281 uint8_t serial_number[16];
1282 uint8_t revision[4];
1283 uint8_t date[8];
1284 };
1285
1286 #define RDP_OPD_DESC_TAG 0x00010008
1287 struct fc_rdp_opd_sfp_desc {
1288 uint32_t tag;
1289 uint32_t length;
1290 struct fc_rdp_opd_sfp_info opd_info;
1291 };
1292
1293 struct fc_rdp_req_frame {
1294 uint32_t rdp_command; /* ELS command opcode (0x18)*/
1295 uint32_t rdp_des_length; /* RDP Payload Word 1 */
1296 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
1297 };
1298
1299
1300 struct fc_rdp_res_frame {
1301 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */
1302 uint32_t length; /* FC Word 1 */
1303 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */
1304 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */
1305 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10 -12 */
1306 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */
1307 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22 -27 */
1308 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */
1309 struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/
1310 struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/
1311 struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/
1312 struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/
1313 struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/
1314 struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/
1315 struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/
1316 struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/
1317 };
1318
1319
1320 /******** FDMI ********/
1321
1322 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
1323 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */
1324
1325 /* Definitions for HBA / Port attribute entries */
1326
1327 /* Attribute Entry */
1328 struct lpfc_fdmi_attr_entry {
1329 union {
1330 uint32_t AttrInt;
1331 uint8_t AttrTypes[32];
1332 uint8_t AttrString[256];
1333 struct lpfc_name AttrWWN;
1334 } un;
1335 };
1336
1337 struct lpfc_fdmi_attr_def { /* Defined in TLV format */
1338 /* Structure is in Big Endian format */
1339 uint32_t AttrType:16;
1340 uint32_t AttrLen:16;
1341 /* Marks start of Value (ATTRIBUTE_ENTRY) */
1342 struct lpfc_fdmi_attr_entry AttrValue;
1343 } __packed;
1344
1345 /*
1346 * HBA Attribute Block
1347 */
1348 struct lpfc_fdmi_attr_block {
1349 uint32_t EntryCnt; /* Number of HBA attribute entries */
1350 struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */
1351 };
1352
1353 /*
1354 * Port Entry
1355 */
1356 struct lpfc_fdmi_port_entry {
1357 struct lpfc_name PortName;
1358 };
1359
1360 /*
1361 * HBA Identifier
1362 */
1363 struct lpfc_fdmi_hba_ident {
1364 struct lpfc_name PortName;
1365 };
1366
1367 /*
1368 * Registered Port List Format
1369 */
1370 struct lpfc_fdmi_reg_port_list {
1371 uint32_t EntryCnt;
1372 struct lpfc_fdmi_port_entry pe;
1373 } __packed;
1374
1375 /*
1376 * Register HBA(RHBA)
1377 */
1378 struct lpfc_fdmi_reg_hba {
1379 struct lpfc_fdmi_hba_ident hi;
1380 struct lpfc_fdmi_reg_port_list rpl;
1381 };
1382
1383 /*
1384 * Register HBA Attributes (RHAT)
1385 */
1386 struct lpfc_fdmi_reg_hbaattr {
1387 struct lpfc_name HBA_PortName;
1388 struct lpfc_fdmi_attr_block ab;
1389 };
1390
1391 /*
1392 * Register Port Attributes (RPA)
1393 */
1394 struct lpfc_fdmi_reg_portattr {
1395 struct lpfc_name PortName;
1396 struct lpfc_fdmi_attr_block ab;
1397 };
1398
1399 /*
1400 * HBA MAnagement Operations Command Codes
1401 */
1402 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
1403 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
1404 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
1405 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
1406 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */
1407 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
1408 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
1409 #define SLI_MGMT_RPRT 0x210 /* Register Port */
1410 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1411 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1412 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */
1413 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
1414 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */
1415
1416 #define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */
1417
1418 /*
1419 * HBA Attribute Types
1420 */
1421 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */
1422 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */
1423 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */
1424 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */
1425 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */
1426 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */
1427 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */
1428 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1429 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */
1430 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */
1431 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1432 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */
1433 #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */
1434 #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */
1435 #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */
1436 #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */
1437 #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */
1438 #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */
1439
1440 /* Bit mask for all individual HBA attributes */
1441 #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001
1442 #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002
1443 #define LPFC_FDMI_HBA_ATTR_sn 0x00000004
1444 #define LPFC_FDMI_HBA_ATTR_model 0x00000008
1445 #define LPFC_FDMI_HBA_ATTR_description 0x00000010
1446 #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020
1447 #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040
1448 #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080
1449 #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100
1450 #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200
1451 #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400
1452 #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800
1453 #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */
1454 #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000
1455 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000
1456 #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000
1457 #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */
1458 #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000
1459
1460 /* Bit mask for FDMI-1 defined HBA attributes */
1461 #define LPFC_FDMI1_HBA_ATTR 0x000007ff
1462
1463 /* Bit mask for FDMI-2 defined HBA attributes */
1464 /* Skip vendor_info and bios_state */
1465 #define LPFC_FDMI2_HBA_ATTR 0x0002efff
1466
1467 /*
1468 * Port Attrubute Types
1469 */
1470 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */
1471 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */
1472 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */
1473 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */
1474 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */
1475 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */
1476 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */
1477 #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */
1478 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */
1479 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */
1480 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */
1481 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */
1482 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */
1483 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */
1484 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */
1485 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */
1486 #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */
1487 #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */
1488 #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */
1489 #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */
1490 #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */
1491 #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */
1492 #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */
1493
1494 /* Bit mask for all individual PORT attributes */
1495 #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001
1496 #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002
1497 #define LPFC_FDMI_PORT_ATTR_speed 0x00000004
1498 #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008
1499 #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010
1500 #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020
1501 #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040
1502 #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080
1503 #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100
1504 #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200
1505 #define LPFC_FDMI_PORT_ATTR_class 0x00000400
1506 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800
1507 #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000
1508 #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000
1509 #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000
1510 #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000
1511 #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */
1512 #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */
1513 #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */
1514 #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */
1515 #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */
1516 #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */
1517 #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */
1518
1519 /* Bit mask for FDMI-1 defined PORT attributes */
1520 #define LPFC_FDMI1_PORT_ATTR 0x0000003f
1521
1522 /* Bit mask for FDMI-2 defined PORT attributes */
1523 #define LPFC_FDMI2_PORT_ATTR 0x0000ffff
1524
1525 /* Bit mask for Smart SAN defined PORT attributes */
1526 #define LPFC_FDMI2_SMART_ATTR 0x007fffff
1527
1528 /* Defines for PORT port state attribute */
1529 #define LPFC_FDMI_PORTSTATE_UNKNOWN 1
1530 #define LPFC_FDMI_PORTSTATE_ONLINE 2
1531
1532 /* Defines for PORT port type attribute */
1533 #define LPFC_FDMI_PORTTYPE_UNKNOWN 0
1534 #define LPFC_FDMI_PORTTYPE_NPORT 1
1535 #define LPFC_FDMI_PORTTYPE_NLPORT 2
1536
1537 /*
1538 * Begin HBA configuration parameters.
1539 * The PCI configuration register BAR assignments are:
1540 * BAR0, offset 0x10 - SLIM base memory address
1541 * BAR1, offset 0x14 - SLIM base memory high address
1542 * BAR2, offset 0x18 - REGISTER base memory address
1543 * BAR3, offset 0x1c - REGISTER base memory high address
1544 * BAR4, offset 0x20 - BIU I/O registers
1545 * BAR5, offset 0x24 - REGISTER base io high address
1546 */
1547
1548 /* Number of rings currently used and available. */
1549 #define MAX_SLI3_CONFIGURED_RINGS 3
1550 #define MAX_SLI3_RINGS 4
1551
1552 /* IOCB / Mailbox is owned by FireFly */
1553 #define OWN_CHIP 1
1554
1555 /* IOCB / Mailbox is owned by Host */
1556 #define OWN_HOST 0
1557
1558 /* Number of 4-byte words in an IOCB. */
1559 #define IOCB_WORD_SZ 8
1560
1561 /* network headers for Dfctl field */
1562 #define FC_NET_HDR 0x20
1563
1564 /* Start FireFly Register definitions */
1565 #define PCI_VENDOR_ID_EMULEX 0x10df
1566 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1567 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1568 #define PCI_DEVICE_ID_BALIUS 0xe131
1569 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1570 #define PCI_DEVICE_ID_LANCER_FC 0xe200
1571 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
1572 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1573 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1574 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300
1575 #define PCI_DEVICE_ID_LANCER_G7_FC 0xf400
1576 #define PCI_DEVICE_ID_SAT_SMB 0xf011
1577 #define PCI_DEVICE_ID_SAT_MID 0xf015
1578 #define PCI_DEVICE_ID_RFLY 0xf095
1579 #define PCI_DEVICE_ID_PFLY 0xf098
1580 #define PCI_DEVICE_ID_LP101 0xf0a1
1581 #define PCI_DEVICE_ID_TFLY 0xf0a5
1582 #define PCI_DEVICE_ID_BSMB 0xf0d1
1583 #define PCI_DEVICE_ID_BMID 0xf0d5
1584 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1585 #define PCI_DEVICE_ID_ZMID 0xf0e5
1586 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1587 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1588 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1589 #define PCI_DEVICE_ID_SAT 0xf100
1590 #define PCI_DEVICE_ID_SAT_SCSP 0xf111
1591 #define PCI_DEVICE_ID_SAT_DCSP 0xf112
1592 #define PCI_DEVICE_ID_FALCON 0xf180
1593 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1594 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1595 #define PCI_DEVICE_ID_CENTAUR 0xf900
1596 #define PCI_DEVICE_ID_PEGASUS 0xf980
1597 #define PCI_DEVICE_ID_THOR 0xfa00
1598 #define PCI_DEVICE_ID_VIPER 0xfb00
1599 #define PCI_DEVICE_ID_LP10000S 0xfc00
1600 #define PCI_DEVICE_ID_LP11000S 0xfc10
1601 #define PCI_DEVICE_ID_LPE11000S 0xfc20
1602 #define PCI_DEVICE_ID_SAT_S 0xfc40
1603 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1604 #define PCI_DEVICE_ID_HELIOS 0xfd00
1605 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1606 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1607 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1608 #define PCI_DEVICE_ID_HORNET 0xfe05
1609 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1610 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1611 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1612 #define PCI_DEVICE_ID_TIGERSHARK 0x0704
1613 #define PCI_DEVICE_ID_TOMCAT 0x0714
1614 #define PCI_DEVICE_ID_SKYHAWK 0x0724
1615 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
1616
1617 #define JEDEC_ID_ADDRESS 0x0080001c
1618 #define FIREFLY_JEDEC_ID 0x1ACC
1619 #define SUPERFLY_JEDEC_ID 0x0020
1620 #define DRAGONFLY_JEDEC_ID 0x0021
1621 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1622 #define CENTAUR_2G_JEDEC_ID 0x0026
1623 #define CENTAUR_1G_JEDEC_ID 0x0028
1624 #define PEGASUS_ORION_JEDEC_ID 0x0036
1625 #define PEGASUS_JEDEC_ID 0x0038
1626 #define THOR_JEDEC_ID 0x0012
1627 #define HELIOS_JEDEC_ID 0x0364
1628 #define ZEPHYR_JEDEC_ID 0x0577
1629 #define VIPER_JEDEC_ID 0x4838
1630 #define SATURN_JEDEC_ID 0x1004
1631 #define HORNET_JDEC_ID 0x2057706D
1632
1633 #define JEDEC_ID_MASK 0x0FFFF000
1634 #define JEDEC_ID_SHIFT 12
1635 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1636
1637 typedef struct { /* FireFly BIU registers */
1638 uint32_t hostAtt; /* See definitions for Host Attention
1639 register */
1640 uint32_t chipAtt; /* See definitions for Chip Attention
1641 register */
1642 uint32_t hostStatus; /* See definitions for Host Status register */
1643 uint32_t hostControl; /* See definitions for Host Control register */
1644 uint32_t buiConfig; /* See definitions for BIU configuration
1645 register */
1646 } FF_REGS;
1647
1648 /* IO Register size in bytes */
1649 #define FF_REG_AREA_SIZE 256
1650
1651 /* Host Attention Register */
1652
1653 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1654
1655 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1656 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1657 #define HA_R0ATT 0x00000008 /* Bit 3 */
1658 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1659 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1660 #define HA_R1ATT 0x00000080 /* Bit 7 */
1661 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1662 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1663 #define HA_R2ATT 0x00000800 /* Bit 11 */
1664 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1665 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1666 #define HA_R3ATT 0x00008000 /* Bit 15 */
1667 #define HA_LATT 0x20000000 /* Bit 29 */
1668 #define HA_MBATT 0x40000000 /* Bit 30 */
1669 #define HA_ERATT 0x80000000 /* Bit 31 */
1670
1671 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1672 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1673 #define HA_RXATT 0x00000008 /* Bit 3 */
1674 #define HA_RXMASK 0x0000000f
1675
1676 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1677 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1678 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1679 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1680
1681 #define HA_R0_POS 3
1682 #define HA_R1_POS 7
1683 #define HA_R2_POS 11
1684 #define HA_R3_POS 15
1685 #define HA_LE_POS 29
1686 #define HA_MB_POS 30
1687 #define HA_ER_POS 31
1688 /* Chip Attention Register */
1689
1690 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1691
1692 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1693 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1694 #define CA_R0ATT 0x00000008 /* Bit 3 */
1695 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1696 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1697 #define CA_R1ATT 0x00000080 /* Bit 7 */
1698 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1699 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1700 #define CA_R2ATT 0x00000800 /* Bit 11 */
1701 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1702 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1703 #define CA_R3ATT 0x00008000 /* Bit 15 */
1704 #define CA_MBATT 0x40000000 /* Bit 30 */
1705
1706 /* Host Status Register */
1707
1708 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1709
1710 #define HS_MBRDY 0x00400000 /* Bit 22 */
1711 #define HS_FFRDY 0x00800000 /* Bit 23 */
1712 #define HS_FFER8 0x01000000 /* Bit 24 */
1713 #define HS_FFER7 0x02000000 /* Bit 25 */
1714 #define HS_FFER6 0x04000000 /* Bit 26 */
1715 #define HS_FFER5 0x08000000 /* Bit 27 */
1716 #define HS_FFER4 0x10000000 /* Bit 28 */
1717 #define HS_FFER3 0x20000000 /* Bit 29 */
1718 #define HS_FFER2 0x40000000 /* Bit 30 */
1719 #define HS_FFER1 0x80000000 /* Bit 31 */
1720 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1721 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1722 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
1723 /* Host Control Register */
1724
1725 #define HC_REG_OFFSET 12 /* Byte offset from register base address */
1726
1727 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1728 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1729 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1730 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1731 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1732 #define HC_INITHBI 0x02000000 /* Bit 25 */
1733 #define HC_INITMB 0x04000000 /* Bit 26 */
1734 #define HC_INITFF 0x08000000 /* Bit 27 */
1735 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1736 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1737
1738 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1739 #define MSIX_DFLT_ID 0
1740 #define MSIX_RNG0_ID 0
1741 #define MSIX_RNG1_ID 1
1742 #define MSIX_RNG2_ID 2
1743 #define MSIX_RNG3_ID 3
1744
1745 #define MSIX_LINK_ID 4
1746 #define MSIX_MBOX_ID 5
1747
1748 #define MSIX_SPARE0_ID 6
1749 #define MSIX_SPARE1_ID 7
1750
1751 /* Mailbox Commands */
1752 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1753 #define MBX_LOAD_SM 0x01
1754 #define MBX_READ_NV 0x02
1755 #define MBX_WRITE_NV 0x03
1756 #define MBX_RUN_BIU_DIAG 0x04
1757 #define MBX_INIT_LINK 0x05
1758 #define MBX_DOWN_LINK 0x06
1759 #define MBX_CONFIG_LINK 0x07
1760 #define MBX_CONFIG_RING 0x09
1761 #define MBX_RESET_RING 0x0A
1762 #define MBX_READ_CONFIG 0x0B
1763 #define MBX_READ_RCONFIG 0x0C
1764 #define MBX_READ_SPARM 0x0D
1765 #define MBX_READ_STATUS 0x0E
1766 #define MBX_READ_RPI 0x0F
1767 #define MBX_READ_XRI 0x10
1768 #define MBX_READ_REV 0x11
1769 #define MBX_READ_LNK_STAT 0x12
1770 #define MBX_REG_LOGIN 0x13
1771 #define MBX_UNREG_LOGIN 0x14
1772 #define MBX_CLEAR_LA 0x16
1773 #define MBX_DUMP_MEMORY 0x17
1774 #define MBX_DUMP_CONTEXT 0x18
1775 #define MBX_RUN_DIAGS 0x19
1776 #define MBX_RESTART 0x1A
1777 #define MBX_UPDATE_CFG 0x1B
1778 #define MBX_DOWN_LOAD 0x1C
1779 #define MBX_DEL_LD_ENTRY 0x1D
1780 #define MBX_RUN_PROGRAM 0x1E
1781 #define MBX_SET_MASK 0x20
1782 #define MBX_SET_VARIABLE 0x21
1783 #define MBX_UNREG_D_ID 0x23
1784 #define MBX_KILL_BOARD 0x24
1785 #define MBX_CONFIG_FARP 0x25
1786 #define MBX_BEACON 0x2A
1787 #define MBX_CONFIG_MSI 0x30
1788 #define MBX_HEARTBEAT 0x31
1789 #define MBX_WRITE_VPARMS 0x32
1790 #define MBX_ASYNCEVT_ENABLE 0x33
1791 #define MBX_READ_EVENT_LOG_STATUS 0x37
1792 #define MBX_READ_EVENT_LOG 0x38
1793 #define MBX_WRITE_EVENT_LOG 0x39
1794
1795 #define MBX_PORT_CAPABILITIES 0x3B
1796 #define MBX_PORT_IOV_CONTROL 0x3C
1797
1798 #define MBX_CONFIG_HBQ 0x7C
1799 #define MBX_LOAD_AREA 0x81
1800 #define MBX_RUN_BIU_DIAG64 0x84
1801 #define MBX_CONFIG_PORT 0x88
1802 #define MBX_READ_SPARM64 0x8D
1803 #define MBX_READ_RPI64 0x8F
1804 #define MBX_REG_LOGIN64 0x93
1805 #define MBX_READ_TOPOLOGY 0x95
1806 #define MBX_REG_VPI 0x96
1807 #define MBX_UNREG_VPI 0x97
1808
1809 #define MBX_WRITE_WWN 0x98
1810 #define MBX_SET_DEBUG 0x99
1811 #define MBX_LOAD_EXP_ROM 0x9C
1812 #define MBX_SLI4_CONFIG 0x9B
1813 #define MBX_SLI4_REQ_FTRS 0x9D
1814 #define MBX_MAX_CMDS 0x9E
1815 #define MBX_RESUME_RPI 0x9E
1816 #define MBX_SLI2_CMD_MASK 0x80
1817 #define MBX_REG_VFI 0x9F
1818 #define MBX_REG_FCFI 0xA0
1819 #define MBX_UNREG_VFI 0xA1
1820 #define MBX_UNREG_FCFI 0xA2
1821 #define MBX_INIT_VFI 0xA3
1822 #define MBX_INIT_VPI 0xA4
1823 #define MBX_ACCESS_VDATA 0xA5
1824 #define MBX_REG_FCFI_MRQ 0xAF
1825
1826 #define MBX_AUTH_PORT 0xF8
1827 #define MBX_SECURITY_MGMT 0xF9
1828
1829 /* IOCB Commands */
1830
1831 #define CMD_RCV_SEQUENCE_CX 0x01
1832 #define CMD_XMIT_SEQUENCE_CR 0x02
1833 #define CMD_XMIT_SEQUENCE_CX 0x03
1834 #define CMD_XMIT_BCAST_CN 0x04
1835 #define CMD_XMIT_BCAST_CX 0x05
1836 #define CMD_QUE_RING_BUF_CN 0x06
1837 #define CMD_QUE_XRI_BUF_CX 0x07
1838 #define CMD_IOCB_CONTINUE_CN 0x08
1839 #define CMD_RET_XRI_BUF_CX 0x09
1840 #define CMD_ELS_REQUEST_CR 0x0A
1841 #define CMD_ELS_REQUEST_CX 0x0B
1842 #define CMD_RCV_ELS_REQ_CX 0x0D
1843 #define CMD_ABORT_XRI_CN 0x0E
1844 #define CMD_ABORT_XRI_CX 0x0F
1845 #define CMD_CLOSE_XRI_CN 0x10
1846 #define CMD_CLOSE_XRI_CX 0x11
1847 #define CMD_CREATE_XRI_CR 0x12
1848 #define CMD_CREATE_XRI_CX 0x13
1849 #define CMD_GET_RPI_CN 0x14
1850 #define CMD_XMIT_ELS_RSP_CX 0x15
1851 #define CMD_GET_RPI_CR 0x16
1852 #define CMD_XRI_ABORTED_CX 0x17
1853 #define CMD_FCP_IWRITE_CR 0x18
1854 #define CMD_FCP_IWRITE_CX 0x19
1855 #define CMD_FCP_IREAD_CR 0x1A
1856 #define CMD_FCP_IREAD_CX 0x1B
1857 #define CMD_FCP_ICMND_CR 0x1C
1858 #define CMD_FCP_ICMND_CX 0x1D
1859 #define CMD_FCP_TSEND_CX 0x1F
1860 #define CMD_FCP_TRECEIVE_CX 0x21
1861 #define CMD_FCP_TRSP_CX 0x23
1862 #define CMD_FCP_AUTO_TRSP_CX 0x29
1863
1864 #define CMD_ADAPTER_MSG 0x20
1865 #define CMD_ADAPTER_DUMP 0x22
1866
1867 /* SLI_2 IOCB Command Set */
1868
1869 #define CMD_ASYNC_STATUS 0x7C
1870 #define CMD_RCV_SEQUENCE64_CX 0x81
1871 #define CMD_XMIT_SEQUENCE64_CR 0x82
1872 #define CMD_XMIT_SEQUENCE64_CX 0x83
1873 #define CMD_XMIT_BCAST64_CN 0x84
1874 #define CMD_XMIT_BCAST64_CX 0x85
1875 #define CMD_QUE_RING_BUF64_CN 0x86
1876 #define CMD_QUE_XRI_BUF64_CX 0x87
1877 #define CMD_IOCB_CONTINUE64_CN 0x88
1878 #define CMD_RET_XRI_BUF64_CX 0x89
1879 #define CMD_ELS_REQUEST64_CR 0x8A
1880 #define CMD_ELS_REQUEST64_CX 0x8B
1881 #define CMD_ABORT_MXRI64_CN 0x8C
1882 #define CMD_RCV_ELS_REQ64_CX 0x8D
1883 #define CMD_XMIT_ELS_RSP64_CX 0x95
1884 #define CMD_XMIT_BLS_RSP64_CX 0x97
1885 #define CMD_FCP_IWRITE64_CR 0x98
1886 #define CMD_FCP_IWRITE64_CX 0x99
1887 #define CMD_FCP_IREAD64_CR 0x9A
1888 #define CMD_FCP_IREAD64_CX 0x9B
1889 #define CMD_FCP_ICMND64_CR 0x9C
1890 #define CMD_FCP_ICMND64_CX 0x9D
1891 #define CMD_FCP_TSEND64_CX 0x9F
1892 #define CMD_FCP_TRECEIVE64_CX 0xA1
1893 #define CMD_FCP_TRSP64_CX 0xA3
1894
1895 #define CMD_QUE_XRI64_CX 0xB3
1896 #define CMD_IOCB_RCV_SEQ64_CX 0xB5
1897 #define CMD_IOCB_RCV_ELS64_CX 0xB7
1898 #define CMD_IOCB_RET_XRI64_CX 0xB9
1899 #define CMD_IOCB_RCV_CONT64_CX 0xBB
1900
1901 #define CMD_GEN_REQUEST64_CR 0xC2
1902 #define CMD_GEN_REQUEST64_CX 0xC3
1903
1904 /* Unhandled SLI-3 Commands */
1905 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1906 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1907 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1908 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1909 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1910 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1911 #define CMD_IOCB_RET_HBQE64_CN 0xCA
1912 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1913 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1914 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1915 #define CMD_IOCB_LOGENTRY_CN 0x94
1916 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1917
1918 /* Data Security SLI Commands */
1919 #define DSSCMD_IWRITE64_CR 0xF8
1920 #define DSSCMD_IWRITE64_CX 0xF9
1921 #define DSSCMD_IREAD64_CR 0xFA
1922 #define DSSCMD_IREAD64_CX 0xFB
1923
1924 #define CMD_MAX_IOCB_CMD 0xFB
1925 #define CMD_IOCB_MASK 0xff
1926
1927 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1928 iocb */
1929 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
1930 /*
1931 * Define Status
1932 */
1933 #define MBX_SUCCESS 0
1934 #define MBXERR_NUM_RINGS 1
1935 #define MBXERR_NUM_IOCBS 2
1936 #define MBXERR_IOCBS_EXCEEDED 3
1937 #define MBXERR_BAD_RING_NUMBER 4
1938 #define MBXERR_MASK_ENTRIES_RANGE 5
1939 #define MBXERR_MASKS_EXCEEDED 6
1940 #define MBXERR_BAD_PROFILE 7
1941 #define MBXERR_BAD_DEF_CLASS 8
1942 #define MBXERR_BAD_MAX_RESPONDER 9
1943 #define MBXERR_BAD_MAX_ORIGINATOR 10
1944 #define MBXERR_RPI_REGISTERED 11
1945 #define MBXERR_RPI_FULL 12
1946 #define MBXERR_NO_RESOURCES 13
1947 #define MBXERR_BAD_RCV_LENGTH 14
1948 #define MBXERR_DMA_ERROR 15
1949 #define MBXERR_ERROR 16
1950 #define MBXERR_LINK_DOWN 0x33
1951 #define MBXERR_SEC_NO_PERMISSION 0xF02
1952 #define MBX_NOT_FINISHED 255
1953
1954 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1955 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1956
1957 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1958
1959 /*
1960 * return code Fail
1961 */
1962 #define FAILURE 1
1963
1964 /*
1965 * Begin Structure Definitions for Mailbox Commands
1966 */
1967
1968 typedef struct {
1969 #ifdef __BIG_ENDIAN_BITFIELD
1970 uint8_t tval;
1971 uint8_t tmask;
1972 uint8_t rval;
1973 uint8_t rmask;
1974 #else /* __LITTLE_ENDIAN_BITFIELD */
1975 uint8_t rmask;
1976 uint8_t rval;
1977 uint8_t tmask;
1978 uint8_t tval;
1979 #endif
1980 } RR_REG;
1981
1982 struct ulp_bde {
1983 uint32_t bdeAddress;
1984 #ifdef __BIG_ENDIAN_BITFIELD
1985 uint32_t bdeReserved:4;
1986 uint32_t bdeAddrHigh:4;
1987 uint32_t bdeSize:24;
1988 #else /* __LITTLE_ENDIAN_BITFIELD */
1989 uint32_t bdeSize:24;
1990 uint32_t bdeAddrHigh:4;
1991 uint32_t bdeReserved:4;
1992 #endif
1993 };
1994
1995 typedef struct ULP_BDL { /* SLI-2 */
1996 #ifdef __BIG_ENDIAN_BITFIELD
1997 uint32_t bdeFlags:8; /* BDL Flags */
1998 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1999 #else /* __LITTLE_ENDIAN_BITFIELD */
2000 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
2001 uint32_t bdeFlags:8; /* BDL Flags */
2002 #endif
2003
2004 uint32_t addrLow; /* Address 0:31 */
2005 uint32_t addrHigh; /* Address 32:63 */
2006 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
2007 } ULP_BDL;
2008
2009 /*
2010 * BlockGuard Definitions
2011 */
2012
2013 enum lpfc_protgrp_type {
2014 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
2015 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
2016 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
2017 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
2018 };
2019
2020 /* PDE Descriptors */
2021 #define LPFC_PDE5_DESCRIPTOR 0x85
2022 #define LPFC_PDE6_DESCRIPTOR 0x86
2023 #define LPFC_PDE7_DESCRIPTOR 0x87
2024
2025 /* BlockGuard Opcodes */
2026 #define BG_OP_IN_NODIF_OUT_CRC 0x0
2027 #define BG_OP_IN_CRC_OUT_NODIF 0x1
2028 #define BG_OP_IN_NODIF_OUT_CSUM 0x2
2029 #define BG_OP_IN_CSUM_OUT_NODIF 0x3
2030 #define BG_OP_IN_CRC_OUT_CRC 0x4
2031 #define BG_OP_IN_CSUM_OUT_CSUM 0x5
2032 #define BG_OP_IN_CRC_OUT_CSUM 0x6
2033 #define BG_OP_IN_CSUM_OUT_CRC 0x7
2034 #define BG_OP_RAW_MODE 0x8
2035
2036 struct lpfc_pde5 {
2037 uint32_t word0;
2038 #define pde5_type_SHIFT 24
2039 #define pde5_type_MASK 0x000000ff
2040 #define pde5_type_WORD word0
2041 #define pde5_rsvd0_SHIFT 0
2042 #define pde5_rsvd0_MASK 0x00ffffff
2043 #define pde5_rsvd0_WORD word0
2044 uint32_t reftag; /* Reference Tag Value */
2045 uint32_t reftagtr; /* Reference Tag Translation Value */
2046 };
2047
2048 struct lpfc_pde6 {
2049 uint32_t word0;
2050 #define pde6_type_SHIFT 24
2051 #define pde6_type_MASK 0x000000ff
2052 #define pde6_type_WORD word0
2053 #define pde6_rsvd0_SHIFT 0
2054 #define pde6_rsvd0_MASK 0x00ffffff
2055 #define pde6_rsvd0_WORD word0
2056 uint32_t word1;
2057 #define pde6_rsvd1_SHIFT 26
2058 #define pde6_rsvd1_MASK 0x0000003f
2059 #define pde6_rsvd1_WORD word1
2060 #define pde6_na_SHIFT 25
2061 #define pde6_na_MASK 0x00000001
2062 #define pde6_na_WORD word1
2063 #define pde6_rsvd2_SHIFT 16
2064 #define pde6_rsvd2_MASK 0x000001FF
2065 #define pde6_rsvd2_WORD word1
2066 #define pde6_apptagtr_SHIFT 0
2067 #define pde6_apptagtr_MASK 0x0000ffff
2068 #define pde6_apptagtr_WORD word1
2069 uint32_t word2;
2070 #define pde6_optx_SHIFT 28
2071 #define pde6_optx_MASK 0x0000000f
2072 #define pde6_optx_WORD word2
2073 #define pde6_oprx_SHIFT 24
2074 #define pde6_oprx_MASK 0x0000000f
2075 #define pde6_oprx_WORD word2
2076 #define pde6_nr_SHIFT 23
2077 #define pde6_nr_MASK 0x00000001
2078 #define pde6_nr_WORD word2
2079 #define pde6_ce_SHIFT 22
2080 #define pde6_ce_MASK 0x00000001
2081 #define pde6_ce_WORD word2
2082 #define pde6_re_SHIFT 21
2083 #define pde6_re_MASK 0x00000001
2084 #define pde6_re_WORD word2
2085 #define pde6_ae_SHIFT 20
2086 #define pde6_ae_MASK 0x00000001
2087 #define pde6_ae_WORD word2
2088 #define pde6_ai_SHIFT 19
2089 #define pde6_ai_MASK 0x00000001
2090 #define pde6_ai_WORD word2
2091 #define pde6_bs_SHIFT 16
2092 #define pde6_bs_MASK 0x00000007
2093 #define pde6_bs_WORD word2
2094 #define pde6_apptagval_SHIFT 0
2095 #define pde6_apptagval_MASK 0x0000ffff
2096 #define pde6_apptagval_WORD word2
2097 };
2098
2099 struct lpfc_pde7 {
2100 uint32_t word0;
2101 #define pde7_type_SHIFT 24
2102 #define pde7_type_MASK 0x000000ff
2103 #define pde7_type_WORD word0
2104 #define pde7_rsvd0_SHIFT 0
2105 #define pde7_rsvd0_MASK 0x00ffffff
2106 #define pde7_rsvd0_WORD word0
2107 uint32_t addrHigh;
2108 uint32_t addrLow;
2109 };
2110
2111 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
2112
2113 typedef struct {
2114 #ifdef __BIG_ENDIAN_BITFIELD
2115 uint32_t rsvd2:25;
2116 uint32_t acknowledgment:1;
2117 uint32_t version:1;
2118 uint32_t erase_or_prog:1;
2119 uint32_t update_flash:1;
2120 uint32_t update_ram:1;
2121 uint32_t method:1;
2122 uint32_t load_cmplt:1;
2123 #else /* __LITTLE_ENDIAN_BITFIELD */
2124 uint32_t load_cmplt:1;
2125 uint32_t method:1;
2126 uint32_t update_ram:1;
2127 uint32_t update_flash:1;
2128 uint32_t erase_or_prog:1;
2129 uint32_t version:1;
2130 uint32_t acknowledgment:1;
2131 uint32_t rsvd2:25;
2132 #endif
2133
2134 uint32_t dl_to_adr_low;
2135 uint32_t dl_to_adr_high;
2136 uint32_t dl_len;
2137 union {
2138 uint32_t dl_from_mbx_offset;
2139 struct ulp_bde dl_from_bde;
2140 struct ulp_bde64 dl_from_bde64;
2141 } un;
2142
2143 } LOAD_SM_VAR;
2144
2145 /* Structure for MB Command READ_NVPARM (02) */
2146
2147 typedef struct {
2148 uint32_t rsvd1[3]; /* Read as all one's */
2149 uint32_t rsvd2; /* Read as all zero's */
2150 uint32_t portname[2]; /* N_PORT name */
2151 uint32_t nodename[2]; /* NODE name */
2152
2153 #ifdef __BIG_ENDIAN_BITFIELD
2154 uint32_t pref_DID:24;
2155 uint32_t hardAL_PA:8;
2156 #else /* __LITTLE_ENDIAN_BITFIELD */
2157 uint32_t hardAL_PA:8;
2158 uint32_t pref_DID:24;
2159 #endif
2160
2161 uint32_t rsvd3[21]; /* Read as all one's */
2162 } READ_NV_VAR;
2163
2164 /* Structure for MB Command WRITE_NVPARMS (03) */
2165
2166 typedef struct {
2167 uint32_t rsvd1[3]; /* Must be all one's */
2168 uint32_t rsvd2; /* Must be all zero's */
2169 uint32_t portname[2]; /* N_PORT name */
2170 uint32_t nodename[2]; /* NODE name */
2171
2172 #ifdef __BIG_ENDIAN_BITFIELD
2173 uint32_t pref_DID:24;
2174 uint32_t hardAL_PA:8;
2175 #else /* __LITTLE_ENDIAN_BITFIELD */
2176 uint32_t hardAL_PA:8;
2177 uint32_t pref_DID:24;
2178 #endif
2179
2180 uint32_t rsvd3[21]; /* Must be all one's */
2181 } WRITE_NV_VAR;
2182
2183 /* Structure for MB Command RUN_BIU_DIAG (04) */
2184 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2185
2186 typedef struct {
2187 uint32_t rsvd1;
2188 union {
2189 struct {
2190 struct ulp_bde xmit_bde;
2191 struct ulp_bde rcv_bde;
2192 } s1;
2193 struct {
2194 struct ulp_bde64 xmit_bde64;
2195 struct ulp_bde64 rcv_bde64;
2196 } s2;
2197 } un;
2198 } BIU_DIAG_VAR;
2199
2200 /* Structure for MB command READ_EVENT_LOG (0x38) */
2201 struct READ_EVENT_LOG_VAR {
2202 uint32_t word1;
2203 #define lpfc_event_log_SHIFT 29
2204 #define lpfc_event_log_MASK 0x00000001
2205 #define lpfc_event_log_WORD word1
2206 #define USE_MAILBOX_RESPONSE 1
2207 uint32_t offset;
2208 struct ulp_bde64 rcv_bde64;
2209 };
2210
2211 /* Structure for MB Command INIT_LINK (05) */
2212
2213 typedef struct {
2214 #ifdef __BIG_ENDIAN_BITFIELD
2215 uint32_t rsvd1:24;
2216 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2217 #else /* __LITTLE_ENDIAN_BITFIELD */
2218 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2219 uint32_t rsvd1:24;
2220 #endif
2221
2222 #ifdef __BIG_ENDIAN_BITFIELD
2223 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2224 uint8_t rsvd2;
2225 uint16_t link_flags;
2226 #else /* __LITTLE_ENDIAN_BITFIELD */
2227 uint16_t link_flags;
2228 uint8_t rsvd2;
2229 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2230 #endif
2231
2232 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
2233 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
2234 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
2235 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
2236 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
2237 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
2238 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
2239
2240 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
2241 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
2242 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
2243
2244 uint32_t link_speed;
2245 #define LINK_SPEED_AUTO 0x0 /* Auto selection */
2246 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
2247 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
2248 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
2249 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
2250 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
2251 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
2252 #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */
2253 #define LINK_SPEED_64G 0x17 /* 64 Gigabaud */
2254 #define LINK_SPEED_128G 0x1A /* 128 Gigabaud */
2255 #define LINK_SPEED_256G 0x1D /* 256 Gigabaud */
2256
2257 } INIT_LINK_VAR;
2258
2259 /* Structure for MB Command DOWN_LINK (06) */
2260
2261 typedef struct {
2262 uint32_t rsvd1;
2263 } DOWN_LINK_VAR;
2264
2265 /* Structure for MB Command CONFIG_LINK (07) */
2266
2267 typedef struct {
2268 #ifdef __BIG_ENDIAN_BITFIELD
2269 uint32_t cr:1;
2270 uint32_t ci:1;
2271 uint32_t cr_delay:6;
2272 uint32_t cr_count:8;
2273 uint32_t rsvd1:8;
2274 uint32_t MaxBBC:8;
2275 #else /* __LITTLE_ENDIAN_BITFIELD */
2276 uint32_t MaxBBC:8;
2277 uint32_t rsvd1:8;
2278 uint32_t cr_count:8;
2279 uint32_t cr_delay:6;
2280 uint32_t ci:1;
2281 uint32_t cr:1;
2282 #endif
2283
2284 uint32_t myId;
2285 uint32_t rsvd2;
2286 uint32_t edtov;
2287 uint32_t arbtov;
2288 uint32_t ratov;
2289 uint32_t rttov;
2290 uint32_t altov;
2291 uint32_t crtov;
2292
2293 #ifdef __BIG_ENDIAN_BITFIELD
2294 uint32_t rsvd4:19;
2295 uint32_t cscn:1;
2296 uint32_t bbscn:4;
2297 uint32_t rsvd3:8;
2298 #else /* __LITTLE_ENDIAN_BITFIELD */
2299 uint32_t rsvd3:8;
2300 uint32_t bbscn:4;
2301 uint32_t cscn:1;
2302 uint32_t rsvd4:19;
2303 #endif
2304
2305 #ifdef __BIG_ENDIAN_BITFIELD
2306 uint32_t rrq_enable:1;
2307 uint32_t rrq_immed:1;
2308 uint32_t rsvd5:29;
2309 uint32_t ack0_enable:1;
2310 #else /* __LITTLE_ENDIAN_BITFIELD */
2311 uint32_t ack0_enable:1;
2312 uint32_t rsvd5:29;
2313 uint32_t rrq_immed:1;
2314 uint32_t rrq_enable:1;
2315 #endif
2316 } CONFIG_LINK;
2317
2318 /* Structure for MB Command PART_SLIM (08)
2319 * will be removed since SLI1 is no longer supported!
2320 */
2321 typedef struct {
2322 #ifdef __BIG_ENDIAN_BITFIELD
2323 uint16_t offCiocb;
2324 uint16_t numCiocb;
2325 uint16_t offRiocb;
2326 uint16_t numRiocb;
2327 #else /* __LITTLE_ENDIAN_BITFIELD */
2328 uint16_t numCiocb;
2329 uint16_t offCiocb;
2330 uint16_t numRiocb;
2331 uint16_t offRiocb;
2332 #endif
2333 } RING_DEF;
2334
2335 typedef struct {
2336 #ifdef __BIG_ENDIAN_BITFIELD
2337 uint32_t unused1:24;
2338 uint32_t numRing:8;
2339 #else /* __LITTLE_ENDIAN_BITFIELD */
2340 uint32_t numRing:8;
2341 uint32_t unused1:24;
2342 #endif
2343
2344 RING_DEF ringdef[4];
2345 uint32_t hbainit;
2346 } PART_SLIM_VAR;
2347
2348 /* Structure for MB Command CONFIG_RING (09) */
2349
2350 typedef struct {
2351 #ifdef __BIG_ENDIAN_BITFIELD
2352 uint32_t unused2:6;
2353 uint32_t recvSeq:1;
2354 uint32_t recvNotify:1;
2355 uint32_t numMask:8;
2356 uint32_t profile:8;
2357 uint32_t unused1:4;
2358 uint32_t ring:4;
2359 #else /* __LITTLE_ENDIAN_BITFIELD */
2360 uint32_t ring:4;
2361 uint32_t unused1:4;
2362 uint32_t profile:8;
2363 uint32_t numMask:8;
2364 uint32_t recvNotify:1;
2365 uint32_t recvSeq:1;
2366 uint32_t unused2:6;
2367 #endif
2368
2369 #ifdef __BIG_ENDIAN_BITFIELD
2370 uint16_t maxRespXchg;
2371 uint16_t maxOrigXchg;
2372 #else /* __LITTLE_ENDIAN_BITFIELD */
2373 uint16_t maxOrigXchg;
2374 uint16_t maxRespXchg;
2375 #endif
2376
2377 RR_REG rrRegs[6];
2378 } CONFIG_RING_VAR;
2379
2380 /* Structure for MB Command RESET_RING (10) */
2381
2382 typedef struct {
2383 uint32_t ring_no;
2384 } RESET_RING_VAR;
2385
2386 /* Structure for MB Command READ_CONFIG (11) */
2387
2388 typedef struct {
2389 #ifdef __BIG_ENDIAN_BITFIELD
2390 uint32_t cr:1;
2391 uint32_t ci:1;
2392 uint32_t cr_delay:6;
2393 uint32_t cr_count:8;
2394 uint32_t InitBBC:8;
2395 uint32_t MaxBBC:8;
2396 #else /* __LITTLE_ENDIAN_BITFIELD */
2397 uint32_t MaxBBC:8;
2398 uint32_t InitBBC:8;
2399 uint32_t cr_count:8;
2400 uint32_t cr_delay:6;
2401 uint32_t ci:1;
2402 uint32_t cr:1;
2403 #endif
2404
2405 #ifdef __BIG_ENDIAN_BITFIELD
2406 uint32_t topology:8;
2407 uint32_t myDid:24;
2408 #else /* __LITTLE_ENDIAN_BITFIELD */
2409 uint32_t myDid:24;
2410 uint32_t topology:8;
2411 #endif
2412
2413 /* Defines for topology (defined previously) */
2414 #ifdef __BIG_ENDIAN_BITFIELD
2415 uint32_t AR:1;
2416 uint32_t IR:1;
2417 uint32_t rsvd1:29;
2418 uint32_t ack0:1;
2419 #else /* __LITTLE_ENDIAN_BITFIELD */
2420 uint32_t ack0:1;
2421 uint32_t rsvd1:29;
2422 uint32_t IR:1;
2423 uint32_t AR:1;
2424 #endif
2425
2426 uint32_t edtov;
2427 uint32_t arbtov;
2428 uint32_t ratov;
2429 uint32_t rttov;
2430 uint32_t altov;
2431 uint32_t lmt;
2432 #define LMT_RESERVED 0x000 /* Not used */
2433 #define LMT_1Gb 0x004
2434 #define LMT_2Gb 0x008
2435 #define LMT_4Gb 0x040
2436 #define LMT_8Gb 0x080
2437 #define LMT_10Gb 0x100
2438 #define LMT_16Gb 0x200
2439 #define LMT_32Gb 0x400
2440 #define LMT_64Gb 0x800
2441 #define LMT_128Gb 0x1000
2442 #define LMT_256Gb 0x2000
2443 uint32_t rsvd2;
2444 uint32_t rsvd3;
2445 uint32_t max_xri;
2446 uint32_t max_iocb;
2447 uint32_t max_rpi;
2448 uint32_t avail_xri;
2449 uint32_t avail_iocb;
2450 uint32_t avail_rpi;
2451 uint32_t max_vpi;
2452 uint32_t rsvd4;
2453 uint32_t rsvd5;
2454 uint32_t avail_vpi;
2455 } READ_CONFIG_VAR;
2456
2457 /* Structure for MB Command READ_RCONFIG (12) */
2458
2459 typedef struct {
2460 #ifdef __BIG_ENDIAN_BITFIELD
2461 uint32_t rsvd2:7;
2462 uint32_t recvNotify:1;
2463 uint32_t numMask:8;
2464 uint32_t profile:8;
2465 uint32_t rsvd1:4;
2466 uint32_t ring:4;
2467 #else /* __LITTLE_ENDIAN_BITFIELD */
2468 uint32_t ring:4;
2469 uint32_t rsvd1:4;
2470 uint32_t profile:8;
2471 uint32_t numMask:8;
2472 uint32_t recvNotify:1;
2473 uint32_t rsvd2:7;
2474 #endif
2475
2476 #ifdef __BIG_ENDIAN_BITFIELD
2477 uint16_t maxResp;
2478 uint16_t maxOrig;
2479 #else /* __LITTLE_ENDIAN_BITFIELD */
2480 uint16_t maxOrig;
2481 uint16_t maxResp;
2482 #endif
2483
2484 RR_REG rrRegs[6];
2485
2486 #ifdef __BIG_ENDIAN_BITFIELD
2487 uint16_t cmdRingOffset;
2488 uint16_t cmdEntryCnt;
2489 uint16_t rspRingOffset;
2490 uint16_t rspEntryCnt;
2491 uint16_t nextCmdOffset;
2492 uint16_t rsvd3;
2493 uint16_t nextRspOffset;
2494 uint16_t rsvd4;
2495 #else /* __LITTLE_ENDIAN_BITFIELD */
2496 uint16_t cmdEntryCnt;
2497 uint16_t cmdRingOffset;
2498 uint16_t rspEntryCnt;
2499 uint16_t rspRingOffset;
2500 uint16_t rsvd3;
2501 uint16_t nextCmdOffset;
2502 uint16_t rsvd4;
2503 uint16_t nextRspOffset;
2504 #endif
2505 } READ_RCONF_VAR;
2506
2507 /* Structure for MB Command READ_SPARM (13) */
2508 /* Structure for MB Command READ_SPARM64 (0x8D) */
2509
2510 typedef struct {
2511 uint32_t rsvd1;
2512 uint32_t rsvd2;
2513 union {
2514 struct ulp_bde sp; /* This BDE points to struct serv_parm
2515 structure */
2516 struct ulp_bde64 sp64;
2517 } un;
2518 #ifdef __BIG_ENDIAN_BITFIELD
2519 uint16_t rsvd3;
2520 uint16_t vpi;
2521 #else /* __LITTLE_ENDIAN_BITFIELD */
2522 uint16_t vpi;
2523 uint16_t rsvd3;
2524 #endif
2525 } READ_SPARM_VAR;
2526
2527 /* Structure for MB Command READ_STATUS (14) */
2528
2529 typedef struct {
2530 #ifdef __BIG_ENDIAN_BITFIELD
2531 uint32_t rsvd1:31;
2532 uint32_t clrCounters:1;
2533 uint16_t activeXriCnt;
2534 uint16_t activeRpiCnt;
2535 #else /* __LITTLE_ENDIAN_BITFIELD */
2536 uint32_t clrCounters:1;
2537 uint32_t rsvd1:31;
2538 uint16_t activeRpiCnt;
2539 uint16_t activeXriCnt;
2540 #endif
2541
2542 uint32_t xmitByteCnt;
2543 uint32_t rcvByteCnt;
2544 uint32_t xmitFrameCnt;
2545 uint32_t rcvFrameCnt;
2546 uint32_t xmitSeqCnt;
2547 uint32_t rcvSeqCnt;
2548 uint32_t totalOrigExchanges;
2549 uint32_t totalRespExchanges;
2550 uint32_t rcvPbsyCnt;
2551 uint32_t rcvFbsyCnt;
2552 } READ_STATUS_VAR;
2553
2554 /* Structure for MB Command READ_RPI (15) */
2555 /* Structure for MB Command READ_RPI64 (0x8F) */
2556
2557 typedef struct {
2558 #ifdef __BIG_ENDIAN_BITFIELD
2559 uint16_t nextRpi;
2560 uint16_t reqRpi;
2561 uint32_t rsvd2:8;
2562 uint32_t DID:24;
2563 #else /* __LITTLE_ENDIAN_BITFIELD */
2564 uint16_t reqRpi;
2565 uint16_t nextRpi;
2566 uint32_t DID:24;
2567 uint32_t rsvd2:8;
2568 #endif
2569
2570 union {
2571 struct ulp_bde sp;
2572 struct ulp_bde64 sp64;
2573 } un;
2574
2575 } READ_RPI_VAR;
2576
2577 /* Structure for MB Command READ_XRI (16) */
2578
2579 typedef struct {
2580 #ifdef __BIG_ENDIAN_BITFIELD
2581 uint16_t nextXri;
2582 uint16_t reqXri;
2583 uint16_t rsvd1;
2584 uint16_t rpi;
2585 uint32_t rsvd2:8;
2586 uint32_t DID:24;
2587 uint32_t rsvd3:8;
2588 uint32_t SID:24;
2589 uint32_t rsvd4;
2590 uint8_t seqId;
2591 uint8_t rsvd5;
2592 uint16_t seqCount;
2593 uint16_t oxId;
2594 uint16_t rxId;
2595 uint32_t rsvd6:30;
2596 uint32_t si:1;
2597 uint32_t exchOrig:1;
2598 #else /* __LITTLE_ENDIAN_BITFIELD */
2599 uint16_t reqXri;
2600 uint16_t nextXri;
2601 uint16_t rpi;
2602 uint16_t rsvd1;
2603 uint32_t DID:24;
2604 uint32_t rsvd2:8;
2605 uint32_t SID:24;
2606 uint32_t rsvd3:8;
2607 uint32_t rsvd4;
2608 uint16_t seqCount;
2609 uint8_t rsvd5;
2610 uint8_t seqId;
2611 uint16_t rxId;
2612 uint16_t oxId;
2613 uint32_t exchOrig:1;
2614 uint32_t si:1;
2615 uint32_t rsvd6:30;
2616 #endif
2617 } READ_XRI_VAR;
2618
2619 /* Structure for MB Command READ_REV (17) */
2620
2621 typedef struct {
2622 #ifdef __BIG_ENDIAN_BITFIELD
2623 uint32_t cv:1;
2624 uint32_t rr:1;
2625 uint32_t rsvd2:2;
2626 uint32_t v3req:1;
2627 uint32_t v3rsp:1;
2628 uint32_t rsvd1:25;
2629 uint32_t rv:1;
2630 #else /* __LITTLE_ENDIAN_BITFIELD */
2631 uint32_t rv:1;
2632 uint32_t rsvd1:25;
2633 uint32_t v3rsp:1;
2634 uint32_t v3req:1;
2635 uint32_t rsvd2:2;
2636 uint32_t rr:1;
2637 uint32_t cv:1;
2638 #endif
2639
2640 uint32_t biuRev;
2641 uint32_t smRev;
2642 union {
2643 uint32_t smFwRev;
2644 struct {
2645 #ifdef __BIG_ENDIAN_BITFIELD
2646 uint8_t ProgType;
2647 uint8_t ProgId;
2648 uint16_t ProgVer:4;
2649 uint16_t ProgRev:4;
2650 uint16_t ProgFixLvl:2;
2651 uint16_t ProgDistType:2;
2652 uint16_t DistCnt:4;
2653 #else /* __LITTLE_ENDIAN_BITFIELD */
2654 uint16_t DistCnt:4;
2655 uint16_t ProgDistType:2;
2656 uint16_t ProgFixLvl:2;
2657 uint16_t ProgRev:4;
2658 uint16_t ProgVer:4;
2659 uint8_t ProgId;
2660 uint8_t ProgType;
2661 #endif
2662
2663 } b;
2664 } un;
2665 uint32_t endecRev;
2666 #ifdef __BIG_ENDIAN_BITFIELD
2667 uint8_t feaLevelHigh;
2668 uint8_t feaLevelLow;
2669 uint8_t fcphHigh;
2670 uint8_t fcphLow;
2671 #else /* __LITTLE_ENDIAN_BITFIELD */
2672 uint8_t fcphLow;
2673 uint8_t fcphHigh;
2674 uint8_t feaLevelLow;
2675 uint8_t feaLevelHigh;
2676 #endif
2677
2678 uint32_t postKernRev;
2679 uint32_t opFwRev;
2680 uint8_t opFwName[16];
2681 uint32_t sli1FwRev;
2682 uint8_t sli1FwName[16];
2683 uint32_t sli2FwRev;
2684 uint8_t sli2FwName[16];
2685 uint32_t sli3Feat;
2686 uint32_t RandomData[6];
2687 } READ_REV_VAR;
2688
2689 /* Structure for MB Command READ_LINK_STAT (18) */
2690
2691 typedef struct {
2692 uint32_t word0;
2693
2694 #define lpfc_read_link_stat_rec_SHIFT 0
2695 #define lpfc_read_link_stat_rec_MASK 0x1
2696 #define lpfc_read_link_stat_rec_WORD word0
2697
2698 #define lpfc_read_link_stat_gec_SHIFT 1
2699 #define lpfc_read_link_stat_gec_MASK 0x1
2700 #define lpfc_read_link_stat_gec_WORD word0
2701
2702 #define lpfc_read_link_stat_w02oftow23of_SHIFT 2
2703 #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF
2704 #define lpfc_read_link_stat_w02oftow23of_WORD word0
2705
2706 #define lpfc_read_link_stat_rsvd_SHIFT 24
2707 #define lpfc_read_link_stat_rsvd_MASK 0x1F
2708 #define lpfc_read_link_stat_rsvd_WORD word0
2709
2710 #define lpfc_read_link_stat_gec2_SHIFT 29
2711 #define lpfc_read_link_stat_gec2_MASK 0x1
2712 #define lpfc_read_link_stat_gec2_WORD word0
2713
2714 #define lpfc_read_link_stat_clrc_SHIFT 30
2715 #define lpfc_read_link_stat_clrc_MASK 0x1
2716 #define lpfc_read_link_stat_clrc_WORD word0
2717
2718 #define lpfc_read_link_stat_clof_SHIFT 31
2719 #define lpfc_read_link_stat_clof_MASK 0x1
2720 #define lpfc_read_link_stat_clof_WORD word0
2721
2722 uint32_t linkFailureCnt;
2723 uint32_t lossSyncCnt;
2724 uint32_t lossSignalCnt;
2725 uint32_t primSeqErrCnt;
2726 uint32_t invalidXmitWord;
2727 uint32_t crcCnt;
2728 uint32_t primSeqTimeout;
2729 uint32_t elasticOverrun;
2730 uint32_t arbTimeout;
2731 uint32_t advRecBufCredit;
2732 uint32_t curRecBufCredit;
2733 uint32_t advTransBufCredit;
2734 uint32_t curTransBufCredit;
2735 uint32_t recEofCount;
2736 uint32_t recEofdtiCount;
2737 uint32_t recEofniCount;
2738 uint32_t recSofcount;
2739 uint32_t rsvd1;
2740 uint32_t rsvd2;
2741 uint32_t recDrpXriCount;
2742 uint32_t fecCorrBlkCount;
2743 uint32_t fecUncorrBlkCount;
2744 } READ_LNK_VAR;
2745
2746 /* Structure for MB Command REG_LOGIN (19) */
2747 /* Structure for MB Command REG_LOGIN64 (0x93) */
2748
2749 typedef struct {
2750 #ifdef __BIG_ENDIAN_BITFIELD
2751 uint16_t rsvd1;
2752 uint16_t rpi;
2753 uint32_t rsvd2:8;
2754 uint32_t did:24;
2755 #else /* __LITTLE_ENDIAN_BITFIELD */
2756 uint16_t rpi;
2757 uint16_t rsvd1;
2758 uint32_t did:24;
2759 uint32_t rsvd2:8;
2760 #endif
2761
2762 union {
2763 struct ulp_bde sp;
2764 struct ulp_bde64 sp64;
2765 } un;
2766
2767 #ifdef __BIG_ENDIAN_BITFIELD
2768 uint16_t rsvd6;
2769 uint16_t vpi;
2770 #else /* __LITTLE_ENDIAN_BITFIELD */
2771 uint16_t vpi;
2772 uint16_t rsvd6;
2773 #endif
2774
2775 } REG_LOGIN_VAR;
2776
2777 /* Word 30 contents for REG_LOGIN */
2778 typedef union {
2779 struct {
2780 #ifdef __BIG_ENDIAN_BITFIELD
2781 uint16_t rsvd1:12;
2782 uint16_t wd30_class:4;
2783 uint16_t xri;
2784 #else /* __LITTLE_ENDIAN_BITFIELD */
2785 uint16_t xri;
2786 uint16_t wd30_class:4;
2787 uint16_t rsvd1:12;
2788 #endif
2789 } f;
2790 uint32_t word;
2791 } REG_WD30;
2792
2793 /* Structure for MB Command UNREG_LOGIN (20) */
2794
2795 typedef struct {
2796 #ifdef __BIG_ENDIAN_BITFIELD
2797 uint16_t rsvd1;
2798 uint16_t rpi;
2799 uint32_t rsvd2;
2800 uint32_t rsvd3;
2801 uint32_t rsvd4;
2802 uint32_t rsvd5;
2803 uint16_t rsvd6;
2804 uint16_t vpi;
2805 #else /* __LITTLE_ENDIAN_BITFIELD */
2806 uint16_t rpi;
2807 uint16_t rsvd1;
2808 uint32_t rsvd2;
2809 uint32_t rsvd3;
2810 uint32_t rsvd4;
2811 uint32_t rsvd5;
2812 uint16_t vpi;
2813 uint16_t rsvd6;
2814 #endif
2815 } UNREG_LOGIN_VAR;
2816
2817 /* Structure for MB Command REG_VPI (0x96) */
2818 typedef struct {
2819 #ifdef __BIG_ENDIAN_BITFIELD
2820 uint32_t rsvd1;
2821 uint32_t rsvd2:7;
2822 uint32_t upd:1;
2823 uint32_t sid:24;
2824 uint32_t wwn[2];
2825 uint32_t rsvd5;
2826 uint16_t vfi;
2827 uint16_t vpi;
2828 #else /* __LITTLE_ENDIAN */
2829 uint32_t rsvd1;
2830 uint32_t sid:24;
2831 uint32_t upd:1;
2832 uint32_t rsvd2:7;
2833 uint32_t wwn[2];
2834 uint32_t rsvd5;
2835 uint16_t vpi;
2836 uint16_t vfi;
2837 #endif
2838 } REG_VPI_VAR;
2839
2840 /* Structure for MB Command UNREG_VPI (0x97) */
2841 typedef struct {
2842 uint32_t rsvd1;
2843 #ifdef __BIG_ENDIAN_BITFIELD
2844 uint16_t rsvd2;
2845 uint16_t sli4_vpi;
2846 #else /* __LITTLE_ENDIAN */
2847 uint16_t sli4_vpi;
2848 uint16_t rsvd2;
2849 #endif
2850 uint32_t rsvd3;
2851 uint32_t rsvd4;
2852 uint32_t rsvd5;
2853 #ifdef __BIG_ENDIAN_BITFIELD
2854 uint16_t rsvd6;
2855 uint16_t vpi;
2856 #else /* __LITTLE_ENDIAN */
2857 uint16_t vpi;
2858 uint16_t rsvd6;
2859 #endif
2860 } UNREG_VPI_VAR;
2861
2862 /* Structure for MB Command UNREG_D_ID (0x23) */
2863
2864 typedef struct {
2865 uint32_t did;
2866 uint32_t rsvd2;
2867 uint32_t rsvd3;
2868 uint32_t rsvd4;
2869 uint32_t rsvd5;
2870 #ifdef __BIG_ENDIAN_BITFIELD
2871 uint16_t rsvd6;
2872 uint16_t vpi;
2873 #else
2874 uint16_t vpi;
2875 uint16_t rsvd6;
2876 #endif
2877 } UNREG_D_ID_VAR;
2878
2879 /* Structure for MB Command READ_TOPOLOGY (0x95) */
2880 struct lpfc_mbx_read_top {
2881 uint32_t eventTag; /* Event tag */
2882 uint32_t word2;
2883 #define lpfc_mbx_read_top_fa_SHIFT 12
2884 #define lpfc_mbx_read_top_fa_MASK 0x00000001
2885 #define lpfc_mbx_read_top_fa_WORD word2
2886 #define lpfc_mbx_read_top_mm_SHIFT 11
2887 #define lpfc_mbx_read_top_mm_MASK 0x00000001
2888 #define lpfc_mbx_read_top_mm_WORD word2
2889 #define lpfc_mbx_read_top_pb_SHIFT 9
2890 #define lpfc_mbx_read_top_pb_MASK 0X00000001
2891 #define lpfc_mbx_read_top_pb_WORD word2
2892 #define lpfc_mbx_read_top_il_SHIFT 8
2893 #define lpfc_mbx_read_top_il_MASK 0x00000001
2894 #define lpfc_mbx_read_top_il_WORD word2
2895 #define lpfc_mbx_read_top_att_type_SHIFT 0
2896 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF
2897 #define lpfc_mbx_read_top_att_type_WORD word2
2898 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
2899 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */
2900 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
2901 #define LPFC_ATT_UNEXP_WWPN 0x06 /* Link is down Unexpected WWWPN */
2902 uint32_t word3;
2903 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24
2904 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
2905 #define lpfc_mbx_read_top_alpa_granted_WORD word3
2906 #define lpfc_mbx_read_top_lip_alps_SHIFT 16
2907 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
2908 #define lpfc_mbx_read_top_lip_alps_WORD word3
2909 #define lpfc_mbx_read_top_lip_type_SHIFT 8
2910 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
2911 #define lpfc_mbx_read_top_lip_type_WORD word3
2912 #define lpfc_mbx_read_top_topology_SHIFT 0
2913 #define lpfc_mbx_read_top_topology_MASK 0x000000FF
2914 #define lpfc_mbx_read_top_topology_WORD word3
2915 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2916 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2917 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */
2918 /* store the LILP AL_PA position map into */
2919 struct ulp_bde64 lilpBde64;
2920 #define LPFC_ALPA_MAP_SIZE 128
2921 uint32_t word7;
2922 #define lpfc_mbx_read_top_ld_lu_SHIFT 31
2923 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
2924 #define lpfc_mbx_read_top_ld_lu_WORD word7
2925 #define lpfc_mbx_read_top_ld_tf_SHIFT 30
2926 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
2927 #define lpfc_mbx_read_top_ld_tf_WORD word7
2928 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
2929 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
2930 #define lpfc_mbx_read_top_ld_link_spd_WORD word7
2931 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
2932 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
2933 #define lpfc_mbx_read_top_ld_nl_port_WORD word7
2934 #define lpfc_mbx_read_top_ld_tx_SHIFT 2
2935 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
2936 #define lpfc_mbx_read_top_ld_tx_WORD word7
2937 #define lpfc_mbx_read_top_ld_rx_SHIFT 0
2938 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
2939 #define lpfc_mbx_read_top_ld_rx_WORD word7
2940 uint32_t word8;
2941 #define lpfc_mbx_read_top_lu_SHIFT 31
2942 #define lpfc_mbx_read_top_lu_MASK 0x00000001
2943 #define lpfc_mbx_read_top_lu_WORD word8
2944 #define lpfc_mbx_read_top_tf_SHIFT 30
2945 #define lpfc_mbx_read_top_tf_MASK 0x00000001
2946 #define lpfc_mbx_read_top_tf_WORD word8
2947 #define lpfc_mbx_read_top_link_spd_SHIFT 8
2948 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
2949 #define lpfc_mbx_read_top_link_spd_WORD word8
2950 #define lpfc_mbx_read_top_nl_port_SHIFT 4
2951 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
2952 #define lpfc_mbx_read_top_nl_port_WORD word8
2953 #define lpfc_mbx_read_top_tx_SHIFT 2
2954 #define lpfc_mbx_read_top_tx_MASK 0x00000003
2955 #define lpfc_mbx_read_top_tx_WORD word8
2956 #define lpfc_mbx_read_top_rx_SHIFT 0
2957 #define lpfc_mbx_read_top_rx_MASK 0x00000003
2958 #define lpfc_mbx_read_top_rx_WORD word8
2959 #define LPFC_LINK_SPEED_UNKNOWN 0x0
2960 #define LPFC_LINK_SPEED_1GHZ 0x04
2961 #define LPFC_LINK_SPEED_2GHZ 0x08
2962 #define LPFC_LINK_SPEED_4GHZ 0x10
2963 #define LPFC_LINK_SPEED_8GHZ 0x20
2964 #define LPFC_LINK_SPEED_10GHZ 0x40
2965 #define LPFC_LINK_SPEED_16GHZ 0x80
2966 #define LPFC_LINK_SPEED_32GHZ 0x90
2967 #define LPFC_LINK_SPEED_64GHZ 0xA0
2968 #define LPFC_LINK_SPEED_128GHZ 0xB0
2969 #define LPFC_LINK_SPEED_256GHZ 0xC0
2970 };
2971
2972 /* Structure for MB Command CLEAR_LA (22) */
2973
2974 typedef struct {
2975 uint32_t eventTag; /* Event tag */
2976 uint32_t rsvd1;
2977 } CLEAR_LA_VAR;
2978
2979 /* Structure for MB Command DUMP */
2980
2981 typedef struct {
2982 #ifdef __BIG_ENDIAN_BITFIELD
2983 uint32_t rsvd:25;
2984 uint32_t ra:1;
2985 uint32_t co:1;
2986 uint32_t cv:1;
2987 uint32_t type:4;
2988 uint32_t entry_index:16;
2989 uint32_t region_id:16;
2990 #else /* __LITTLE_ENDIAN_BITFIELD */
2991 uint32_t type:4;
2992 uint32_t cv:1;
2993 uint32_t co:1;
2994 uint32_t ra:1;
2995 uint32_t rsvd:25;
2996 uint32_t region_id:16;
2997 uint32_t entry_index:16;
2998 #endif
2999
3000 uint32_t sli4_length;
3001 uint32_t word_cnt;
3002 uint32_t resp_offset;
3003 } DUMP_VAR;
3004
3005 #define DMP_MEM_REG 0x1
3006 #define DMP_NV_PARAMS 0x2
3007 #define DMP_LMSD 0x3 /* Link Module Serial Data */
3008 #define DMP_WELL_KNOWN 0x4
3009
3010 #define DMP_REGION_VPD 0xe
3011 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
3012 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
3013 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
3014
3015 #define DMP_REGION_VPORT 0x16 /* VPort info region */
3016 #define DMP_VPORT_REGION_SIZE 0x200
3017 #define DMP_MBOX_OFFSET_WORD 0x5
3018
3019 #define DMP_REGION_23 0x17 /* fcoe param and port state region */
3020 #define DMP_RGN23_SIZE 0x400
3021
3022 #define WAKE_UP_PARMS_REGION_ID 4
3023 #define WAKE_UP_PARMS_WORD_SIZE 15
3024
3025 struct vport_rec {
3026 uint8_t wwpn[8];
3027 uint8_t wwnn[8];
3028 };
3029
3030 #define VPORT_INFO_SIG 0x32324752
3031 #define VPORT_INFO_REV_MASK 0xff
3032 #define VPORT_INFO_REV 0x1
3033 #define MAX_STATIC_VPORT_COUNT 16
3034 struct static_vport_info {
3035 uint32_t signature;
3036 uint32_t rev;
3037 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
3038 uint32_t resvd[66];
3039 };
3040
3041 /* Option rom version structure */
3042 struct prog_id {
3043 #ifdef __BIG_ENDIAN_BITFIELD
3044 uint8_t type;
3045 uint8_t id;
3046 uint32_t ver:4; /* Major Version */
3047 uint32_t rev:4; /* Revision */
3048 uint32_t lev:2; /* Level */
3049 uint32_t dist:2; /* Dist Type */
3050 uint32_t num:4; /* number after dist type */
3051 #else /* __LITTLE_ENDIAN_BITFIELD */
3052 uint32_t num:4; /* number after dist type */
3053 uint32_t dist:2; /* Dist Type */
3054 uint32_t lev:2; /* Level */
3055 uint32_t rev:4; /* Revision */
3056 uint32_t ver:4; /* Major Version */
3057 uint8_t id;
3058 uint8_t type;
3059 #endif
3060 };
3061
3062 /* Structure for MB Command UPDATE_CFG (0x1B) */
3063
3064 struct update_cfg_var {
3065 #ifdef __BIG_ENDIAN_BITFIELD
3066 uint32_t rsvd2:16;
3067 uint32_t type:8;
3068 uint32_t rsvd:1;
3069 uint32_t ra:1;
3070 uint32_t co:1;
3071 uint32_t cv:1;
3072 uint32_t req:4;
3073 uint32_t entry_length:16;
3074 uint32_t region_id:16;
3075 #else /* __LITTLE_ENDIAN_BITFIELD */
3076 uint32_t req:4;
3077 uint32_t cv:1;
3078 uint32_t co:1;
3079 uint32_t ra:1;
3080 uint32_t rsvd:1;
3081 uint32_t type:8;
3082 uint32_t rsvd2:16;
3083 uint32_t region_id:16;
3084 uint32_t entry_length:16;
3085 #endif
3086
3087 uint32_t resp_info;
3088 uint32_t byte_cnt;
3089 uint32_t data_offset;
3090 };
3091
3092 struct hbq_mask {
3093 #ifdef __BIG_ENDIAN_BITFIELD
3094 uint8_t tmatch;
3095 uint8_t tmask;
3096 uint8_t rctlmatch;
3097 uint8_t rctlmask;
3098 #else /* __LITTLE_ENDIAN */
3099 uint8_t rctlmask;
3100 uint8_t rctlmatch;
3101 uint8_t tmask;
3102 uint8_t tmatch;
3103 #endif
3104 };
3105
3106
3107 /* Structure for MB Command CONFIG_HBQ (7c) */
3108
3109 struct config_hbq_var {
3110 #ifdef __BIG_ENDIAN_BITFIELD
3111 uint32_t rsvd1 :7;
3112 uint32_t recvNotify :1; /* Receive Notification */
3113 uint32_t numMask :8; /* # Mask Entries */
3114 uint32_t profile :8; /* Selection Profile */
3115 uint32_t rsvd2 :8;
3116 #else /* __LITTLE_ENDIAN */
3117 uint32_t rsvd2 :8;
3118 uint32_t profile :8; /* Selection Profile */
3119 uint32_t numMask :8; /* # Mask Entries */
3120 uint32_t recvNotify :1; /* Receive Notification */
3121 uint32_t rsvd1 :7;
3122 #endif
3123
3124 #ifdef __BIG_ENDIAN_BITFIELD
3125 uint32_t hbqId :16;
3126 uint32_t rsvd3 :12;
3127 uint32_t ringMask :4;
3128 #else /* __LITTLE_ENDIAN */
3129 uint32_t ringMask :4;
3130 uint32_t rsvd3 :12;
3131 uint32_t hbqId :16;
3132 #endif
3133
3134 #ifdef __BIG_ENDIAN_BITFIELD
3135 uint32_t entry_count :16;
3136 uint32_t rsvd4 :8;
3137 uint32_t headerLen :8;
3138 #else /* __LITTLE_ENDIAN */
3139 uint32_t headerLen :8;
3140 uint32_t rsvd4 :8;
3141 uint32_t entry_count :16;
3142 #endif
3143
3144 uint32_t hbqaddrLow;
3145 uint32_t hbqaddrHigh;
3146
3147 #ifdef __BIG_ENDIAN_BITFIELD
3148 uint32_t rsvd5 :31;
3149 uint32_t logEntry :1;
3150 #else /* __LITTLE_ENDIAN */
3151 uint32_t logEntry :1;
3152 uint32_t rsvd5 :31;
3153 #endif
3154
3155 uint32_t rsvd6; /* w7 */
3156 uint32_t rsvd7; /* w8 */
3157 uint32_t rsvd8; /* w9 */
3158
3159 struct hbq_mask hbqMasks[6];
3160
3161
3162 union {
3163 uint32_t allprofiles[12];
3164
3165 struct {
3166 #ifdef __BIG_ENDIAN_BITFIELD
3167 uint32_t seqlenoff :16;
3168 uint32_t maxlen :16;
3169 #else /* __LITTLE_ENDIAN */
3170 uint32_t maxlen :16;
3171 uint32_t seqlenoff :16;
3172 #endif
3173 #ifdef __BIG_ENDIAN_BITFIELD
3174 uint32_t rsvd1 :28;
3175 uint32_t seqlenbcnt :4;
3176 #else /* __LITTLE_ENDIAN */
3177 uint32_t seqlenbcnt :4;
3178 uint32_t rsvd1 :28;
3179 #endif
3180 uint32_t rsvd[10];
3181 } profile2;
3182
3183 struct {
3184 #ifdef __BIG_ENDIAN_BITFIELD
3185 uint32_t seqlenoff :16;
3186 uint32_t maxlen :16;
3187 #else /* __LITTLE_ENDIAN */
3188 uint32_t maxlen :16;
3189 uint32_t seqlenoff :16;
3190 #endif
3191 #ifdef __BIG_ENDIAN_BITFIELD
3192 uint32_t cmdcodeoff :28;
3193 uint32_t rsvd1 :12;
3194 uint32_t seqlenbcnt :4;
3195 #else /* __LITTLE_ENDIAN */
3196 uint32_t seqlenbcnt :4;
3197 uint32_t rsvd1 :12;
3198 uint32_t cmdcodeoff :28;
3199 #endif
3200 uint32_t cmdmatch[8];
3201
3202 uint32_t rsvd[2];
3203 } profile3;
3204
3205 struct {
3206 #ifdef __BIG_ENDIAN_BITFIELD
3207 uint32_t seqlenoff :16;
3208 uint32_t maxlen :16;
3209 #else /* __LITTLE_ENDIAN */
3210 uint32_t maxlen :16;
3211 uint32_t seqlenoff :16;
3212 #endif
3213 #ifdef __BIG_ENDIAN_BITFIELD
3214 uint32_t cmdcodeoff :28;
3215 uint32_t rsvd1 :12;
3216 uint32_t seqlenbcnt :4;
3217 #else /* __LITTLE_ENDIAN */
3218 uint32_t seqlenbcnt :4;
3219 uint32_t rsvd1 :12;
3220 uint32_t cmdcodeoff :28;
3221 #endif
3222 uint32_t cmdmatch[8];
3223
3224 uint32_t rsvd[2];
3225 } profile5;
3226
3227 } profiles;
3228
3229 };
3230
3231
3232
3233 /* Structure for MB Command CONFIG_PORT (0x88) */
3234 typedef struct {
3235 #ifdef __BIG_ENDIAN_BITFIELD
3236 uint32_t cBE : 1;
3237 uint32_t cET : 1;
3238 uint32_t cHpcb : 1;
3239 uint32_t cMA : 1;
3240 uint32_t sli_mode : 4;
3241 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3242 * config block */
3243 #else /* __LITTLE_ENDIAN */
3244 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3245 * config block */
3246 uint32_t sli_mode : 4;
3247 uint32_t cMA : 1;
3248 uint32_t cHpcb : 1;
3249 uint32_t cET : 1;
3250 uint32_t cBE : 1;
3251 #endif
3252
3253 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
3254 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
3255 uint32_t hbainit[5];
3256 #ifdef __BIG_ENDIAN_BITFIELD
3257 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3258 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3259 #else /* __LITTLE_ENDIAN */
3260 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3261 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3262 #endif
3263
3264 #ifdef __BIG_ENDIAN_BITFIELD
3265 uint32_t rsvd1 : 20; /* Reserved */
3266 uint32_t casabt : 1; /* Configure async abts status notice */
3267 uint32_t rsvd2 : 2; /* Reserved */
3268 uint32_t cbg : 1; /* Configure BlockGuard */
3269 uint32_t cmv : 1; /* Configure Max VPIs */
3270 uint32_t ccrp : 1; /* Config Command Ring Polling */
3271 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3272 uint32_t chbs : 1; /* Cofigure Host Backing store */
3273 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3274 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3275 uint32_t cmx : 1; /* Configure Max XRIs */
3276 uint32_t cmr : 1; /* Configure Max RPIs */
3277 #else /* __LITTLE_ENDIAN */
3278 uint32_t cmr : 1; /* Configure Max RPIs */
3279 uint32_t cmx : 1; /* Configure Max XRIs */
3280 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3281 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3282 uint32_t chbs : 1; /* Cofigure Host Backing store */
3283 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3284 uint32_t ccrp : 1; /* Config Command Ring Polling */
3285 uint32_t cmv : 1; /* Configure Max VPIs */
3286 uint32_t cbg : 1; /* Configure BlockGuard */
3287 uint32_t rsvd2 : 2; /* Reserved */
3288 uint32_t casabt : 1; /* Configure async abts status notice */
3289 uint32_t rsvd1 : 20; /* Reserved */
3290 #endif
3291 #ifdef __BIG_ENDIAN_BITFIELD
3292 uint32_t rsvd3 : 20; /* Reserved */
3293 uint32_t gasabt : 1; /* Grant async abts status notice */
3294 uint32_t rsvd4 : 2; /* Reserved */
3295 uint32_t gbg : 1; /* Grant BlockGuard */
3296 uint32_t gmv : 1; /* Grant Max VPIs */
3297 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3298 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3299 uint32_t ghbs : 1; /* Grant Host Backing Store */
3300 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3301 uint32_t gerbm : 1; /* Grant ERBM Request */
3302 uint32_t gmx : 1; /* Grant Max XRIs */
3303 uint32_t gmr : 1; /* Grant Max RPIs */
3304 #else /* __LITTLE_ENDIAN */
3305 uint32_t gmr : 1; /* Grant Max RPIs */
3306 uint32_t gmx : 1; /* Grant Max XRIs */
3307 uint32_t gerbm : 1; /* Grant ERBM Request */
3308 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3309 uint32_t ghbs : 1; /* Grant Host Backing Store */
3310 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3311 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3312 uint32_t gmv : 1; /* Grant Max VPIs */
3313 uint32_t gbg : 1; /* Grant BlockGuard */
3314 uint32_t rsvd4 : 2; /* Reserved */
3315 uint32_t gasabt : 1; /* Grant async abts status notice */
3316 uint32_t rsvd3 : 20; /* Reserved */
3317 #endif
3318
3319 #ifdef __BIG_ENDIAN_BITFIELD
3320 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3321 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3322 #else /* __LITTLE_ENDIAN */
3323 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3324 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3325 #endif
3326
3327 #ifdef __BIG_ENDIAN_BITFIELD
3328 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3329 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3330 #else /* __LITTLE_ENDIAN */
3331 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3332 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3333 #endif
3334
3335 uint32_t rsvd6; /* Reserved */
3336
3337 #ifdef __BIG_ENDIAN_BITFIELD
3338 uint32_t rsvd7 : 16;
3339 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3340 #else /* __LITTLE_ENDIAN */
3341 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3342 uint32_t rsvd7 : 16;
3343 #endif
3344
3345 } CONFIG_PORT_VAR;
3346
3347 /* Structure for MB Command CONFIG_MSI (0x30) */
3348 struct config_msi_var {
3349 #ifdef __BIG_ENDIAN_BITFIELD
3350 uint32_t dfltMsgNum:8; /* Default message number */
3351 uint32_t rsvd1:11; /* Reserved */
3352 uint32_t NID:5; /* Number of secondary attention IDs */
3353 uint32_t rsvd2:5; /* Reserved */
3354 uint32_t dfltPresent:1; /* Default message number present */
3355 uint32_t addFlag:1; /* Add association flag */
3356 uint32_t reportFlag:1; /* Report association flag */
3357 #else /* __LITTLE_ENDIAN_BITFIELD */
3358 uint32_t reportFlag:1; /* Report association flag */
3359 uint32_t addFlag:1; /* Add association flag */
3360 uint32_t dfltPresent:1; /* Default message number present */
3361 uint32_t rsvd2:5; /* Reserved */
3362 uint32_t NID:5; /* Number of secondary attention IDs */
3363 uint32_t rsvd1:11; /* Reserved */
3364 uint32_t dfltMsgNum:8; /* Default message number */
3365 #endif
3366 uint32_t attentionConditions[2];
3367 uint8_t attentionId[16];
3368 uint8_t messageNumberByHA[64];
3369 uint8_t messageNumberByID[16];
3370 uint32_t autoClearHA[2];
3371 #ifdef __BIG_ENDIAN_BITFIELD
3372 uint32_t rsvd3:16;
3373 uint32_t autoClearID:16;
3374 #else /* __LITTLE_ENDIAN_BITFIELD */
3375 uint32_t autoClearID:16;
3376 uint32_t rsvd3:16;
3377 #endif
3378 uint32_t rsvd4;
3379 };
3380
3381 /* SLI-2 Port Control Block */
3382
3383 /* SLIM POINTER */
3384 #define SLIMOFF 0x30 /* WORD */
3385
3386 typedef struct _SLI2_RDSC {
3387 uint32_t cmdEntries;
3388 uint32_t cmdAddrLow;
3389 uint32_t cmdAddrHigh;
3390
3391 uint32_t rspEntries;
3392 uint32_t rspAddrLow;
3393 uint32_t rspAddrHigh;
3394 } SLI2_RDSC;
3395
3396 typedef struct _PCB {
3397 #ifdef __BIG_ENDIAN_BITFIELD
3398 uint32_t type:8;
3399 #define TYPE_NATIVE_SLI2 0x01
3400 uint32_t feature:8;
3401 #define FEATURE_INITIAL_SLI2 0x01
3402 uint32_t rsvd:12;
3403 uint32_t maxRing:4;
3404 #else /* __LITTLE_ENDIAN_BITFIELD */
3405 uint32_t maxRing:4;
3406 uint32_t rsvd:12;
3407 uint32_t feature:8;
3408 #define FEATURE_INITIAL_SLI2 0x01
3409 uint32_t type:8;
3410 #define TYPE_NATIVE_SLI2 0x01
3411 #endif
3412
3413 uint32_t mailBoxSize;
3414 uint32_t mbAddrLow;
3415 uint32_t mbAddrHigh;
3416
3417 uint32_t hgpAddrLow;
3418 uint32_t hgpAddrHigh;
3419
3420 uint32_t pgpAddrLow;
3421 uint32_t pgpAddrHigh;
3422 SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3423 } PCB_t;
3424
3425 /* NEW_FEATURE */
3426 typedef struct {
3427 #ifdef __BIG_ENDIAN_BITFIELD
3428 uint32_t rsvd0:27;
3429 uint32_t discardFarp:1;
3430 uint32_t IPEnable:1;
3431 uint32_t nodeName:1;
3432 uint32_t portName:1;
3433 uint32_t filterEnable:1;
3434 #else /* __LITTLE_ENDIAN_BITFIELD */
3435 uint32_t filterEnable:1;
3436 uint32_t portName:1;
3437 uint32_t nodeName:1;
3438 uint32_t IPEnable:1;
3439 uint32_t discardFarp:1;
3440 uint32_t rsvd:27;
3441 #endif
3442
3443 uint8_t portname[8]; /* Used to be struct lpfc_name */
3444 uint8_t nodename[8];
3445 uint32_t rsvd1;
3446 uint32_t rsvd2;
3447 uint32_t rsvd3;
3448 uint32_t IPAddress;
3449 } CONFIG_FARP_VAR;
3450
3451 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3452
3453 typedef struct {
3454 #ifdef __BIG_ENDIAN_BITFIELD
3455 uint32_t rsvd:30;
3456 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3457 #else /* __LITTLE_ENDIAN */
3458 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3459 uint32_t rsvd:30;
3460 #endif
3461 } ASYNCEVT_ENABLE_VAR;
3462
3463 /* Union of all Mailbox Command types */
3464 #define MAILBOX_CMD_WSIZE 32
3465 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3466 /* ext_wsize times 4 bytes should not be greater than max xmit size */
3467 #define MAILBOX_EXT_WSIZE 512
3468 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3469 #define MAILBOX_HBA_EXT_OFFSET 0x100
3470 /* max mbox xmit size is a page size for sysfs IO operations */
3471 #define MAILBOX_SYSFS_MAX 4096
3472
3473 typedef union {
3474 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3475 * feature/max ring number
3476 */
3477 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
3478 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
3479 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
3480 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
3481 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
3482 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
3483 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
3484 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
3485 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
3486 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
3487 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
3488 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
3489 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
3490 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
3491 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
3492 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
3493 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
3494 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
3495 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
3496 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
3497 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
3498 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
3499 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3500 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3501 * NEW_FEATURE
3502 */
3503 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
3504 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3505 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
3506 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3507 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3508 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
3509 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3510 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3511 * (READ_EVENT_LOG)
3512 */
3513 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
3514 } MAILVARIANTS;
3515
3516 /*
3517 * SLI-2 specific structures
3518 */
3519
3520 struct lpfc_hgp {
3521 __le32 cmdPutInx;
3522 __le32 rspGetInx;
3523 };
3524
3525 struct lpfc_pgp {
3526 __le32 cmdGetInx;
3527 __le32 rspPutInx;
3528 };
3529
3530 struct sli2_desc {
3531 uint32_t unused1[16];
3532 struct lpfc_hgp host[MAX_SLI3_RINGS];
3533 struct lpfc_pgp port[MAX_SLI3_RINGS];
3534 };
3535
3536 struct sli3_desc {
3537 struct lpfc_hgp host[MAX_SLI3_RINGS];
3538 uint32_t reserved[8];
3539 uint32_t hbq_put[16];
3540 };
3541
3542 struct sli3_pgp {
3543 struct lpfc_pgp port[MAX_SLI3_RINGS];
3544 uint32_t hbq_get[16];
3545 };
3546
3547 union sli_var {
3548 struct sli2_desc s2;
3549 struct sli3_desc s3;
3550 struct sli3_pgp s3_pgp;
3551 };
3552
3553 typedef struct {
3554 #ifdef __BIG_ENDIAN_BITFIELD
3555 uint16_t mbxStatus;
3556 uint8_t mbxCommand;
3557 uint8_t mbxReserved:6;
3558 uint8_t mbxHc:1;
3559 uint8_t mbxOwner:1; /* Low order bit first word */
3560 #else /* __LITTLE_ENDIAN_BITFIELD */
3561 uint8_t mbxOwner:1; /* Low order bit first word */
3562 uint8_t mbxHc:1;
3563 uint8_t mbxReserved:6;
3564 uint8_t mbxCommand;
3565 uint16_t mbxStatus;
3566 #endif
3567
3568 MAILVARIANTS un;
3569 union sli_var us;
3570 } MAILBOX_t;
3571
3572 /*
3573 * Begin Structure Definitions for IOCB Commands
3574 */
3575
3576 typedef struct {
3577 #ifdef __BIG_ENDIAN_BITFIELD
3578 uint8_t statAction;
3579 uint8_t statRsn;
3580 uint8_t statBaExp;
3581 uint8_t statLocalError;
3582 #else /* __LITTLE_ENDIAN_BITFIELD */
3583 uint8_t statLocalError;
3584 uint8_t statBaExp;
3585 uint8_t statRsn;
3586 uint8_t statAction;
3587 #endif
3588 /* statRsn P/F_RJT reason codes */
3589 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3590 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3591 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3592 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3593 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3594 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3595 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3596 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3597 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3598 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3599 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3600 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3601 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3602 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3603 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3604 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
3605 #define RJT_XCHG_ERR 0x11 /* Exchange error */
3606 #define RJT_PROT_ERR 0x12 /* Protocol error */
3607 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3608 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3609 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3610 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3611 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3612 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3613 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3614 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3615
3616 #define IOERR_SUCCESS 0x00 /* statLocalError */
3617 #define IOERR_MISSING_CONTINUE 0x01
3618 #define IOERR_SEQUENCE_TIMEOUT 0x02
3619 #define IOERR_INTERNAL_ERROR 0x03
3620 #define IOERR_INVALID_RPI 0x04
3621 #define IOERR_NO_XRI 0x05
3622 #define IOERR_ILLEGAL_COMMAND 0x06
3623 #define IOERR_XCHG_DROPPED 0x07
3624 #define IOERR_ILLEGAL_FIELD 0x08
3625 #define IOERR_BAD_CONTINUE 0x09
3626 #define IOERR_TOO_MANY_BUFFERS 0x0A
3627 #define IOERR_RCV_BUFFER_WAITING 0x0B
3628 #define IOERR_NO_CONNECTION 0x0C
3629 #define IOERR_TX_DMA_FAILED 0x0D
3630 #define IOERR_RX_DMA_FAILED 0x0E
3631 #define IOERR_ILLEGAL_FRAME 0x0F
3632 #define IOERR_EXTRA_DATA 0x10
3633 #define IOERR_NO_RESOURCES 0x11
3634 #define IOERR_RESERVED 0x12
3635 #define IOERR_ILLEGAL_LENGTH 0x13
3636 #define IOERR_UNSUPPORTED_FEATURE 0x14
3637 #define IOERR_ABORT_IN_PROGRESS 0x15
3638 #define IOERR_ABORT_REQUESTED 0x16
3639 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3640 #define IOERR_LOOP_OPEN_FAILURE 0x18
3641 #define IOERR_RING_RESET 0x19
3642 #define IOERR_LINK_DOWN 0x1A
3643 #define IOERR_CORRUPTED_DATA 0x1B
3644 #define IOERR_CORRUPTED_RPI 0x1C
3645 #define IOERR_OUT_OF_ORDER_DATA 0x1D
3646 #define IOERR_OUT_OF_ORDER_ACK 0x1E
3647 #define IOERR_DUP_FRAME 0x1F
3648 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3649 #define IOERR_BAD_HOST_ADDRESS 0x21
3650 #define IOERR_RCV_HDRBUF_WAITING 0x22
3651 #define IOERR_MISSING_HDR_BUFFER 0x23
3652 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3653 #define IOERR_ABORTMULT_REQUESTED 0x25
3654 #define IOERR_BUFFER_SHORTAGE 0x28
3655 #define IOERR_DEFAULT 0x29
3656 #define IOERR_CNT 0x2A
3657 #define IOERR_SLER_FAILURE 0x46
3658 #define IOERR_SLER_CMD_RCV_FAILURE 0x47
3659 #define IOERR_SLER_REC_RJT_ERR 0x48
3660 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3661 #define IOERR_SLER_SRR_RJT_ERR 0x4A
3662 #define IOERR_SLER_RRQ_RJT_ERR 0x4C
3663 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3664 #define IOERR_SLER_ABTS_ERR 0x4E
3665 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3666 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3667 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3668 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
3669 #define IOERR_DRVR_MASK 0x100
3670 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3671 #define IOERR_SLI_BRESET 0x102
3672 #define IOERR_SLI_ABORTED 0x103
3673 #define IOERR_PARAM_MASK 0x1ff
3674 } PARM_ERR;
3675
3676 typedef union {
3677 struct {
3678 #ifdef __BIG_ENDIAN_BITFIELD
3679 uint8_t Rctl; /* R_CTL field */
3680 uint8_t Type; /* TYPE field */
3681 uint8_t Dfctl; /* DF_CTL field */
3682 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3683 #else /* __LITTLE_ENDIAN_BITFIELD */
3684 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3685 uint8_t Dfctl; /* DF_CTL field */
3686 uint8_t Type; /* TYPE field */
3687 uint8_t Rctl; /* R_CTL field */
3688 #endif
3689
3690 #define BC 0x02 /* Broadcast Received - Fctl */
3691 #define SI 0x04 /* Sequence Initiative */
3692 #define LA 0x08 /* Ignore Link Attention state */
3693 #define LS 0x80 /* Last Sequence */
3694 } hcsw;
3695 uint32_t reserved;
3696 } WORD5;
3697
3698 /* IOCB Command template for a generic response */
3699 typedef struct {
3700 uint32_t reserved[4];
3701 PARM_ERR perr;
3702 } GENERIC_RSP;
3703
3704 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3705 typedef struct {
3706 struct ulp_bde xrsqbde[2];
3707 uint32_t xrsqRo; /* Starting Relative Offset */
3708 WORD5 w5; /* Header control/status word */
3709 } XR_SEQ_FIELDS;
3710
3711 /* IOCB Command template for ELS_REQUEST */
3712 typedef struct {
3713 struct ulp_bde elsReq;
3714 struct ulp_bde elsRsp;
3715
3716 #ifdef __BIG_ENDIAN_BITFIELD
3717 uint32_t word4Rsvd:7;
3718 uint32_t fl:1;
3719 uint32_t myID:24;
3720 uint32_t word5Rsvd:8;
3721 uint32_t remoteID:24;
3722 #else /* __LITTLE_ENDIAN_BITFIELD */
3723 uint32_t myID:24;
3724 uint32_t fl:1;
3725 uint32_t word4Rsvd:7;
3726 uint32_t remoteID:24;
3727 uint32_t word5Rsvd:8;
3728 #endif
3729 } ELS_REQUEST;
3730
3731 /* IOCB Command template for RCV_ELS_REQ */
3732 typedef struct {
3733 struct ulp_bde elsReq[2];
3734 uint32_t parmRo;
3735
3736 #ifdef __BIG_ENDIAN_BITFIELD
3737 uint32_t word5Rsvd:8;
3738 uint32_t remoteID:24;
3739 #else /* __LITTLE_ENDIAN_BITFIELD */
3740 uint32_t remoteID:24;
3741 uint32_t word5Rsvd:8;
3742 #endif
3743 } RCV_ELS_REQ;
3744
3745 /* IOCB Command template for ABORT / CLOSE_XRI */
3746 typedef struct {
3747 uint32_t rsvd[3];
3748 uint32_t abortType;
3749 #define ABORT_TYPE_ABTX 0x00000000
3750 #define ABORT_TYPE_ABTS 0x00000001
3751 uint32_t parm;
3752 #ifdef __BIG_ENDIAN_BITFIELD
3753 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3754 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3755 #else /* __LITTLE_ENDIAN_BITFIELD */
3756 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3757 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3758 #endif
3759 } AC_XRI;
3760
3761 /* IOCB Command template for ABORT_MXRI64 */
3762 typedef struct {
3763 uint32_t rsvd[3];
3764 uint32_t abortType;
3765 uint32_t parm;
3766 uint32_t iotag32;
3767 } A_MXRI64;
3768
3769 /* IOCB Command template for GET_RPI */
3770 typedef struct {
3771 uint32_t rsvd[4];
3772 uint32_t parmRo;
3773 #ifdef __BIG_ENDIAN_BITFIELD
3774 uint32_t word5Rsvd:8;
3775 uint32_t remoteID:24;
3776 #else /* __LITTLE_ENDIAN_BITFIELD */
3777 uint32_t remoteID:24;
3778 uint32_t word5Rsvd:8;
3779 #endif
3780 } GET_RPI;
3781
3782 /* IOCB Command template for all FCP Initiator commands */
3783 typedef struct {
3784 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3785 struct ulp_bde fcpi_rsp; /* Rcv buffer */
3786 uint32_t fcpi_parm;
3787 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3788 } FCPI_FIELDS;
3789
3790 /* IOCB Command template for all FCP Target commands */
3791 typedef struct {
3792 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3793 uint32_t fcpt_Offset;
3794 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3795 } FCPT_FIELDS;
3796
3797 /* SLI-2 IOCB structure definitions */
3798
3799 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3800 typedef struct {
3801 ULP_BDL bdl;
3802 uint32_t xrsqRo; /* Starting Relative Offset */
3803 WORD5 w5; /* Header control/status word */
3804 } XMT_SEQ_FIELDS64;
3805
3806 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3807 #define xmit_els_remoteID xrsqRo
3808
3809 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3810 typedef struct {
3811 struct ulp_bde64 rcvBde;
3812 uint32_t rsvd1;
3813 uint32_t xrsqRo; /* Starting Relative Offset */
3814 WORD5 w5; /* Header control/status word */
3815 } RCV_SEQ_FIELDS64;
3816
3817 /* IOCB Command template for ELS_REQUEST64 */
3818 typedef struct {
3819 ULP_BDL bdl;
3820 #ifdef __BIG_ENDIAN_BITFIELD
3821 uint32_t word4Rsvd:7;
3822 uint32_t fl:1;
3823 uint32_t myID:24;
3824 uint32_t word5Rsvd:8;
3825 uint32_t remoteID:24;
3826 #else /* __LITTLE_ENDIAN_BITFIELD */
3827 uint32_t myID:24;
3828 uint32_t fl:1;
3829 uint32_t word4Rsvd:7;
3830 uint32_t remoteID:24;
3831 uint32_t word5Rsvd:8;
3832 #endif
3833 } ELS_REQUEST64;
3834
3835 /* IOCB Command template for GEN_REQUEST64 */
3836 typedef struct {
3837 ULP_BDL bdl;
3838 uint32_t xrsqRo; /* Starting Relative Offset */
3839 WORD5 w5; /* Header control/status word */
3840 } GEN_REQUEST64;
3841
3842 /* IOCB Command template for RCV_ELS_REQ64 */
3843 typedef struct {
3844 struct ulp_bde64 elsReq;
3845 uint32_t rcvd1;
3846 uint32_t parmRo;
3847
3848 #ifdef __BIG_ENDIAN_BITFIELD
3849 uint32_t word5Rsvd:8;
3850 uint32_t remoteID:24;
3851 #else /* __LITTLE_ENDIAN_BITFIELD */
3852 uint32_t remoteID:24;
3853 uint32_t word5Rsvd:8;
3854 #endif
3855 } RCV_ELS_REQ64;
3856
3857 /* IOCB Command template for RCV_SEQ64 */
3858 struct rcv_seq64 {
3859 struct ulp_bde64 elsReq;
3860 uint32_t hbq_1;
3861 uint32_t parmRo;
3862 #ifdef __BIG_ENDIAN_BITFIELD
3863 uint32_t rctl:8;
3864 uint32_t type:8;
3865 uint32_t dfctl:8;
3866 uint32_t ls:1;
3867 uint32_t fs:1;
3868 uint32_t rsvd2:3;
3869 uint32_t si:1;
3870 uint32_t bc:1;
3871 uint32_t rsvd3:1;
3872 #else /* __LITTLE_ENDIAN_BITFIELD */
3873 uint32_t rsvd3:1;
3874 uint32_t bc:1;
3875 uint32_t si:1;
3876 uint32_t rsvd2:3;
3877 uint32_t fs:1;
3878 uint32_t ls:1;
3879 uint32_t dfctl:8;
3880 uint32_t type:8;
3881 uint32_t rctl:8;
3882 #endif
3883 };
3884
3885 /* IOCB Command template for all 64 bit FCP Initiator commands */
3886 typedef struct {
3887 ULP_BDL bdl;
3888 uint32_t fcpi_parm;
3889 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3890 } FCPI_FIELDS64;
3891
3892 /* IOCB Command template for all 64 bit FCP Target commands */
3893 typedef struct {
3894 ULP_BDL bdl;
3895 uint32_t fcpt_Offset;
3896 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3897 } FCPT_FIELDS64;
3898
3899 /* IOCB Command template for Async Status iocb commands */
3900 typedef struct {
3901 uint32_t rsvd[4];
3902 uint32_t param;
3903 #ifdef __BIG_ENDIAN_BITFIELD
3904 uint16_t evt_code; /* High order bits word 5 */
3905 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3906 #else /* __LITTLE_ENDIAN_BITFIELD */
3907 uint16_t sub_ctxt_tag; /* High order bits word 5 */
3908 uint16_t evt_code; /* Low order bits word 5 */
3909 #endif
3910 } ASYNCSTAT_FIELDS;
3911 #define ASYNC_TEMP_WARN 0x100
3912 #define ASYNC_TEMP_SAFE 0x101
3913 #define ASYNC_STATUS_CN 0x102
3914
3915 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3916 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3917
3918 struct rcv_sli3 {
3919 #ifdef __BIG_ENDIAN_BITFIELD
3920 uint16_t ox_id;
3921 uint16_t seq_cnt;
3922
3923 uint16_t vpi;
3924 uint16_t word9Rsvd;
3925 #else /* __LITTLE_ENDIAN */
3926 uint16_t seq_cnt;
3927 uint16_t ox_id;
3928
3929 uint16_t word9Rsvd;
3930 uint16_t vpi;
3931 #endif
3932 uint32_t word10Rsvd;
3933 uint32_t acc_len; /* accumulated length */
3934 struct ulp_bde64 bde2;
3935 };
3936
3937 /* Structure used for a single HBQ entry */
3938 struct lpfc_hbq_entry {
3939 struct ulp_bde64 bde;
3940 uint32_t buffer_tag;
3941 };
3942
3943 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3944 typedef struct {
3945 struct lpfc_hbq_entry buff;
3946 uint32_t rsvd;
3947 uint32_t rsvd1;
3948 } QUE_XRI64_CX_FIELDS;
3949
3950 struct que_xri64cx_ext_fields {
3951 uint32_t iotag64_low;
3952 uint32_t iotag64_high;
3953 uint32_t ebde_count;
3954 uint32_t rsvd;
3955 struct lpfc_hbq_entry buff[5];
3956 };
3957
3958 struct sli3_bg_fields {
3959 uint32_t filler[6]; /* word 8-13 in IOCB */
3960 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
3961 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3962 #define BGS_BIDIR_BG_PROF_MASK 0xff000000
3963 #define BGS_BIDIR_BG_PROF_SHIFT 24
3964 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3965 #define BGS_BIDIR_ERR_COND_SHIFT 16
3966 #define BGS_BG_PROFILE_MASK 0x0000ff00
3967 #define BGS_BG_PROFILE_SHIFT 8
3968 #define BGS_INVALID_PROF_MASK 0x00000020
3969 #define BGS_INVALID_PROF_SHIFT 5
3970 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3971 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4
3972 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
3973 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3974 #define BGS_REFTAG_ERR_MASK 0x00000004
3975 #define BGS_REFTAG_ERR_SHIFT 2
3976 #define BGS_APPTAG_ERR_MASK 0x00000002
3977 #define BGS_APPTAG_ERR_SHIFT 1
3978 #define BGS_GUARD_ERR_MASK 0x00000001
3979 #define BGS_GUARD_ERR_SHIFT 0
3980 uint32_t bgstat; /* word 15 - BlockGuard Status */
3981 };
3982
3983 static inline uint32_t
lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)3984 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3985 {
3986 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
3987 BGS_BIDIR_BG_PROF_SHIFT;
3988 }
3989
3990 static inline uint32_t
lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)3991 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3992 {
3993 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
3994 BGS_BIDIR_ERR_COND_SHIFT;
3995 }
3996
3997 static inline uint32_t
lpfc_bgs_get_bg_prof(uint32_t bgstat)3998 lpfc_bgs_get_bg_prof(uint32_t bgstat)
3999 {
4000 return (bgstat & BGS_BG_PROFILE_MASK) >>
4001 BGS_BG_PROFILE_SHIFT;
4002 }
4003
4004 static inline uint32_t
lpfc_bgs_get_invalid_prof(uint32_t bgstat)4005 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
4006 {
4007 return (bgstat & BGS_INVALID_PROF_MASK) >>
4008 BGS_INVALID_PROF_SHIFT;
4009 }
4010
4011 static inline uint32_t
lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)4012 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
4013 {
4014 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
4015 BGS_UNINIT_DIF_BLOCK_SHIFT;
4016 }
4017
4018 static inline uint32_t
lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)4019 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
4020 {
4021 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
4022 BGS_HI_WATER_MARK_PRESENT_SHIFT;
4023 }
4024
4025 static inline uint32_t
lpfc_bgs_get_reftag_err(uint32_t bgstat)4026 lpfc_bgs_get_reftag_err(uint32_t bgstat)
4027 {
4028 return (bgstat & BGS_REFTAG_ERR_MASK) >>
4029 BGS_REFTAG_ERR_SHIFT;
4030 }
4031
4032 static inline uint32_t
lpfc_bgs_get_apptag_err(uint32_t bgstat)4033 lpfc_bgs_get_apptag_err(uint32_t bgstat)
4034 {
4035 return (bgstat & BGS_APPTAG_ERR_MASK) >>
4036 BGS_APPTAG_ERR_SHIFT;
4037 }
4038
4039 static inline uint32_t
lpfc_bgs_get_guard_err(uint32_t bgstat)4040 lpfc_bgs_get_guard_err(uint32_t bgstat)
4041 {
4042 return (bgstat & BGS_GUARD_ERR_MASK) >>
4043 BGS_GUARD_ERR_SHIFT;
4044 }
4045
4046 #define LPFC_EXT_DATA_BDE_COUNT 3
4047 struct fcp_irw_ext {
4048 uint32_t io_tag64_low;
4049 uint32_t io_tag64_high;
4050 #ifdef __BIG_ENDIAN_BITFIELD
4051 uint8_t reserved1;
4052 uint8_t reserved2;
4053 uint8_t reserved3;
4054 uint8_t ebde_count;
4055 #else /* __LITTLE_ENDIAN */
4056 uint8_t ebde_count;
4057 uint8_t reserved3;
4058 uint8_t reserved2;
4059 uint8_t reserved1;
4060 #endif
4061 uint32_t reserved4;
4062 struct ulp_bde64 rbde; /* response bde */
4063 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
4064 uint8_t icd[32]; /* immediate command data (32 bytes) */
4065 };
4066
4067 typedef struct _IOCB { /* IOCB structure */
4068 union {
4069 GENERIC_RSP grsp; /* Generic response */
4070 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
4071 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
4072 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
4073 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
4074 A_MXRI64 amxri; /* abort multiple xri command overlay */
4075 GET_RPI getrpi; /* GET_RPI template */
4076 FCPI_FIELDS fcpi; /* FCP Initiator template */
4077 FCPT_FIELDS fcpt; /* FCP target template */
4078
4079 /* SLI-2 structures */
4080
4081 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
4082 * bde_64s */
4083 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
4084 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
4085 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
4086 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
4087 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
4088 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
4089 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
4090 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
4091 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
4092 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
4093 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
4094 } un;
4095 union {
4096 struct {
4097 #ifdef __BIG_ENDIAN_BITFIELD
4098 uint16_t ulpContext; /* High order bits word 6 */
4099 uint16_t ulpIoTag; /* Low order bits word 6 */
4100 #else /* __LITTLE_ENDIAN_BITFIELD */
4101 uint16_t ulpIoTag; /* Low order bits word 6 */
4102 uint16_t ulpContext; /* High order bits word 6 */
4103 #endif
4104 } t1;
4105 struct {
4106 #ifdef __BIG_ENDIAN_BITFIELD
4107 uint16_t ulpContext; /* High order bits word 6 */
4108 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4109 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4110 #else /* __LITTLE_ENDIAN_BITFIELD */
4111 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4112 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4113 uint16_t ulpContext; /* High order bits word 6 */
4114 #endif
4115 } t2;
4116 } un1;
4117 #define ulpContext un1.t1.ulpContext
4118 #define ulpIoTag un1.t1.ulpIoTag
4119 #define ulpIoTag0 un1.t2.ulpIoTag0
4120
4121 #ifdef __BIG_ENDIAN_BITFIELD
4122 uint32_t ulpTimeout:8;
4123 uint32_t ulpXS:1;
4124 uint32_t ulpFCP2Rcvy:1;
4125 uint32_t ulpPU:2;
4126 uint32_t ulpIr:1;
4127 uint32_t ulpClass:3;
4128 uint32_t ulpCommand:8;
4129 uint32_t ulpStatus:4;
4130 uint32_t ulpBdeCount:2;
4131 uint32_t ulpLe:1;
4132 uint32_t ulpOwner:1; /* Low order bit word 7 */
4133 #else /* __LITTLE_ENDIAN_BITFIELD */
4134 uint32_t ulpOwner:1; /* Low order bit word 7 */
4135 uint32_t ulpLe:1;
4136 uint32_t ulpBdeCount:2;
4137 uint32_t ulpStatus:4;
4138 uint32_t ulpCommand:8;
4139 uint32_t ulpClass:3;
4140 uint32_t ulpIr:1;
4141 uint32_t ulpPU:2;
4142 uint32_t ulpFCP2Rcvy:1;
4143 uint32_t ulpXS:1;
4144 uint32_t ulpTimeout:8;
4145 #endif
4146
4147 union {
4148 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
4149
4150 /* words 8-31 used for que_xri_cx iocb */
4151 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
4152 struct fcp_irw_ext fcp_ext;
4153 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
4154
4155 /* words 8-15 for BlockGuard */
4156 struct sli3_bg_fields sli3_bg;
4157 } unsli3;
4158
4159 #define ulpCt_h ulpXS
4160 #define ulpCt_l ulpFCP2Rcvy
4161
4162 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
4163 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
4164 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
4165 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
4166 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
4167 #define PARM_NPIV_DID 3
4168 #define CLASS1 0 /* Class 1 */
4169 #define CLASS2 1 /* Class 2 */
4170 #define CLASS3 2 /* Class 3 */
4171 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
4172
4173 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
4174 #define IOSTAT_FCP_RSP_ERROR 0x1
4175 #define IOSTAT_REMOTE_STOP 0x2
4176 #define IOSTAT_LOCAL_REJECT 0x3
4177 #define IOSTAT_NPORT_RJT 0x4
4178 #define IOSTAT_FABRIC_RJT 0x5
4179 #define IOSTAT_NPORT_BSY 0x6
4180 #define IOSTAT_FABRIC_BSY 0x7
4181 #define IOSTAT_INTERMED_RSP 0x8
4182 #define IOSTAT_LS_RJT 0x9
4183 #define IOSTAT_BA_RJT 0xA
4184 #define IOSTAT_RSVD1 0xB
4185 #define IOSTAT_RSVD2 0xC
4186 #define IOSTAT_RSVD3 0xD
4187 #define IOSTAT_RSVD4 0xE
4188 #define IOSTAT_NEED_BUFFER 0xF
4189 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
4190 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
4191 #define IOSTAT_CNT 0x11
4192
4193 } IOCB_t;
4194
4195
4196 #define SLI1_SLIM_SIZE (4 * 1024)
4197
4198 /* Up to 498 IOCBs will fit into 16k
4199 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
4200 */
4201 #define SLI2_SLIM_SIZE (64 * 1024)
4202
4203 /* Maximum IOCBs that will fit in SLI2 slim */
4204 #define MAX_SLI2_IOCB 498
4205 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
4206 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
4207 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
4208
4209 /* HBQ entries are 4 words each = 4k */
4210 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
4211 lpfc_sli_hbq_count())
4212
4213 struct lpfc_sli2_slim {
4214 MAILBOX_t mbx;
4215 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
4216 PCB_t pcb;
4217 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
4218 };
4219
4220 /*
4221 * This function checks PCI device to allow special handling for LC HBAs.
4222 *
4223 * Parameters:
4224 * device : struct pci_dev 's device field
4225 *
4226 * return 1 => TRUE
4227 * 0 => FALSE
4228 */
4229 static inline int
lpfc_is_LC_HBA(unsigned short device)4230 lpfc_is_LC_HBA(unsigned short device)
4231 {
4232 if ((device == PCI_DEVICE_ID_TFLY) ||
4233 (device == PCI_DEVICE_ID_PFLY) ||
4234 (device == PCI_DEVICE_ID_LP101) ||
4235 (device == PCI_DEVICE_ID_BMID) ||
4236 (device == PCI_DEVICE_ID_BSMB) ||
4237 (device == PCI_DEVICE_ID_ZMID) ||
4238 (device == PCI_DEVICE_ID_ZSMB) ||
4239 (device == PCI_DEVICE_ID_SAT_MID) ||
4240 (device == PCI_DEVICE_ID_SAT_SMB) ||
4241 (device == PCI_DEVICE_ID_RFLY))
4242 return 1;
4243 else
4244 return 0;
4245 }
4246
4247 /*
4248 * Determine if an IOCB failed because of a link event or firmware reset.
4249 */
4250
4251 static inline int
lpfc_error_lost_link(IOCB_t * iocbp)4252 lpfc_error_lost_link(IOCB_t *iocbp)
4253 {
4254 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
4255 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
4256 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
4257 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
4258 }
4259
4260 #define MENLO_TRANSPORT_TYPE 0xfe
4261 #define MENLO_CONTEXT 0
4262 #define MENLO_PU 3
4263 #define MENLO_TIMEOUT 30
4264 #define SETVAR_MLOMNT 0x103107
4265 #define SETVAR_MLORST 0x103007
4266
4267 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
4268