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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2012 ARM Ltd.
4  */
5 #ifndef __ASM_PGTABLE_HWDEF_H
6 #define __ASM_PGTABLE_HWDEF_H
7 
8 #include <asm/memory.h>
9 
10 /*
11  * Number of page-table levels required to address 'va_bits' wide
12  * address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT)
13  * bits with (PAGE_SHIFT - 3) bits at each page table level. Hence:
14  *
15  *  levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3))
16  *
17  * where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d))
18  *
19  * We cannot include linux/kernel.h which defines DIV_ROUND_UP here
20  * due to build issues. So we open code DIV_ROUND_UP here:
21  *
22  *	((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3))
23  *
24  * which gets simplified as :
25  */
26 #define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3))
27 
28 /*
29  * Size mapped by an entry at level n ( 0 <= n <= 3)
30  * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits
31  * in the final page. The maximum number of translation levels supported by
32  * the architecture is 4. Hence, starting at level n, we have further
33  * ((4 - n) - 1) levels of translation excluding the offset within the page.
34  * So, the total number of bits mapped by an entry at level n is :
35  *
36  *  ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT
37  *
38  * Rearranging it a bit we get :
39  *   (4 - n) * (PAGE_SHIFT - 3) + 3
40  */
41 #define ARM64_HW_PGTABLE_LEVEL_SHIFT(n)	((PAGE_SHIFT - 3) * (4 - (n)) + 3)
42 
43 #define PTRS_PER_PTE		(1 << (PAGE_SHIFT - 3))
44 
45 /*
46  * PMD_SHIFT determines the size a level 2 page table entry can map.
47  */
48 #if CONFIG_PGTABLE_LEVELS > 2
49 #define PMD_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(2)
50 #define PMD_SIZE		(_AC(1, UL) << PMD_SHIFT)
51 #define PMD_MASK		(~(PMD_SIZE-1))
52 #define PTRS_PER_PMD		PTRS_PER_PTE
53 #endif
54 
55 /*
56  * PUD_SHIFT determines the size a level 1 page table entry can map.
57  */
58 #if CONFIG_PGTABLE_LEVELS > 3
59 #define PUD_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(1)
60 #define PUD_SIZE		(_AC(1, UL) << PUD_SHIFT)
61 #define PUD_MASK		(~(PUD_SIZE-1))
62 #define PTRS_PER_PUD		PTRS_PER_PTE
63 #endif
64 
65 /*
66  * PGDIR_SHIFT determines the size a top-level page table entry can map
67  * (depending on the configuration, this level can be 0, 1 or 2).
68  */
69 #define PGDIR_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS)
70 #define PGDIR_SIZE		(_AC(1, UL) << PGDIR_SHIFT)
71 #define PGDIR_MASK		(~(PGDIR_SIZE-1))
72 #define PTRS_PER_PGD		(1 << (VA_BITS - PGDIR_SHIFT))
73 
74 /*
75  * Section address mask and size definitions.
76  */
77 #define SECTION_SHIFT		PMD_SHIFT
78 #define SECTION_SIZE		(_AC(1, UL) << SECTION_SHIFT)
79 #define SECTION_MASK		(~(SECTION_SIZE-1))
80 
81 /*
82  * Contiguous page definitions.
83  */
84 #define CONT_PTE_SHIFT		(CONFIG_ARM64_CONT_PTE_SHIFT + PAGE_SHIFT)
85 #define CONT_PTES		(1 << (CONT_PTE_SHIFT - PAGE_SHIFT))
86 #define CONT_PTE_SIZE		(CONT_PTES * PAGE_SIZE)
87 #define CONT_PTE_MASK		(~(CONT_PTE_SIZE - 1))
88 
89 #define CONT_PMD_SHIFT		(CONFIG_ARM64_CONT_PMD_SHIFT + PMD_SHIFT)
90 #define CONT_PMDS		(1 << (CONT_PMD_SHIFT - PMD_SHIFT))
91 #define CONT_PMD_SIZE		(CONT_PMDS * PMD_SIZE)
92 #define CONT_PMD_MASK		(~(CONT_PMD_SIZE - 1))
93 
94 /*
95  * Hardware page table definitions.
96  *
97  * Level 1 descriptor (PUD).
98  */
99 #define PUD_TYPE_TABLE		(_AT(pudval_t, 3) << 0)
100 #define PUD_TABLE_BIT		(_AT(pudval_t, 1) << 1)
101 #define PUD_TYPE_MASK		(_AT(pudval_t, 3) << 0)
102 #define PUD_TYPE_SECT		(_AT(pudval_t, 1) << 0)
103 #define PUD_SECT_RDONLY		(_AT(pudval_t, 1) << 7)		/* AP[2] */
104 
105 /*
106  * Level 2 descriptor (PMD).
107  */
108 #define PMD_TYPE_MASK		(_AT(pmdval_t, 3) << 0)
109 #define PMD_TYPE_TABLE		(_AT(pmdval_t, 3) << 0)
110 #define PMD_TYPE_SECT		(_AT(pmdval_t, 1) << 0)
111 #define PMD_TABLE_BIT		(_AT(pmdval_t, 1) << 1)
112 
113 /*
114  * Section
115  */
116 #define PMD_SECT_VALID		(_AT(pmdval_t, 1) << 0)
117 #define PMD_SECT_USER		(_AT(pmdval_t, 1) << 6)		/* AP[1] */
118 #define PMD_SECT_RDONLY		(_AT(pmdval_t, 1) << 7)		/* AP[2] */
119 #define PMD_SECT_S		(_AT(pmdval_t, 3) << 8)
120 #define PMD_SECT_AF		(_AT(pmdval_t, 1) << 10)
121 #define PMD_SECT_NG		(_AT(pmdval_t, 1) << 11)
122 #define PMD_SECT_CONT		(_AT(pmdval_t, 1) << 52)
123 #define PMD_SECT_PXN		(_AT(pmdval_t, 1) << 53)
124 #define PMD_SECT_UXN		(_AT(pmdval_t, 1) << 54)
125 
126 /*
127  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
128  */
129 #define PMD_ATTRINDX(t)		(_AT(pmdval_t, (t)) << 2)
130 #define PMD_ATTRINDX_MASK	(_AT(pmdval_t, 7) << 2)
131 
132 /*
133  * Level 3 descriptor (PTE).
134  */
135 #define PTE_VALID		(_AT(pteval_t, 1) << 0)
136 #define PTE_TYPE_MASK		(_AT(pteval_t, 3) << 0)
137 #define PTE_TYPE_PAGE		(_AT(pteval_t, 3) << 0)
138 #define PTE_TABLE_BIT		(_AT(pteval_t, 1) << 1)
139 #define PTE_USER		(_AT(pteval_t, 1) << 6)		/* AP[1] */
140 #define PTE_RDONLY		(_AT(pteval_t, 1) << 7)		/* AP[2] */
141 #define PTE_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
142 #define PTE_AF			(_AT(pteval_t, 1) << 10)	/* Access Flag */
143 #define PTE_NG			(_AT(pteval_t, 1) << 11)	/* nG */
144 #define PTE_GP			(_AT(pteval_t, 1) << 50)	/* BTI guarded */
145 #define PTE_DBM			(_AT(pteval_t, 1) << 51)	/* Dirty Bit Management */
146 #define PTE_CONT		(_AT(pteval_t, 1) << 52)	/* Contiguous range */
147 #define PTE_PXN			(_AT(pteval_t, 1) << 53)	/* Privileged XN */
148 #define PTE_UXN			(_AT(pteval_t, 1) << 54)	/* User XN */
149 
150 #define PTE_ADDR_LOW		(((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
151 #ifdef CONFIG_ARM64_PA_BITS_52
152 #define PTE_ADDR_HIGH		(_AT(pteval_t, 0xf) << 12)
153 #define PTE_ADDR_MASK		(PTE_ADDR_LOW | PTE_ADDR_HIGH)
154 #else
155 #define PTE_ADDR_MASK		PTE_ADDR_LOW
156 #endif
157 
158 /*
159  * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
160  */
161 #define PTE_ATTRINDX(t)		(_AT(pteval_t, (t)) << 2)
162 #define PTE_ATTRINDX_MASK	(_AT(pteval_t, 7) << 2)
163 
164 /*
165  * Memory Attribute override for Stage-2 (MemAttr[3:0])
166  */
167 #define PTE_S2_MEMATTR(t)	(_AT(pteval_t, (t)) << 2)
168 
169 /*
170  * Highest possible physical address supported.
171  */
172 #define PHYS_MASK_SHIFT		(CONFIG_ARM64_PA_BITS)
173 #define PHYS_MASK		((UL(1) << PHYS_MASK_SHIFT) - 1)
174 
175 #define TTBR_CNP_BIT		(UL(1) << 0)
176 
177 /*
178  * TCR flags.
179  */
180 #define TCR_T0SZ_OFFSET		0
181 #define TCR_T1SZ_OFFSET		16
182 #define TCR_T0SZ(x)		((UL(64) - (x)) << TCR_T0SZ_OFFSET)
183 #define TCR_T1SZ(x)		((UL(64) - (x)) << TCR_T1SZ_OFFSET)
184 #define TCR_TxSZ(x)		(TCR_T0SZ(x) | TCR_T1SZ(x))
185 #define TCR_TxSZ_WIDTH		6
186 #define TCR_T0SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
187 #define TCR_T1SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
188 
189 #define TCR_EPD0_SHIFT		7
190 #define TCR_EPD0_MASK		(UL(1) << TCR_EPD0_SHIFT)
191 #define TCR_IRGN0_SHIFT		8
192 #define TCR_IRGN0_MASK		(UL(3) << TCR_IRGN0_SHIFT)
193 #define TCR_IRGN0_NC		(UL(0) << TCR_IRGN0_SHIFT)
194 #define TCR_IRGN0_WBWA		(UL(1) << TCR_IRGN0_SHIFT)
195 #define TCR_IRGN0_WT		(UL(2) << TCR_IRGN0_SHIFT)
196 #define TCR_IRGN0_WBnWA		(UL(3) << TCR_IRGN0_SHIFT)
197 
198 #define TCR_EPD1_SHIFT		23
199 #define TCR_EPD1_MASK		(UL(1) << TCR_EPD1_SHIFT)
200 #define TCR_IRGN1_SHIFT		24
201 #define TCR_IRGN1_MASK		(UL(3) << TCR_IRGN1_SHIFT)
202 #define TCR_IRGN1_NC		(UL(0) << TCR_IRGN1_SHIFT)
203 #define TCR_IRGN1_WBWA		(UL(1) << TCR_IRGN1_SHIFT)
204 #define TCR_IRGN1_WT		(UL(2) << TCR_IRGN1_SHIFT)
205 #define TCR_IRGN1_WBnWA		(UL(3) << TCR_IRGN1_SHIFT)
206 
207 #define TCR_IRGN_NC		(TCR_IRGN0_NC | TCR_IRGN1_NC)
208 #define TCR_IRGN_WBWA		(TCR_IRGN0_WBWA | TCR_IRGN1_WBWA)
209 #define TCR_IRGN_WT		(TCR_IRGN0_WT | TCR_IRGN1_WT)
210 #define TCR_IRGN_WBnWA		(TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA)
211 #define TCR_IRGN_MASK		(TCR_IRGN0_MASK | TCR_IRGN1_MASK)
212 
213 
214 #define TCR_ORGN0_SHIFT		10
215 #define TCR_ORGN0_MASK		(UL(3) << TCR_ORGN0_SHIFT)
216 #define TCR_ORGN0_NC		(UL(0) << TCR_ORGN0_SHIFT)
217 #define TCR_ORGN0_WBWA		(UL(1) << TCR_ORGN0_SHIFT)
218 #define TCR_ORGN0_WT		(UL(2) << TCR_ORGN0_SHIFT)
219 #define TCR_ORGN0_WBnWA		(UL(3) << TCR_ORGN0_SHIFT)
220 
221 #define TCR_ORGN1_SHIFT		26
222 #define TCR_ORGN1_MASK		(UL(3) << TCR_ORGN1_SHIFT)
223 #define TCR_ORGN1_NC		(UL(0) << TCR_ORGN1_SHIFT)
224 #define TCR_ORGN1_WBWA		(UL(1) << TCR_ORGN1_SHIFT)
225 #define TCR_ORGN1_WT		(UL(2) << TCR_ORGN1_SHIFT)
226 #define TCR_ORGN1_WBnWA		(UL(3) << TCR_ORGN1_SHIFT)
227 
228 #define TCR_ORGN_NC		(TCR_ORGN0_NC | TCR_ORGN1_NC)
229 #define TCR_ORGN_WBWA		(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)
230 #define TCR_ORGN_WT		(TCR_ORGN0_WT | TCR_ORGN1_WT)
231 #define TCR_ORGN_WBnWA		(TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA)
232 #define TCR_ORGN_MASK		(TCR_ORGN0_MASK | TCR_ORGN1_MASK)
233 
234 #define TCR_SH0_SHIFT		12
235 #define TCR_SH0_MASK		(UL(3) << TCR_SH0_SHIFT)
236 #define TCR_SH0_INNER		(UL(3) << TCR_SH0_SHIFT)
237 
238 #define TCR_SH1_SHIFT		28
239 #define TCR_SH1_MASK		(UL(3) << TCR_SH1_SHIFT)
240 #define TCR_SH1_INNER		(UL(3) << TCR_SH1_SHIFT)
241 #define TCR_SHARED		(TCR_SH0_INNER | TCR_SH1_INNER)
242 
243 #define TCR_TG0_SHIFT		14
244 #define TCR_TG0_MASK		(UL(3) << TCR_TG0_SHIFT)
245 #define TCR_TG0_4K		(UL(0) << TCR_TG0_SHIFT)
246 #define TCR_TG0_64K		(UL(1) << TCR_TG0_SHIFT)
247 #define TCR_TG0_16K		(UL(2) << TCR_TG0_SHIFT)
248 
249 #define TCR_TG1_SHIFT		30
250 #define TCR_TG1_MASK		(UL(3) << TCR_TG1_SHIFT)
251 #define TCR_TG1_16K		(UL(1) << TCR_TG1_SHIFT)
252 #define TCR_TG1_4K		(UL(2) << TCR_TG1_SHIFT)
253 #define TCR_TG1_64K		(UL(3) << TCR_TG1_SHIFT)
254 
255 #define TCR_IPS_SHIFT		32
256 #define TCR_IPS_MASK		(UL(7) << TCR_IPS_SHIFT)
257 #define TCR_A1			(UL(1) << 22)
258 #define TCR_ASID16		(UL(1) << 36)
259 #define TCR_TBI0		(UL(1) << 37)
260 #define TCR_TBI1		(UL(1) << 38)
261 #define TCR_HA			(UL(1) << 39)
262 #define TCR_HD			(UL(1) << 40)
263 #define TCR_TBID1		(UL(1) << 52)
264 #define TCR_NFD0		(UL(1) << 53)
265 #define TCR_NFD1		(UL(1) << 54)
266 #define TCR_E0PD0		(UL(1) << 55)
267 #define TCR_E0PD1		(UL(1) << 56)
268 
269 /*
270  * TTBR.
271  */
272 #ifdef CONFIG_ARM64_PA_BITS_52
273 /*
274  * This should be GENMASK_ULL(47, 2).
275  * TTBR_ELx[1] is RES0 in this configuration.
276  */
277 #define TTBR_BADDR_MASK_52	(((UL(1) << 46) - 1) << 2)
278 #endif
279 
280 #ifdef CONFIG_ARM64_VA_BITS_52
281 /* Must be at least 64-byte aligned to prevent corruption of the TTBR */
282 #define TTBR1_BADDR_4852_OFFSET	(((UL(1) << (52 - PGDIR_SHIFT)) - \
283 				 (UL(1) << (48 - PGDIR_SHIFT))) * 8)
284 #endif
285 
286 #endif
287