1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 #ifndef _IXGBE_H_
5 #define _IXGBE_H_
6
7 #include <linux/bitops.h>
8 #include <linux/types.h>
9 #include <linux/pci.h>
10 #include <linux/netdevice.h>
11 #include <linux/cpumask.h>
12 #include <linux/aer.h>
13 #include <linux/if_vlan.h>
14 #include <linux/jiffies.h>
15 #include <linux/phy.h>
16
17 #include <linux/timecounter.h>
18 #include <linux/net_tstamp.h>
19 #include <linux/ptp_clock_kernel.h>
20
21 #include "ixgbe_type.h"
22 #include "ixgbe_common.h"
23 #include "ixgbe_dcb.h"
24 #if IS_ENABLED(CONFIG_FCOE)
25 #define IXGBE_FCOE
26 #include "ixgbe_fcoe.h"
27 #endif /* IS_ENABLED(CONFIG_FCOE) */
28 #ifdef CONFIG_IXGBE_DCA
29 #include <linux/dca.h>
30 #endif
31 #include "ixgbe_ipsec.h"
32
33 #include <net/xdp.h>
34
35 /* common prefix used by pr_<> macros */
36 #undef pr_fmt
37 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
38
39 /* TX/RX descriptor defines */
40 #define IXGBE_DEFAULT_TXD 512
41 #define IXGBE_DEFAULT_TX_WORK 256
42 #define IXGBE_MAX_TXD 4096
43 #define IXGBE_MIN_TXD 64
44
45 #if (PAGE_SIZE < 8192)
46 #define IXGBE_DEFAULT_RXD 512
47 #else
48 #define IXGBE_DEFAULT_RXD 128
49 #endif
50 #define IXGBE_MAX_RXD 4096
51 #define IXGBE_MIN_RXD 64
52
53 /* flow control */
54 #define IXGBE_MIN_FCRTL 0x40
55 #define IXGBE_MAX_FCRTL 0x7FF80
56 #define IXGBE_MIN_FCRTH 0x600
57 #define IXGBE_MAX_FCRTH 0x7FFF0
58 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
59 #define IXGBE_MIN_FCPAUSE 0
60 #define IXGBE_MAX_FCPAUSE 0xFFFF
61
62 /* Supported Rx Buffer Sizes */
63 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */
64 #define IXGBE_RXBUFFER_1536 1536
65 #define IXGBE_RXBUFFER_2K 2048
66 #define IXGBE_RXBUFFER_3K 3072
67 #define IXGBE_RXBUFFER_4K 4096
68 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
69
70 #define IXGBE_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
71
72 /* Attempt to maximize the headroom available for incoming frames. We
73 * use a 2K buffer for receives and need 1536/1534 to store the data for
74 * the frame. This leaves us with 512 bytes of room. From that we need
75 * to deduct the space needed for the shared info and the padding needed
76 * to IP align the frame.
77 *
78 * Note: For cache line sizes 256 or larger this value is going to end
79 * up negative. In these cases we should fall back to the 3K
80 * buffers.
81 */
82 #if (PAGE_SIZE < 8192)
83 #define IXGBE_MAX_2K_FRAME_BUILD_SKB (IXGBE_RXBUFFER_1536 - NET_IP_ALIGN)
84 #define IXGBE_2K_TOO_SMALL_WITH_PADDING \
85 ((NET_SKB_PAD + IXGBE_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K))
86
ixgbe_compute_pad(int rx_buf_len)87 static inline int ixgbe_compute_pad(int rx_buf_len)
88 {
89 int page_size, pad_size;
90
91 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
92 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len;
93
94 return pad_size;
95 }
96
ixgbe_skb_pad(void)97 static inline int ixgbe_skb_pad(void)
98 {
99 int rx_buf_len;
100
101 /* If a 2K buffer cannot handle a standard Ethernet frame then
102 * optimize padding for a 3K buffer instead of a 1.5K buffer.
103 *
104 * For a 3K buffer we need to add enough padding to allow for
105 * tailroom due to NET_IP_ALIGN possibly shifting us out of
106 * cache-line alignment.
107 */
108 if (IXGBE_2K_TOO_SMALL_WITH_PADDING)
109 rx_buf_len = IXGBE_RXBUFFER_3K + SKB_DATA_ALIGN(NET_IP_ALIGN);
110 else
111 rx_buf_len = IXGBE_RXBUFFER_1536;
112
113 /* if needed make room for NET_IP_ALIGN */
114 rx_buf_len -= NET_IP_ALIGN;
115
116 return ixgbe_compute_pad(rx_buf_len);
117 }
118
119 #define IXGBE_SKB_PAD ixgbe_skb_pad()
120 #else
121 #define IXGBE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
122 #endif
123
124 /*
125 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
126 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more,
127 * this adds up to 448 bytes of extra data.
128 *
129 * Since netdev_alloc_skb now allocates a page fragment we can use a value
130 * of 256 and the resultant skb will have a truesize of 960 or less.
131 */
132 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
133
134 /* How many Rx Buffers do we bundle into one write to the hardware ? */
135 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
136
137 #define IXGBE_RX_DMA_ATTR \
138 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
139
140 enum ixgbe_tx_flags {
141 /* cmd_type flags */
142 IXGBE_TX_FLAGS_HW_VLAN = 0x01,
143 IXGBE_TX_FLAGS_TSO = 0x02,
144 IXGBE_TX_FLAGS_TSTAMP = 0x04,
145
146 /* olinfo flags */
147 IXGBE_TX_FLAGS_CC = 0x08,
148 IXGBE_TX_FLAGS_IPV4 = 0x10,
149 IXGBE_TX_FLAGS_CSUM = 0x20,
150 IXGBE_TX_FLAGS_IPSEC = 0x40,
151
152 /* software defined flags */
153 IXGBE_TX_FLAGS_SW_VLAN = 0x80,
154 IXGBE_TX_FLAGS_FCOE = 0x100,
155 };
156
157 /* VLAN info */
158 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
159 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
160 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
161 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
162
163 #define IXGBE_MAX_VF_MC_ENTRIES 30
164 #define IXGBE_MAX_VF_FUNCTIONS 64
165 #define IXGBE_MAX_VFTA_ENTRIES 128
166 #define MAX_EMULATION_MAC_ADDRS 16
167 #define IXGBE_MAX_PF_MACVLANS 15
168 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
169 #define IXGBE_82599_VF_DEVICE_ID 0x10ED
170 #define IXGBE_X540_VF_DEVICE_ID 0x1515
171
172 struct vf_data_storage {
173 struct pci_dev *vfdev;
174 unsigned char vf_mac_addresses[ETH_ALEN];
175 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
176 u16 num_vf_mc_hashes;
177 bool clear_to_send;
178 bool pf_set_mac;
179 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
180 u16 pf_qos;
181 u16 tx_rate;
182 u8 spoofchk_enabled;
183 bool rss_query_enabled;
184 u8 trusted;
185 int xcast_mode;
186 unsigned int vf_api;
187 };
188
189 enum ixgbevf_xcast_modes {
190 IXGBEVF_XCAST_MODE_NONE = 0,
191 IXGBEVF_XCAST_MODE_MULTI,
192 IXGBEVF_XCAST_MODE_ALLMULTI,
193 IXGBEVF_XCAST_MODE_PROMISC,
194 };
195
196 struct vf_macvlans {
197 struct list_head l;
198 int vf;
199 bool free;
200 bool is_macvlan;
201 u8 vf_macvlan[ETH_ALEN];
202 };
203
204 #define IXGBE_MAX_TXD_PWR 14
205 #define IXGBE_MAX_DATA_PER_TXD (1u << IXGBE_MAX_TXD_PWR)
206
207 /* Tx Descriptors needed, worst case */
208 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
209 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
210
211 /* wrapper around a pointer to a socket buffer,
212 * so a DMA handle can be stored along with the buffer */
213 struct ixgbe_tx_buffer {
214 union ixgbe_adv_tx_desc *next_to_watch;
215 unsigned long time_stamp;
216 union {
217 struct sk_buff *skb;
218 struct xdp_frame *xdpf;
219 };
220 unsigned int bytecount;
221 unsigned short gso_segs;
222 __be16 protocol;
223 DEFINE_DMA_UNMAP_ADDR(dma);
224 DEFINE_DMA_UNMAP_LEN(len);
225 u32 tx_flags;
226 };
227
228 struct ixgbe_rx_buffer {
229 union {
230 struct {
231 struct sk_buff *skb;
232 dma_addr_t dma;
233 struct page *page;
234 __u32 page_offset;
235 __u16 pagecnt_bias;
236 };
237 struct {
238 bool discard;
239 struct xdp_buff *xdp;
240 };
241 };
242 };
243
244 struct ixgbe_queue_stats {
245 u64 packets;
246 u64 bytes;
247 };
248
249 struct ixgbe_tx_queue_stats {
250 u64 restart_queue;
251 u64 tx_busy;
252 u64 tx_done_old;
253 };
254
255 struct ixgbe_rx_queue_stats {
256 u64 rsc_count;
257 u64 rsc_flush;
258 u64 non_eop_descs;
259 u64 alloc_rx_page;
260 u64 alloc_rx_page_failed;
261 u64 alloc_rx_buff_failed;
262 u64 csum_err;
263 };
264
265 #define IXGBE_TS_HDR_LEN 8
266
267 enum ixgbe_ring_state_t {
268 __IXGBE_RX_3K_BUFFER,
269 __IXGBE_RX_BUILD_SKB_ENABLED,
270 __IXGBE_RX_RSC_ENABLED,
271 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
272 __IXGBE_RX_FCOE,
273 __IXGBE_TX_FDIR_INIT_DONE,
274 __IXGBE_TX_XPS_INIT_DONE,
275 __IXGBE_TX_DETECT_HANG,
276 __IXGBE_HANG_CHECK_ARMED,
277 __IXGBE_TX_XDP_RING,
278 __IXGBE_TX_DISABLED,
279 };
280
281 #define ring_uses_build_skb(ring) \
282 test_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &(ring)->state)
283
284 struct ixgbe_fwd_adapter {
285 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
286 struct net_device *netdev;
287 unsigned int tx_base_queue;
288 unsigned int rx_base_queue;
289 int pool;
290 };
291
292 #define check_for_tx_hang(ring) \
293 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
294 #define set_check_for_tx_hang(ring) \
295 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
296 #define clear_check_for_tx_hang(ring) \
297 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
298 #define ring_is_rsc_enabled(ring) \
299 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
300 #define set_ring_rsc_enabled(ring) \
301 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
302 #define clear_ring_rsc_enabled(ring) \
303 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
304 #define ring_is_xdp(ring) \
305 test_bit(__IXGBE_TX_XDP_RING, &(ring)->state)
306 #define set_ring_xdp(ring) \
307 set_bit(__IXGBE_TX_XDP_RING, &(ring)->state)
308 #define clear_ring_xdp(ring) \
309 clear_bit(__IXGBE_TX_XDP_RING, &(ring)->state)
310 struct ixgbe_ring {
311 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
312 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
313 struct net_device *netdev; /* netdev ring belongs to */
314 struct bpf_prog *xdp_prog;
315 struct device *dev; /* device for DMA mapping */
316 void *desc; /* descriptor ring memory */
317 union {
318 struct ixgbe_tx_buffer *tx_buffer_info;
319 struct ixgbe_rx_buffer *rx_buffer_info;
320 };
321 unsigned long state;
322 u8 __iomem *tail;
323 dma_addr_t dma; /* phys. address of descriptor ring */
324 unsigned int size; /* length in bytes */
325
326 u16 count; /* amount of descriptors */
327
328 u8 queue_index; /* needed for multiqueue queue management */
329 u8 reg_idx; /* holds the special value that gets
330 * the hardware register offset
331 * associated with this ring, which is
332 * different for DCB and RSS modes
333 */
334 u16 next_to_use;
335 u16 next_to_clean;
336
337 unsigned long last_rx_timestamp;
338
339 union {
340 u16 next_to_alloc;
341 struct {
342 u8 atr_sample_rate;
343 u8 atr_count;
344 };
345 };
346
347 u8 dcb_tc;
348 struct ixgbe_queue_stats stats;
349 struct u64_stats_sync syncp;
350 union {
351 struct ixgbe_tx_queue_stats tx_stats;
352 struct ixgbe_rx_queue_stats rx_stats;
353 };
354 struct xdp_rxq_info xdp_rxq;
355 struct xsk_buff_pool *xsk_pool;
356 u16 ring_idx; /* {rx,tx,xdp}_ring back reference idx */
357 u16 rx_buf_len;
358 } ____cacheline_internodealigned_in_smp;
359
360 enum ixgbe_ring_f_enum {
361 RING_F_NONE = 0,
362 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
363 RING_F_RSS,
364 RING_F_FDIR,
365 #ifdef IXGBE_FCOE
366 RING_F_FCOE,
367 #endif /* IXGBE_FCOE */
368
369 RING_F_ARRAY_SIZE /* must be last in enum set */
370 };
371
372 #define IXGBE_MAX_RSS_INDICES 16
373 #define IXGBE_MAX_RSS_INDICES_X550 63
374 #define IXGBE_MAX_VMDQ_INDICES 64
375 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */
376 #define IXGBE_MAX_FCOE_INDICES 8
377 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
378 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
379 #define MAX_XDP_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
380 #define IXGBE_MAX_L2A_QUEUES 4
381 #define IXGBE_BAD_L2A_QUEUE 3
382 #define IXGBE_MAX_MACVLANS 63
383
384 struct ixgbe_ring_feature {
385 u16 limit; /* upper limit on feature indices */
386 u16 indices; /* current value of indices */
387 u16 mask; /* Mask used for feature to ring mapping */
388 u16 offset; /* offset to start of feature */
389 } ____cacheline_internodealigned_in_smp;
390
391 #define IXGBE_82599_VMDQ_8Q_MASK 0x78
392 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C
393 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E
394
395 /*
396 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
397 * this is twice the size of a half page we need to double the page order
398 * for FCoE enabled Rx queues.
399 */
ixgbe_rx_bufsz(struct ixgbe_ring * ring)400 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
401 {
402 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
403 return IXGBE_RXBUFFER_3K;
404 #if (PAGE_SIZE < 8192)
405 if (ring_uses_build_skb(ring))
406 return IXGBE_MAX_2K_FRAME_BUILD_SKB;
407 #endif
408 return IXGBE_RXBUFFER_2K;
409 }
410
ixgbe_rx_pg_order(struct ixgbe_ring * ring)411 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
412 {
413 #if (PAGE_SIZE < 8192)
414 if (test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
415 return 1;
416 #endif
417 return 0;
418 }
419 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
420
421 #define IXGBE_ITR_ADAPTIVE_MIN_INC 2
422 #define IXGBE_ITR_ADAPTIVE_MIN_USECS 10
423 #define IXGBE_ITR_ADAPTIVE_MAX_USECS 126
424 #define IXGBE_ITR_ADAPTIVE_LATENCY 0x80
425 #define IXGBE_ITR_ADAPTIVE_BULK 0x00
426
427 struct ixgbe_ring_container {
428 struct ixgbe_ring *ring; /* pointer to linked list of rings */
429 unsigned long next_update; /* jiffies value of last update */
430 unsigned int total_bytes; /* total bytes processed this int */
431 unsigned int total_packets; /* total packets processed this int */
432 u16 work_limit; /* total work allowed per interrupt */
433 u8 count; /* total number of rings in vector */
434 u8 itr; /* current ITR setting for ring */
435 };
436
437 /* iterator for handling rings in ring container */
438 #define ixgbe_for_each_ring(pos, head) \
439 for (pos = (head).ring; pos != NULL; pos = pos->next)
440
441 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
442 ? 8 : 1)
443 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
444
445 /* MAX_Q_VECTORS of these are allocated,
446 * but we only use one per queue-specific vector.
447 */
448 struct ixgbe_q_vector {
449 struct ixgbe_adapter *adapter;
450 #ifdef CONFIG_IXGBE_DCA
451 int cpu; /* CPU for DCA */
452 #endif
453 u16 v_idx; /* index of q_vector within array, also used for
454 * finding the bit in EICR and friends that
455 * represents the vector for this ring */
456 u16 itr; /* Interrupt throttle rate written to EITR */
457 struct ixgbe_ring_container rx, tx;
458
459 struct napi_struct napi;
460 cpumask_t affinity_mask;
461 int numa_node;
462 struct rcu_head rcu; /* to avoid race with update stats on free */
463 char name[IFNAMSIZ + 9];
464
465 /* for dynamic allocation of rings associated with this q_vector */
466 struct ixgbe_ring ring[] ____cacheline_internodealigned_in_smp;
467 };
468
469 #ifdef CONFIG_IXGBE_HWMON
470
471 #define IXGBE_HWMON_TYPE_LOC 0
472 #define IXGBE_HWMON_TYPE_TEMP 1
473 #define IXGBE_HWMON_TYPE_CAUTION 2
474 #define IXGBE_HWMON_TYPE_MAX 3
475
476 struct hwmon_attr {
477 struct device_attribute dev_attr;
478 struct ixgbe_hw *hw;
479 struct ixgbe_thermal_diode_data *sensor;
480 char name[12];
481 };
482
483 struct hwmon_buff {
484 struct attribute_group group;
485 const struct attribute_group *groups[2];
486 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1];
487 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4];
488 unsigned int n_hwmon;
489 };
490 #endif /* CONFIG_IXGBE_HWMON */
491
492 /*
493 * microsecond values for various ITR rates shifted by 2 to fit itr register
494 * with the first 3 bits reserved 0
495 */
496 #define IXGBE_MIN_RSC_ITR 24
497 #define IXGBE_100K_ITR 40
498 #define IXGBE_20K_ITR 200
499 #define IXGBE_12K_ITR 336
500
501 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
ixgbe_test_staterr(union ixgbe_adv_rx_desc * rx_desc,const u32 stat_err_bits)502 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
503 const u32 stat_err_bits)
504 {
505 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
506 }
507
ixgbe_desc_unused(struct ixgbe_ring * ring)508 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
509 {
510 u16 ntc = ring->next_to_clean;
511 u16 ntu = ring->next_to_use;
512
513 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
514 }
515
516 #define IXGBE_RX_DESC(R, i) \
517 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
518 #define IXGBE_TX_DESC(R, i) \
519 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
520 #define IXGBE_TX_CTXTDESC(R, i) \
521 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
522
523 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
524 #ifdef IXGBE_FCOE
525 /* Use 3K as the baby jumbo frame size for FCoE */
526 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
527 #endif /* IXGBE_FCOE */
528
529 #define OTHER_VECTOR 1
530 #define NON_Q_VECTORS (OTHER_VECTOR)
531
532 #define MAX_MSIX_VECTORS_82599 64
533 #define MAX_Q_VECTORS_82599 64
534 #define MAX_MSIX_VECTORS_82598 18
535 #define MAX_Q_VECTORS_82598 16
536
537 struct ixgbe_mac_addr {
538 u8 addr[ETH_ALEN];
539 u16 pool;
540 u16 state; /* bitmask */
541 };
542
543 #define IXGBE_MAC_STATE_DEFAULT 0x1
544 #define IXGBE_MAC_STATE_MODIFIED 0x2
545 #define IXGBE_MAC_STATE_IN_USE 0x4
546
547 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599
548 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
549
550 #define MIN_MSIX_Q_VECTORS 1
551 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
552
553 /* default to trying for four seconds */
554 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
555 #define IXGBE_SFP_POLL_JIFFIES (2 * HZ) /* SFP poll every 2 seconds */
556
557 /* board specific private data structure */
558 struct ixgbe_adapter {
559 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
560 /* OS defined structs */
561 struct net_device *netdev;
562 struct bpf_prog *xdp_prog;
563 struct pci_dev *pdev;
564 struct mii_bus *mii_bus;
565
566 unsigned long state;
567
568 /* Some features need tri-state capability,
569 * thus the additional *_CAPABLE flags.
570 */
571 u32 flags;
572 #define IXGBE_FLAG_MSI_ENABLED BIT(1)
573 #define IXGBE_FLAG_MSIX_ENABLED BIT(3)
574 #define IXGBE_FLAG_RX_1BUF_CAPABLE BIT(4)
575 #define IXGBE_FLAG_RX_PS_CAPABLE BIT(5)
576 #define IXGBE_FLAG_RX_PS_ENABLED BIT(6)
577 #define IXGBE_FLAG_DCA_ENABLED BIT(8)
578 #define IXGBE_FLAG_DCA_CAPABLE BIT(9)
579 #define IXGBE_FLAG_IMIR_ENABLED BIT(10)
580 #define IXGBE_FLAG_MQ_CAPABLE BIT(11)
581 #define IXGBE_FLAG_DCB_ENABLED BIT(12)
582 #define IXGBE_FLAG_VMDQ_CAPABLE BIT(13)
583 #define IXGBE_FLAG_VMDQ_ENABLED BIT(14)
584 #define IXGBE_FLAG_FAN_FAIL_CAPABLE BIT(15)
585 #define IXGBE_FLAG_NEED_LINK_UPDATE BIT(16)
586 #define IXGBE_FLAG_NEED_LINK_CONFIG BIT(17)
587 #define IXGBE_FLAG_FDIR_HASH_CAPABLE BIT(18)
588 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE BIT(19)
589 #define IXGBE_FLAG_FCOE_CAPABLE BIT(20)
590 #define IXGBE_FLAG_FCOE_ENABLED BIT(21)
591 #define IXGBE_FLAG_SRIOV_CAPABLE BIT(22)
592 #define IXGBE_FLAG_SRIOV_ENABLED BIT(23)
593 #define IXGBE_FLAG_RX_HWTSTAMP_ENABLED BIT(25)
594 #define IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER BIT(26)
595 #define IXGBE_FLAG_DCB_CAPABLE BIT(27)
596
597 u32 flags2;
598 #define IXGBE_FLAG2_RSC_CAPABLE BIT(0)
599 #define IXGBE_FLAG2_RSC_ENABLED BIT(1)
600 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE BIT(2)
601 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT BIT(3)
602 #define IXGBE_FLAG2_SEARCH_FOR_SFP BIT(4)
603 #define IXGBE_FLAG2_SFP_NEEDS_RESET BIT(5)
604 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT BIT(7)
605 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP BIT(8)
606 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP BIT(9)
607 #define IXGBE_FLAG2_PTP_PPS_ENABLED BIT(10)
608 #define IXGBE_FLAG2_PHY_INTERRUPT BIT(11)
609 #define IXGBE_FLAG2_VLAN_PROMISC BIT(13)
610 #define IXGBE_FLAG2_EEE_CAPABLE BIT(14)
611 #define IXGBE_FLAG2_EEE_ENABLED BIT(15)
612 #define IXGBE_FLAG2_RX_LEGACY BIT(16)
613 #define IXGBE_FLAG2_IPSEC_ENABLED BIT(17)
614 #define IXGBE_FLAG2_VF_IPSEC_ENABLED BIT(18)
615
616 /* Tx fast path data */
617 int num_tx_queues;
618 u16 tx_itr_setting;
619 u16 tx_work_limit;
620 u64 tx_ipsec;
621
622 /* Rx fast path data */
623 int num_rx_queues;
624 u16 rx_itr_setting;
625 u64 rx_ipsec;
626
627 /* Port number used to identify VXLAN traffic */
628 __be16 vxlan_port;
629 __be16 geneve_port;
630
631 /* XDP */
632 int num_xdp_queues;
633 struct ixgbe_ring *xdp_ring[MAX_XDP_QUEUES];
634 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled rings */
635
636 /* TX */
637 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
638
639 u64 restart_queue;
640 u64 lsc_int;
641 u32 tx_timeout_count;
642
643 /* RX */
644 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
645 int num_rx_pools; /* == num_rx_queues in 82598 */
646 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
647 u64 hw_csum_rx_error;
648 u64 hw_rx_no_dma_resources;
649 u64 rsc_total_count;
650 u64 rsc_total_flush;
651 u64 non_eop_descs;
652 u32 alloc_rx_page;
653 u32 alloc_rx_page_failed;
654 u32 alloc_rx_buff_failed;
655
656 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
657
658 /* DCB parameters */
659 struct ieee_pfc *ixgbe_ieee_pfc;
660 struct ieee_ets *ixgbe_ieee_ets;
661 struct ixgbe_dcb_config dcb_cfg;
662 struct ixgbe_dcb_config temp_dcb_cfg;
663 u8 hw_tcs;
664 u8 dcb_set_bitmap;
665 u8 dcbx_cap;
666 enum ixgbe_fc_mode last_lfc_mode;
667
668 int num_q_vectors; /* current number of q_vectors for device */
669 int max_q_vectors; /* true count of q_vectors for device */
670 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
671 struct msix_entry *msix_entries;
672
673 u32 test_icr;
674 struct ixgbe_ring test_tx_ring;
675 struct ixgbe_ring test_rx_ring;
676
677 /* structs defined in ixgbe_hw.h */
678 struct ixgbe_hw hw;
679 u16 msg_enable;
680 struct ixgbe_hw_stats stats;
681
682 u64 tx_busy;
683 unsigned int tx_ring_count;
684 unsigned int xdp_ring_count;
685 unsigned int rx_ring_count;
686
687 u32 link_speed;
688 bool link_up;
689 unsigned long sfp_poll_time;
690 unsigned long link_check_timeout;
691
692 struct timer_list service_timer;
693 struct work_struct service_task;
694
695 struct hlist_head fdir_filter_list;
696 unsigned long fdir_overflow; /* number of times ATR was backed off */
697 union ixgbe_atr_input fdir_mask;
698 int fdir_filter_count;
699 u32 fdir_pballoc;
700 u32 atr_sample_rate;
701 spinlock_t fdir_perfect_lock;
702
703 #ifdef IXGBE_FCOE
704 struct ixgbe_fcoe fcoe;
705 #endif /* IXGBE_FCOE */
706 u8 __iomem *io_addr; /* Mainly for iounmap use */
707 u32 wol;
708
709 u16 bridge_mode;
710
711 char eeprom_id[NVM_VER_SIZE];
712 u16 eeprom_cap;
713
714 u32 interrupt_event;
715 u32 led_reg;
716
717 struct ptp_clock *ptp_clock;
718 struct ptp_clock_info ptp_caps;
719 struct work_struct ptp_tx_work;
720 struct sk_buff *ptp_tx_skb;
721 struct hwtstamp_config tstamp_config;
722 unsigned long ptp_tx_start;
723 unsigned long last_overflow_check;
724 unsigned long last_rx_ptp_check;
725 unsigned long last_rx_timestamp;
726 spinlock_t tmreg_lock;
727 struct cyclecounter hw_cc;
728 struct timecounter hw_tc;
729 u32 base_incval;
730 u32 tx_hwtstamp_timeouts;
731 u32 tx_hwtstamp_skipped;
732 u32 rx_hwtstamp_cleared;
733 void (*ptp_setup_sdp)(struct ixgbe_adapter *);
734
735 /* SR-IOV */
736 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
737 unsigned int num_vfs;
738 struct vf_data_storage *vfinfo;
739 int vf_rate_link_speed;
740 struct vf_macvlans vf_mvs;
741 struct vf_macvlans *mv_list;
742
743 u32 timer_event_accumulator;
744 u32 vferr_refcount;
745 struct ixgbe_mac_addr *mac_table;
746 struct kobject *info_kobj;
747 #ifdef CONFIG_IXGBE_HWMON
748 struct hwmon_buff *ixgbe_hwmon_buff;
749 #endif /* CONFIG_IXGBE_HWMON */
750 #ifdef CONFIG_DEBUG_FS
751 struct dentry *ixgbe_dbg_adapter;
752 #endif /*CONFIG_DEBUG_FS*/
753
754 u8 default_up;
755 /* Bitmask indicating in use pools */
756 DECLARE_BITMAP(fwd_bitmask, IXGBE_MAX_MACVLANS + 1);
757
758 #define IXGBE_MAX_LINK_HANDLE 10
759 struct ixgbe_jump_table *jump_tables[IXGBE_MAX_LINK_HANDLE];
760 unsigned long tables;
761
762 /* maximum number of RETA entries among all devices supported by ixgbe
763 * driver: currently it's x550 device in non-SRIOV mode
764 */
765 #define IXGBE_MAX_RETA_ENTRIES 512
766 u8 rss_indir_tbl[IXGBE_MAX_RETA_ENTRIES];
767
768 #define IXGBE_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
769 u32 *rss_key;
770
771 #ifdef CONFIG_IXGBE_IPSEC
772 struct ixgbe_ipsec *ipsec;
773 #endif /* CONFIG_IXGBE_IPSEC */
774 spinlock_t vfs_lock;
775 };
776
ixgbe_max_rss_indices(struct ixgbe_adapter * adapter)777 static inline u8 ixgbe_max_rss_indices(struct ixgbe_adapter *adapter)
778 {
779 switch (adapter->hw.mac.type) {
780 case ixgbe_mac_82598EB:
781 case ixgbe_mac_82599EB:
782 case ixgbe_mac_X540:
783 return IXGBE_MAX_RSS_INDICES;
784 case ixgbe_mac_X550:
785 case ixgbe_mac_X550EM_x:
786 case ixgbe_mac_x550em_a:
787 return IXGBE_MAX_RSS_INDICES_X550;
788 default:
789 return 0;
790 }
791 }
792
793 struct ixgbe_fdir_filter {
794 struct hlist_node fdir_node;
795 union ixgbe_atr_input filter;
796 u16 sw_idx;
797 u64 action;
798 };
799
800 enum ixgbe_state_t {
801 __IXGBE_TESTING,
802 __IXGBE_RESETTING,
803 __IXGBE_DOWN,
804 __IXGBE_DISABLED,
805 __IXGBE_REMOVING,
806 __IXGBE_SERVICE_SCHED,
807 __IXGBE_SERVICE_INITED,
808 __IXGBE_IN_SFP_INIT,
809 __IXGBE_PTP_RUNNING,
810 __IXGBE_PTP_TX_IN_PROGRESS,
811 __IXGBE_RESET_REQUESTED,
812 };
813
814 struct ixgbe_cb {
815 union { /* Union defining head/tail partner */
816 struct sk_buff *head;
817 struct sk_buff *tail;
818 };
819 dma_addr_t dma;
820 u16 append_cnt;
821 bool page_released;
822 };
823 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
824
825 enum ixgbe_boards {
826 board_82598,
827 board_82599,
828 board_X540,
829 board_X550,
830 board_X550EM_x,
831 board_x550em_x_fw,
832 board_x550em_a,
833 board_x550em_a_fw,
834 };
835
836 extern const struct ixgbe_info ixgbe_82598_info;
837 extern const struct ixgbe_info ixgbe_82599_info;
838 extern const struct ixgbe_info ixgbe_X540_info;
839 extern const struct ixgbe_info ixgbe_X550_info;
840 extern const struct ixgbe_info ixgbe_X550EM_x_info;
841 extern const struct ixgbe_info ixgbe_x550em_x_fw_info;
842 extern const struct ixgbe_info ixgbe_x550em_a_info;
843 extern const struct ixgbe_info ixgbe_x550em_a_fw_info;
844 #ifdef CONFIG_IXGBE_DCB
845 extern const struct dcbnl_rtnl_ops ixgbe_dcbnl_ops;
846 #endif
847
848 extern char ixgbe_driver_name[];
849 #ifdef IXGBE_FCOE
850 extern char ixgbe_default_device_descr[];
851 #endif /* IXGBE_FCOE */
852
853 int ixgbe_open(struct net_device *netdev);
854 int ixgbe_close(struct net_device *netdev);
855 void ixgbe_up(struct ixgbe_adapter *adapter);
856 void ixgbe_down(struct ixgbe_adapter *adapter);
857 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
858 void ixgbe_reset(struct ixgbe_adapter *adapter);
859 void ixgbe_set_ethtool_ops(struct net_device *netdev);
860 int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
861 int ixgbe_setup_tx_resources(struct ixgbe_ring *);
862 void ixgbe_free_rx_resources(struct ixgbe_ring *);
863 void ixgbe_free_tx_resources(struct ixgbe_ring *);
864 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
865 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
866 void ixgbe_disable_rx(struct ixgbe_adapter *adapter);
867 void ixgbe_disable_tx(struct ixgbe_adapter *adapter);
868 void ixgbe_update_stats(struct ixgbe_adapter *adapter);
869 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
870 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
871 u16 subdevice_id);
872 #ifdef CONFIG_PCI_IOV
873 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);
874 #endif
875 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
876 const u8 *addr, u16 queue);
877 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
878 const u8 *addr, u16 queue);
879 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid);
880 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
881 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *,
882 struct ixgbe_ring *);
883 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
884 struct ixgbe_tx_buffer *);
885 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
886 void ixgbe_write_eitr(struct ixgbe_q_vector *);
887 int ixgbe_poll(struct napi_struct *napi, int budget);
888 int ethtool_ioctl(struct ifreq *ifr);
889 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
890 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
891 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
892 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
893 union ixgbe_atr_hash_dword input,
894 union ixgbe_atr_hash_dword common,
895 u8 queue);
896 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
897 union ixgbe_atr_input *input_mask);
898 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
899 union ixgbe_atr_input *input,
900 u16 soft_id, u8 queue);
901 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
902 union ixgbe_atr_input *input,
903 u16 soft_id);
904 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
905 union ixgbe_atr_input *mask);
906 int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
907 struct ixgbe_fdir_filter *input,
908 u16 sw_idx);
909 void ixgbe_set_rx_mode(struct net_device *netdev);
910 #ifdef CONFIG_IXGBE_DCB
911 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
912 #endif
913 int ixgbe_setup_tc(struct net_device *dev, u8 tc);
914 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
915 void ixgbe_do_reset(struct net_device *netdev);
916 #ifdef CONFIG_IXGBE_HWMON
917 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
918 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
919 #endif /* CONFIG_IXGBE_HWMON */
920 #ifdef IXGBE_FCOE
921 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
922 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
923 u8 *hdr_len);
924 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
925 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb);
926 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
927 struct scatterlist *sgl, unsigned int sgc);
928 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
929 struct scatterlist *sgl, unsigned int sgc);
930 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
931 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
932 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
933 int ixgbe_fcoe_enable(struct net_device *netdev);
934 int ixgbe_fcoe_disable(struct net_device *netdev);
935 #ifdef CONFIG_IXGBE_DCB
936 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
937 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
938 #endif /* CONFIG_IXGBE_DCB */
939 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
940 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
941 struct netdev_fcoe_hbainfo *info);
942 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
943 #endif /* IXGBE_FCOE */
944 #ifdef CONFIG_DEBUG_FS
945 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter);
946 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter);
947 void ixgbe_dbg_init(void);
948 void ixgbe_dbg_exit(void);
949 #else
ixgbe_dbg_adapter_init(struct ixgbe_adapter * adapter)950 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {}
ixgbe_dbg_adapter_exit(struct ixgbe_adapter * adapter)951 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {}
ixgbe_dbg_init(void)952 static inline void ixgbe_dbg_init(void) {}
ixgbe_dbg_exit(void)953 static inline void ixgbe_dbg_exit(void) {}
954 #endif /* CONFIG_DEBUG_FS */
txring_txq(const struct ixgbe_ring * ring)955 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
956 {
957 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
958 }
959
960 void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
961 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter);
962 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
963 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
964 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter);
965 void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter);
966 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *, struct sk_buff *);
967 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *, struct sk_buff *skb);
ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)968 static inline void ixgbe_ptp_rx_hwtstamp(struct ixgbe_ring *rx_ring,
969 union ixgbe_adv_rx_desc *rx_desc,
970 struct sk_buff *skb)
971 {
972 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_TSIP))) {
973 ixgbe_ptp_rx_pktstamp(rx_ring->q_vector, skb);
974 return;
975 }
976
977 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
978 return;
979
980 ixgbe_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
981
982 /* Update the last_rx_timestamp timer in order to enable watchdog check
983 * for error case of latched timestamp on a dropped packet.
984 */
985 rx_ring->last_rx_timestamp = jiffies;
986 }
987
988 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
989 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
990 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
991 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter);
992 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter);
993 #ifdef CONFIG_PCI_IOV
994 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter);
995 #endif
996
997 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
998 struct ixgbe_adapter *adapter,
999 struct ixgbe_ring *tx_ring);
1000 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter);
1001 void ixgbe_store_key(struct ixgbe_adapter *adapter);
1002 void ixgbe_store_reta(struct ixgbe_adapter *adapter);
1003 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
1004 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
1005 #ifdef CONFIG_IXGBE_IPSEC
1006 void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter);
1007 void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter);
1008 void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter);
1009 void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring,
1010 union ixgbe_adv_rx_desc *rx_desc,
1011 struct sk_buff *skb);
1012 int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
1013 struct ixgbe_ipsec_tx_data *itd);
1014 void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter, u32 vf);
1015 int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf);
1016 int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter, u32 *mbuf, u32 vf);
1017 #else
ixgbe_init_ipsec_offload(struct ixgbe_adapter * adapter)1018 static inline void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter) { }
ixgbe_stop_ipsec_offload(struct ixgbe_adapter * adapter)1019 static inline void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter) { }
ixgbe_ipsec_restore(struct ixgbe_adapter * adapter)1020 static inline void ixgbe_ipsec_restore(struct ixgbe_adapter *adapter) { }
ixgbe_ipsec_rx(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1021 static inline void ixgbe_ipsec_rx(struct ixgbe_ring *rx_ring,
1022 union ixgbe_adv_rx_desc *rx_desc,
1023 struct sk_buff *skb) { }
ixgbe_ipsec_tx(struct ixgbe_ring * tx_ring,struct ixgbe_tx_buffer * first,struct ixgbe_ipsec_tx_data * itd)1024 static inline int ixgbe_ipsec_tx(struct ixgbe_ring *tx_ring,
1025 struct ixgbe_tx_buffer *first,
1026 struct ixgbe_ipsec_tx_data *itd) { return 0; }
ixgbe_ipsec_vf_clear(struct ixgbe_adapter * adapter,u32 vf)1027 static inline void ixgbe_ipsec_vf_clear(struct ixgbe_adapter *adapter,
1028 u32 vf) { }
ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter * adapter,u32 * mbuf,u32 vf)1029 static inline int ixgbe_ipsec_vf_add_sa(struct ixgbe_adapter *adapter,
1030 u32 *mbuf, u32 vf) { return -EACCES; }
ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter * adapter,u32 * mbuf,u32 vf)1031 static inline int ixgbe_ipsec_vf_del_sa(struct ixgbe_adapter *adapter,
1032 u32 *mbuf, u32 vf) { return -EACCES; }
1033 #endif /* CONFIG_IXGBE_IPSEC */
1034
ixgbe_enabled_xdp_adapter(struct ixgbe_adapter * adapter)1035 static inline bool ixgbe_enabled_xdp_adapter(struct ixgbe_adapter *adapter)
1036 {
1037 return !!adapter->xdp_prog;
1038 }
1039
1040 #endif /* _IXGBE_H_ */
1041