| /drivers/clk/mediatek/ |
| D | clk-mt8167.c | 657 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
687 #define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ argument
738 #define GATE_TOP0(_id, _name, _parent, _shift) { \ argument
747 #define GATE_TOP0_I(_id, _name, _parent, _shift) { \ argument
756 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
765 #define GATE_TOP2(_id, _name, _parent, _shift) { \ argument
774 #define GATE_TOP2_I(_id, _name, _parent, _shift) { \ argument
783 #define GATE_TOP3(_id, _name, _parent, _shift) { \ argument
792 #define GATE_TOP4_I(_id, _name, _parent, _shift) { \ argument
801 #define GATE_TOP5(_id, _name, _parent, _shift) { \ argument
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| D | clk-mt8183-ipu_conn.c | 44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \ argument
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \ argument
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \ argument
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \ argument
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \ argument
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| D | clk-mt8516.c | 467 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
527 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
536 #define GATE_TOP2(_id, _name, _parent, _shift) { \ argument
545 #define GATE_TOP2_I(_id, _name, _parent, _shift) { \ argument
554 #define GATE_TOP3(_id, _name, _parent, _shift) { \ argument
563 #define GATE_TOP4_I(_id, _name, _parent, _shift) { \ argument
572 #define GATE_TOP5(_id, _name, _parent, _shift) { \ argument
736 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
756 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
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| D | clk-mt8173.c | 622 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
661 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
670 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
737 #define GATE_IMG(_id, _name, _parent, _shift) { \ argument
768 #define GATE_VDEC0(_id, _name, _parent, _shift) { \ argument
777 #define GATE_VDEC1(_id, _name, _parent, _shift) { \ argument
791 #define GATE_VENC(_id, _name, _parent, _shift) { \ argument
807 #define GATE_VENCLT(_id, _name, _parent, _shift) { \ argument
923 #define APMIXED_USB(_id, _name, _parent, _reg_ofs) { \ argument
938 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
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| D | clk-mt7622.c | 24 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ argument
45 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
52 #define GATE_APMIXED(_id, _name, _parent, _shift) { \ argument
61 #define GATE_INFRA(_id, _name, _parent, _shift) { \ argument
70 #define GATE_TOP0(_id, _name, _parent, _shift) { \ argument
79 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
88 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
97 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
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| D | clk-mt2701-aud.c | 18 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
27 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
36 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
45 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
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| D | clk-mt6765.c | 485 #define GATE_TOP0(_id, _name, _parent, _shift) { \ argument
494 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
503 #define GATE_TOP2(_id, _name, _parent, _shift) { \ argument
561 #define GATE_IFR2(_id, _name, _parent, _shift) { \ argument
570 #define GATE_IFR3(_id, _name, _parent, _shift) { \ argument
579 #define GATE_IFR4(_id, _name, _parent, _shift) { \ argument
588 #define GATE_IFR5(_id, _name, _parent, _shift) { \ argument
676 #define GATE_APMIXED(_id, _name, _parent, _shift) { \ argument
716 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
740 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
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| D | clk-mt8183.c | 756 #define GATE_TOP(_id, _name, _parent, _shift) \ argument
790 #define GATE_INFRA0(_id, _name, _parent, _shift) \ argument
794 #define GATE_INFRA1(_id, _name, _parent, _shift) \ argument
798 #define GATE_INFRA2(_id, _name, _parent, _shift) \ argument
802 #define GATE_INFRA3(_id, _name, _parent, _shift) \ argument
1013 #define GATE_PERI(_id, _name, _parent, _shift) \ argument
1027 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
1031 #define GATE_APMIXED(_id, _name, _parent, _shift) \ argument
1067 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
1094 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
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| D | clk-mt7622-aud.c | 19 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
28 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
37 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
46 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
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| D | clk-mt6797.c | 424 #define GATE_ICG0(_id, _name, _parent, _shift) { \ argument
433 #define GATE_ICG1(_id, _name, _parent, _shift) \ argument
436 #define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \ argument
446 #define GATE_ICG2(_id, _name, _parent, _shift) \ argument
449 #define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \ argument
615 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
635 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
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| D | clk-mt6779.c | 867 #define GATE_INFRA0(_id, _name, _parent, _shift) \ argument
870 #define GATE_INFRA1(_id, _name, _parent, _shift) \ argument
873 #define GATE_INFRA2(_id, _name, _parent, _shift) \ argument
876 #define GATE_INFRA3(_id, _name, _parent, _shift) \ argument
1105 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
1109 #define GATE_APMIXED(_id, _name, _parent, _shift) \ argument
1144 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
1171 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
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| D | clk-mt2712.c | 960 #define GATE_TOP0(_id, _name, _parent, _shift) { \ argument
969 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
1000 #define GATE_INFRA(_id, _name, _parent, _shift) { \ argument
1037 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
1046 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
1055 #define GATE_PERI2(_id, _name, _parent, _shift) { \ argument
1166 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
1189 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
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| D | clk-mt7629.c | 24 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
45 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
52 #define GATE_APMIXED(_id, _name, _parent, _shift) { \ argument
61 #define GATE_INFRA(_id, _name, _parent, _shift) { \ argument
70 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
79 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
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| D | clk-mt2712-mm.c | 33 #define GATE_MM0(_id, _name, _parent, _shift) { \ argument
42 #define GATE_MM1(_id, _name, _parent, _shift) { \ argument
51 #define GATE_MM2(_id, _name, _parent, _shift) { \ argument
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| D | clk-mtk.h | 29 #define FIXED_CLK(_id, _name, _parent, _rate) { \ argument
47 #define FACTOR(_id, _name, _parent, _mult, _div) { \ argument
81 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
101 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
110 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
114 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
118 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument
131 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ argument
190 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
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| /drivers/clk/renesas/ |
| D | rcar-gen3-cpg.h | 34 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
37 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ argument
42 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ argument
47 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ argument
50 #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \ argument
54 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
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| D | renesas-cpg-mssr.h | 44 #define DEF_TYPE(_name, _id, _type...) \ argument
46 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
49 #define DEF_INPUT(_name, _id) \ argument
51 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
55 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
57 #define DEF_RATE(_name, _id, _rate) \ argument
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| /drivers/clk/samsung/ |
| D | clk.h | 42 #define ALIAS(_id, dname, a) \ argument
67 #define FRATE(_id, cname, pname, f, frate) \ argument
94 #define FFACTOR(_id, cname, pname, m, d, f) \ argument
128 #define __MUX(_id, cname, pnames, o, s, w, f, mf) \ argument
141 #define MUX(_id, cname, pnames, o, s, w) \ argument
144 #define MUX_F(_id, cname, pnames, o, s, w, f, mf) \ argument
169 #define __DIV(_id, cname, pname, o, s, w, f, df, t) \ argument
182 #define DIV(_id, cname, pname, o, s, w) \ argument
185 #define DIV_F(_id, cname, pname, o, s, w, f, df) \ argument
188 #define DIV_T(_id, cname, pname, o, s, w, t) \ argument
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| /drivers/clk/rockchip/ |
| D | clk.h | 295 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ argument
425 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ argument
446 #define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \ argument
468 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \ argument
486 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\ argument
505 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \ argument
523 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \ argument
542 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \ argument
562 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\ argument
579 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \ argument
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| /drivers/clk/pistachio/ |
| D | clk.h | 19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
86 #define FIXED_FACTOR(_id, _name, _pname, _div) \ argument
119 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument
130 #define PLL_FIXED(_id, _name, _pname, _type, _reg) \ argument
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| /drivers/clk/zte/ |
| D | clk.h | 60 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
80 #define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \ argument
98 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \ argument
114 #define MUX(_id, _name, _parent, _reg, _shift, _width) \ argument
122 #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \ argument
147 #define AUDIO_DIV(_id, _name, _parent, _reg) \ argument
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| /drivers/net/ethernet/mellanox/mlxsw/ |
| D | spectrum_trap.c | 222 #define MLXSW_SP_TRAP_DROP(_id, _group_id) \ argument
227 #define MLXSW_SP_TRAP_DROP_EXT(_id, _group_id, _metadata) \ argument
232 #define MLXSW_SP_TRAP_BUFFER_DROP(_id) \ argument
237 #define MLXSW_SP_TRAP_DRIVER_DROP(_id, _group_id) \ argument
243 #define MLXSW_SP_TRAP_EXCEPTION(_id, _group_id) \ argument
248 #define MLXSW_SP_TRAP_CONTROL(_id, _group_id, _action) \ argument
253 #define MLXSW_SP_RXL_DISCARD(_id, _group_id) \ argument
258 #define MLXSW_SP_RXL_ACL_DISCARD(_id, _en_group_id, _dis_group_id) \ argument
267 #define MLXSW_SP_RXL_EXCEPTION(_id, _group_id, _action) \ argument
271 #define MLXSW_SP_RXL_NO_MARK(_id, _group_id, _action, _is_ctrl) \ argument
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| /drivers/staging/media/atomisp/include/media/ |
| D | lm3554.h | 27 #define v4l2_queryctrl_entry_integer(_id, _name,\ argument
40 #define v4l2_queryctrl_entry_boolean(_id, _name,\ argument
53 #define s_ctrl_id_entry_integer(_id, _name, \ argument
65 #define s_ctrl_id_entry_boolean(_id, _name, \ argument
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| /drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hw_catalog.c | 329 #define SSPP_BLK(_name, _id, _base, _features, \ argument
389 #define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \ argument
457 #define DSPP_BLK(_name, _id, _base) \ argument
484 #define PP_BLK_TE(_name, _id, _base) \ argument
491 #define PP_BLK(_name, _id, _base) \ argument
523 #define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _features) \ argument
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| /drivers/interconnect/imx/ |
| D | imx.h | 41 #define DEFINE_BUS_INTERCONNECT(_name, _id, _adj, ...) \ argument
50 #define DEFINE_BUS_MASTER(_name, _id, _dest_id) \ argument
53 #define DEFINE_BUS_SLAVE(_name, _id, _adj) \ argument
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