1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
3
4
5 #include "msm_gem.h"
6 #include "msm_mmu.h"
7 #include "msm_gpu_trace.h"
8 #include "a6xx_gpu.h"
9 #include "a6xx_gmu.xml.h"
10
11 #include <linux/devfreq.h>
12
13 #define GPU_PAS_ID 13
14
_a6xx_check_idle(struct msm_gpu * gpu)15 static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
16 {
17 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
18 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
19
20 /* Check that the GMU is idle */
21 if (!a6xx_gmu_isidle(&a6xx_gpu->gmu))
22 return false;
23
24 /* Check tha the CX master is idle */
25 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) &
26 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER)
27 return false;
28
29 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) &
30 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT);
31 }
32
a6xx_idle(struct msm_gpu * gpu,struct msm_ringbuffer * ring)33 bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
34 {
35 /* wait for CP to drain ringbuffer: */
36 if (!adreno_idle(gpu, ring))
37 return false;
38
39 if (spin_until(_a6xx_check_idle(gpu))) {
40 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n",
41 gpu->name, __builtin_return_address(0),
42 gpu_read(gpu, REG_A6XX_RBBM_STATUS),
43 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS),
44 gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
45 gpu_read(gpu, REG_A6XX_CP_RB_WPTR));
46 return false;
47 }
48
49 return true;
50 }
51
a6xx_flush(struct msm_gpu * gpu,struct msm_ringbuffer * ring)52 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
53 {
54 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
55 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
56 uint32_t wptr;
57 unsigned long flags;
58
59 /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */
60 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) {
61 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
62
63 OUT_PKT7(ring, CP_WHERE_AM_I, 2);
64 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring)));
65 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring)));
66 }
67
68 spin_lock_irqsave(&ring->preempt_lock, flags);
69
70 /* Copy the shadow to the actual register */
71 ring->cur = ring->next;
72
73 /* Make sure to wrap wptr if we need to */
74 wptr = get_wptr(ring);
75
76 spin_unlock_irqrestore(&ring->preempt_lock, flags);
77
78 /* Make sure everything is posted before making a decision */
79 mb();
80
81 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);
82 }
83
get_stats_counter(struct msm_ringbuffer * ring,u32 counter,u64 iova)84 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter,
85 u64 iova)
86 {
87 OUT_PKT7(ring, CP_REG_TO_MEM, 3);
88 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) |
89 CP_REG_TO_MEM_0_CNT(2) |
90 CP_REG_TO_MEM_0_64B);
91 OUT_RING(ring, lower_32_bits(iova));
92 OUT_RING(ring, upper_32_bits(iova));
93 }
94
a6xx_set_pagetable(struct a6xx_gpu * a6xx_gpu,struct msm_ringbuffer * ring,struct msm_file_private * ctx)95 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
96 struct msm_ringbuffer *ring, struct msm_file_private *ctx)
97 {
98 phys_addr_t ttbr;
99 u32 asid;
100 u64 memptr = rbmemptr(ring, ttbr0);
101
102 if (ctx->seqno == a6xx_gpu->cur_ctx_seqno)
103 return;
104
105 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))
106 return;
107
108 /* Execute the table update */
109 OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
110 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
111
112 OUT_RING(ring,
113 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
114 CP_SMMU_TABLE_UPDATE_1_ASID(asid));
115 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
116 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
117
118 /*
119 * Write the new TTBR0 to the memstore. This is good for debugging.
120 */
121 OUT_PKT7(ring, CP_MEM_WRITE, 4);
122 OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
123 OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
124 OUT_RING(ring, lower_32_bits(ttbr));
125 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr));
126
127 /*
128 * And finally, trigger a uche flush to be sure there isn't anything
129 * lingering in that part of the GPU
130 */
131
132 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
133 OUT_RING(ring, 0x31);
134
135 a6xx_gpu->cur_ctx_seqno = ctx->seqno;
136 }
137
a6xx_submit(struct msm_gpu * gpu,struct msm_gem_submit * submit)138 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
139 {
140 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
141 struct msm_drm_private *priv = gpu->dev->dev_private;
142 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
143 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
144 struct msm_ringbuffer *ring = submit->ring;
145 unsigned int i;
146
147 a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
148
149 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
150 rbmemptr_stats(ring, index, cpcycles_start));
151
152 /*
153 * For PM4 the GMU register offsets are calculated from the base of the
154 * GPU registers so we need to add 0x1a800 to the register value on A630
155 * to get the right value from PM4.
156 */
157 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
158 rbmemptr_stats(ring, index, alwayson_start));
159
160 /* Invalidate CCU depth and color */
161 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
162 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH));
163
164 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
165 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR));
166
167 /* Submit the commands */
168 for (i = 0; i < submit->nr_cmds; i++) {
169 switch (submit->cmd[i].type) {
170 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
171 break;
172 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
173 if (priv->lastctx == submit->queue->ctx)
174 break;
175 fallthrough;
176 case MSM_SUBMIT_CMD_BUF:
177 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3);
178 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
179 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));
180 OUT_RING(ring, submit->cmd[i].size);
181 break;
182 }
183 }
184
185 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
186 rbmemptr_stats(ring, index, cpcycles_end));
187 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
188 rbmemptr_stats(ring, index, alwayson_end));
189
190 /* Write the fence to the scratch register */
191 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);
192 OUT_RING(ring, submit->seqno);
193
194 /*
195 * Execute a CACHE_FLUSH_TS event. This will ensure that the
196 * timestamp is written to the memory and then triggers the interrupt
197 */
198 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
199 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) |
200 CP_EVENT_WRITE_0_IRQ);
201 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));
202 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));
203 OUT_RING(ring, submit->seqno);
204
205 trace_msm_gpu_submit_flush(submit,
206 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
207 REG_A6XX_CP_ALWAYS_ON_COUNTER_HI));
208
209 a6xx_flush(gpu, ring);
210 }
211
212 const struct adreno_reglist a630_hwcg[] = {
213 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
214 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
215 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
216 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
217 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
218 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
219 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
220 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
221 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
222 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
223 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
224 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
225 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
226 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
227 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
228 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
229 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
230 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
231 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
232 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
233 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
234 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
235 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
236 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
237 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
238 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
239 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
240 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
241 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
242 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
243 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
244 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
245 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
246 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
247 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
248 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
249 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
250 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
251 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
252 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
253 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
254 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
255 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
256 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
257 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
258 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
259 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
260 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
261 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
262 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
263 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
264 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
265 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
266 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
267 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
268 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
269 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
270 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
271 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
272 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
273 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
274 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
275 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
276 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
277 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
278 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
279 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
280 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
281 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
282 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
283 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
284 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
285 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
286 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
287 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
288 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
289 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
290 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
291 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
292 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
293 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
294 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
295 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
296 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
297 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
298 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
299 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
300 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
301 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
302 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
303 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
304 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
305 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
306 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
307 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
308 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
309 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
310 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
311 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
312 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
313 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
314 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
315 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
316 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
317 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
318 {},
319 };
320
321 const struct adreno_reglist a640_hwcg[] = {
322 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
323 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
324 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
325 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
326 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
327 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
328 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
329 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
330 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
331 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
332 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
333 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
334 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
335 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
336 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
337 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
338 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
339 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
340 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
341 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
342 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
343 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
344 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
345 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
346 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
347 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
348 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
349 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
350 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
351 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
352 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
353 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
354 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
355 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
356 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
357 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
358 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
359 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
360 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
361 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
362 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
363 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
364 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
365 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
366 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
367 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
368 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
369 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
370 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
371 {},
372 };
373
374 const struct adreno_reglist a650_hwcg[] = {
375 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
376 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
377 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
378 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
379 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
380 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
381 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
382 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
383 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
384 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
385 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
386 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
387 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
388 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
389 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
390 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
391 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
392 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
393 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
394 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
395 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
396 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
397 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
398 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
399 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
400 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
401 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
402 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
403 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
404 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
405 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
406 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
407 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
408 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
409 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
410 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
411 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
412 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
413 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
414 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
415 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
416 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
417 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
418 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
419 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
420 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
421 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
422 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
423 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
424 {},
425 };
426
a6xx_set_hwcg(struct msm_gpu * gpu,bool state)427 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
428 {
429 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
430 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
431 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
432 const struct adreno_reglist *reg;
433 unsigned int i;
434 u32 val, clock_cntl_on;
435
436 if (!adreno_gpu->info->hwcg)
437 return;
438
439 if (adreno_is_a630(adreno_gpu))
440 clock_cntl_on = 0x8aa8aa02;
441 else
442 clock_cntl_on = 0x8aa8aa82;
443
444 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);
445
446 /* Don't re-program the registers if they are already correct */
447 if ((!state && !val) || (state && (val == clock_cntl_on)))
448 return;
449
450 /* Disable SP clock before programming HWCG registers */
451 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
452
453 for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++)
454 gpu_write(gpu, reg->offset, state ? reg->value : 0);
455
456 /* Enable SP clock */
457 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
458
459 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
460 }
461
462 /* For a615, a616, a618, A619, a630, a640 and a680 */
463 static const u32 a6xx_protect[] = {
464 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
465 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
466 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
467 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
468 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
469 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
470 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
471 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
472 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
473 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
474 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
475 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
476 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
477 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
478 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
479 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
480 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
481 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
482 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
483 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
484 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
485 A6XX_PROTECT_NORDWR(0x09e70, 0x0001),
486 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
487 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
488 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
489 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
490 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
491 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
492 A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
493 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
494 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
495 A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */
496 };
497
498 /* These are for a620 and a650 */
499 static const u32 a650_protect[] = {
500 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
501 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
502 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
503 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
504 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
505 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
506 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
507 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
508 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
509 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
510 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
511 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
512 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
513 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
514 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
515 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
516 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
517 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
518 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
519 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
520 A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
521 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
522 A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
523 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
524 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
525 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
526 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
527 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
528 A6XX_PROTECT_NORDWR(0x0b608, 0x0007),
529 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
530 A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
531 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
532 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
533 A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
534 A6XX_PROTECT_NORDWR(0x1a800, 0x1fff),
535 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
536 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
537 A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
538 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
539 };
540
a6xx_set_cp_protect(struct msm_gpu * gpu)541 static void a6xx_set_cp_protect(struct msm_gpu *gpu)
542 {
543 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
544 const u32 *regs = a6xx_protect;
545 unsigned i, count = ARRAY_SIZE(a6xx_protect), count_max = 32;
546
547 BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32);
548 BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
549
550 if (adreno_is_a650(adreno_gpu)) {
551 regs = a650_protect;
552 count = ARRAY_SIZE(a650_protect);
553 count_max = 48;
554 }
555
556 /*
557 * Enable access protection to privileged registers, fault on an access
558 * protect violation and select the last span to protect from the start
559 * address all the way to the end of the register address space
560 */
561 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3));
562
563 for (i = 0; i < count - 1; i++)
564 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]);
565 /* last CP_PROTECT to have "infinite" length on the last entry */
566 gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]);
567 }
568
a6xx_set_ubwc_config(struct msm_gpu * gpu)569 static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
570 {
571 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
572 u32 lower_bit = 2;
573 u32 amsbc = 0;
574 u32 rgb565_predicator = 0;
575 u32 uavflagprd_inv = 0;
576
577 /* a618 is using the hw default values */
578 if (adreno_is_a618(adreno_gpu))
579 return;
580
581 if (adreno_is_a640(adreno_gpu))
582 amsbc = 1;
583
584 if (adreno_is_a650(adreno_gpu)) {
585 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
586 lower_bit = 3;
587 amsbc = 1;
588 rgb565_predicator = 1;
589 uavflagprd_inv = 2;
590 }
591
592 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
593 rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1);
594 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1);
595 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
596 uavflagprd_inv << 4 | lower_bit << 1);
597 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21);
598 }
599
a6xx_cp_init(struct msm_gpu * gpu)600 static int a6xx_cp_init(struct msm_gpu *gpu)
601 {
602 struct msm_ringbuffer *ring = gpu->rb[0];
603
604 OUT_PKT7(ring, CP_ME_INIT, 8);
605
606 OUT_RING(ring, 0x0000002f);
607
608 /* Enable multiple hardware contexts */
609 OUT_RING(ring, 0x00000003);
610
611 /* Enable error detection */
612 OUT_RING(ring, 0x20000000);
613
614 /* Don't enable header dump */
615 OUT_RING(ring, 0x00000000);
616 OUT_RING(ring, 0x00000000);
617
618 /* No workarounds enabled */
619 OUT_RING(ring, 0x00000000);
620
621 /* Pad rest of the cmds with 0's */
622 OUT_RING(ring, 0x00000000);
623 OUT_RING(ring, 0x00000000);
624
625 a6xx_flush(gpu, ring);
626 return a6xx_idle(gpu, ring) ? 0 : -EINVAL;
627 }
628
a6xx_ucode_check_version(struct a6xx_gpu * a6xx_gpu,struct drm_gem_object * obj)629 static void a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu,
630 struct drm_gem_object *obj)
631 {
632 u32 *buf = msm_gem_get_vaddr_active(obj);
633
634 if (IS_ERR(buf))
635 return;
636
637 /*
638 * If the lowest nibble is 0xa that is an indication that this microcode
639 * has been patched. The actual version is in dword [3] but we only care
640 * about the patchlevel which is the lowest nibble of dword [3]
641 *
642 * Otherwise check that the firmware is greater than or equal to 1.90
643 * which was the first version that had this fix built in
644 */
645 if (((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1)
646 a6xx_gpu->has_whereami = true;
647 else if ((buf[0] & 0xfff) > 0x190)
648 a6xx_gpu->has_whereami = true;
649
650 msm_gem_put_vaddr(obj);
651 }
652
a6xx_ucode_init(struct msm_gpu * gpu)653 static int a6xx_ucode_init(struct msm_gpu *gpu)
654 {
655 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
656 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
657
658 if (!a6xx_gpu->sqe_bo) {
659 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu,
660 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova);
661
662 if (IS_ERR(a6xx_gpu->sqe_bo)) {
663 int ret = PTR_ERR(a6xx_gpu->sqe_bo);
664
665 a6xx_gpu->sqe_bo = NULL;
666 DRM_DEV_ERROR(&gpu->pdev->dev,
667 "Could not allocate SQE ucode: %d\n", ret);
668
669 return ret;
670 }
671
672 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw");
673 a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo);
674 }
675
676 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO,
677 REG_A6XX_CP_SQE_INSTR_BASE_HI, a6xx_gpu->sqe_iova);
678
679 return 0;
680 }
681
a6xx_zap_shader_init(struct msm_gpu * gpu)682 static int a6xx_zap_shader_init(struct msm_gpu *gpu)
683 {
684 static bool loaded;
685 int ret;
686
687 if (loaded)
688 return 0;
689
690 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID);
691
692 loaded = !ret;
693 return ret;
694 }
695
696 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \
697 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \
698 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \
699 A6XX_RBBM_INT_0_MASK_CP_IB2 | \
700 A6XX_RBBM_INT_0_MASK_CP_IB1 | \
701 A6XX_RBBM_INT_0_MASK_CP_RB | \
702 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \
703 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \
704 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
705 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
706 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR)
707
a6xx_hw_init(struct msm_gpu * gpu)708 static int a6xx_hw_init(struct msm_gpu *gpu)
709 {
710 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
711 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
712 int ret;
713
714 /* Make sure the GMU keeps the GPU on while we set it up */
715 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
716
717 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
718
719 /*
720 * Disable the trusted memory range - we don't actually supported secure
721 * memory rendering at this point in time and we don't want to block off
722 * part of the virtual memory space.
723 */
724 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,
725 REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);
726 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
727
728 /* Turn on 64 bit addressing for all blocks */
729 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1);
730 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1);
731 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1);
732 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1);
733 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1);
734 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1);
735 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1);
736 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1);
737 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1);
738 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1);
739 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
740 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
741
742 /* enable hardware clockgating */
743 a6xx_set_hwcg(gpu, true);
744
745 /* VBIF/GBIF start*/
746 if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) {
747 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
748 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
749 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
750 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
751 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
752 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);
753 } else {
754 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
755 }
756
757 if (adreno_is_a630(adreno_gpu))
758 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
759
760 /* Make all blocks contribute to the GPU BUSY perf counter */
761 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
762
763 /* Disable L2 bypass in the UCHE */
764 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0);
765 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff);
766 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000);
767 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff);
768 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);
769 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);
770
771 if (!adreno_is_a650(adreno_gpu)) {
772 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
773 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
774 REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
775
776 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,
777 REG_A6XX_UCHE_GMEM_RANGE_MAX_HI,
778 0x00100000 + adreno_gpu->gmem - 1);
779 }
780
781 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
782 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
783
784 if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu))
785 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
786 else
787 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
788 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
789
790 /* Setting the mem pool size */
791 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
792
793 /* Setting the primFifo thresholds default values */
794 if (adreno_is_a650(adreno_gpu))
795 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000);
796 else if (adreno_is_a640(adreno_gpu))
797 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000);
798 else
799 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));
800
801 /* Set the AHB default slave response to "ERROR" */
802 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
803
804 /* Turn on performance counters */
805 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);
806
807 /* Select CP0 to always count cycles */
808 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
809
810 a6xx_set_ubwc_config(gpu);
811
812 /* Enable fault detection */
813 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,
814 (1 << 30) | 0x1fffff);
815
816 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);
817
818 /* Set weights for bicubic filtering */
819 if (adreno_is_a650(adreno_gpu)) {
820 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
821 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
822 0x3fe05ff4);
823 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
824 0x3fa0ebee);
825 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
826 0x3f5193ed);
827 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
828 0x3f0243f0);
829 }
830
831 /* Protect registers from the CP */
832 a6xx_set_cp_protect(gpu);
833
834 /* Enable expanded apriv for targets that support it */
835 if (gpu->hw_apriv) {
836 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
837 (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1));
838 }
839
840 /* Enable interrupts */
841 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK);
842
843 ret = adreno_hw_init(gpu);
844 if (ret)
845 goto out;
846
847 ret = a6xx_ucode_init(gpu);
848 if (ret)
849 goto out;
850
851 /* Set the ringbuffer address */
852 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, REG_A6XX_CP_RB_BASE_HI,
853 gpu->rb[0]->iova);
854
855 /* Targets that support extended APRIV can use the RPTR shadow from
856 * hardware but all the other ones need to disable the feature. Targets
857 * that support the WHERE_AM_I opcode can use that instead
858 */
859 if (adreno_gpu->base.hw_apriv)
860 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT);
861 else
862 gpu_write(gpu, REG_A6XX_CP_RB_CNTL,
863 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
864
865 /*
866 * Expanded APRIV and targets that support WHERE_AM_I both need a
867 * privileged buffer to store the RPTR shadow
868 */
869
870 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) {
871 if (!a6xx_gpu->shadow_bo) {
872 a6xx_gpu->shadow = msm_gem_kernel_new_locked(gpu->dev,
873 sizeof(u32) * gpu->nr_rings,
874 MSM_BO_UNCACHED | MSM_BO_MAP_PRIV,
875 gpu->aspace, &a6xx_gpu->shadow_bo,
876 &a6xx_gpu->shadow_iova);
877
878 if (IS_ERR(a6xx_gpu->shadow))
879 return PTR_ERR(a6xx_gpu->shadow);
880 }
881
882 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR_LO,
883 REG_A6XX_CP_RB_RPTR_ADDR_HI,
884 shadowptr(a6xx_gpu, gpu->rb[0]));
885 }
886
887 /* Always come up on rb 0 */
888 a6xx_gpu->cur_ring = gpu->rb[0];
889
890 a6xx_gpu->cur_ctx_seqno = 0;
891
892 /* Enable the SQE_to start the CP engine */
893 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);
894
895 ret = a6xx_cp_init(gpu);
896 if (ret)
897 goto out;
898
899 /*
900 * Try to load a zap shader into the secure world. If successful
901 * we can use the CP to switch out of secure mode. If not then we
902 * have no resource but to try to switch ourselves out manually. If we
903 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will
904 * be blocked and a permissions violation will soon follow.
905 */
906 ret = a6xx_zap_shader_init(gpu);
907 if (!ret) {
908 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1);
909 OUT_RING(gpu->rb[0], 0x00000000);
910
911 a6xx_flush(gpu, gpu->rb[0]);
912 if (!a6xx_idle(gpu, gpu->rb[0]))
913 return -EINVAL;
914 } else if (ret == -ENODEV) {
915 /*
916 * This device does not use zap shader (but print a warning
917 * just in case someone got their dt wrong.. hopefully they
918 * have a debug UART to realize the error of their ways...
919 * if you mess this up you are about to crash horribly)
920 */
921 dev_warn_once(gpu->dev->dev,
922 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n");
923 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0);
924 ret = 0;
925 } else {
926 return ret;
927 }
928
929 out:
930 /*
931 * Tell the GMU that we are done touching the GPU and it can start power
932 * management
933 */
934 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
935
936 if (a6xx_gpu->gmu.legacy) {
937 /* Take the GMU out of its special boot mode */
938 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);
939 }
940
941 return ret;
942 }
943
a6xx_dump(struct msm_gpu * gpu)944 static void a6xx_dump(struct msm_gpu *gpu)
945 {
946 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n",
947 gpu_read(gpu, REG_A6XX_RBBM_STATUS));
948 adreno_dump(gpu);
949 }
950
951 #define VBIF_RESET_ACK_TIMEOUT 100
952 #define VBIF_RESET_ACK_MASK 0x00f0
953
a6xx_recover(struct msm_gpu * gpu)954 static void a6xx_recover(struct msm_gpu *gpu)
955 {
956 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
957 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
958 int i;
959
960 adreno_dump_info(gpu);
961
962 for (i = 0; i < 8; i++)
963 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i,
964 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i)));
965
966 if (hang_debug)
967 a6xx_dump(gpu);
968
969 /*
970 * Turn off keep alive that might have been enabled by the hang
971 * interrupt
972 */
973 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
974
975 gpu->funcs->pm_suspend(gpu);
976 gpu->funcs->pm_resume(gpu);
977
978 msm_gpu_hw_init(gpu);
979 }
980
a6xx_fault_handler(void * arg,unsigned long iova,int flags)981 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags)
982 {
983 struct msm_gpu *gpu = arg;
984
985 pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n",
986 iova, flags,
987 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
988 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
989 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
990 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
991
992 return -EFAULT;
993 }
994
a6xx_cp_hw_err_irq(struct msm_gpu * gpu)995 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu)
996 {
997 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS);
998
999 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) {
1000 u32 val;
1001
1002 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1);
1003 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA);
1004 dev_err_ratelimited(&gpu->pdev->dev,
1005 "CP | opcode error | possible opcode=0x%8.8X\n",
1006 val);
1007 }
1008
1009 if (status & A6XX_CP_INT_CP_UCODE_ERROR)
1010 dev_err_ratelimited(&gpu->pdev->dev,
1011 "CP ucode error interrupt\n");
1012
1013 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR)
1014 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n",
1015 gpu_read(gpu, REG_A6XX_CP_HW_FAULT));
1016
1017 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) {
1018 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS);
1019
1020 dev_err_ratelimited(&gpu->pdev->dev,
1021 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n",
1022 val & (1 << 20) ? "READ" : "WRITE",
1023 (val & 0x3ffff), val);
1024 }
1025
1026 if (status & A6XX_CP_INT_CP_AHB_ERROR)
1027 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n");
1028
1029 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR)
1030 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n");
1031
1032 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR)
1033 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n");
1034
1035 }
1036
a6xx_fault_detect_irq(struct msm_gpu * gpu)1037 static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
1038 {
1039 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1040 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1041 struct drm_device *dev = gpu->dev;
1042 struct msm_drm_private *priv = dev->dev_private;
1043 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
1044
1045 /*
1046 * Force the GPU to stay on until after we finish
1047 * collecting information
1048 */
1049 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);
1050
1051 DRM_DEV_ERROR(&gpu->pdev->dev,
1052 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",
1053 ring ? ring->id : -1, ring ? ring->seqno : 0,
1054 gpu_read(gpu, REG_A6XX_RBBM_STATUS),
1055 gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
1056 gpu_read(gpu, REG_A6XX_CP_RB_WPTR),
1057 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE, REG_A6XX_CP_IB1_BASE_HI),
1058 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),
1059 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI),
1060 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));
1061
1062 /* Turn off the hangcheck timer to keep it from bothering us */
1063 del_timer(&gpu->hangcheck_timer);
1064
1065 queue_work(priv->wq, &gpu->recover_work);
1066 }
1067
a6xx_irq(struct msm_gpu * gpu)1068 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
1069 {
1070 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS);
1071
1072 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status);
1073
1074 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
1075 a6xx_fault_detect_irq(gpu);
1076
1077 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR)
1078 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n");
1079
1080 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR)
1081 a6xx_cp_hw_err_irq(gpu);
1082
1083 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW)
1084 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n");
1085
1086 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW)
1087 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n");
1088
1089 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
1090 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
1091
1092 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
1093 msm_gpu_retire(gpu);
1094
1095 return IRQ_HANDLED;
1096 }
1097
a6xx_pm_resume(struct msm_gpu * gpu)1098 static int a6xx_pm_resume(struct msm_gpu *gpu)
1099 {
1100 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1101 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1102 int ret;
1103
1104 gpu->needs_hw_init = true;
1105
1106 trace_msm_gpu_resume(0);
1107
1108 ret = a6xx_gmu_resume(a6xx_gpu);
1109 if (ret)
1110 return ret;
1111
1112 msm_gpu_resume_devfreq(gpu);
1113
1114 return 0;
1115 }
1116
a6xx_pm_suspend(struct msm_gpu * gpu)1117 static int a6xx_pm_suspend(struct msm_gpu *gpu)
1118 {
1119 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1120 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1121 int i, ret;
1122
1123 trace_msm_gpu_suspend(0);
1124
1125 devfreq_suspend_device(gpu->devfreq.devfreq);
1126
1127 ret = a6xx_gmu_stop(a6xx_gpu);
1128 if (ret)
1129 return ret;
1130
1131 if (a6xx_gpu->shadow_bo)
1132 for (i = 0; i < gpu->nr_rings; i++)
1133 a6xx_gpu->shadow[i] = 0;
1134
1135 return 0;
1136 }
1137
a6xx_get_timestamp(struct msm_gpu * gpu,uint64_t * value)1138 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
1139 {
1140 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1141 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1142 static DEFINE_MUTEX(perfcounter_oob);
1143
1144 mutex_lock(&perfcounter_oob);
1145
1146 /* Force the GPU power on so we can read this register */
1147 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
1148
1149 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
1150 REG_A6XX_CP_ALWAYS_ON_COUNTER_HI);
1151
1152 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
1153 mutex_unlock(&perfcounter_oob);
1154 return 0;
1155 }
1156
a6xx_active_ring(struct msm_gpu * gpu)1157 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu)
1158 {
1159 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1160 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1161
1162 return a6xx_gpu->cur_ring;
1163 }
1164
a6xx_destroy(struct msm_gpu * gpu)1165 static void a6xx_destroy(struct msm_gpu *gpu)
1166 {
1167 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1168 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1169
1170 if (a6xx_gpu->sqe_bo) {
1171 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
1172 drm_gem_object_put(a6xx_gpu->sqe_bo);
1173 }
1174
1175 if (a6xx_gpu->shadow_bo) {
1176 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace);
1177 drm_gem_object_put(a6xx_gpu->shadow_bo);
1178 }
1179
1180 a6xx_gmu_remove(a6xx_gpu);
1181
1182 adreno_gpu_cleanup(adreno_gpu);
1183 kfree(a6xx_gpu);
1184 }
1185
a6xx_gpu_busy(struct msm_gpu * gpu)1186 static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
1187 {
1188 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1189 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1190 u64 busy_cycles, busy_time;
1191
1192
1193 /* Only read the gpu busy if the hardware is already active */
1194 if (pm_runtime_get_if_in_use(a6xx_gpu->gmu.dev) == 0)
1195 return 0;
1196
1197 busy_cycles = gmu_read64(&a6xx_gpu->gmu,
1198 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
1199 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H);
1200
1201 busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10;
1202 do_div(busy_time, 192);
1203
1204 gpu->devfreq.busy_cycles = busy_cycles;
1205
1206 pm_runtime_put(a6xx_gpu->gmu.dev);
1207
1208 if (WARN_ON(busy_time > ~0LU))
1209 return ~0LU;
1210
1211 return (unsigned long)busy_time;
1212 }
1213
1214 static struct msm_gem_address_space *
a6xx_create_private_address_space(struct msm_gpu * gpu)1215 a6xx_create_private_address_space(struct msm_gpu *gpu)
1216 {
1217 struct msm_mmu *mmu;
1218
1219 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);
1220
1221 if (IS_ERR(mmu))
1222 return ERR_CAST(mmu);
1223
1224 return msm_gem_address_space_create(mmu,
1225 "gpu", 0x100000000ULL, SZ_4G);
1226 }
1227
a6xx_get_rptr(struct msm_gpu * gpu,struct msm_ringbuffer * ring)1228 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
1229 {
1230 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1231 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1232
1233 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami)
1234 return a6xx_gpu->shadow[ring->id];
1235
1236 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR);
1237 }
1238
1239 static const struct adreno_gpu_funcs funcs = {
1240 .base = {
1241 .get_param = adreno_get_param,
1242 .hw_init = a6xx_hw_init,
1243 .pm_suspend = a6xx_pm_suspend,
1244 .pm_resume = a6xx_pm_resume,
1245 .recover = a6xx_recover,
1246 .submit = a6xx_submit,
1247 .active_ring = a6xx_active_ring,
1248 .irq = a6xx_irq,
1249 .destroy = a6xx_destroy,
1250 #if defined(CONFIG_DRM_MSM_GPU_STATE)
1251 .show = a6xx_show,
1252 #endif
1253 .gpu_busy = a6xx_gpu_busy,
1254 .gpu_get_freq = a6xx_gmu_get_freq,
1255 .gpu_set_freq = a6xx_gmu_set_freq,
1256 #if defined(CONFIG_DRM_MSM_GPU_STATE)
1257 .gpu_state_get = a6xx_gpu_state_get,
1258 .gpu_state_put = a6xx_gpu_state_put,
1259 #endif
1260 .create_address_space = adreno_iommu_create_address_space,
1261 .create_private_address_space = a6xx_create_private_address_space,
1262 .get_rptr = a6xx_get_rptr,
1263 },
1264 .get_timestamp = a6xx_get_timestamp,
1265 };
1266
a6xx_gpu_init(struct drm_device * dev)1267 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
1268 {
1269 struct msm_drm_private *priv = dev->dev_private;
1270 struct platform_device *pdev = priv->gpu_pdev;
1271 struct adreno_platform_config *config = pdev->dev.platform_data;
1272 const struct adreno_info *info;
1273 struct device_node *node;
1274 struct a6xx_gpu *a6xx_gpu;
1275 struct adreno_gpu *adreno_gpu;
1276 struct msm_gpu *gpu;
1277 int ret;
1278
1279 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL);
1280 if (!a6xx_gpu)
1281 return ERR_PTR(-ENOMEM);
1282
1283 adreno_gpu = &a6xx_gpu->base;
1284 gpu = &adreno_gpu->base;
1285
1286 adreno_gpu->registers = NULL;
1287
1288 /*
1289 * We need to know the platform type before calling into adreno_gpu_init
1290 * so that the hw_apriv flag can be correctly set. Snoop into the info
1291 * and grab the revision number
1292 */
1293 info = adreno_info(config->rev);
1294
1295 if (info && info->revn == 650)
1296 adreno_gpu->base.hw_apriv = true;
1297
1298 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
1299 if (ret) {
1300 a6xx_destroy(&(a6xx_gpu->base.base));
1301 return ERR_PTR(ret);
1302 }
1303
1304 /* Check if there is a GMU phandle and set it up */
1305 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);
1306
1307 /* FIXME: How do we gracefully handle this? */
1308 BUG_ON(!node);
1309
1310 ret = a6xx_gmu_init(a6xx_gpu, node);
1311 of_node_put(node);
1312 if (ret) {
1313 a6xx_destroy(&(a6xx_gpu->base.base));
1314 return ERR_PTR(ret);
1315 }
1316
1317 if (gpu->aspace)
1318 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
1319 a6xx_fault_handler);
1320
1321 return gpu;
1322 }
1323