1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013-2014 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
7 */
8
9 #include "adreno_gpu.h"
10
11 #define ANY_ID 0xff
12
13 bool hang_debug = false;
14 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
15 module_param_named(hang_debug, hang_debug, bool, 0600);
16
17 bool snapshot_debugbus = false;
18 MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)");
19 module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600);
20
21 static const struct adreno_info gpulist[] = {
22 {
23 .rev = ADRENO_REV(2, 0, 0, 0),
24 .revn = 200,
25 .name = "A200",
26 .fw = {
27 [ADRENO_FW_PM4] = "yamato_pm4.fw",
28 [ADRENO_FW_PFP] = "yamato_pfp.fw",
29 },
30 .gmem = SZ_256K,
31 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
32 .init = a2xx_gpu_init,
33 }, { /* a200 on i.mx51 has only 128kib gmem */
34 .rev = ADRENO_REV(2, 0, 0, 1),
35 .revn = 201,
36 .name = "A200",
37 .fw = {
38 [ADRENO_FW_PM4] = "yamato_pm4.fw",
39 [ADRENO_FW_PFP] = "yamato_pfp.fw",
40 },
41 .gmem = SZ_128K,
42 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
43 .init = a2xx_gpu_init,
44 }, {
45 .rev = ADRENO_REV(2, 2, 0, ANY_ID),
46 .revn = 220,
47 .name = "A220",
48 .fw = {
49 [ADRENO_FW_PM4] = "leia_pm4_470.fw",
50 [ADRENO_FW_PFP] = "leia_pfp_470.fw",
51 },
52 .gmem = SZ_512K,
53 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
54 .init = a2xx_gpu_init,
55 }, {
56 .rev = ADRENO_REV(3, 0, 5, ANY_ID),
57 .revn = 305,
58 .name = "A305",
59 .fw = {
60 [ADRENO_FW_PM4] = "a300_pm4.fw",
61 [ADRENO_FW_PFP] = "a300_pfp.fw",
62 },
63 .gmem = SZ_256K,
64 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
65 .init = a3xx_gpu_init,
66 }, {
67 .rev = ADRENO_REV(3, 0, 6, 0),
68 .revn = 307, /* because a305c is revn==306 */
69 .name = "A306",
70 .fw = {
71 [ADRENO_FW_PM4] = "a300_pm4.fw",
72 [ADRENO_FW_PFP] = "a300_pfp.fw",
73 },
74 .gmem = SZ_128K,
75 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
76 .init = a3xx_gpu_init,
77 }, {
78 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
79 .revn = 320,
80 .name = "A320",
81 .fw = {
82 [ADRENO_FW_PM4] = "a300_pm4.fw",
83 [ADRENO_FW_PFP] = "a300_pfp.fw",
84 },
85 .gmem = SZ_512K,
86 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
87 .init = a3xx_gpu_init,
88 }, {
89 .rev = ADRENO_REV(3, 3, 0, ANY_ID),
90 .revn = 330,
91 .name = "A330",
92 .fw = {
93 [ADRENO_FW_PM4] = "a330_pm4.fw",
94 [ADRENO_FW_PFP] = "a330_pfp.fw",
95 },
96 .gmem = SZ_1M,
97 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
98 .init = a3xx_gpu_init,
99 }, {
100 .rev = ADRENO_REV(4, 0, 5, ANY_ID),
101 .revn = 405,
102 .name = "A405",
103 .fw = {
104 [ADRENO_FW_PM4] = "a420_pm4.fw",
105 [ADRENO_FW_PFP] = "a420_pfp.fw",
106 },
107 .gmem = SZ_256K,
108 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
109 .init = a4xx_gpu_init,
110 }, {
111 .rev = ADRENO_REV(4, 2, 0, ANY_ID),
112 .revn = 420,
113 .name = "A420",
114 .fw = {
115 [ADRENO_FW_PM4] = "a420_pm4.fw",
116 [ADRENO_FW_PFP] = "a420_pfp.fw",
117 },
118 .gmem = (SZ_1M + SZ_512K),
119 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
120 .init = a4xx_gpu_init,
121 }, {
122 .rev = ADRENO_REV(4, 3, 0, ANY_ID),
123 .revn = 430,
124 .name = "A430",
125 .fw = {
126 [ADRENO_FW_PM4] = "a420_pm4.fw",
127 [ADRENO_FW_PFP] = "a420_pfp.fw",
128 },
129 .gmem = (SZ_1M + SZ_512K),
130 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
131 .init = a4xx_gpu_init,
132 }, {
133 .rev = ADRENO_REV(5, 1, 0, ANY_ID),
134 .revn = 510,
135 .name = "A510",
136 .fw = {
137 [ADRENO_FW_PM4] = "a530_pm4.fw",
138 [ADRENO_FW_PFP] = "a530_pfp.fw",
139 },
140 .gmem = SZ_256K,
141 /*
142 * Increase inactive period to 250 to avoid bouncing
143 * the GDSC which appears to make it grumpy
144 */
145 .inactive_period = 250,
146 .init = a5xx_gpu_init,
147 }, {
148 .rev = ADRENO_REV(5, 3, 0, 2),
149 .revn = 530,
150 .name = "A530",
151 .fw = {
152 [ADRENO_FW_PM4] = "a530_pm4.fw",
153 [ADRENO_FW_PFP] = "a530_pfp.fw",
154 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
155 },
156 .gmem = SZ_1M,
157 /*
158 * Increase inactive period to 250 to avoid bouncing
159 * the GDSC which appears to make it grumpy
160 */
161 .inactive_period = 250,
162 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
163 ADRENO_QUIRK_FAULT_DETECT_MASK,
164 .init = a5xx_gpu_init,
165 .zapfw = "a530_zap.mdt",
166 }, {
167 .rev = ADRENO_REV(5, 4, 0, 2),
168 .revn = 540,
169 .name = "A540",
170 .fw = {
171 [ADRENO_FW_PM4] = "a530_pm4.fw",
172 [ADRENO_FW_PFP] = "a530_pfp.fw",
173 [ADRENO_FW_GPMU] = "a540_gpmu.fw2",
174 },
175 .gmem = SZ_1M,
176 /*
177 * Increase inactive period to 250 to avoid bouncing
178 * the GDSC which appears to make it grumpy
179 */
180 .inactive_period = 250,
181 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
182 .init = a5xx_gpu_init,
183 .zapfw = "a540_zap.mdt",
184 }, {
185 .rev = ADRENO_REV(6, 1, 8, ANY_ID),
186 .revn = 618,
187 .name = "A618",
188 .fw = {
189 [ADRENO_FW_SQE] = "a630_sqe.fw",
190 [ADRENO_FW_GMU] = "a630_gmu.bin",
191 },
192 .gmem = SZ_512K,
193 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
194 .init = a6xx_gpu_init,
195 }, {
196 .rev = ADRENO_REV(6, 3, 0, ANY_ID),
197 .revn = 630,
198 .name = "A630",
199 .fw = {
200 [ADRENO_FW_SQE] = "a630_sqe.fw",
201 [ADRENO_FW_GMU] = "a630_gmu.bin",
202 },
203 .gmem = SZ_1M,
204 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
205 .init = a6xx_gpu_init,
206 .zapfw = "a630_zap.mdt",
207 .hwcg = a630_hwcg,
208 }, {
209 .rev = ADRENO_REV(6, 4, 0, ANY_ID),
210 .revn = 640,
211 .name = "A640",
212 .fw = {
213 [ADRENO_FW_SQE] = "a630_sqe.fw",
214 [ADRENO_FW_GMU] = "a640_gmu.bin",
215 },
216 .gmem = SZ_1M,
217 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
218 .init = a6xx_gpu_init,
219 .zapfw = "a640_zap.mdt",
220 .hwcg = a640_hwcg,
221 }, {
222 .rev = ADRENO_REV(6, 5, 0, ANY_ID),
223 .revn = 650,
224 .name = "A650",
225 .fw = {
226 [ADRENO_FW_SQE] = "a650_sqe.fw",
227 [ADRENO_FW_GMU] = "a650_gmu.bin",
228 },
229 .gmem = SZ_1M + SZ_128K,
230 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
231 .init = a6xx_gpu_init,
232 .zapfw = "a650_zap.mdt",
233 .hwcg = a650_hwcg,
234 },
235 };
236
237 MODULE_FIRMWARE("qcom/a300_pm4.fw");
238 MODULE_FIRMWARE("qcom/a300_pfp.fw");
239 MODULE_FIRMWARE("qcom/a330_pm4.fw");
240 MODULE_FIRMWARE("qcom/a330_pfp.fw");
241 MODULE_FIRMWARE("qcom/a420_pm4.fw");
242 MODULE_FIRMWARE("qcom/a420_pfp.fw");
243 MODULE_FIRMWARE("qcom/a530_pm4.fw");
244 MODULE_FIRMWARE("qcom/a530_pfp.fw");
245 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
246 MODULE_FIRMWARE("qcom/a530_zap.mdt");
247 MODULE_FIRMWARE("qcom/a530_zap.b00");
248 MODULE_FIRMWARE("qcom/a530_zap.b01");
249 MODULE_FIRMWARE("qcom/a530_zap.b02");
250 MODULE_FIRMWARE("qcom/a630_sqe.fw");
251 MODULE_FIRMWARE("qcom/a630_gmu.bin");
252 MODULE_FIRMWARE("qcom/a630_zap.mbn");
253
_rev_match(uint8_t entry,uint8_t id)254 static inline bool _rev_match(uint8_t entry, uint8_t id)
255 {
256 return (entry == ANY_ID) || (entry == id);
257 }
258
adreno_info(struct adreno_rev rev)259 const struct adreno_info *adreno_info(struct adreno_rev rev)
260 {
261 int i;
262
263 /* identify gpu: */
264 for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
265 const struct adreno_info *info = &gpulist[i];
266 if (_rev_match(info->rev.core, rev.core) &&
267 _rev_match(info->rev.major, rev.major) &&
268 _rev_match(info->rev.minor, rev.minor) &&
269 _rev_match(info->rev.patchid, rev.patchid))
270 return info;
271 }
272
273 return NULL;
274 }
275
adreno_load_gpu(struct drm_device * dev)276 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
277 {
278 struct msm_drm_private *priv = dev->dev_private;
279 struct platform_device *pdev = priv->gpu_pdev;
280 struct msm_gpu *gpu = NULL;
281 struct adreno_gpu *adreno_gpu;
282 int ret;
283
284 if (pdev)
285 gpu = dev_to_gpu(&pdev->dev);
286
287 if (!gpu) {
288 dev_err_once(dev->dev, "no GPU device was found\n");
289 return NULL;
290 }
291
292 adreno_gpu = to_adreno_gpu(gpu);
293
294 /*
295 * The number one reason for HW init to fail is if the firmware isn't
296 * loaded yet. Try that first and don't bother continuing on
297 * otherwise
298 */
299
300 ret = adreno_load_fw(adreno_gpu);
301 if (ret)
302 return NULL;
303
304 /*
305 * Now that we have firmware loaded, and are ready to begin
306 * booting the gpu, go ahead and enable runpm:
307 */
308 pm_runtime_enable(&pdev->dev);
309
310 ret = pm_runtime_get_sync(&pdev->dev);
311 if (ret < 0) {
312 pm_runtime_put_sync(&pdev->dev);
313 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret);
314 return NULL;
315 }
316
317 mutex_lock(&dev->struct_mutex);
318 ret = msm_gpu_hw_init(gpu);
319 mutex_unlock(&dev->struct_mutex);
320 pm_runtime_put_autosuspend(&pdev->dev);
321 if (ret) {
322 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret);
323 return NULL;
324 }
325
326 #ifdef CONFIG_DEBUG_FS
327 if (gpu->funcs->debugfs_init) {
328 gpu->funcs->debugfs_init(gpu, dev->primary);
329 gpu->funcs->debugfs_init(gpu, dev->render);
330 }
331 #endif
332
333 return gpu;
334 }
335
set_gpu_pdev(struct drm_device * dev,struct platform_device * pdev)336 static void set_gpu_pdev(struct drm_device *dev,
337 struct platform_device *pdev)
338 {
339 struct msm_drm_private *priv = dev->dev_private;
340 priv->gpu_pdev = pdev;
341 }
342
find_chipid(struct device * dev,struct adreno_rev * rev)343 static int find_chipid(struct device *dev, struct adreno_rev *rev)
344 {
345 struct device_node *node = dev->of_node;
346 const char *compat;
347 int ret;
348 u32 chipid;
349
350 /* first search the compat strings for qcom,adreno-XYZ.W: */
351 ret = of_property_read_string_index(node, "compatible", 0, &compat);
352 if (ret == 0) {
353 unsigned int r, patch;
354
355 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 ||
356 sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) {
357 rev->core = r / 100;
358 r %= 100;
359 rev->major = r / 10;
360 r %= 10;
361 rev->minor = r;
362 rev->patchid = patch;
363
364 return 0;
365 }
366 }
367
368 /* and if that fails, fall back to legacy "qcom,chipid" property: */
369 ret = of_property_read_u32(node, "qcom,chipid", &chipid);
370 if (ret) {
371 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret);
372 return ret;
373 }
374
375 rev->core = (chipid >> 24) & 0xff;
376 rev->major = (chipid >> 16) & 0xff;
377 rev->minor = (chipid >> 8) & 0xff;
378 rev->patchid = (chipid & 0xff);
379
380 dev_warn(dev, "Using legacy qcom,chipid binding!\n");
381 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
382 rev->core, rev->major, rev->minor, rev->patchid);
383
384 return 0;
385 }
386
adreno_bind(struct device * dev,struct device * master,void * data)387 static int adreno_bind(struct device *dev, struct device *master, void *data)
388 {
389 static struct adreno_platform_config config = {};
390 const struct adreno_info *info;
391 struct drm_device *drm = dev_get_drvdata(master);
392 struct msm_drm_private *priv = drm->dev_private;
393 struct msm_gpu *gpu;
394 int ret;
395
396 ret = find_chipid(dev, &config.rev);
397 if (ret)
398 return ret;
399
400 dev->platform_data = &config;
401 set_gpu_pdev(drm, to_platform_device(dev));
402
403 info = adreno_info(config.rev);
404
405 if (!info) {
406 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
407 config.rev.core, config.rev.major,
408 config.rev.minor, config.rev.patchid);
409 return -ENXIO;
410 }
411
412 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
413 config.rev.minor, config.rev.patchid);
414
415 priv->is_a2xx = config.rev.core == 2;
416
417 gpu = info->init(drm);
418 if (IS_ERR(gpu)) {
419 dev_warn(drm->dev, "failed to load adreno gpu\n");
420 return PTR_ERR(gpu);
421 }
422
423 return 0;
424 }
425
adreno_unbind(struct device * dev,struct device * master,void * data)426 static void adreno_unbind(struct device *dev, struct device *master,
427 void *data)
428 {
429 struct msm_gpu *gpu = dev_to_gpu(dev);
430
431 pm_runtime_force_suspend(dev);
432 gpu->funcs->destroy(gpu);
433
434 set_gpu_pdev(dev_get_drvdata(master), NULL);
435 }
436
437 static const struct component_ops a3xx_ops = {
438 .bind = adreno_bind,
439 .unbind = adreno_unbind,
440 };
441
adreno_device_register_headless(void)442 static void adreno_device_register_headless(void)
443 {
444 /* on imx5, we don't have a top-level mdp/dpu node
445 * this creates a dummy node for the driver for that case
446 */
447 struct platform_device_info dummy_info = {
448 .parent = NULL,
449 .name = "msm",
450 .id = -1,
451 .res = NULL,
452 .num_res = 0,
453 .data = NULL,
454 .size_data = 0,
455 .dma_mask = ~0,
456 };
457 platform_device_register_full(&dummy_info);
458 }
459
adreno_probe(struct platform_device * pdev)460 static int adreno_probe(struct platform_device *pdev)
461 {
462
463 int ret;
464
465 ret = component_add(&pdev->dev, &a3xx_ops);
466 if (ret)
467 return ret;
468
469 if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon"))
470 adreno_device_register_headless();
471
472 return 0;
473 }
474
adreno_remove(struct platform_device * pdev)475 static int adreno_remove(struct platform_device *pdev)
476 {
477 component_del(&pdev->dev, &a3xx_ops);
478 return 0;
479 }
480
481 static const struct of_device_id dt_match[] = {
482 { .compatible = "qcom,adreno" },
483 { .compatible = "qcom,adreno-3xx" },
484 /* for compatibility with imx5 gpu: */
485 { .compatible = "amd,imageon" },
486 /* for backwards compat w/ downstream kgsl DT files: */
487 { .compatible = "qcom,kgsl-3d0" },
488 {}
489 };
490
491 #ifdef CONFIG_PM
adreno_resume(struct device * dev)492 static int adreno_resume(struct device *dev)
493 {
494 struct msm_gpu *gpu = dev_to_gpu(dev);
495
496 return gpu->funcs->pm_resume(gpu);
497 }
498
adreno_suspend(struct device * dev)499 static int adreno_suspend(struct device *dev)
500 {
501 struct msm_gpu *gpu = dev_to_gpu(dev);
502
503 return gpu->funcs->pm_suspend(gpu);
504 }
505 #endif
506
507 static const struct dev_pm_ops adreno_pm_ops = {
508 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
509 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
510 };
511
512 static struct platform_driver adreno_driver = {
513 .probe = adreno_probe,
514 .remove = adreno_remove,
515 .driver = {
516 .name = "adreno",
517 .of_match_table = dt_match,
518 .pm = &adreno_pm_ops,
519 },
520 };
521
adreno_register(void)522 void __init adreno_register(void)
523 {
524 platform_driver_register(&adreno_driver);
525 }
526
adreno_unregister(void)527 void __exit adreno_unregister(void)
528 {
529 platform_driver_unregister(&adreno_driver);
530 }
531