1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Contains CPU specific errata definitions
4 *
5 * Copyright (C) 2014 ARM Ltd.
6 */
7
8 #include <linux/arm-smccc.h>
9 #include <linux/types.h>
10 #include <linux/cpu.h>
11 #include <asm/cpu.h>
12 #include <asm/cputype.h>
13 #include <asm/cpufeature.h>
14 #include <asm/kvm_asm.h>
15 #include <asm/smp_plat.h>
16
17 static bool __maybe_unused
is_affected_midr_range(const struct arm64_cpu_capabilities * entry,int scope)18 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
19 {
20 const struct arm64_midr_revidr *fix;
21 u32 midr = read_cpuid_id(), revidr;
22
23 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
24 if (!is_midr_in_range(midr, &entry->midr_range))
25 return false;
26
27 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
28 revidr = read_cpuid(REVIDR_EL1);
29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
31 return false;
32
33 return true;
34 }
35
36 static bool __maybe_unused
is_affected_midr_range_list(const struct arm64_cpu_capabilities * entry,int scope)37 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
38 int scope)
39 {
40 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
42 }
43
44 static bool __maybe_unused
is_kryo_midr(const struct arm64_cpu_capabilities * entry,int scope)45 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
46 {
47 u32 model;
48
49 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
50
51 model = read_cpuid_id();
52 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
53 MIDR_ARCHITECTURE_MASK;
54
55 return model == entry->midr_range.model;
56 }
57
58 static bool
has_mismatched_cache_type(const struct arm64_cpu_capabilities * entry,int scope)59 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
60 int scope)
61 {
62 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
63 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
64 u64 ctr_raw, ctr_real;
65
66 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
67
68 /*
69 * We want to make sure that all the CPUs in the system expose
70 * a consistent CTR_EL0 to make sure that applications behaves
71 * correctly with migration.
72 *
73 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
74 *
75 * 1) It is safe if the system doesn't support IDC, as CPU anyway
76 * reports IDC = 0, consistent with the rest.
77 *
78 * 2) If the system has IDC, it is still safe as we trap CTR_EL0
79 * access on this CPU via the ARM64_HAS_CACHE_IDC capability.
80 *
81 * So, we need to make sure either the raw CTR_EL0 or the effective
82 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
83 */
84 ctr_raw = read_cpuid_cachetype() & mask;
85 ctr_real = read_cpuid_effective_cachetype() & mask;
86
87 return (ctr_real != sys) && (ctr_raw != sys);
88 }
89
90 static void
cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities * cap)91 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
92 {
93 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
94 bool enable_uct_trap = false;
95
96 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
97 if ((read_cpuid_cachetype() & mask) !=
98 (arm64_ftr_reg_ctrel0.sys_val & mask))
99 enable_uct_trap = true;
100
101 /* ... or if the system is affected by an erratum */
102 if (cap->capability == ARM64_WORKAROUND_1542419)
103 enable_uct_trap = true;
104
105 if (enable_uct_trap)
106 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
107 }
108
109 #ifdef CONFIG_ARM64_ERRATUM_1463225
110 DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
111
112 static bool
has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities * entry,int scope)113 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
114 int scope)
115 {
116 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
117 }
118 #endif
119
120 static void __maybe_unused
cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities * __unused)121 cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
122 {
123 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
124 }
125
126 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
127 .matches = is_affected_midr_range, \
128 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
129
130 #define CAP_MIDR_ALL_VERSIONS(model) \
131 .matches = is_affected_midr_range, \
132 .midr_range = MIDR_ALL_VERSIONS(model)
133
134 #define MIDR_FIXED(rev, revidr_mask) \
135 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
136
137 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
138 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
139 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
140
141 #define CAP_MIDR_RANGE_LIST(list) \
142 .matches = is_affected_midr_range_list, \
143 .midr_range_list = list
144
145 /* Errata affecting a range of revisions of given model variant */
146 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
147 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
148
149 /* Errata affecting a single variant/revision of a model */
150 #define ERRATA_MIDR_REV(model, var, rev) \
151 ERRATA_MIDR_RANGE(model, var, rev, var, rev)
152
153 /* Errata affecting all variants/revisions of a given a model */
154 #define ERRATA_MIDR_ALL_VERSIONS(model) \
155 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
156 CAP_MIDR_ALL_VERSIONS(model)
157
158 /* Errata affecting a list of midr ranges, with same work around */
159 #define ERRATA_MIDR_RANGE_LIST(midr_list) \
160 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
161 CAP_MIDR_RANGE_LIST(midr_list)
162
163 static const __maybe_unused struct midr_range tx2_family_cpus[] = {
164 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
165 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
166 {},
167 };
168
169 static bool __maybe_unused
needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities * entry,int scope)170 needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
171 int scope)
172 {
173 int i;
174
175 if (!is_affected_midr_range_list(entry, scope) ||
176 !is_hyp_mode_available())
177 return false;
178
179 for_each_possible_cpu(i) {
180 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
181 return true;
182 }
183
184 return false;
185 }
186
187 static bool __maybe_unused
has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities * entry,int scope)188 has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
189 int scope)
190 {
191 u32 midr = read_cpuid_id();
192 bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
193 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
194
195 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
196 return is_midr_in_range(midr, &range) && has_dic;
197 }
198
199 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
200 static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
201 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
202 {
203 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
204 },
205 {
206 .midr_range.model = MIDR_QCOM_KRYO,
207 .matches = is_kryo_midr,
208 },
209 #endif
210 #ifdef CONFIG_ARM64_ERRATUM_1286807
211 {
212 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
213 },
214 {
215 /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */
216 ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
217 },
218 #endif
219 {},
220 };
221 #endif
222
223 #ifdef CONFIG_CAVIUM_ERRATUM_27456
224 const struct midr_range cavium_erratum_27456_cpus[] = {
225 /* Cavium ThunderX, T88 pass 1.x - 2.1 */
226 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
227 /* Cavium ThunderX, T81 pass 1.0 */
228 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
229 {},
230 };
231 #endif
232
233 #ifdef CONFIG_CAVIUM_ERRATUM_30115
234 static const struct midr_range cavium_erratum_30115_cpus[] = {
235 /* Cavium ThunderX, T88 pass 1.x - 2.2 */
236 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
237 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
238 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
239 /* Cavium ThunderX, T83 pass 1.0 */
240 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
241 {},
242 };
243 #endif
244
245 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
246 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
247 {
248 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
249 },
250 {
251 .midr_range.model = MIDR_QCOM_KRYO,
252 .matches = is_kryo_midr,
253 },
254 {},
255 };
256 #endif
257
258 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
259 static const struct midr_range workaround_clean_cache[] = {
260 #if defined(CONFIG_ARM64_ERRATUM_826319) || \
261 defined(CONFIG_ARM64_ERRATUM_827319) || \
262 defined(CONFIG_ARM64_ERRATUM_824069)
263 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
264 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
265 #endif
266 #ifdef CONFIG_ARM64_ERRATUM_819472
267 /* Cortex-A53 r0p[01] : ARM errata 819472 */
268 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
269 #endif
270 {},
271 };
272 #endif
273
274 #ifdef CONFIG_ARM64_ERRATUM_1418040
275 /*
276 * - 1188873 affects r0p0 to r2p0
277 * - 1418040 affects r0p0 to r3p1
278 */
279 static const struct midr_range erratum_1418040_list[] = {
280 /* Cortex-A76 r0p0 to r3p1 */
281 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
282 /* Neoverse-N1 r0p0 to r3p1 */
283 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
284 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
285 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
286 {},
287 };
288 #endif
289
290 #ifdef CONFIG_ARM64_ERRATUM_845719
291 static const struct midr_range erratum_845719_list[] = {
292 /* Cortex-A53 r0p[01234] */
293 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
294 /* Brahma-B53 r0p[0] */
295 MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
296 /* Kryo2XX Silver rAp4 */
297 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4),
298 {},
299 };
300 #endif
301
302 #ifdef CONFIG_ARM64_ERRATUM_843419
303 static const struct arm64_cpu_capabilities erratum_843419_list[] = {
304 {
305 /* Cortex-A53 r0p[01234] */
306 .matches = is_affected_midr_range,
307 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
308 MIDR_FIXED(0x4, BIT(8)),
309 },
310 {
311 /* Brahma-B53 r0p[0] */
312 .matches = is_affected_midr_range,
313 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
314 },
315 {},
316 };
317 #endif
318
319 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
320 static const struct midr_range erratum_speculative_at_list[] = {
321 #ifdef CONFIG_ARM64_ERRATUM_1165522
322 /* Cortex A76 r0p0 to r2p0 */
323 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
324 #endif
325 #ifdef CONFIG_ARM64_ERRATUM_1319367
326 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
327 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
328 #endif
329 #ifdef CONFIG_ARM64_ERRATUM_1530923
330 /* Cortex A55 r0p0 to r2p0 */
331 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
332 /* Kryo4xx Silver (rdpe => r1p0) */
333 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
334 #endif
335 {},
336 };
337 #endif
338
339 #ifdef CONFIG_ARM64_ERRATUM_1463225
340 static const struct midr_range erratum_1463225[] = {
341 /* Cortex-A76 r0p0 - r3p1 */
342 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
343 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
344 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
345 {},
346 };
347 #endif
348
349 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
350 static const struct midr_range tsb_flush_fail_cpus[] = {
351 #ifdef CONFIG_ARM64_ERRATUM_2067961
352 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
353 #endif
354 #ifdef CONFIG_ARM64_ERRATUM_2054223
355 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
356 #endif
357 {},
358 };
359 #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */
360
361 #ifdef CONFIG_ARM64_ERRATUM_1742098
362 static struct midr_range broken_aarch32_aes[] = {
363 MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf),
364 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
365 {},
366 };
367 #endif
368
369 const struct arm64_cpu_capabilities arm64_errata[] = {
370 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
371 {
372 .desc = "ARM errata 826319, 827319, 824069, or 819472",
373 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
374 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
375 .cpu_enable = cpu_enable_cache_maint_trap,
376 },
377 #endif
378 #ifdef CONFIG_ARM64_ERRATUM_832075
379 {
380 /* Cortex-A57 r0p0 - r1p2 */
381 .desc = "ARM erratum 832075",
382 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
383 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
384 0, 0,
385 1, 2),
386 },
387 #endif
388 #ifdef CONFIG_ARM64_ERRATUM_834220
389 {
390 /* Cortex-A57 r0p0 - r1p2 */
391 .desc = "ARM erratum 834220",
392 .capability = ARM64_WORKAROUND_834220,
393 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
394 0, 0,
395 1, 2),
396 },
397 #endif
398 #ifdef CONFIG_ARM64_ERRATUM_843419
399 {
400 .desc = "ARM erratum 843419",
401 .capability = ARM64_WORKAROUND_843419,
402 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
403 .matches = cpucap_multi_entry_cap_matches,
404 .match_list = erratum_843419_list,
405 },
406 #endif
407 #ifdef CONFIG_ARM64_ERRATUM_845719
408 {
409 .desc = "ARM erratum 845719",
410 .capability = ARM64_WORKAROUND_845719,
411 ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
412 },
413 #endif
414 #ifdef CONFIG_CAVIUM_ERRATUM_23154
415 {
416 /* Cavium ThunderX, pass 1.x */
417 .desc = "Cavium erratum 23154",
418 .capability = ARM64_WORKAROUND_CAVIUM_23154,
419 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
420 },
421 #endif
422 #ifdef CONFIG_CAVIUM_ERRATUM_27456
423 {
424 .desc = "Cavium erratum 27456",
425 .capability = ARM64_WORKAROUND_CAVIUM_27456,
426 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
427 },
428 #endif
429 #ifdef CONFIG_CAVIUM_ERRATUM_30115
430 {
431 .desc = "Cavium erratum 30115",
432 .capability = ARM64_WORKAROUND_CAVIUM_30115,
433 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
434 },
435 #endif
436 {
437 .desc = "Mismatched cache type (CTR_EL0)",
438 .capability = ARM64_MISMATCHED_CACHE_TYPE,
439 .matches = has_mismatched_cache_type,
440 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
441 .cpu_enable = cpu_enable_trap_ctr_access,
442 },
443 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
444 {
445 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
446 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
447 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
448 .matches = cpucap_multi_entry_cap_matches,
449 .match_list = qcom_erratum_1003_list,
450 },
451 #endif
452 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
453 {
454 .desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
455 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
456 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
457 .matches = cpucap_multi_entry_cap_matches,
458 .match_list = arm64_repeat_tlbi_list,
459 },
460 #endif
461 #ifdef CONFIG_ARM64_ERRATUM_858921
462 {
463 /* Cortex-A73 all versions */
464 .desc = "ARM erratum 858921",
465 .capability = ARM64_WORKAROUND_858921,
466 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
467 },
468 #endif
469 {
470 .desc = "Spectre-v2",
471 .capability = ARM64_SPECTRE_V2,
472 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
473 .matches = has_spectre_v2,
474 .cpu_enable = spectre_v2_enable_mitigation,
475 },
476 #ifdef CONFIG_RANDOMIZE_BASE
477 {
478 /* Must come after the Spectre-v2 entry */
479 .desc = "Spectre-v3a",
480 .capability = ARM64_SPECTRE_V3A,
481 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
482 .matches = has_spectre_v3a,
483 .cpu_enable = spectre_v3a_enable_mitigation,
484 },
485 #endif
486 {
487 .desc = "Spectre-v4",
488 .capability = ARM64_SPECTRE_V4,
489 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
490 .matches = has_spectre_v4,
491 .cpu_enable = spectre_v4_enable_mitigation,
492 },
493 {
494 .desc = "Spectre-BHB",
495 .capability = ARM64_SPECTRE_BHB,
496 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
497 .matches = is_spectre_bhb_affected,
498 .cpu_enable = spectre_bhb_enable_mitigation,
499 },
500 #ifdef CONFIG_ARM64_ERRATUM_1418040
501 {
502 .desc = "ARM erratum 1418040",
503 .capability = ARM64_WORKAROUND_1418040,
504 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
505 /*
506 * We need to allow affected CPUs to come in late, but
507 * also need the non-affected CPUs to be able to come
508 * in at any point in time. Wonderful.
509 */
510 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
511 },
512 #endif
513 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
514 {
515 .desc = "ARM errata 1165522, 1319367, or 1530923",
516 .capability = ARM64_WORKAROUND_SPECULATIVE_AT,
517 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
518 },
519 #endif
520 #ifdef CONFIG_ARM64_ERRATUM_1463225
521 {
522 .desc = "ARM erratum 1463225",
523 .capability = ARM64_WORKAROUND_1463225,
524 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
525 .matches = has_cortex_a76_erratum_1463225,
526 .midr_range_list = erratum_1463225,
527 },
528 #endif
529 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
530 {
531 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
532 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
533 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
534 .matches = needs_tx2_tvm_workaround,
535 },
536 {
537 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
538 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
539 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
540 },
541 #endif
542 #ifdef CONFIG_ARM64_ERRATUM_1542419
543 {
544 /* we depend on the firmware portion for correctness */
545 .desc = "ARM erratum 1542419 (kernel portion)",
546 .capability = ARM64_WORKAROUND_1542419,
547 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
548 .matches = has_neoverse_n1_erratum_1542419,
549 .cpu_enable = cpu_enable_trap_ctr_access,
550 },
551 #endif
552 #ifdef CONFIG_ARM64_ERRATUM_1508412
553 {
554 /* we depend on the firmware portion for correctness */
555 .desc = "ARM erratum 1508412 (kernel portion)",
556 .capability = ARM64_WORKAROUND_1508412,
557 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77,
558 0, 0,
559 1, 0),
560 },
561 #endif
562 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
563 {
564 .desc = "ARM erratum 2067961 or 2054223",
565 .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE,
566 ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus),
567 },
568 #endif
569 #ifdef CONFIG_ARM64_ERRATUM_2457168
570 {
571 .desc = "ARM erratum 2457168",
572 .capability = ARM64_WORKAROUND_2457168,
573 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
574 /* Cortex-A510 r0p0-r1p1 */
575 CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1)
576 },
577 #endif
578 #ifdef CONFIG_ARM64_ERRATUM_1742098
579 {
580 .desc = "ARM erratum 1742098",
581 .capability = ARM64_WORKAROUND_1742098,
582 CAP_MIDR_RANGE_LIST(broken_aarch32_aes),
583 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
584 },
585 #endif
586 {
587 }
588 };
589