1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
23 u32 queues, bool drop);
24
ath9k_parse_mpdudensity(u8 mpdudensity)25 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
26 {
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58 }
59
ath9k_has_pending_frames(struct ath_softc * sc,struct ath_txq * txq,bool sw_pending)60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
61 bool sw_pending)
62 {
63 bool pending = false;
64
65 spin_lock_bh(&txq->axq_lock);
66
67 if (txq->axq_depth) {
68 pending = true;
69 goto out;
70 }
71
72 if (!sw_pending)
73 goto out;
74
75 if (txq->mac80211_qnum >= 0) {
76 struct ath_acq *acq;
77
78 acq = &sc->cur_chan->acq[txq->mac80211_qnum];
79 if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old))
80 pending = true;
81 }
82 out:
83 spin_unlock_bh(&txq->axq_lock);
84 return pending;
85 }
86
ath9k_setpower(struct ath_softc * sc,enum ath9k_power_mode mode)87 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
88 {
89 unsigned long flags;
90 bool ret;
91
92 spin_lock_irqsave(&sc->sc_pm_lock, flags);
93 ret = ath9k_hw_setpower(sc->sc_ah, mode);
94 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
95
96 return ret;
97 }
98
ath_ps_full_sleep(struct timer_list * t)99 void ath_ps_full_sleep(struct timer_list *t)
100 {
101 struct ath_softc *sc = from_timer(sc, t, sleep_timer);
102 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
103 unsigned long flags;
104 bool reset;
105
106 spin_lock_irqsave(&common->cc_lock, flags);
107 ath_hw_cycle_counters_update(common);
108 spin_unlock_irqrestore(&common->cc_lock, flags);
109
110 ath9k_hw_setrxabort(sc->sc_ah, 1);
111 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
112
113 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
114 }
115
ath9k_ps_wakeup(struct ath_softc * sc)116 void ath9k_ps_wakeup(struct ath_softc *sc)
117 {
118 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
119 unsigned long flags;
120 enum ath9k_power_mode power_mode;
121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (++sc->ps_usecount != 1)
124 goto unlock;
125
126 del_timer_sync(&sc->sleep_timer);
127 power_mode = sc->sc_ah->power_mode;
128 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
129
130 /*
131 * While the hardware is asleep, the cycle counters contain no
132 * useful data. Better clear them now so that they don't mess up
133 * survey data results.
134 */
135 if (power_mode != ATH9K_PM_AWAKE) {
136 spin_lock(&common->cc_lock);
137 ath_hw_cycle_counters_update(common);
138 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
139 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
140 spin_unlock(&common->cc_lock);
141 }
142
143 unlock:
144 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
145 }
146
ath9k_ps_restore(struct ath_softc * sc)147 void ath9k_ps_restore(struct ath_softc *sc)
148 {
149 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
150 enum ath9k_power_mode mode;
151 unsigned long flags;
152
153 spin_lock_irqsave(&sc->sc_pm_lock, flags);
154 if (--sc->ps_usecount != 0)
155 goto unlock;
156
157 if (sc->ps_idle) {
158 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
159 goto unlock;
160 }
161
162 if (sc->ps_enabled &&
163 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
164 PS_WAIT_FOR_CAB |
165 PS_WAIT_FOR_PSPOLL_DATA |
166 PS_WAIT_FOR_TX_ACK |
167 PS_WAIT_FOR_ANI))) {
168 mode = ATH9K_PM_NETWORK_SLEEP;
169 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
170 ath9k_btcoex_stop_gen_timer(sc);
171 } else {
172 goto unlock;
173 }
174
175 spin_lock(&common->cc_lock);
176 ath_hw_cycle_counters_update(common);
177 spin_unlock(&common->cc_lock);
178
179 ath9k_hw_setpower(sc->sc_ah, mode);
180
181 unlock:
182 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
183 }
184
__ath_cancel_work(struct ath_softc * sc)185 static void __ath_cancel_work(struct ath_softc *sc)
186 {
187 cancel_work_sync(&sc->paprd_work);
188 cancel_delayed_work_sync(&sc->hw_check_work);
189 cancel_delayed_work_sync(&sc->hw_pll_work);
190
191 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
192 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
193 cancel_work_sync(&sc->mci_work);
194 #endif
195 }
196
ath_cancel_work(struct ath_softc * sc)197 void ath_cancel_work(struct ath_softc *sc)
198 {
199 __ath_cancel_work(sc);
200 cancel_work_sync(&sc->hw_reset_work);
201 }
202
ath_restart_work(struct ath_softc * sc)203 void ath_restart_work(struct ath_softc *sc)
204 {
205 ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work,
206 msecs_to_jiffies(ATH_HW_CHECK_POLL_INT));
207
208 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
209 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
210 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
211
212 ath_start_ani(sc);
213 }
214
ath_prepare_reset(struct ath_softc * sc)215 static bool ath_prepare_reset(struct ath_softc *sc)
216 {
217 struct ath_hw *ah = sc->sc_ah;
218 bool ret = true;
219
220 ieee80211_stop_queues(sc->hw);
221 ath_stop_ani(sc);
222 ath9k_hw_disable_interrupts(ah);
223
224 if (AR_SREV_9300_20_OR_LATER(ah)) {
225 ret &= ath_stoprecv(sc);
226 ret &= ath_drain_all_txq(sc);
227 } else {
228 ret &= ath_drain_all_txq(sc);
229 ret &= ath_stoprecv(sc);
230 }
231
232 return ret;
233 }
234
ath_complete_reset(struct ath_softc * sc,bool start)235 static bool ath_complete_reset(struct ath_softc *sc, bool start)
236 {
237 struct ath_hw *ah = sc->sc_ah;
238 struct ath_common *common = ath9k_hw_common(ah);
239 unsigned long flags;
240
241 ath9k_calculate_summary_state(sc, sc->cur_chan);
242 ath_startrecv(sc);
243 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
244 sc->cur_chan->txpower,
245 &sc->cur_chan->cur_txpower);
246 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
247
248 if (!sc->cur_chan->offchannel && start) {
249 /* restore per chanctx TSF timer */
250 if (sc->cur_chan->tsf_val) {
251 u32 offset;
252
253 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
254 NULL);
255 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
256 }
257
258
259 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
260 goto work;
261
262 if (ah->opmode == NL80211_IFTYPE_STATION &&
263 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
264 spin_lock_irqsave(&sc->sc_pm_lock, flags);
265 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
266 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
267 } else {
268 ath9k_set_beacon(sc);
269 }
270 work:
271 ath_restart_work(sc);
272 ath_txq_schedule_all(sc);
273 }
274
275 sc->gtt_cnt = 0;
276
277 ath9k_hw_set_interrupts(ah);
278 ath9k_hw_enable_interrupts(ah);
279 ieee80211_wake_queues(sc->hw);
280 ath9k_p2p_ps_timer(sc);
281
282 return true;
283 }
284
ath_reset_internal(struct ath_softc * sc,struct ath9k_channel * hchan)285 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
286 {
287 struct ath_hw *ah = sc->sc_ah;
288 struct ath_common *common = ath9k_hw_common(ah);
289 struct ath9k_hw_cal_data *caldata = NULL;
290 bool fastcc = true;
291 int r;
292
293 __ath_cancel_work(sc);
294
295 disable_irq(sc->irq);
296 tasklet_disable(&sc->intr_tq);
297 tasklet_disable(&sc->bcon_tasklet);
298 spin_lock_bh(&sc->sc_pcu_lock);
299
300 if (!sc->cur_chan->offchannel) {
301 fastcc = false;
302 caldata = &sc->cur_chan->caldata;
303 }
304
305 if (!hchan) {
306 fastcc = false;
307 hchan = ah->curchan;
308 }
309
310 if (!hchan) {
311 fastcc = false;
312 hchan = ath9k_cmn_get_channel(sc->hw, ah, &sc->cur_chan->chandef);
313 }
314
315 if (!ath_prepare_reset(sc))
316 fastcc = false;
317
318 if (ath9k_is_chanctx_enabled())
319 fastcc = false;
320
321 spin_lock_bh(&sc->chan_lock);
322 sc->cur_chandef = sc->cur_chan->chandef;
323 spin_unlock_bh(&sc->chan_lock);
324
325 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
326 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
327
328 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
329 if (r) {
330 ath_err(common,
331 "Unable to reset channel, reset status %d\n", r);
332
333 ath9k_hw_enable_interrupts(ah);
334 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
335
336 goto out;
337 }
338
339 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
340 sc->cur_chan->offchannel)
341 ath9k_mci_set_txpower(sc, true, false);
342
343 if (!ath_complete_reset(sc, true))
344 r = -EIO;
345
346 out:
347 enable_irq(sc->irq);
348 spin_unlock_bh(&sc->sc_pcu_lock);
349 tasklet_enable(&sc->bcon_tasklet);
350 tasklet_enable(&sc->intr_tq);
351
352 return r;
353 }
354
ath_node_attach(struct ath_softc * sc,struct ieee80211_sta * sta,struct ieee80211_vif * vif)355 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
356 struct ieee80211_vif *vif)
357 {
358 struct ath_node *an;
359 an = (struct ath_node *)sta->drv_priv;
360
361 an->sc = sc;
362 an->sta = sta;
363 an->vif = vif;
364 memset(&an->key_idx, 0, sizeof(an->key_idx));
365
366 ath_tx_node_init(sc, an);
367
368 ath_dynack_node_init(sc->sc_ah, an);
369 }
370
ath_node_detach(struct ath_softc * sc,struct ieee80211_sta * sta)371 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
372 {
373 struct ath_node *an = (struct ath_node *)sta->drv_priv;
374 ath_tx_node_cleanup(sc, an);
375
376 ath_dynack_node_deinit(sc->sc_ah, an);
377 }
378
ath9k_tasklet(struct tasklet_struct * t)379 void ath9k_tasklet(struct tasklet_struct *t)
380 {
381 struct ath_softc *sc = from_tasklet(sc, t, intr_tq);
382 struct ath_hw *ah = sc->sc_ah;
383 struct ath_common *common = ath9k_hw_common(ah);
384 enum ath_reset_type type;
385 unsigned long flags;
386 u32 status;
387 u32 rxmask;
388
389 spin_lock_irqsave(&sc->intr_lock, flags);
390 status = sc->intrstatus;
391 sc->intrstatus = 0;
392 spin_unlock_irqrestore(&sc->intr_lock, flags);
393
394 ath9k_ps_wakeup(sc);
395 spin_lock(&sc->sc_pcu_lock);
396
397 if (status & ATH9K_INT_FATAL) {
398 type = RESET_TYPE_FATAL_INT;
399 ath9k_queue_reset(sc, type);
400 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
401 goto out;
402 }
403
404 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
405 (status & ATH9K_INT_BB_WATCHDOG)) {
406 spin_lock_irqsave(&common->cc_lock, flags);
407 ath_hw_cycle_counters_update(common);
408 ar9003_hw_bb_watchdog_dbg_info(ah);
409 spin_unlock_irqrestore(&common->cc_lock, flags);
410
411 if (ar9003_hw_bb_watchdog_check(ah)) {
412 type = RESET_TYPE_BB_WATCHDOG;
413 ath9k_queue_reset(sc, type);
414
415 ath_dbg(common, RESET,
416 "BB_WATCHDOG: Skipping interrupts\n");
417 goto out;
418 }
419 }
420
421 if (status & ATH9K_INT_GTT) {
422 sc->gtt_cnt++;
423
424 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
425 type = RESET_TYPE_TX_GTT;
426 ath9k_queue_reset(sc, type);
427 ath_dbg(common, RESET,
428 "GTT: Skipping interrupts\n");
429 goto out;
430 }
431 }
432
433 spin_lock_irqsave(&sc->sc_pm_lock, flags);
434 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
435 /*
436 * TSF sync does not look correct; remain awake to sync with
437 * the next Beacon.
438 */
439 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
440 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
441 }
442 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
443
444 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
445 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
446 ATH9K_INT_RXORN);
447 else
448 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
449
450 if (status & rxmask) {
451 /* Check for high priority Rx first */
452 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
453 (status & ATH9K_INT_RXHP))
454 ath_rx_tasklet(sc, 0, true);
455
456 ath_rx_tasklet(sc, 0, false);
457 }
458
459 if (status & ATH9K_INT_TX) {
460 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
461 /*
462 * For EDMA chips, TX completion is enabled for the
463 * beacon queue, so if a beacon has been transmitted
464 * successfully after a GTT interrupt, the GTT counter
465 * gets reset to zero here.
466 */
467 sc->gtt_cnt = 0;
468
469 ath_tx_edma_tasklet(sc);
470 } else {
471 ath_tx_tasklet(sc);
472 }
473
474 wake_up(&sc->tx_wait);
475 }
476
477 if (status & ATH9K_INT_GENTIMER)
478 ath_gen_timer_isr(sc->sc_ah);
479
480 ath9k_btcoex_handle_interrupt(sc, status);
481
482 /* re-enable hardware interrupt */
483 ath9k_hw_resume_interrupts(ah);
484 out:
485 spin_unlock(&sc->sc_pcu_lock);
486 ath9k_ps_restore(sc);
487 }
488
ath_isr(int irq,void * dev)489 irqreturn_t ath_isr(int irq, void *dev)
490 {
491 #define SCHED_INTR ( \
492 ATH9K_INT_FATAL | \
493 ATH9K_INT_BB_WATCHDOG | \
494 ATH9K_INT_RXORN | \
495 ATH9K_INT_RXEOL | \
496 ATH9K_INT_RX | \
497 ATH9K_INT_RXLP | \
498 ATH9K_INT_RXHP | \
499 ATH9K_INT_TX | \
500 ATH9K_INT_BMISS | \
501 ATH9K_INT_CST | \
502 ATH9K_INT_GTT | \
503 ATH9K_INT_TSFOOR | \
504 ATH9K_INT_GENTIMER | \
505 ATH9K_INT_MCI)
506
507 struct ath_softc *sc = dev;
508 struct ath_hw *ah = sc->sc_ah;
509 struct ath_common *common = ath9k_hw_common(ah);
510 enum ath9k_int status;
511 u32 sync_cause = 0;
512 bool sched = false;
513
514 /*
515 * The hardware is not ready/present, don't
516 * touch anything. Note this can happen early
517 * on if the IRQ is shared.
518 */
519 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
520 return IRQ_NONE;
521
522 /* shared irq, not for us */
523 if (!ath9k_hw_intrpend(ah))
524 return IRQ_NONE;
525
526 /*
527 * Figure out the reason(s) for the interrupt. Note
528 * that the hal returns a pseudo-ISR that may include
529 * bits we haven't explicitly enabled so we mask the
530 * value to insure we only process bits we requested.
531 */
532 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
533 ath9k_debug_sync_cause(sc, sync_cause);
534 status &= ah->imask; /* discard unasked-for bits */
535
536 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {
537 ath9k_hw_kill_interrupts(sc->sc_ah);
538 return IRQ_HANDLED;
539 }
540
541 /*
542 * If there are no status bits set, then this interrupt was not
543 * for me (should have been caught above).
544 */
545 if (!status)
546 return IRQ_NONE;
547
548 /* Cache the status */
549 spin_lock(&sc->intr_lock);
550 sc->intrstatus |= status;
551 spin_unlock(&sc->intr_lock);
552
553 if (status & SCHED_INTR)
554 sched = true;
555
556 /*
557 * If a FATAL interrupt is received, we have to reset the chip
558 * immediately.
559 */
560 if (status & ATH9K_INT_FATAL)
561 goto chip_reset;
562
563 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
564 (status & ATH9K_INT_BB_WATCHDOG))
565 goto chip_reset;
566
567 if (status & ATH9K_INT_SWBA)
568 tasklet_schedule(&sc->bcon_tasklet);
569
570 if (status & ATH9K_INT_TXURN)
571 ath9k_hw_updatetxtriglevel(ah, true);
572
573 if (status & ATH9K_INT_RXEOL) {
574 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
575 ath9k_hw_set_interrupts(ah);
576 }
577
578 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
579 if (status & ATH9K_INT_TIM_TIMER) {
580 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
581 goto chip_reset;
582 /* Clear RxAbort bit so that we can
583 * receive frames */
584 ath9k_setpower(sc, ATH9K_PM_AWAKE);
585 spin_lock(&sc->sc_pm_lock);
586 ath9k_hw_setrxabort(sc->sc_ah, 0);
587 sc->ps_flags |= PS_WAIT_FOR_BEACON;
588 spin_unlock(&sc->sc_pm_lock);
589 }
590
591 chip_reset:
592
593 ath_debug_stat_interrupt(sc, status);
594
595 if (sched) {
596 /* turn off every interrupt */
597 ath9k_hw_kill_interrupts(ah);
598 tasklet_schedule(&sc->intr_tq);
599 }
600
601 return IRQ_HANDLED;
602
603 #undef SCHED_INTR
604 }
605
606 /*
607 * This function is called when a HW reset cannot be deferred
608 * and has to be immediate.
609 */
ath_reset(struct ath_softc * sc,struct ath9k_channel * hchan)610 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
611 {
612 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
613 int r;
614
615 ath9k_hw_kill_interrupts(sc->sc_ah);
616 set_bit(ATH_OP_HW_RESET, &common->op_flags);
617
618 ath9k_ps_wakeup(sc);
619 r = ath_reset_internal(sc, hchan);
620 ath9k_ps_restore(sc);
621
622 return r;
623 }
624
625 /*
626 * When a HW reset can be deferred, it is added to the
627 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
628 * queueing.
629 */
ath9k_queue_reset(struct ath_softc * sc,enum ath_reset_type type)630 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
631 {
632 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
633 #ifdef CONFIG_ATH9K_DEBUGFS
634 RESET_STAT_INC(sc, type);
635 #endif
636 ath9k_hw_kill_interrupts(sc->sc_ah);
637 set_bit(ATH_OP_HW_RESET, &common->op_flags);
638 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
639 }
640
ath_reset_work(struct work_struct * work)641 void ath_reset_work(struct work_struct *work)
642 {
643 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
644
645 ath9k_ps_wakeup(sc);
646 ath_reset_internal(sc, NULL);
647 ath9k_ps_restore(sc);
648 }
649
650 /**********************/
651 /* mac80211 callbacks */
652 /**********************/
653
ath9k_start(struct ieee80211_hw * hw)654 static int ath9k_start(struct ieee80211_hw *hw)
655 {
656 struct ath_softc *sc = hw->priv;
657 struct ath_hw *ah = sc->sc_ah;
658 struct ath_common *common = ath9k_hw_common(ah);
659 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
660 struct ath_chanctx *ctx = sc->cur_chan;
661 struct ath9k_channel *init_channel;
662 int r;
663
664 ath_dbg(common, CONFIG,
665 "Starting driver with initial channel: %d MHz\n",
666 curchan->center_freq);
667
668 ath9k_ps_wakeup(sc);
669 mutex_lock(&sc->mutex);
670
671 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
672 sc->cur_chandef = hw->conf.chandef;
673
674 /* Reset SERDES registers */
675 ath9k_hw_configpcipowersave(ah, false);
676
677 /*
678 * The basic interface to setting the hardware in a good
679 * state is ``reset''. On return the hardware is known to
680 * be powered up and with interrupts disabled. This must
681 * be followed by initialization of the appropriate bits
682 * and then setup of the interrupt mask.
683 */
684 spin_lock_bh(&sc->sc_pcu_lock);
685
686 atomic_set(&ah->intr_ref_cnt, -1);
687
688 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
689 if (r) {
690 ath_err(common,
691 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
692 r, curchan->center_freq);
693 ah->reset_power_on = false;
694 }
695
696 /* Setup our intr mask. */
697 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
698 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
699 ATH9K_INT_GLOBAL;
700
701 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
702 ah->imask |= ATH9K_INT_RXHP |
703 ATH9K_INT_RXLP;
704 else
705 ah->imask |= ATH9K_INT_RX;
706
707 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
708 ah->imask |= ATH9K_INT_BB_WATCHDOG;
709
710 /*
711 * Enable GTT interrupts only for AR9003/AR9004 chips
712 * for now.
713 */
714 if (AR_SREV_9300_20_OR_LATER(ah))
715 ah->imask |= ATH9K_INT_GTT;
716
717 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
718 ah->imask |= ATH9K_INT_CST;
719
720 ath_mci_enable(sc);
721
722 clear_bit(ATH_OP_INVALID, &common->op_flags);
723 sc->sc_ah->is_monitoring = false;
724
725 if (!ath_complete_reset(sc, false))
726 ah->reset_power_on = false;
727
728 if (ah->led_pin >= 0) {
729 ath9k_hw_set_gpio(ah, ah->led_pin,
730 (ah->config.led_active_high) ? 1 : 0);
731 ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL,
732 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
733 }
734
735 /*
736 * Reset key cache to sane defaults (all entries cleared) instead of
737 * semi-random values after suspend/resume.
738 */
739 ath9k_cmn_init_crypto(sc->sc_ah);
740
741 ath9k_hw_reset_tsf(ah);
742
743 spin_unlock_bh(&sc->sc_pcu_lock);
744
745 ath9k_rng_start(sc);
746
747 mutex_unlock(&sc->mutex);
748
749 ath9k_ps_restore(sc);
750
751 return 0;
752 }
753
ath9k_tx(struct ieee80211_hw * hw,struct ieee80211_tx_control * control,struct sk_buff * skb)754 static void ath9k_tx(struct ieee80211_hw *hw,
755 struct ieee80211_tx_control *control,
756 struct sk_buff *skb)
757 {
758 struct ath_softc *sc = hw->priv;
759 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
760 struct ath_tx_control txctl;
761 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
762 unsigned long flags;
763
764 if (sc->ps_enabled) {
765 /*
766 * mac80211 does not set PM field for normal data frames, so we
767 * need to update that based on the current PS mode.
768 */
769 if (ieee80211_is_data(hdr->frame_control) &&
770 !ieee80211_is_nullfunc(hdr->frame_control) &&
771 !ieee80211_has_pm(hdr->frame_control)) {
772 ath_dbg(common, PS,
773 "Add PM=1 for a TX frame while in PS mode\n");
774 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
775 }
776 }
777
778 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
779 /*
780 * We are using PS-Poll and mac80211 can request TX while in
781 * power save mode. Need to wake up hardware for the TX to be
782 * completed and if needed, also for RX of buffered frames.
783 */
784 ath9k_ps_wakeup(sc);
785 spin_lock_irqsave(&sc->sc_pm_lock, flags);
786 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
787 ath9k_hw_setrxabort(sc->sc_ah, 0);
788 if (ieee80211_is_pspoll(hdr->frame_control)) {
789 ath_dbg(common, PS,
790 "Sending PS-Poll to pick a buffered frame\n");
791 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
792 } else {
793 ath_dbg(common, PS, "Wake up to complete TX\n");
794 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
795 }
796 /*
797 * The actual restore operation will happen only after
798 * the ps_flags bit is cleared. We are just dropping
799 * the ps_usecount here.
800 */
801 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
802 ath9k_ps_restore(sc);
803 }
804
805 /*
806 * Cannot tx while the hardware is in full sleep, it first needs a full
807 * chip reset to recover from that
808 */
809 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
810 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
811 goto exit;
812 }
813
814 memset(&txctl, 0, sizeof(struct ath_tx_control));
815 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
816 txctl.sta = control->sta;
817
818 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
819
820 if (ath_tx_start(hw, skb, &txctl) != 0) {
821 ath_dbg(common, XMIT, "TX failed\n");
822 TX_STAT_INC(sc, txctl.txq->axq_qnum, txfailed);
823 goto exit;
824 }
825
826 return;
827 exit:
828 ieee80211_free_txskb(hw, skb);
829 }
830
ath9k_txq_list_has_key(struct list_head * txq_list,u32 keyix)831 static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix)
832 {
833 struct ath_buf *bf;
834 struct ieee80211_tx_info *txinfo;
835 struct ath_frame_info *fi;
836
837 list_for_each_entry(bf, txq_list, list) {
838 if (bf->bf_state.stale || !bf->bf_mpdu)
839 continue;
840
841 txinfo = IEEE80211_SKB_CB(bf->bf_mpdu);
842 fi = (struct ath_frame_info *)&txinfo->status.status_driver_data[0];
843 if (fi->keyix == keyix)
844 return true;
845 }
846
847 return false;
848 }
849
ath9k_txq_has_key(struct ath_softc * sc,u32 keyix)850 static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix)
851 {
852 struct ath_hw *ah = sc->sc_ah;
853 int i, j;
854 struct ath_txq *txq;
855 bool key_in_use = false;
856
857 for (i = 0; !key_in_use && i < ATH9K_NUM_TX_QUEUES; i++) {
858 if (!ATH_TXQ_SETUP(sc, i))
859 continue;
860 txq = &sc->tx.txq[i];
861 if (!txq->axq_depth)
862 continue;
863 if (!ath9k_hw_numtxpending(ah, txq->axq_qnum))
864 continue;
865
866 ath_txq_lock(sc, txq);
867 key_in_use = ath9k_txq_list_has_key(&txq->axq_q, keyix);
868 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
869 int idx = txq->txq_tailidx;
870
871 for (j = 0; !key_in_use &&
872 !list_empty(&txq->txq_fifo[idx]) &&
873 j < ATH_TXFIFO_DEPTH; j++) {
874 key_in_use = ath9k_txq_list_has_key(
875 &txq->txq_fifo[idx], keyix);
876 INCR(idx, ATH_TXFIFO_DEPTH);
877 }
878 }
879 ath_txq_unlock(sc, txq);
880 }
881
882 return key_in_use;
883 }
884
ath9k_pending_key_del(struct ath_softc * sc,u8 keyix)885 static void ath9k_pending_key_del(struct ath_softc *sc, u8 keyix)
886 {
887 struct ath_hw *ah = sc->sc_ah;
888 struct ath_common *common = ath9k_hw_common(ah);
889
890 if (!test_bit(keyix, ah->pending_del_keymap) ||
891 ath9k_txq_has_key(sc, keyix))
892 return;
893
894 /* No more TXQ frames point to this key cache entry, so delete it. */
895 clear_bit(keyix, ah->pending_del_keymap);
896 ath_key_delete(common, keyix);
897 }
898
ath9k_stop(struct ieee80211_hw * hw)899 static void ath9k_stop(struct ieee80211_hw *hw)
900 {
901 struct ath_softc *sc = hw->priv;
902 struct ath_hw *ah = sc->sc_ah;
903 struct ath_common *common = ath9k_hw_common(ah);
904 bool prev_idle;
905 int i;
906
907 ath9k_deinit_channel_context(sc);
908
909 mutex_lock(&sc->mutex);
910
911 ath9k_rng_stop(sc);
912
913 ath_cancel_work(sc);
914
915 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
916 ath_dbg(common, ANY, "Device not present\n");
917 mutex_unlock(&sc->mutex);
918 return;
919 }
920
921 /* Ensure HW is awake when we try to shut it down. */
922 ath9k_ps_wakeup(sc);
923
924 spin_lock_bh(&sc->sc_pcu_lock);
925
926 /* prevent tasklets to enable interrupts once we disable them */
927 ah->imask &= ~ATH9K_INT_GLOBAL;
928
929 /* make sure h/w will not generate any interrupt
930 * before setting the invalid flag. */
931 ath9k_hw_disable_interrupts(ah);
932
933 spin_unlock_bh(&sc->sc_pcu_lock);
934
935 /* we can now sync irq and kill any running tasklets, since we already
936 * disabled interrupts and not holding a spin lock */
937 synchronize_irq(sc->irq);
938 tasklet_kill(&sc->intr_tq);
939 tasklet_kill(&sc->bcon_tasklet);
940
941 prev_idle = sc->ps_idle;
942 sc->ps_idle = true;
943
944 spin_lock_bh(&sc->sc_pcu_lock);
945
946 if (ah->led_pin >= 0) {
947 ath9k_hw_set_gpio(ah, ah->led_pin,
948 (ah->config.led_active_high) ? 0 : 1);
949 ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL);
950 }
951
952 ath_prepare_reset(sc);
953
954 if (sc->rx.frag) {
955 dev_kfree_skb_any(sc->rx.frag);
956 sc->rx.frag = NULL;
957 }
958
959 if (!ah->curchan)
960 ah->curchan = ath9k_cmn_get_channel(hw, ah,
961 &sc->cur_chan->chandef);
962
963 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
964
965 set_bit(ATH_OP_INVALID, &common->op_flags);
966
967 ath9k_hw_phy_disable(ah);
968
969 ath9k_hw_configpcipowersave(ah, true);
970
971 spin_unlock_bh(&sc->sc_pcu_lock);
972
973 for (i = 0; i < ATH_KEYMAX; i++)
974 ath9k_pending_key_del(sc, i);
975
976 /* Clear key cache entries explicitly to get rid of any potentially
977 * remaining keys.
978 */
979 ath9k_cmn_init_crypto(sc->sc_ah);
980
981 ath9k_ps_restore(sc);
982
983 sc->ps_idle = prev_idle;
984
985 mutex_unlock(&sc->mutex);
986
987 ath_dbg(common, CONFIG, "Driver halt\n");
988 }
989
ath9k_uses_beacons(int type)990 static bool ath9k_uses_beacons(int type)
991 {
992 switch (type) {
993 case NL80211_IFTYPE_AP:
994 case NL80211_IFTYPE_ADHOC:
995 case NL80211_IFTYPE_MESH_POINT:
996 return true;
997 default:
998 return false;
999 }
1000 }
1001
ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data * iter_data,struct ieee80211_vif * vif)1002 static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data,
1003 struct ieee80211_vif *vif)
1004 {
1005 /* Use the first (configured) interface, but prefering AP interfaces. */
1006 if (!iter_data->primary_beacon_vif) {
1007 iter_data->primary_beacon_vif = vif;
1008 } else {
1009 if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP &&
1010 vif->type == NL80211_IFTYPE_AP)
1011 iter_data->primary_beacon_vif = vif;
1012 }
1013
1014 iter_data->beacons = true;
1015 iter_data->nbcnvifs += 1;
1016 }
1017
ath9k_vif_iter(struct ath9k_vif_iter_data * iter_data,u8 * mac,struct ieee80211_vif * vif)1018 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
1019 u8 *mac, struct ieee80211_vif *vif)
1020 {
1021 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1022 int i;
1023
1024 if (iter_data->has_hw_macaddr) {
1025 for (i = 0; i < ETH_ALEN; i++)
1026 iter_data->mask[i] &=
1027 ~(iter_data->hw_macaddr[i] ^ mac[i]);
1028 } else {
1029 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
1030 iter_data->has_hw_macaddr = true;
1031 }
1032
1033 if (!vif->bss_conf.use_short_slot)
1034 iter_data->slottime = 20;
1035
1036 switch (vif->type) {
1037 case NL80211_IFTYPE_AP:
1038 iter_data->naps++;
1039 if (vif->bss_conf.enable_beacon)
1040 ath9k_vif_iter_set_beacon(iter_data, vif);
1041 break;
1042 case NL80211_IFTYPE_STATION:
1043 iter_data->nstations++;
1044 if (avp->assoc && !iter_data->primary_sta)
1045 iter_data->primary_sta = vif;
1046 break;
1047 case NL80211_IFTYPE_OCB:
1048 iter_data->nocbs++;
1049 break;
1050 case NL80211_IFTYPE_ADHOC:
1051 iter_data->nadhocs++;
1052 if (vif->bss_conf.enable_beacon)
1053 ath9k_vif_iter_set_beacon(iter_data, vif);
1054 break;
1055 case NL80211_IFTYPE_MESH_POINT:
1056 iter_data->nmeshes++;
1057 if (vif->bss_conf.enable_beacon)
1058 ath9k_vif_iter_set_beacon(iter_data, vif);
1059 break;
1060 case NL80211_IFTYPE_WDS:
1061 iter_data->nwds++;
1062 break;
1063 default:
1064 break;
1065 }
1066 }
1067
ath9k_update_bssid_mask(struct ath_softc * sc,struct ath_chanctx * ctx,struct ath9k_vif_iter_data * iter_data)1068 static void ath9k_update_bssid_mask(struct ath_softc *sc,
1069 struct ath_chanctx *ctx,
1070 struct ath9k_vif_iter_data *iter_data)
1071 {
1072 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1073 struct ath_vif *avp;
1074 int i;
1075
1076 if (!ath9k_is_chanctx_enabled())
1077 return;
1078
1079 list_for_each_entry(avp, &ctx->vifs, list) {
1080 if (ctx->nvifs_assigned != 1)
1081 continue;
1082
1083 if (!iter_data->has_hw_macaddr)
1084 continue;
1085
1086 ether_addr_copy(common->curbssid, avp->bssid);
1087
1088 /* perm_addr will be used as the p2p device address. */
1089 for (i = 0; i < ETH_ALEN; i++)
1090 iter_data->mask[i] &=
1091 ~(iter_data->hw_macaddr[i] ^
1092 sc->hw->wiphy->perm_addr[i]);
1093 }
1094 }
1095
1096 /* Called with sc->mutex held. */
ath9k_calculate_iter_data(struct ath_softc * sc,struct ath_chanctx * ctx,struct ath9k_vif_iter_data * iter_data)1097 void ath9k_calculate_iter_data(struct ath_softc *sc,
1098 struct ath_chanctx *ctx,
1099 struct ath9k_vif_iter_data *iter_data)
1100 {
1101 struct ath_vif *avp;
1102
1103 /*
1104 * The hardware will use primary station addr together with the
1105 * BSSID mask when matching addresses.
1106 */
1107 memset(iter_data, 0, sizeof(*iter_data));
1108 eth_broadcast_addr(iter_data->mask);
1109 iter_data->slottime = 9;
1110
1111 list_for_each_entry(avp, &ctx->vifs, list)
1112 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1113
1114 ath9k_update_bssid_mask(sc, ctx, iter_data);
1115 }
1116
ath9k_set_assoc_state(struct ath_softc * sc,struct ieee80211_vif * vif,bool changed)1117 static void ath9k_set_assoc_state(struct ath_softc *sc,
1118 struct ieee80211_vif *vif, bool changed)
1119 {
1120 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1121 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1122 unsigned long flags;
1123
1124 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1125
1126 ether_addr_copy(common->curbssid, avp->bssid);
1127 common->curaid = avp->aid;
1128 ath9k_hw_write_associd(sc->sc_ah);
1129
1130 if (changed) {
1131 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1132 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1133
1134 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1135 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1136 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1137 }
1138
1139 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1140 ath9k_mci_update_wlan_channels(sc, false);
1141
1142 ath_dbg(common, CONFIG,
1143 "Primary Station interface: %pM, BSSID: %pM\n",
1144 vif->addr, common->curbssid);
1145 }
1146
1147 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
ath9k_set_offchannel_state(struct ath_softc * sc)1148 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1149 {
1150 struct ath_hw *ah = sc->sc_ah;
1151 struct ath_common *common = ath9k_hw_common(ah);
1152 struct ieee80211_vif *vif = NULL;
1153
1154 ath9k_ps_wakeup(sc);
1155
1156 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1157 vif = sc->offchannel.scan_vif;
1158 else
1159 vif = sc->offchannel.roc_vif;
1160
1161 if (WARN_ON(!vif))
1162 goto exit;
1163
1164 eth_zero_addr(common->curbssid);
1165 eth_broadcast_addr(common->bssidmask);
1166 memcpy(common->macaddr, vif->addr, ETH_ALEN);
1167 common->curaid = 0;
1168 ah->opmode = vif->type;
1169 ah->imask &= ~ATH9K_INT_SWBA;
1170 ah->imask &= ~ATH9K_INT_TSFOOR;
1171 ah->slottime = 9;
1172
1173 ath_hw_setbssidmask(common);
1174 ath9k_hw_setopmode(ah);
1175 ath9k_hw_write_associd(sc->sc_ah);
1176 ath9k_hw_set_interrupts(ah);
1177 ath9k_hw_init_global_settings(ah);
1178
1179 exit:
1180 ath9k_ps_restore(sc);
1181 }
1182 #endif
1183
1184 /* Called with sc->mutex held. */
ath9k_calculate_summary_state(struct ath_softc * sc,struct ath_chanctx * ctx)1185 void ath9k_calculate_summary_state(struct ath_softc *sc,
1186 struct ath_chanctx *ctx)
1187 {
1188 struct ath_hw *ah = sc->sc_ah;
1189 struct ath_common *common = ath9k_hw_common(ah);
1190 struct ath9k_vif_iter_data iter_data;
1191
1192 ath_chanctx_check_active(sc, ctx);
1193
1194 if (ctx != sc->cur_chan)
1195 return;
1196
1197 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1198 if (ctx == &sc->offchannel.chan)
1199 return ath9k_set_offchannel_state(sc);
1200 #endif
1201
1202 ath9k_ps_wakeup(sc);
1203 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1204
1205 if (iter_data.has_hw_macaddr)
1206 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1207
1208 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1209 ath_hw_setbssidmask(common);
1210
1211 if (iter_data.naps > 0) {
1212 ath9k_hw_set_tsfadjust(ah, true);
1213 ah->opmode = NL80211_IFTYPE_AP;
1214 } else {
1215 ath9k_hw_set_tsfadjust(ah, false);
1216 if (iter_data.beacons)
1217 ath9k_beacon_ensure_primary_slot(sc);
1218
1219 if (iter_data.nmeshes)
1220 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1221 else if (iter_data.nocbs)
1222 ah->opmode = NL80211_IFTYPE_OCB;
1223 else if (iter_data.nwds)
1224 ah->opmode = NL80211_IFTYPE_AP;
1225 else if (iter_data.nadhocs)
1226 ah->opmode = NL80211_IFTYPE_ADHOC;
1227 else
1228 ah->opmode = NL80211_IFTYPE_STATION;
1229 }
1230
1231 ath9k_hw_setopmode(ah);
1232
1233 ctx->switch_after_beacon = false;
1234 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1235 ah->imask |= ATH9K_INT_TSFOOR;
1236 else {
1237 ah->imask &= ~ATH9K_INT_TSFOOR;
1238 if (iter_data.naps == 1 && iter_data.beacons)
1239 ctx->switch_after_beacon = true;
1240 }
1241
1242 if (ah->opmode == NL80211_IFTYPE_STATION) {
1243 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1244
1245 if (iter_data.primary_sta) {
1246 iter_data.primary_beacon_vif = iter_data.primary_sta;
1247 iter_data.beacons = true;
1248 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1249 changed);
1250 ctx->primary_sta = iter_data.primary_sta;
1251 } else {
1252 ctx->primary_sta = NULL;
1253 eth_zero_addr(common->curbssid);
1254 common->curaid = 0;
1255 ath9k_hw_write_associd(sc->sc_ah);
1256 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1257 ath9k_mci_update_wlan_channels(sc, true);
1258 }
1259 }
1260 sc->nbcnvifs = iter_data.nbcnvifs;
1261 ath9k_beacon_config(sc, iter_data.primary_beacon_vif,
1262 iter_data.beacons);
1263 ath9k_hw_set_interrupts(ah);
1264
1265 if (ah->slottime != iter_data.slottime) {
1266 ah->slottime = iter_data.slottime;
1267 ath9k_hw_init_global_settings(ah);
1268 }
1269
1270 if (iter_data.primary_sta)
1271 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1272 else
1273 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1274
1275 ath_dbg(common, CONFIG,
1276 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1277 common->macaddr, common->curbssid, common->bssidmask);
1278
1279 ath9k_ps_restore(sc);
1280 }
1281
ath9k_tpc_vif_iter(void * data,u8 * mac,struct ieee80211_vif * vif)1282 static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1283 {
1284 int *power = data;
1285
1286 if (vif->bss_conf.txpower == INT_MIN)
1287 return;
1288
1289 if (*power < vif->bss_conf.txpower)
1290 *power = vif->bss_conf.txpower;
1291 }
1292
1293 /* Called with sc->mutex held. */
ath9k_set_txpower(struct ath_softc * sc,struct ieee80211_vif * vif)1294 void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1295 {
1296 int power;
1297 struct ath_hw *ah = sc->sc_ah;
1298 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1299
1300 ath9k_ps_wakeup(sc);
1301 if (ah->tpc_enabled) {
1302 power = (vif) ? vif->bss_conf.txpower : -1;
1303 ieee80211_iterate_active_interfaces_atomic(
1304 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1305 ath9k_tpc_vif_iter, &power);
1306 if (power == -1)
1307 power = sc->hw->conf.power_level;
1308 } else {
1309 power = sc->hw->conf.power_level;
1310 }
1311 sc->cur_chan->txpower = 2 * power;
1312 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1313 sc->cur_chan->cur_txpower = reg->max_power_level;
1314 ath9k_ps_restore(sc);
1315 }
1316
ath9k_assign_hw_queues(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1317 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1318 struct ieee80211_vif *vif)
1319 {
1320 int i;
1321
1322 if (!ath9k_is_chanctx_enabled())
1323 return;
1324
1325 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1326 vif->hw_queue[i] = i;
1327
1328 if (vif->type == NL80211_IFTYPE_AP ||
1329 vif->type == NL80211_IFTYPE_MESH_POINT)
1330 vif->cab_queue = hw->queues - 2;
1331 else
1332 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1333 }
1334
ath9k_add_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1335 static int ath9k_add_interface(struct ieee80211_hw *hw,
1336 struct ieee80211_vif *vif)
1337 {
1338 struct ath_softc *sc = hw->priv;
1339 struct ath_hw *ah = sc->sc_ah;
1340 struct ath_common *common = ath9k_hw_common(ah);
1341 struct ath_vif *avp = (void *)vif->drv_priv;
1342 struct ath_node *an = &avp->mcast_node;
1343
1344 mutex_lock(&sc->mutex);
1345 if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1346 if (sc->cur_chan->nvifs >= 1) {
1347 mutex_unlock(&sc->mutex);
1348 return -EOPNOTSUPP;
1349 }
1350 sc->tx99_vif = vif;
1351 }
1352
1353 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1354 sc->cur_chan->nvifs++;
1355
1356 if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
1357 vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
1358
1359 if (ath9k_uses_beacons(vif->type))
1360 ath9k_beacon_assign_slot(sc, vif);
1361
1362 avp->vif = vif;
1363 if (!ath9k_is_chanctx_enabled()) {
1364 avp->chanctx = sc->cur_chan;
1365 list_add_tail(&avp->list, &avp->chanctx->vifs);
1366 }
1367
1368 ath9k_calculate_summary_state(sc, avp->chanctx);
1369
1370 ath9k_assign_hw_queues(hw, vif);
1371
1372 ath9k_set_txpower(sc, vif);
1373
1374 an->sc = sc;
1375 an->sta = NULL;
1376 an->vif = vif;
1377 an->no_ps_filter = true;
1378 ath_tx_node_init(sc, an);
1379
1380 mutex_unlock(&sc->mutex);
1381 return 0;
1382 }
1383
ath9k_change_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif,enum nl80211_iftype new_type,bool p2p)1384 static int ath9k_change_interface(struct ieee80211_hw *hw,
1385 struct ieee80211_vif *vif,
1386 enum nl80211_iftype new_type,
1387 bool p2p)
1388 {
1389 struct ath_softc *sc = hw->priv;
1390 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1391 struct ath_vif *avp = (void *)vif->drv_priv;
1392
1393 mutex_lock(&sc->mutex);
1394
1395 if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1396 mutex_unlock(&sc->mutex);
1397 return -EOPNOTSUPP;
1398 }
1399
1400 ath_dbg(common, CONFIG, "Change Interface\n");
1401
1402 if (ath9k_uses_beacons(vif->type))
1403 ath9k_beacon_remove_slot(sc, vif);
1404
1405 vif->type = new_type;
1406 vif->p2p = p2p;
1407
1408 if (ath9k_uses_beacons(vif->type))
1409 ath9k_beacon_assign_slot(sc, vif);
1410
1411 ath9k_assign_hw_queues(hw, vif);
1412 ath9k_calculate_summary_state(sc, avp->chanctx);
1413
1414 ath9k_set_txpower(sc, vif);
1415
1416 mutex_unlock(&sc->mutex);
1417 return 0;
1418 }
1419
ath9k_remove_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1420 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1421 struct ieee80211_vif *vif)
1422 {
1423 struct ath_softc *sc = hw->priv;
1424 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1425 struct ath_vif *avp = (void *)vif->drv_priv;
1426
1427 ath_dbg(common, CONFIG, "Detach Interface\n");
1428
1429 mutex_lock(&sc->mutex);
1430
1431 ath9k_p2p_remove_vif(sc, vif);
1432
1433 sc->cur_chan->nvifs--;
1434 sc->tx99_vif = NULL;
1435 if (!ath9k_is_chanctx_enabled())
1436 list_del(&avp->list);
1437
1438 if (ath9k_uses_beacons(vif->type))
1439 ath9k_beacon_remove_slot(sc, vif);
1440
1441 ath_tx_node_cleanup(sc, &avp->mcast_node);
1442
1443 ath9k_calculate_summary_state(sc, avp->chanctx);
1444
1445 ath9k_set_txpower(sc, NULL);
1446
1447 mutex_unlock(&sc->mutex);
1448 }
1449
ath9k_enable_ps(struct ath_softc * sc)1450 static void ath9k_enable_ps(struct ath_softc *sc)
1451 {
1452 struct ath_hw *ah = sc->sc_ah;
1453 struct ath_common *common = ath9k_hw_common(ah);
1454
1455 if (IS_ENABLED(CONFIG_ATH9K_TX99))
1456 return;
1457
1458 sc->ps_enabled = true;
1459 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1460 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1461 ah->imask |= ATH9K_INT_TIM_TIMER;
1462 ath9k_hw_set_interrupts(ah);
1463 }
1464 ath9k_hw_setrxabort(ah, 1);
1465 }
1466 ath_dbg(common, PS, "PowerSave enabled\n");
1467 }
1468
ath9k_disable_ps(struct ath_softc * sc)1469 static void ath9k_disable_ps(struct ath_softc *sc)
1470 {
1471 struct ath_hw *ah = sc->sc_ah;
1472 struct ath_common *common = ath9k_hw_common(ah);
1473
1474 if (IS_ENABLED(CONFIG_ATH9K_TX99))
1475 return;
1476
1477 sc->ps_enabled = false;
1478 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1479 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1480 ath9k_hw_setrxabort(ah, 0);
1481 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1482 PS_WAIT_FOR_CAB |
1483 PS_WAIT_FOR_PSPOLL_DATA |
1484 PS_WAIT_FOR_TX_ACK);
1485 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1486 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1487 ath9k_hw_set_interrupts(ah);
1488 }
1489 }
1490 ath_dbg(common, PS, "PowerSave disabled\n");
1491 }
1492
ath9k_config(struct ieee80211_hw * hw,u32 changed)1493 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1494 {
1495 struct ath_softc *sc = hw->priv;
1496 struct ath_hw *ah = sc->sc_ah;
1497 struct ath_common *common = ath9k_hw_common(ah);
1498 struct ieee80211_conf *conf = &hw->conf;
1499 struct ath_chanctx *ctx = sc->cur_chan;
1500
1501 ath9k_ps_wakeup(sc);
1502 mutex_lock(&sc->mutex);
1503
1504 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1505 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1506 if (sc->ps_idle) {
1507 ath_cancel_work(sc);
1508 ath9k_stop_btcoex(sc);
1509 } else {
1510 ath9k_start_btcoex(sc);
1511 /*
1512 * The chip needs a reset to properly wake up from
1513 * full sleep
1514 */
1515 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1516 }
1517 }
1518
1519 /*
1520 * We just prepare to enable PS. We have to wait until our AP has
1521 * ACK'd our null data frame to disable RX otherwise we'll ignore
1522 * those ACKs and end up retransmitting the same null data frames.
1523 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1524 */
1525 if (changed & IEEE80211_CONF_CHANGE_PS) {
1526 unsigned long flags;
1527 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1528 if (conf->flags & IEEE80211_CONF_PS)
1529 ath9k_enable_ps(sc);
1530 else
1531 ath9k_disable_ps(sc);
1532 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1533 }
1534
1535 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1536 if (conf->flags & IEEE80211_CONF_MONITOR) {
1537 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1538 sc->sc_ah->is_monitoring = true;
1539 } else {
1540 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1541 sc->sc_ah->is_monitoring = false;
1542 }
1543 }
1544
1545 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1546 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1547 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1548 }
1549
1550 if (changed & IEEE80211_CONF_CHANGE_POWER)
1551 ath9k_set_txpower(sc, NULL);
1552
1553 mutex_unlock(&sc->mutex);
1554 ath9k_ps_restore(sc);
1555
1556 return 0;
1557 }
1558
1559 #define SUPPORTED_FILTERS \
1560 (FIF_ALLMULTI | \
1561 FIF_CONTROL | \
1562 FIF_PSPOLL | \
1563 FIF_OTHER_BSS | \
1564 FIF_BCN_PRBRESP_PROMISC | \
1565 FIF_PROBE_REQ | \
1566 FIF_MCAST_ACTION | \
1567 FIF_FCSFAIL)
1568
1569 /* FIXME: sc->sc_full_reset ? */
ath9k_configure_filter(struct ieee80211_hw * hw,unsigned int changed_flags,unsigned int * total_flags,u64 multicast)1570 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1571 unsigned int changed_flags,
1572 unsigned int *total_flags,
1573 u64 multicast)
1574 {
1575 struct ath_softc *sc = hw->priv;
1576 struct ath_chanctx *ctx;
1577 u32 rfilt;
1578
1579 changed_flags &= SUPPORTED_FILTERS;
1580 *total_flags &= SUPPORTED_FILTERS;
1581
1582 spin_lock_bh(&sc->chan_lock);
1583 ath_for_each_chanctx(sc, ctx)
1584 ctx->rxfilter = *total_flags;
1585 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1586 sc->offchannel.chan.rxfilter = *total_flags;
1587 #endif
1588 spin_unlock_bh(&sc->chan_lock);
1589
1590 ath9k_ps_wakeup(sc);
1591 rfilt = ath_calcrxfilter(sc);
1592 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1593 ath9k_ps_restore(sc);
1594
1595 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1596 rfilt);
1597 }
1598
ath9k_sta_add(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1599 static int ath9k_sta_add(struct ieee80211_hw *hw,
1600 struct ieee80211_vif *vif,
1601 struct ieee80211_sta *sta)
1602 {
1603 struct ath_softc *sc = hw->priv;
1604 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1605 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1606 struct ieee80211_key_conf ps_key = { };
1607 int key;
1608
1609 ath_node_attach(sc, sta, vif);
1610
1611 if (vif->type != NL80211_IFTYPE_AP &&
1612 vif->type != NL80211_IFTYPE_AP_VLAN)
1613 return 0;
1614
1615 key = ath_key_config(common, vif, sta, &ps_key);
1616 if (key > 0) {
1617 an->ps_key = key;
1618 an->key_idx[0] = key;
1619 }
1620
1621 return 0;
1622 }
1623
ath9k_del_ps_key(struct ath_softc * sc,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1624 static void ath9k_del_ps_key(struct ath_softc *sc,
1625 struct ieee80211_vif *vif,
1626 struct ieee80211_sta *sta)
1627 {
1628 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1629 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1630
1631 if (!an->ps_key)
1632 return;
1633
1634 ath_key_delete(common, an->ps_key);
1635 an->ps_key = 0;
1636 an->key_idx[0] = 0;
1637 }
1638
ath9k_sta_remove(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1639 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1640 struct ieee80211_vif *vif,
1641 struct ieee80211_sta *sta)
1642 {
1643 struct ath_softc *sc = hw->priv;
1644
1645 ath9k_del_ps_key(sc, vif, sta);
1646 ath_node_detach(sc, sta);
1647
1648 return 0;
1649 }
1650
ath9k_sta_state(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta,enum ieee80211_sta_state old_state,enum ieee80211_sta_state new_state)1651 static int ath9k_sta_state(struct ieee80211_hw *hw,
1652 struct ieee80211_vif *vif,
1653 struct ieee80211_sta *sta,
1654 enum ieee80211_sta_state old_state,
1655 enum ieee80211_sta_state new_state)
1656 {
1657 struct ath_softc *sc = hw->priv;
1658 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1659 int ret = 0;
1660
1661 if (old_state == IEEE80211_STA_NOTEXIST &&
1662 new_state == IEEE80211_STA_NONE) {
1663 ret = ath9k_sta_add(hw, vif, sta);
1664 ath_dbg(common, CONFIG,
1665 "Add station: %pM\n", sta->addr);
1666 } else if (old_state == IEEE80211_STA_NONE &&
1667 new_state == IEEE80211_STA_NOTEXIST) {
1668 ret = ath9k_sta_remove(hw, vif, sta);
1669 ath_dbg(common, CONFIG,
1670 "Remove station: %pM\n", sta->addr);
1671 }
1672
1673 if (ath9k_is_chanctx_enabled()) {
1674 if (vif->type == NL80211_IFTYPE_STATION) {
1675 if (old_state == IEEE80211_STA_ASSOC &&
1676 new_state == IEEE80211_STA_AUTHORIZED)
1677 ath_chanctx_event(sc, vif,
1678 ATH_CHANCTX_EVENT_AUTHORIZED);
1679 }
1680 }
1681
1682 return ret;
1683 }
1684
ath9k_sta_set_tx_filter(struct ath_hw * ah,struct ath_node * an,bool set)1685 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1686 struct ath_node *an,
1687 bool set)
1688 {
1689 int i;
1690
1691 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1692 if (!an->key_idx[i])
1693 continue;
1694 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1695 }
1696 }
1697
ath9k_sta_notify(struct ieee80211_hw * hw,struct ieee80211_vif * vif,enum sta_notify_cmd cmd,struct ieee80211_sta * sta)1698 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1699 struct ieee80211_vif *vif,
1700 enum sta_notify_cmd cmd,
1701 struct ieee80211_sta *sta)
1702 {
1703 struct ath_softc *sc = hw->priv;
1704 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1705
1706 switch (cmd) {
1707 case STA_NOTIFY_SLEEP:
1708 an->sleeping = true;
1709 ath_tx_aggr_sleep(sta, sc, an);
1710 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1711 break;
1712 case STA_NOTIFY_AWAKE:
1713 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1714 an->sleeping = false;
1715 ath_tx_aggr_wakeup(sc, an);
1716 break;
1717 }
1718 }
1719
ath9k_conf_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u16 queue,const struct ieee80211_tx_queue_params * params)1720 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1721 struct ieee80211_vif *vif, u16 queue,
1722 const struct ieee80211_tx_queue_params *params)
1723 {
1724 struct ath_softc *sc = hw->priv;
1725 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1726 struct ath_txq *txq;
1727 struct ath9k_tx_queue_info qi;
1728 int ret = 0;
1729
1730 if (queue >= IEEE80211_NUM_ACS)
1731 return 0;
1732
1733 txq = sc->tx.txq_map[queue];
1734
1735 ath9k_ps_wakeup(sc);
1736 mutex_lock(&sc->mutex);
1737
1738 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1739
1740 qi.tqi_aifs = params->aifs;
1741 qi.tqi_cwmin = params->cw_min;
1742 qi.tqi_cwmax = params->cw_max;
1743 qi.tqi_burstTime = params->txop * 32;
1744
1745 ath_dbg(common, CONFIG,
1746 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1747 queue, txq->axq_qnum, params->aifs, params->cw_min,
1748 params->cw_max, params->txop);
1749
1750 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1751 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1752 if (ret)
1753 ath_err(common, "TXQ Update failed\n");
1754
1755 mutex_unlock(&sc->mutex);
1756 ath9k_ps_restore(sc);
1757
1758 return ret;
1759 }
1760
ath9k_set_key(struct ieee80211_hw * hw,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key)1761 static int ath9k_set_key(struct ieee80211_hw *hw,
1762 enum set_key_cmd cmd,
1763 struct ieee80211_vif *vif,
1764 struct ieee80211_sta *sta,
1765 struct ieee80211_key_conf *key)
1766 {
1767 struct ath_softc *sc = hw->priv;
1768 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1769 struct ath_node *an = NULL;
1770 int ret = 0, i;
1771
1772 if (ath9k_modparam_nohwcrypt)
1773 return -ENOSPC;
1774
1775 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1776 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1777 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1778 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1779 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1780 /*
1781 * For now, disable hw crypto for the RSN IBSS group keys. This
1782 * could be optimized in the future to use a modified key cache
1783 * design to support per-STA RX GTK, but until that gets
1784 * implemented, use of software crypto for group addressed
1785 * frames is a acceptable to allow RSN IBSS to be used.
1786 */
1787 return -EOPNOTSUPP;
1788 }
1789
1790 /* There may be MPDUs queued for the outgoing PTK key. Flush queues to
1791 * make sure these are not send unencrypted or with a wrong (new) key
1792 */
1793 if (cmd == DISABLE_KEY && key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
1794 ieee80211_stop_queues(hw);
1795 ath9k_flush(hw, vif, 0, true);
1796 ieee80211_wake_queues(hw);
1797 }
1798
1799 mutex_lock(&sc->mutex);
1800 ath9k_ps_wakeup(sc);
1801 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1802 if (sta)
1803 an = (struct ath_node *)sta->drv_priv;
1804
1805 /* Delete pending key cache entries if no more frames are pointing to
1806 * them in TXQs.
1807 */
1808 for (i = 0; i < ATH_KEYMAX; i++)
1809 ath9k_pending_key_del(sc, i);
1810
1811 switch (cmd) {
1812 case SET_KEY:
1813 if (sta)
1814 ath9k_del_ps_key(sc, vif, sta);
1815
1816 key->hw_key_idx = 0;
1817 ret = ath_key_config(common, vif, sta, key);
1818 if (ret >= 0) {
1819 key->hw_key_idx = ret;
1820 /* push IV and Michael MIC generation to stack */
1821 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1822 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1823 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1824 if (sc->sc_ah->sw_mgmt_crypto_tx &&
1825 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1826 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1827 ret = 0;
1828 }
1829 if (an && key->hw_key_idx) {
1830 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1831 if (an->key_idx[i])
1832 continue;
1833 an->key_idx[i] = key->hw_key_idx;
1834 break;
1835 }
1836 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1837 }
1838 break;
1839 case DISABLE_KEY:
1840 if (ath9k_txq_has_key(sc, key->hw_key_idx)) {
1841 /* Delay key cache entry deletion until there are no
1842 * remaining TXQ frames pointing to this entry.
1843 */
1844 set_bit(key->hw_key_idx, sc->sc_ah->pending_del_keymap);
1845 ath_hw_keysetmac(common, key->hw_key_idx, NULL);
1846 } else {
1847 ath_key_delete(common, key->hw_key_idx);
1848 }
1849 if (an) {
1850 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1851 if (an->key_idx[i] != key->hw_key_idx)
1852 continue;
1853 an->key_idx[i] = 0;
1854 break;
1855 }
1856 }
1857 key->hw_key_idx = 0;
1858 break;
1859 default:
1860 ret = -EINVAL;
1861 }
1862
1863 ath9k_ps_restore(sc);
1864 mutex_unlock(&sc->mutex);
1865
1866 return ret;
1867 }
1868
ath9k_bss_info_changed(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf,u32 changed)1869 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1870 struct ieee80211_vif *vif,
1871 struct ieee80211_bss_conf *bss_conf,
1872 u32 changed)
1873 {
1874 #define CHECK_ANI \
1875 (BSS_CHANGED_ASSOC | \
1876 BSS_CHANGED_IBSS | \
1877 BSS_CHANGED_BEACON_ENABLED)
1878
1879 struct ath_softc *sc = hw->priv;
1880 struct ath_hw *ah = sc->sc_ah;
1881 struct ath_common *common = ath9k_hw_common(ah);
1882 struct ath_vif *avp = (void *)vif->drv_priv;
1883 int slottime;
1884
1885 ath9k_ps_wakeup(sc);
1886 mutex_lock(&sc->mutex);
1887
1888 if (changed & BSS_CHANGED_ASSOC) {
1889 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1890 bss_conf->bssid, bss_conf->assoc);
1891
1892 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1893 avp->aid = bss_conf->aid;
1894 avp->assoc = bss_conf->assoc;
1895
1896 ath9k_calculate_summary_state(sc, avp->chanctx);
1897 }
1898
1899 if ((changed & BSS_CHANGED_IBSS) ||
1900 (changed & BSS_CHANGED_OCB)) {
1901 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1902 common->curaid = bss_conf->aid;
1903 ath9k_hw_write_associd(sc->sc_ah);
1904 }
1905
1906 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1907 (changed & BSS_CHANGED_BEACON_INT) ||
1908 (changed & BSS_CHANGED_BEACON_INFO)) {
1909 ath9k_calculate_summary_state(sc, avp->chanctx);
1910 }
1911
1912 if ((avp->chanctx == sc->cur_chan) &&
1913 (changed & BSS_CHANGED_ERP_SLOT)) {
1914 if (bss_conf->use_short_slot)
1915 slottime = 9;
1916 else
1917 slottime = 20;
1918
1919 if (vif->type == NL80211_IFTYPE_AP) {
1920 /*
1921 * Defer update, so that connected stations can adjust
1922 * their settings at the same time.
1923 * See beacon.c for more details
1924 */
1925 sc->beacon.slottime = slottime;
1926 sc->beacon.updateslot = UPDATE;
1927 } else {
1928 ah->slottime = slottime;
1929 ath9k_hw_init_global_settings(ah);
1930 }
1931 }
1932
1933 if (changed & BSS_CHANGED_P2P_PS)
1934 ath9k_p2p_bss_info_changed(sc, vif);
1935
1936 if (changed & CHECK_ANI)
1937 ath_check_ani(sc);
1938
1939 if (changed & BSS_CHANGED_TXPOWER) {
1940 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1941 vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1942 ath9k_set_txpower(sc, vif);
1943 }
1944
1945 mutex_unlock(&sc->mutex);
1946 ath9k_ps_restore(sc);
1947
1948 #undef CHECK_ANI
1949 }
1950
ath9k_get_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1951 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1952 {
1953 struct ath_softc *sc = hw->priv;
1954 struct ath_vif *avp = (void *)vif->drv_priv;
1955 u64 tsf;
1956
1957 mutex_lock(&sc->mutex);
1958 ath9k_ps_wakeup(sc);
1959 /* Get current TSF either from HW or kernel time. */
1960 if (sc->cur_chan == avp->chanctx) {
1961 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1962 } else {
1963 tsf = sc->cur_chan->tsf_val +
1964 ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL);
1965 }
1966 tsf += le64_to_cpu(avp->tsf_adjust);
1967 ath9k_ps_restore(sc);
1968 mutex_unlock(&sc->mutex);
1969
1970 return tsf;
1971 }
1972
ath9k_set_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u64 tsf)1973 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1974 struct ieee80211_vif *vif,
1975 u64 tsf)
1976 {
1977 struct ath_softc *sc = hw->priv;
1978 struct ath_vif *avp = (void *)vif->drv_priv;
1979
1980 mutex_lock(&sc->mutex);
1981 ath9k_ps_wakeup(sc);
1982 tsf -= le64_to_cpu(avp->tsf_adjust);
1983 ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
1984 if (sc->cur_chan == avp->chanctx)
1985 ath9k_hw_settsf64(sc->sc_ah, tsf);
1986 avp->chanctx->tsf_val = tsf;
1987 ath9k_ps_restore(sc);
1988 mutex_unlock(&sc->mutex);
1989 }
1990
ath9k_reset_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif)1991 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1992 {
1993 struct ath_softc *sc = hw->priv;
1994 struct ath_vif *avp = (void *)vif->drv_priv;
1995
1996 mutex_lock(&sc->mutex);
1997
1998 ath9k_ps_wakeup(sc);
1999 ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
2000 if (sc->cur_chan == avp->chanctx)
2001 ath9k_hw_reset_tsf(sc->sc_ah);
2002 avp->chanctx->tsf_val = 0;
2003 ath9k_ps_restore(sc);
2004
2005 mutex_unlock(&sc->mutex);
2006 }
2007
ath9k_ampdu_action(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_ampdu_params * params)2008 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2009 struct ieee80211_vif *vif,
2010 struct ieee80211_ampdu_params *params)
2011 {
2012 struct ath_softc *sc = hw->priv;
2013 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2014 bool flush = false;
2015 int ret = 0;
2016 struct ieee80211_sta *sta = params->sta;
2017 struct ath_node *an = (struct ath_node *)sta->drv_priv;
2018 enum ieee80211_ampdu_mlme_action action = params->action;
2019 u16 tid = params->tid;
2020 u16 *ssn = ¶ms->ssn;
2021 struct ath_atx_tid *atid;
2022
2023 mutex_lock(&sc->mutex);
2024
2025 switch (action) {
2026 case IEEE80211_AMPDU_RX_START:
2027 break;
2028 case IEEE80211_AMPDU_RX_STOP:
2029 break;
2030 case IEEE80211_AMPDU_TX_START:
2031 if (ath9k_is_chanctx_enabled()) {
2032 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2033 ret = -EBUSY;
2034 break;
2035 }
2036 }
2037 ath9k_ps_wakeup(sc);
2038 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2039 if (!ret)
2040 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
2041 ath9k_ps_restore(sc);
2042 break;
2043 case IEEE80211_AMPDU_TX_STOP_FLUSH:
2044 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
2045 flush = true;
2046 fallthrough;
2047 case IEEE80211_AMPDU_TX_STOP_CONT:
2048 ath9k_ps_wakeup(sc);
2049 ath_tx_aggr_stop(sc, sta, tid);
2050 if (!flush)
2051 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2052 ath9k_ps_restore(sc);
2053 break;
2054 case IEEE80211_AMPDU_TX_OPERATIONAL:
2055 atid = ath_node_to_tid(an, tid);
2056 atid->baw_size = IEEE80211_MIN_AMPDU_BUF <<
2057 sta->ht_cap.ampdu_factor;
2058 break;
2059 default:
2060 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
2061 }
2062
2063 mutex_unlock(&sc->mutex);
2064
2065 return ret;
2066 }
2067
ath9k_get_survey(struct ieee80211_hw * hw,int idx,struct survey_info * survey)2068 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2069 struct survey_info *survey)
2070 {
2071 struct ath_softc *sc = hw->priv;
2072 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2073 struct ieee80211_supported_band *sband;
2074 struct ieee80211_channel *chan;
2075 unsigned long flags;
2076 int pos;
2077
2078 if (IS_ENABLED(CONFIG_ATH9K_TX99))
2079 return -EOPNOTSUPP;
2080
2081 spin_lock_irqsave(&common->cc_lock, flags);
2082 if (idx == 0)
2083 ath_update_survey_stats(sc);
2084
2085 sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
2086 if (sband && idx >= sband->n_channels) {
2087 idx -= sband->n_channels;
2088 sband = NULL;
2089 }
2090
2091 if (!sband)
2092 sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
2093
2094 if (!sband || idx >= sband->n_channels) {
2095 spin_unlock_irqrestore(&common->cc_lock, flags);
2096 return -ENOENT;
2097 }
2098
2099 chan = &sband->channels[idx];
2100 pos = chan->hw_value;
2101 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2102 survey->channel = chan;
2103 spin_unlock_irqrestore(&common->cc_lock, flags);
2104
2105 return 0;
2106 }
2107
ath9k_enable_dynack(struct ath_softc * sc)2108 static void ath9k_enable_dynack(struct ath_softc *sc)
2109 {
2110 #ifdef CONFIG_ATH9K_DYNACK
2111 u32 rfilt;
2112 struct ath_hw *ah = sc->sc_ah;
2113
2114 ath_dynack_reset(ah);
2115
2116 ah->dynack.enabled = true;
2117 rfilt = ath_calcrxfilter(sc);
2118 ath9k_hw_setrxfilter(ah, rfilt);
2119 #endif
2120 }
2121
ath9k_set_coverage_class(struct ieee80211_hw * hw,s16 coverage_class)2122 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
2123 s16 coverage_class)
2124 {
2125 struct ath_softc *sc = hw->priv;
2126 struct ath_hw *ah = sc->sc_ah;
2127
2128 if (IS_ENABLED(CONFIG_ATH9K_TX99))
2129 return;
2130
2131 mutex_lock(&sc->mutex);
2132
2133 if (coverage_class >= 0) {
2134 ah->coverage_class = coverage_class;
2135 if (ah->dynack.enabled) {
2136 u32 rfilt;
2137
2138 ah->dynack.enabled = false;
2139 rfilt = ath_calcrxfilter(sc);
2140 ath9k_hw_setrxfilter(ah, rfilt);
2141 }
2142 ath9k_ps_wakeup(sc);
2143 ath9k_hw_init_global_settings(ah);
2144 ath9k_ps_restore(sc);
2145 } else if (!ah->dynack.enabled) {
2146 ath9k_enable_dynack(sc);
2147 }
2148
2149 mutex_unlock(&sc->mutex);
2150 }
2151
ath9k_has_tx_pending(struct ath_softc * sc,bool sw_pending)2152 static bool ath9k_has_tx_pending(struct ath_softc *sc,
2153 bool sw_pending)
2154 {
2155 int i, npend = 0;
2156
2157 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2158 if (!ATH_TXQ_SETUP(sc, i))
2159 continue;
2160
2161 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2162 sw_pending);
2163 if (npend)
2164 break;
2165 }
2166
2167 return !!npend;
2168 }
2169
ath9k_flush(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u32 queues,bool drop)2170 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2171 u32 queues, bool drop)
2172 {
2173 struct ath_softc *sc = hw->priv;
2174 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2175
2176 if (ath9k_is_chanctx_enabled()) {
2177 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2178 goto flush;
2179
2180 /*
2181 * If MCC is active, extend the flush timeout
2182 * and wait for the HW/SW queues to become
2183 * empty. This needs to be done outside the
2184 * sc->mutex lock to allow the channel scheduler
2185 * to switch channel contexts.
2186 *
2187 * The vif queues have been stopped in mac80211,
2188 * so there won't be any incoming frames.
2189 */
2190 __ath9k_flush(hw, queues, drop, true, true);
2191 return;
2192 }
2193 flush:
2194 mutex_lock(&sc->mutex);
2195 __ath9k_flush(hw, queues, drop, true, false);
2196 mutex_unlock(&sc->mutex);
2197 }
2198
__ath9k_flush(struct ieee80211_hw * hw,u32 queues,bool drop,bool sw_pending,bool timeout_override)2199 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
2200 bool sw_pending, bool timeout_override)
2201 {
2202 struct ath_softc *sc = hw->priv;
2203 struct ath_hw *ah = sc->sc_ah;
2204 struct ath_common *common = ath9k_hw_common(ah);
2205 int timeout;
2206 bool drain_txq;
2207
2208 cancel_delayed_work_sync(&sc->hw_check_work);
2209
2210 if (ah->ah_flags & AH_UNPLUGGED) {
2211 ath_dbg(common, ANY, "Device has been unplugged!\n");
2212 return;
2213 }
2214
2215 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2216 ath_dbg(common, ANY, "Device not present\n");
2217 return;
2218 }
2219
2220 spin_lock_bh(&sc->chan_lock);
2221 if (timeout_override)
2222 timeout = HZ / 5;
2223 else
2224 timeout = sc->cur_chan->flush_timeout;
2225 spin_unlock_bh(&sc->chan_lock);
2226
2227 ath_dbg(common, CHAN_CTX,
2228 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2229
2230 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2231 timeout) > 0)
2232 drop = false;
2233
2234 if (drop) {
2235 ath9k_ps_wakeup(sc);
2236 spin_lock_bh(&sc->sc_pcu_lock);
2237 drain_txq = ath_drain_all_txq(sc);
2238 spin_unlock_bh(&sc->sc_pcu_lock);
2239
2240 if (!drain_txq)
2241 ath_reset(sc, NULL);
2242
2243 ath9k_ps_restore(sc);
2244 }
2245
2246 ieee80211_queue_delayed_work(hw, &sc->hw_check_work,
2247 msecs_to_jiffies(ATH_HW_CHECK_POLL_INT));
2248 }
2249
ath9k_tx_frames_pending(struct ieee80211_hw * hw)2250 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2251 {
2252 struct ath_softc *sc = hw->priv;
2253
2254 return ath9k_has_tx_pending(sc, true);
2255 }
2256
ath9k_tx_last_beacon(struct ieee80211_hw * hw)2257 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2258 {
2259 struct ath_softc *sc = hw->priv;
2260 struct ath_hw *ah = sc->sc_ah;
2261 struct ieee80211_vif *vif;
2262 struct ath_vif *avp;
2263 struct ath_buf *bf;
2264 struct ath_tx_status ts;
2265 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2266 int status;
2267
2268 vif = sc->beacon.bslot[0];
2269 if (!vif)
2270 return 0;
2271
2272 if (!vif->bss_conf.enable_beacon)
2273 return 0;
2274
2275 avp = (void *)vif->drv_priv;
2276
2277 if (!sc->beacon.tx_processed && !edma) {
2278 tasklet_disable(&sc->bcon_tasklet);
2279
2280 bf = avp->av_bcbuf;
2281 if (!bf || !bf->bf_mpdu)
2282 goto skip;
2283
2284 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2285 if (status == -EINPROGRESS)
2286 goto skip;
2287
2288 sc->beacon.tx_processed = true;
2289 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2290
2291 skip:
2292 tasklet_enable(&sc->bcon_tasklet);
2293 }
2294
2295 return sc->beacon.tx_last;
2296 }
2297
ath9k_get_stats(struct ieee80211_hw * hw,struct ieee80211_low_level_stats * stats)2298 static int ath9k_get_stats(struct ieee80211_hw *hw,
2299 struct ieee80211_low_level_stats *stats)
2300 {
2301 struct ath_softc *sc = hw->priv;
2302 struct ath_hw *ah = sc->sc_ah;
2303 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2304
2305 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2306 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2307 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2308 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2309 return 0;
2310 }
2311
fill_chainmask(u32 cap,u32 new)2312 static u32 fill_chainmask(u32 cap, u32 new)
2313 {
2314 u32 filled = 0;
2315 int i;
2316
2317 for (i = 0; cap && new; i++, cap >>= 1) {
2318 if (!(cap & BIT(0)))
2319 continue;
2320
2321 if (new & BIT(0))
2322 filled |= BIT(i);
2323
2324 new >>= 1;
2325 }
2326
2327 return filled;
2328 }
2329
validate_antenna_mask(struct ath_hw * ah,u32 val)2330 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2331 {
2332 if (AR_SREV_9300_20_OR_LATER(ah))
2333 return true;
2334
2335 switch (val & 0x7) {
2336 case 0x1:
2337 case 0x3:
2338 case 0x7:
2339 return true;
2340 case 0x2:
2341 return (ah->caps.rx_chainmask == 1);
2342 default:
2343 return false;
2344 }
2345 }
2346
ath9k_set_antenna(struct ieee80211_hw * hw,u32 tx_ant,u32 rx_ant)2347 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2348 {
2349 struct ath_softc *sc = hw->priv;
2350 struct ath_hw *ah = sc->sc_ah;
2351
2352 if (ah->caps.rx_chainmask != 1)
2353 rx_ant |= tx_ant;
2354
2355 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2356 return -EINVAL;
2357
2358 sc->ant_rx = rx_ant;
2359 sc->ant_tx = tx_ant;
2360
2361 if (ah->caps.rx_chainmask == 1)
2362 return 0;
2363
2364 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2365 if (AR_SREV_9100(ah))
2366 ah->rxchainmask = 0x7;
2367 else
2368 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2369
2370 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2371 ath9k_cmn_reload_chainmask(ah);
2372
2373 return 0;
2374 }
2375
ath9k_get_antenna(struct ieee80211_hw * hw,u32 * tx_ant,u32 * rx_ant)2376 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2377 {
2378 struct ath_softc *sc = hw->priv;
2379
2380 *tx_ant = sc->ant_tx;
2381 *rx_ant = sc->ant_rx;
2382 return 0;
2383 }
2384
ath9k_sw_scan_start(struct ieee80211_hw * hw,struct ieee80211_vif * vif,const u8 * mac_addr)2385 static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2386 struct ieee80211_vif *vif,
2387 const u8 *mac_addr)
2388 {
2389 struct ath_softc *sc = hw->priv;
2390 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2391 set_bit(ATH_OP_SCANNING, &common->op_flags);
2392 }
2393
ath9k_sw_scan_complete(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2394 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2395 struct ieee80211_vif *vif)
2396 {
2397 struct ath_softc *sc = hw->priv;
2398 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2399 clear_bit(ATH_OP_SCANNING, &common->op_flags);
2400 }
2401
2402 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2403
ath9k_cancel_pending_offchannel(struct ath_softc * sc)2404 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2405 {
2406 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2407
2408 if (sc->offchannel.roc_vif) {
2409 ath_dbg(common, CHAN_CTX,
2410 "%s: Aborting RoC\n", __func__);
2411
2412 del_timer_sync(&sc->offchannel.timer);
2413 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2414 ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
2415 }
2416
2417 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2418 ath_dbg(common, CHAN_CTX,
2419 "%s: Aborting HW scan\n", __func__);
2420
2421 del_timer_sync(&sc->offchannel.timer);
2422 ath_scan_complete(sc, true);
2423 }
2424 }
2425
ath9k_hw_scan(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_scan_request * hw_req)2426 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2427 struct ieee80211_scan_request *hw_req)
2428 {
2429 struct cfg80211_scan_request *req = &hw_req->req;
2430 struct ath_softc *sc = hw->priv;
2431 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2432 int ret = 0;
2433
2434 mutex_lock(&sc->mutex);
2435
2436 if (WARN_ON(sc->offchannel.scan_req)) {
2437 ret = -EBUSY;
2438 goto out;
2439 }
2440
2441 ath9k_ps_wakeup(sc);
2442 set_bit(ATH_OP_SCANNING, &common->op_flags);
2443 sc->offchannel.scan_vif = vif;
2444 sc->offchannel.scan_req = req;
2445 sc->offchannel.scan_idx = 0;
2446
2447 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2448 vif->addr);
2449
2450 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2451 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2452 ath_offchannel_next(sc);
2453 }
2454
2455 out:
2456 mutex_unlock(&sc->mutex);
2457
2458 return ret;
2459 }
2460
ath9k_cancel_hw_scan(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2461 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2462 struct ieee80211_vif *vif)
2463 {
2464 struct ath_softc *sc = hw->priv;
2465 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2466
2467 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2468
2469 mutex_lock(&sc->mutex);
2470 del_timer_sync(&sc->offchannel.timer);
2471 ath_scan_complete(sc, true);
2472 mutex_unlock(&sc->mutex);
2473 }
2474
ath9k_remain_on_channel(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_channel * chan,int duration,enum ieee80211_roc_type type)2475 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2476 struct ieee80211_vif *vif,
2477 struct ieee80211_channel *chan, int duration,
2478 enum ieee80211_roc_type type)
2479 {
2480 struct ath_softc *sc = hw->priv;
2481 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2482 int ret = 0;
2483
2484 mutex_lock(&sc->mutex);
2485
2486 if (WARN_ON(sc->offchannel.roc_vif)) {
2487 ret = -EBUSY;
2488 goto out;
2489 }
2490
2491 ath9k_ps_wakeup(sc);
2492 sc->offchannel.roc_vif = vif;
2493 sc->offchannel.roc_chan = chan;
2494 sc->offchannel.roc_duration = duration;
2495
2496 ath_dbg(common, CHAN_CTX,
2497 "RoC request on vif: %pM, type: %d duration: %d\n",
2498 vif->addr, type, duration);
2499
2500 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2501 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2502 ath_offchannel_next(sc);
2503 }
2504
2505 out:
2506 mutex_unlock(&sc->mutex);
2507
2508 return ret;
2509 }
2510
ath9k_cancel_remain_on_channel(struct ieee80211_hw * hw,struct ieee80211_vif * vif)2511 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw,
2512 struct ieee80211_vif *vif)
2513 {
2514 struct ath_softc *sc = hw->priv;
2515 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2516
2517 mutex_lock(&sc->mutex);
2518
2519 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2520 del_timer_sync(&sc->offchannel.timer);
2521
2522 if (sc->offchannel.roc_vif) {
2523 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2524 ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
2525 }
2526
2527 mutex_unlock(&sc->mutex);
2528
2529 return 0;
2530 }
2531
ath9k_add_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf)2532 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2533 struct ieee80211_chanctx_conf *conf)
2534 {
2535 struct ath_softc *sc = hw->priv;
2536 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2537 struct ath_chanctx *ctx, **ptr;
2538 int pos;
2539
2540 mutex_lock(&sc->mutex);
2541
2542 ath_for_each_chanctx(sc, ctx) {
2543 if (ctx->assigned)
2544 continue;
2545
2546 ptr = (void *) conf->drv_priv;
2547 *ptr = ctx;
2548 ctx->assigned = true;
2549 pos = ctx - &sc->chanctx[0];
2550 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2551
2552 ath_dbg(common, CHAN_CTX,
2553 "Add channel context: %d MHz\n",
2554 conf->def.chan->center_freq);
2555
2556 ath_chanctx_set_channel(sc, ctx, &conf->def);
2557
2558 mutex_unlock(&sc->mutex);
2559 return 0;
2560 }
2561
2562 mutex_unlock(&sc->mutex);
2563 return -ENOSPC;
2564 }
2565
2566
ath9k_remove_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf)2567 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2568 struct ieee80211_chanctx_conf *conf)
2569 {
2570 struct ath_softc *sc = hw->priv;
2571 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2572 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2573
2574 mutex_lock(&sc->mutex);
2575
2576 ath_dbg(common, CHAN_CTX,
2577 "Remove channel context: %d MHz\n",
2578 conf->def.chan->center_freq);
2579
2580 ctx->assigned = false;
2581 ctx->hw_queue_base = 0;
2582 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2583
2584 mutex_unlock(&sc->mutex);
2585 }
2586
ath9k_change_chanctx(struct ieee80211_hw * hw,struct ieee80211_chanctx_conf * conf,u32 changed)2587 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2588 struct ieee80211_chanctx_conf *conf,
2589 u32 changed)
2590 {
2591 struct ath_softc *sc = hw->priv;
2592 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2593 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2594
2595 mutex_lock(&sc->mutex);
2596 ath_dbg(common, CHAN_CTX,
2597 "Change channel context: %d MHz\n",
2598 conf->def.chan->center_freq);
2599 ath_chanctx_set_channel(sc, ctx, &conf->def);
2600 mutex_unlock(&sc->mutex);
2601 }
2602
ath9k_assign_vif_chanctx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_chanctx_conf * conf)2603 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2604 struct ieee80211_vif *vif,
2605 struct ieee80211_chanctx_conf *conf)
2606 {
2607 struct ath_softc *sc = hw->priv;
2608 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2609 struct ath_vif *avp = (void *)vif->drv_priv;
2610 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2611 int i;
2612
2613 ath9k_cancel_pending_offchannel(sc);
2614
2615 mutex_lock(&sc->mutex);
2616
2617 ath_dbg(common, CHAN_CTX,
2618 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2619 vif->addr, vif->type, vif->p2p,
2620 conf->def.chan->center_freq);
2621
2622 avp->chanctx = ctx;
2623 ctx->nvifs_assigned++;
2624 list_add_tail(&avp->list, &ctx->vifs);
2625 ath9k_calculate_summary_state(sc, ctx);
2626 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2627 vif->hw_queue[i] = ctx->hw_queue_base + i;
2628
2629 mutex_unlock(&sc->mutex);
2630
2631 return 0;
2632 }
2633
ath9k_unassign_vif_chanctx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_chanctx_conf * conf)2634 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2635 struct ieee80211_vif *vif,
2636 struct ieee80211_chanctx_conf *conf)
2637 {
2638 struct ath_softc *sc = hw->priv;
2639 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2640 struct ath_vif *avp = (void *)vif->drv_priv;
2641 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2642 int ac;
2643
2644 ath9k_cancel_pending_offchannel(sc);
2645
2646 mutex_lock(&sc->mutex);
2647
2648 ath_dbg(common, CHAN_CTX,
2649 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2650 vif->addr, vif->type, vif->p2p,
2651 conf->def.chan->center_freq);
2652
2653 avp->chanctx = NULL;
2654 ctx->nvifs_assigned--;
2655 list_del(&avp->list);
2656 ath9k_calculate_summary_state(sc, ctx);
2657 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2658 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2659
2660 mutex_unlock(&sc->mutex);
2661 }
2662
ath9k_mgd_prepare_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u16 duration)2663 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2664 struct ieee80211_vif *vif,
2665 u16 duration)
2666 {
2667 struct ath_softc *sc = hw->priv;
2668 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2669 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2670 struct ath_beacon_config *cur_conf;
2671 struct ath_chanctx *go_ctx;
2672 unsigned long timeout;
2673 bool changed = false;
2674 u32 beacon_int;
2675
2676 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2677 return;
2678
2679 if (!avp->chanctx)
2680 return;
2681
2682 mutex_lock(&sc->mutex);
2683
2684 spin_lock_bh(&sc->chan_lock);
2685 if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2686 changed = true;
2687 spin_unlock_bh(&sc->chan_lock);
2688
2689 if (!changed)
2690 goto out;
2691
2692 ath9k_cancel_pending_offchannel(sc);
2693
2694 go_ctx = ath_is_go_chanctx_present(sc);
2695
2696 if (go_ctx) {
2697 /*
2698 * Wait till the GO interface gets a chance
2699 * to send out an NoA.
2700 */
2701 spin_lock_bh(&sc->chan_lock);
2702 sc->sched.mgd_prepare_tx = true;
2703 cur_conf = &go_ctx->beacon;
2704 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2705 spin_unlock_bh(&sc->chan_lock);
2706
2707 timeout = usecs_to_jiffies(beacon_int * 2);
2708 init_completion(&sc->go_beacon);
2709
2710 mutex_unlock(&sc->mutex);
2711
2712 if (wait_for_completion_timeout(&sc->go_beacon,
2713 timeout) == 0) {
2714 ath_dbg(common, CHAN_CTX,
2715 "Failed to send new NoA\n");
2716
2717 spin_lock_bh(&sc->chan_lock);
2718 sc->sched.mgd_prepare_tx = false;
2719 spin_unlock_bh(&sc->chan_lock);
2720 }
2721
2722 mutex_lock(&sc->mutex);
2723 }
2724
2725 ath_dbg(common, CHAN_CTX,
2726 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2727 __func__, vif->addr);
2728
2729 spin_lock_bh(&sc->chan_lock);
2730 sc->next_chan = avp->chanctx;
2731 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2732 spin_unlock_bh(&sc->chan_lock);
2733
2734 ath_chanctx_set_next(sc, true);
2735 out:
2736 mutex_unlock(&sc->mutex);
2737 }
2738
ath9k_fill_chanctx_ops(void)2739 void ath9k_fill_chanctx_ops(void)
2740 {
2741 if (!ath9k_is_chanctx_enabled())
2742 return;
2743
2744 ath9k_ops.hw_scan = ath9k_hw_scan;
2745 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2746 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
2747 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2748 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2749 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2750 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2751 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2752 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
2753 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
2754 }
2755
2756 #endif
2757
ath9k_get_txpower(struct ieee80211_hw * hw,struct ieee80211_vif * vif,int * dbm)2758 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2759 int *dbm)
2760 {
2761 struct ath_softc *sc = hw->priv;
2762 struct ath_vif *avp = (void *)vif->drv_priv;
2763
2764 mutex_lock(&sc->mutex);
2765 if (avp->chanctx)
2766 *dbm = avp->chanctx->cur_txpower;
2767 else
2768 *dbm = sc->cur_chan->cur_txpower;
2769 mutex_unlock(&sc->mutex);
2770
2771 *dbm /= 2;
2772
2773 return 0;
2774 }
2775
2776 struct ieee80211_ops ath9k_ops = {
2777 .tx = ath9k_tx,
2778 .start = ath9k_start,
2779 .stop = ath9k_stop,
2780 .add_interface = ath9k_add_interface,
2781 .change_interface = ath9k_change_interface,
2782 .remove_interface = ath9k_remove_interface,
2783 .config = ath9k_config,
2784 .configure_filter = ath9k_configure_filter,
2785 .sta_state = ath9k_sta_state,
2786 .sta_notify = ath9k_sta_notify,
2787 .conf_tx = ath9k_conf_tx,
2788 .bss_info_changed = ath9k_bss_info_changed,
2789 .set_key = ath9k_set_key,
2790 .get_tsf = ath9k_get_tsf,
2791 .set_tsf = ath9k_set_tsf,
2792 .reset_tsf = ath9k_reset_tsf,
2793 .ampdu_action = ath9k_ampdu_action,
2794 .get_survey = ath9k_get_survey,
2795 .rfkill_poll = ath9k_rfkill_poll_state,
2796 .set_coverage_class = ath9k_set_coverage_class,
2797 .flush = ath9k_flush,
2798 .tx_frames_pending = ath9k_tx_frames_pending,
2799 .tx_last_beacon = ath9k_tx_last_beacon,
2800 .release_buffered_frames = ath9k_release_buffered_frames,
2801 .get_stats = ath9k_get_stats,
2802 .set_antenna = ath9k_set_antenna,
2803 .get_antenna = ath9k_get_antenna,
2804
2805 #ifdef CONFIG_ATH9K_WOW
2806 .suspend = ath9k_suspend,
2807 .resume = ath9k_resume,
2808 .set_wakeup = ath9k_set_wakeup,
2809 #endif
2810
2811 #ifdef CONFIG_ATH9K_DEBUGFS
2812 .get_et_sset_count = ath9k_get_et_sset_count,
2813 .get_et_stats = ath9k_get_et_stats,
2814 .get_et_strings = ath9k_get_et_strings,
2815 #endif
2816
2817 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2818 .sta_add_debugfs = ath9k_sta_add_debugfs,
2819 #endif
2820 .sw_scan_start = ath9k_sw_scan_start,
2821 .sw_scan_complete = ath9k_sw_scan_complete,
2822 .get_txpower = ath9k_get_txpower,
2823 .wake_tx_queue = ath9k_wake_tx_queue,
2824 };
2825