1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF 8
25 #define L_LTF 8
26 #define L_SIG 4
27 #define HT_SIG 8
28 #define HT_STF 4
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36
37
38 static u16 bits_per_symbol[][2] = {
39 /* 20MHz 40MHz */
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 };
49
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq,
54 struct ieee80211_sta *sta);
55 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
56 struct ath_txq *txq, struct list_head *bf_q,
57 struct ieee80211_sta *sta,
58 struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
63 int txok);
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
65 struct ath_buf *bf);
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
67 struct ath_txq *txq,
68 struct ath_atx_tid *tid,
69 struct sk_buff *skb);
70 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
71 struct ath_tx_control *txctl);
72
73 enum {
74 MCS_HT20,
75 MCS_HT20_SGI,
76 MCS_HT40,
77 MCS_HT40_SGI,
78 };
79
80 /*********************/
81 /* Aggregation logic */
82 /*********************/
83
ath_tx_status(struct ieee80211_hw * hw,struct sk_buff * skb)84 static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
85 {
86 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
87 struct ieee80211_sta *sta = info->status.status_driver_data[0];
88
89 if (info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS |
90 IEEE80211_TX_STATUS_EOSP)) {
91 ieee80211_tx_status(hw, skb);
92 return;
93 }
94
95 if (sta)
96 ieee80211_tx_status_noskb(hw, sta, info);
97
98 dev_kfree_skb(skb);
99 }
100
ath_txq_unlock_complete(struct ath_softc * sc,struct ath_txq * txq)101 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
102 __releases(&txq->axq_lock)
103 {
104 struct ieee80211_hw *hw = sc->hw;
105 struct sk_buff_head q;
106 struct sk_buff *skb;
107
108 __skb_queue_head_init(&q);
109 skb_queue_splice_init(&txq->complete_q, &q);
110 spin_unlock_bh(&txq->axq_lock);
111
112 while ((skb = __skb_dequeue(&q)))
113 ath_tx_status(hw, skb);
114 }
115
ath_tx_queue_tid(struct ath_softc * sc,struct ath_atx_tid * tid)116 void ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
117 {
118 struct ieee80211_txq *queue =
119 container_of((void *)tid, struct ieee80211_txq, drv_priv);
120
121 ieee80211_schedule_txq(sc->hw, queue);
122 }
123
ath9k_wake_tx_queue(struct ieee80211_hw * hw,struct ieee80211_txq * queue)124 void ath9k_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *queue)
125 {
126 struct ath_softc *sc = hw->priv;
127 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
128 struct ath_atx_tid *tid = (struct ath_atx_tid *) queue->drv_priv;
129 struct ath_txq *txq = tid->txq;
130
131 ath_dbg(common, QUEUE, "Waking TX queue: %pM (%d)\n",
132 queue->sta ? queue->sta->addr : queue->vif->addr,
133 tid->tidno);
134
135 ath_txq_lock(sc, txq);
136 ath_txq_schedule(sc, txq);
137 ath_txq_unlock(sc, txq);
138 }
139
get_frame_info(struct sk_buff * skb)140 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
141 {
142 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
143 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
144 sizeof(tx_info->status.status_driver_data));
145 return (struct ath_frame_info *) &tx_info->status.status_driver_data[0];
146 }
147
ath_send_bar(struct ath_atx_tid * tid,u16 seqno)148 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
149 {
150 if (!tid->an->sta)
151 return;
152
153 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
154 seqno << IEEE80211_SEQ_SEQ_SHIFT);
155 }
156
ath_set_rates(struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ath_buf * bf)157 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
158 struct ath_buf *bf)
159 {
160 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
161 ARRAY_SIZE(bf->rates));
162 }
163
ath_txq_skb_done(struct ath_softc * sc,struct ath_txq * txq,struct sk_buff * skb)164 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
165 struct sk_buff *skb)
166 {
167 struct ath_frame_info *fi = get_frame_info(skb);
168 int q = fi->txq;
169
170 if (q < 0)
171 return;
172
173 txq = sc->tx.txq_map[q];
174 if (WARN_ON(--txq->pending_frames < 0))
175 txq->pending_frames = 0;
176
177 }
178
179 static struct ath_atx_tid *
ath_get_skb_tid(struct ath_softc * sc,struct ath_node * an,struct sk_buff * skb)180 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
181 {
182 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
183 return ATH_AN_2_TID(an, tidno);
184 }
185
186 static int
ath_tid_pull(struct ath_atx_tid * tid,struct sk_buff ** skbuf)187 ath_tid_pull(struct ath_atx_tid *tid, struct sk_buff **skbuf)
188 {
189 struct ieee80211_txq *txq = container_of((void*)tid, struct ieee80211_txq, drv_priv);
190 struct ath_softc *sc = tid->an->sc;
191 struct ieee80211_hw *hw = sc->hw;
192 struct ath_tx_control txctl = {
193 .txq = tid->txq,
194 .sta = tid->an->sta,
195 };
196 struct sk_buff *skb;
197 struct ath_frame_info *fi;
198 int q, ret;
199
200 skb = ieee80211_tx_dequeue(hw, txq);
201 if (!skb)
202 return -ENOENT;
203
204 ret = ath_tx_prepare(hw, skb, &txctl);
205 if (ret) {
206 ieee80211_free_txskb(hw, skb);
207 return ret;
208 }
209
210 q = skb_get_queue_mapping(skb);
211 if (tid->txq == sc->tx.txq_map[q]) {
212 fi = get_frame_info(skb);
213 fi->txq = q;
214 ++tid->txq->pending_frames;
215 }
216
217 *skbuf = skb;
218 return 0;
219 }
220
ath_tid_dequeue(struct ath_atx_tid * tid,struct sk_buff ** skb)221 static int ath_tid_dequeue(struct ath_atx_tid *tid,
222 struct sk_buff **skb)
223 {
224 int ret = 0;
225 *skb = __skb_dequeue(&tid->retry_q);
226 if (!*skb)
227 ret = ath_tid_pull(tid, skb);
228
229 return ret;
230 }
231
ath_tx_flush_tid(struct ath_softc * sc,struct ath_atx_tid * tid)232 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
233 {
234 struct ath_txq *txq = tid->txq;
235 struct sk_buff *skb;
236 struct ath_buf *bf;
237 struct list_head bf_head;
238 struct ath_tx_status ts;
239 struct ath_frame_info *fi;
240 bool sendbar = false;
241
242 INIT_LIST_HEAD(&bf_head);
243
244 memset(&ts, 0, sizeof(ts));
245
246 while ((skb = __skb_dequeue(&tid->retry_q))) {
247 fi = get_frame_info(skb);
248 bf = fi->bf;
249 if (!bf) {
250 ath_txq_skb_done(sc, txq, skb);
251 ieee80211_free_txskb(sc->hw, skb);
252 continue;
253 }
254
255 if (fi->baw_tracked) {
256 ath_tx_update_baw(sc, tid, bf);
257 sendbar = true;
258 }
259
260 list_add_tail(&bf->list, &bf_head);
261 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
262 }
263
264 if (sendbar) {
265 ath_txq_unlock(sc, txq);
266 ath_send_bar(tid, tid->seq_start);
267 ath_txq_lock(sc, txq);
268 }
269 }
270
ath_tx_update_baw(struct ath_softc * sc,struct ath_atx_tid * tid,struct ath_buf * bf)271 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
272 struct ath_buf *bf)
273 {
274 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
275 u16 seqno = bf->bf_state.seqno;
276 int index, cindex;
277
278 if (!fi->baw_tracked)
279 return;
280
281 index = ATH_BA_INDEX(tid->seq_start, seqno);
282 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
283
284 __clear_bit(cindex, tid->tx_buf);
285
286 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
287 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
288 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
289 if (tid->bar_index >= 0)
290 tid->bar_index--;
291 }
292 }
293
ath_tx_addto_baw(struct ath_softc * sc,struct ath_atx_tid * tid,struct ath_buf * bf)294 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
295 struct ath_buf *bf)
296 {
297 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
298 u16 seqno = bf->bf_state.seqno;
299 int index, cindex;
300
301 if (fi->baw_tracked)
302 return;
303
304 index = ATH_BA_INDEX(tid->seq_start, seqno);
305 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
306 __set_bit(cindex, tid->tx_buf);
307 fi->baw_tracked = 1;
308
309 if (index >= ((tid->baw_tail - tid->baw_head) &
310 (ATH_TID_MAX_BUFS - 1))) {
311 tid->baw_tail = cindex;
312 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
313 }
314 }
315
ath_tid_drain(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid)316 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
317 struct ath_atx_tid *tid)
318
319 {
320 struct sk_buff *skb;
321 struct ath_buf *bf;
322 struct list_head bf_head;
323 struct ath_tx_status ts;
324 struct ath_frame_info *fi;
325 int ret;
326
327 memset(&ts, 0, sizeof(ts));
328 INIT_LIST_HEAD(&bf_head);
329
330 while ((ret = ath_tid_dequeue(tid, &skb)) == 0) {
331 fi = get_frame_info(skb);
332 bf = fi->bf;
333
334 if (!bf) {
335 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL);
336 continue;
337 }
338
339 list_add_tail(&bf->list, &bf_head);
340 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
341 }
342 }
343
ath_tx_set_retry(struct ath_softc * sc,struct ath_txq * txq,struct sk_buff * skb,int count)344 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
345 struct sk_buff *skb, int count)
346 {
347 struct ath_frame_info *fi = get_frame_info(skb);
348 struct ath_buf *bf = fi->bf;
349 struct ieee80211_hdr *hdr;
350 int prev = fi->retries;
351
352 TX_STAT_INC(sc, txq->axq_qnum, a_retries);
353 fi->retries += count;
354
355 if (prev > 0)
356 return;
357
358 hdr = (struct ieee80211_hdr *)skb->data;
359 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
360 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
361 sizeof(*hdr), DMA_TO_DEVICE);
362 }
363
ath_tx_get_buffer(struct ath_softc * sc)364 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
365 {
366 struct ath_buf *bf = NULL;
367
368 spin_lock_bh(&sc->tx.txbuflock);
369
370 if (unlikely(list_empty(&sc->tx.txbuf))) {
371 spin_unlock_bh(&sc->tx.txbuflock);
372 return NULL;
373 }
374
375 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
376 list_del(&bf->list);
377
378 spin_unlock_bh(&sc->tx.txbuflock);
379
380 return bf;
381 }
382
ath_tx_return_buffer(struct ath_softc * sc,struct ath_buf * bf)383 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
384 {
385 spin_lock_bh(&sc->tx.txbuflock);
386 list_add_tail(&bf->list, &sc->tx.txbuf);
387 spin_unlock_bh(&sc->tx.txbuflock);
388 }
389
ath_clone_txbuf(struct ath_softc * sc,struct ath_buf * bf)390 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
391 {
392 struct ath_buf *tbf;
393
394 tbf = ath_tx_get_buffer(sc);
395 if (WARN_ON(!tbf))
396 return NULL;
397
398 ATH_TXBUF_RESET(tbf);
399
400 tbf->bf_mpdu = bf->bf_mpdu;
401 tbf->bf_buf_addr = bf->bf_buf_addr;
402 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
403 tbf->bf_state = bf->bf_state;
404 tbf->bf_state.stale = false;
405
406 return tbf;
407 }
408
ath_tx_count_frames(struct ath_softc * sc,struct ath_buf * bf,struct ath_tx_status * ts,int txok,int * nframes,int * nbad)409 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
410 struct ath_tx_status *ts, int txok,
411 int *nframes, int *nbad)
412 {
413 u16 seq_st = 0;
414 u32 ba[WME_BA_BMP_SIZE >> 5];
415 int ba_index;
416 int isaggr = 0;
417
418 *nbad = 0;
419 *nframes = 0;
420
421 isaggr = bf_isaggr(bf);
422 if (isaggr) {
423 seq_st = ts->ts_seqnum;
424 memcpy(ba, &ts->ba, WME_BA_BMP_SIZE >> 3);
425 }
426
427 while (bf) {
428 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
429
430 (*nframes)++;
431 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
432 (*nbad)++;
433
434 bf = bf->bf_next;
435 }
436 }
437
438
ath_tx_complete_aggr(struct ath_softc * sc,struct ath_txq * txq,struct ath_buf * bf,struct list_head * bf_q,struct ieee80211_sta * sta,struct ath_atx_tid * tid,struct ath_tx_status * ts,int txok)439 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
440 struct ath_buf *bf, struct list_head *bf_q,
441 struct ieee80211_sta *sta,
442 struct ath_atx_tid *tid,
443 struct ath_tx_status *ts, int txok)
444 {
445 struct ath_node *an = NULL;
446 struct sk_buff *skb;
447 struct ieee80211_tx_info *tx_info;
448 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
449 struct list_head bf_head;
450 struct sk_buff_head bf_pending;
451 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
452 u32 ba[WME_BA_BMP_SIZE >> 5];
453 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
454 bool rc_update = true, isba;
455 struct ieee80211_tx_rate rates[4];
456 struct ath_frame_info *fi;
457 int nframes;
458 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
459 int i, retries;
460 int bar_index = -1;
461
462 skb = bf->bf_mpdu;
463 tx_info = IEEE80211_SKB_CB(skb);
464
465 memcpy(rates, bf->rates, sizeof(rates));
466
467 retries = ts->ts_longretry + 1;
468 for (i = 0; i < ts->ts_rateindex; i++)
469 retries += rates[i].count;
470
471 if (!sta) {
472 INIT_LIST_HEAD(&bf_head);
473 while (bf) {
474 bf_next = bf->bf_next;
475
476 if (!bf->bf_state.stale || bf_next != NULL)
477 list_move_tail(&bf->list, &bf_head);
478
479 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0);
480
481 bf = bf_next;
482 }
483 return;
484 }
485
486 an = (struct ath_node *)sta->drv_priv;
487 seq_first = tid->seq_start;
488 isba = ts->ts_flags & ATH9K_TX_BA;
489
490 /*
491 * The hardware occasionally sends a tx status for the wrong TID.
492 * In this case, the BA status cannot be considered valid and all
493 * subframes need to be retransmitted
494 *
495 * Only BlockAcks have a TID and therefore normal Acks cannot be
496 * checked
497 */
498 if (isba && tid->tidno != ts->tid)
499 txok = false;
500
501 isaggr = bf_isaggr(bf);
502 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
503
504 if (isaggr && txok) {
505 if (ts->ts_flags & ATH9K_TX_BA) {
506 seq_st = ts->ts_seqnum;
507 memcpy(ba, &ts->ba, WME_BA_BMP_SIZE >> 3);
508 } else {
509 /*
510 * AR5416 can become deaf/mute when BA
511 * issue happens. Chip needs to be reset.
512 * But AP code may have sychronization issues
513 * when perform internal reset in this routine.
514 * Only enable reset in STA mode for now.
515 */
516 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
517 needreset = 1;
518 }
519 }
520
521 __skb_queue_head_init(&bf_pending);
522
523 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
524 while (bf) {
525 u16 seqno = bf->bf_state.seqno;
526
527 txfail = txpending = sendbar = 0;
528 bf_next = bf->bf_next;
529
530 skb = bf->bf_mpdu;
531 tx_info = IEEE80211_SKB_CB(skb);
532 fi = get_frame_info(skb);
533
534 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
535 !tid->active) {
536 /*
537 * Outside of the current BlockAck window,
538 * maybe part of a previous session
539 */
540 txfail = 1;
541 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
542 /* transmit completion, subframe is
543 * acked by block ack */
544 acked_cnt++;
545 } else if (!isaggr && txok) {
546 /* transmit completion */
547 acked_cnt++;
548 } else if (flush) {
549 txpending = 1;
550 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
551 if (txok || !an->sleeping)
552 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
553 retries);
554
555 txpending = 1;
556 } else {
557 txfail = 1;
558 txfail_cnt++;
559 bar_index = max_t(int, bar_index,
560 ATH_BA_INDEX(seq_first, seqno));
561 }
562
563 /*
564 * Make sure the last desc is reclaimed if it
565 * not a holding desc.
566 */
567 INIT_LIST_HEAD(&bf_head);
568 if (bf_next != NULL || !bf_last->bf_state.stale)
569 list_move_tail(&bf->list, &bf_head);
570
571 if (!txpending) {
572 /*
573 * complete the acked-ones/xretried ones; update
574 * block-ack window
575 */
576 ath_tx_update_baw(sc, tid, bf);
577
578 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
579 memcpy(tx_info->control.rates, rates, sizeof(rates));
580 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
581 rc_update = false;
582 if (bf == bf->bf_lastbf)
583 ath_dynack_sample_tx_ts(sc->sc_ah,
584 bf->bf_mpdu,
585 ts, sta);
586 }
587
588 ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts,
589 !txfail);
590 } else {
591 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
592 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
593 ieee80211_sta_eosp(sta);
594 }
595 /* retry the un-acked ones */
596 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
597 struct ath_buf *tbf;
598
599 tbf = ath_clone_txbuf(sc, bf_last);
600 /*
601 * Update tx baw and complete the
602 * frame with failed status if we
603 * run out of tx buf.
604 */
605 if (!tbf) {
606 ath_tx_update_baw(sc, tid, bf);
607
608 ath_tx_complete_buf(sc, bf, txq,
609 &bf_head, NULL, ts,
610 0);
611 bar_index = max_t(int, bar_index,
612 ATH_BA_INDEX(seq_first, seqno));
613 break;
614 }
615
616 fi->bf = tbf;
617 }
618
619 /*
620 * Put this buffer to the temporary pending
621 * queue to retain ordering
622 */
623 __skb_queue_tail(&bf_pending, skb);
624 }
625
626 bf = bf_next;
627 }
628
629 /* prepend un-acked frames to the beginning of the pending frame queue */
630 if (!skb_queue_empty(&bf_pending)) {
631 if (an->sleeping)
632 ieee80211_sta_set_buffered(sta, tid->tidno, true);
633
634 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
635 if (!an->sleeping) {
636 ath_tx_queue_tid(sc, tid);
637 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
638 tid->clear_ps_filter = true;
639 }
640 }
641
642 if (bar_index >= 0) {
643 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
644
645 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
646 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
647
648 ath_txq_unlock(sc, txq);
649 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
650 ath_txq_lock(sc, txq);
651 }
652
653 if (needreset)
654 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
655 }
656
bf_is_ampdu_not_probing(struct ath_buf * bf)657 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
658 {
659 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
660 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
661 }
662
ath_tx_count_airtime(struct ath_softc * sc,struct ieee80211_sta * sta,struct ath_buf * bf,struct ath_tx_status * ts,u8 tid)663 static void ath_tx_count_airtime(struct ath_softc *sc,
664 struct ieee80211_sta *sta,
665 struct ath_buf *bf,
666 struct ath_tx_status *ts,
667 u8 tid)
668 {
669 u32 airtime = 0;
670 int i;
671
672 airtime += ts->duration * (ts->ts_longretry + 1);
673 for(i = 0; i < ts->ts_rateindex; i++) {
674 int rate_dur = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, i);
675 airtime += rate_dur * bf->rates[i].count;
676 }
677
678 ieee80211_sta_register_airtime(sta, tid, airtime, 0);
679 }
680
ath_tx_process_buffer(struct ath_softc * sc,struct ath_txq * txq,struct ath_tx_status * ts,struct ath_buf * bf,struct list_head * bf_head)681 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
682 struct ath_tx_status *ts, struct ath_buf *bf,
683 struct list_head *bf_head)
684 {
685 struct ieee80211_hw *hw = sc->hw;
686 struct ieee80211_tx_info *info;
687 struct ieee80211_sta *sta;
688 struct ieee80211_hdr *hdr;
689 struct ath_atx_tid *tid = NULL;
690 bool txok, flush;
691
692 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
693 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
694 txq->axq_tx_inprogress = false;
695
696 txq->axq_depth--;
697 if (bf_is_ampdu_not_probing(bf))
698 txq->axq_ampdu_depth--;
699
700 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc,
701 ts->ts_rateindex);
702
703 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
704 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
705 if (sta) {
706 struct ath_node *an = (struct ath_node *)sta->drv_priv;
707 tid = ath_get_skb_tid(sc, an, bf->bf_mpdu);
708 ath_tx_count_airtime(sc, sta, bf, ts, tid->tidno);
709 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
710 tid->clear_ps_filter = true;
711 }
712
713 if (!bf_isampdu(bf)) {
714 if (!flush) {
715 info = IEEE80211_SKB_CB(bf->bf_mpdu);
716 memcpy(info->control.rates, bf->rates,
717 sizeof(info->control.rates));
718 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
719 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts,
720 sta);
721 }
722 ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok);
723 } else
724 ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok);
725
726 if (!flush)
727 ath_txq_schedule(sc, txq);
728 }
729
ath_lookup_legacy(struct ath_buf * bf)730 static bool ath_lookup_legacy(struct ath_buf *bf)
731 {
732 struct sk_buff *skb;
733 struct ieee80211_tx_info *tx_info;
734 struct ieee80211_tx_rate *rates;
735 int i;
736
737 skb = bf->bf_mpdu;
738 tx_info = IEEE80211_SKB_CB(skb);
739 rates = tx_info->control.rates;
740
741 for (i = 0; i < 4; i++) {
742 if (!rates[i].count || rates[i].idx < 0)
743 break;
744
745 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
746 return true;
747 }
748
749 return false;
750 }
751
ath_lookup_rate(struct ath_softc * sc,struct ath_buf * bf,struct ath_atx_tid * tid)752 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
753 struct ath_atx_tid *tid)
754 {
755 struct sk_buff *skb;
756 struct ieee80211_tx_info *tx_info;
757 struct ieee80211_tx_rate *rates;
758 u32 max_4ms_framelen, frmlen;
759 u16 aggr_limit, bt_aggr_limit, legacy = 0;
760 int q = tid->txq->mac80211_qnum;
761 int i;
762
763 skb = bf->bf_mpdu;
764 tx_info = IEEE80211_SKB_CB(skb);
765 rates = bf->rates;
766
767 /*
768 * Find the lowest frame length among the rate series that will have a
769 * 4ms (or TXOP limited) transmit duration.
770 */
771 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
772
773 for (i = 0; i < 4; i++) {
774 int modeidx;
775
776 if (!rates[i].count)
777 continue;
778
779 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
780 legacy = 1;
781 break;
782 }
783
784 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
785 modeidx = MCS_HT40;
786 else
787 modeidx = MCS_HT20;
788
789 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
790 modeidx++;
791
792 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
793 max_4ms_framelen = min(max_4ms_framelen, frmlen);
794 }
795
796 /*
797 * limit aggregate size by the minimum rate if rate selected is
798 * not a probe rate, if rate selected is a probe rate then
799 * avoid aggregation of this packet.
800 */
801 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
802 return 0;
803
804 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
805
806 /*
807 * Override the default aggregation limit for BTCOEX.
808 */
809 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
810 if (bt_aggr_limit)
811 aggr_limit = bt_aggr_limit;
812
813 if (tid->an->maxampdu)
814 aggr_limit = min(aggr_limit, tid->an->maxampdu);
815
816 return aggr_limit;
817 }
818
819 /*
820 * Returns the number of delimiters to be added to
821 * meet the minimum required mpdudensity.
822 */
ath_compute_num_delims(struct ath_softc * sc,struct ath_atx_tid * tid,struct ath_buf * bf,u16 frmlen,bool first_subfrm)823 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
824 struct ath_buf *bf, u16 frmlen,
825 bool first_subfrm)
826 {
827 #define FIRST_DESC_NDELIMS 60
828 u32 nsymbits, nsymbols;
829 u16 minlen;
830 u8 flags, rix;
831 int width, streams, half_gi, ndelim, mindelim;
832 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
833
834 /* Select standard number of delimiters based on frame length alone */
835 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
836
837 /*
838 * If encryption enabled, hardware requires some more padding between
839 * subframes.
840 * TODO - this could be improved to be dependent on the rate.
841 * The hardware can keep up at lower rates, but not higher rates
842 */
843 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
844 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
845 ndelim += ATH_AGGR_ENCRYPTDELIM;
846
847 /*
848 * Add delimiter when using RTS/CTS with aggregation
849 * and non enterprise AR9003 card
850 */
851 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
852 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
853 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
854
855 /*
856 * Convert desired mpdu density from microeconds to bytes based
857 * on highest rate in rate series (i.e. first rate) to determine
858 * required minimum length for subframe. Take into account
859 * whether high rate is 20 or 40Mhz and half or full GI.
860 *
861 * If there is no mpdu density restriction, no further calculation
862 * is needed.
863 */
864
865 if (tid->an->mpdudensity == 0)
866 return ndelim;
867
868 rix = bf->rates[0].idx;
869 flags = bf->rates[0].flags;
870 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
871 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
872
873 if (half_gi)
874 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
875 else
876 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
877
878 if (nsymbols == 0)
879 nsymbols = 1;
880
881 streams = HT_RC_2_STREAMS(rix);
882 nsymbits = bits_per_symbol[rix % 8][width] * streams;
883 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
884
885 if (frmlen < minlen) {
886 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
887 ndelim = max(mindelim, ndelim);
888 }
889
890 return ndelim;
891 }
892
893 static int
ath_tx_get_tid_subframe(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid,struct ath_buf ** buf)894 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
895 struct ath_atx_tid *tid, struct ath_buf **buf)
896 {
897 struct ieee80211_tx_info *tx_info;
898 struct ath_frame_info *fi;
899 struct ath_buf *bf;
900 struct sk_buff *skb, *first_skb = NULL;
901 u16 seqno;
902 int ret;
903
904 while (1) {
905 ret = ath_tid_dequeue(tid, &skb);
906 if (ret < 0)
907 return ret;
908
909 fi = get_frame_info(skb);
910 bf = fi->bf;
911 if (!fi->bf)
912 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
913 else
914 bf->bf_state.stale = false;
915
916 if (!bf) {
917 ath_txq_skb_done(sc, txq, skb);
918 ieee80211_free_txskb(sc->hw, skb);
919 continue;
920 }
921
922 bf->bf_next = NULL;
923 bf->bf_lastbf = bf;
924
925 tx_info = IEEE80211_SKB_CB(skb);
926 tx_info->flags &= ~(IEEE80211_TX_CTL_CLEAR_PS_FILT |
927 IEEE80211_TX_STATUS_EOSP);
928
929 /*
930 * No aggregation session is running, but there may be frames
931 * from a previous session or a failed attempt in the queue.
932 * Send them out as normal data frames
933 */
934 if (!tid->active)
935 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
936
937 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
938 bf->bf_state.bf_type = 0;
939 break;
940 }
941
942 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
943 seqno = bf->bf_state.seqno;
944
945 /* do not step over block-ack window */
946 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
947 __skb_queue_tail(&tid->retry_q, skb);
948
949 /* If there are other skbs in the retry q, they are
950 * probably within the BAW, so loop immediately to get
951 * one of them. Otherwise the queue can get stuck. */
952 if (!skb_queue_is_first(&tid->retry_q, skb) &&
953 !WARN_ON(skb == first_skb)) {
954 if(!first_skb) /* infinite loop prevention */
955 first_skb = skb;
956 continue;
957 }
958 return -EINPROGRESS;
959 }
960
961 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
962 struct ath_tx_status ts = {};
963 struct list_head bf_head;
964
965 INIT_LIST_HEAD(&bf_head);
966 list_add(&bf->list, &bf_head);
967 ath_tx_update_baw(sc, tid, bf);
968 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
969 continue;
970 }
971
972 if (bf_isampdu(bf))
973 ath_tx_addto_baw(sc, tid, bf);
974
975 break;
976 }
977
978 *buf = bf;
979 return 0;
980 }
981
982 static int
ath_tx_form_aggr(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid,struct list_head * bf_q,struct ath_buf * bf_first)983 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
984 struct ath_atx_tid *tid, struct list_head *bf_q,
985 struct ath_buf *bf_first)
986 {
987 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
988 struct ath_buf *bf = bf_first, *bf_prev = NULL;
989 int nframes = 0, ndelim, ret;
990 u16 aggr_limit = 0, al = 0, bpad = 0,
991 al_delta, h_baw = tid->baw_size / 2;
992 struct ieee80211_tx_info *tx_info;
993 struct ath_frame_info *fi;
994 struct sk_buff *skb;
995
996
997 bf = bf_first;
998 aggr_limit = ath_lookup_rate(sc, bf, tid);
999
1000 while (bf)
1001 {
1002 skb = bf->bf_mpdu;
1003 fi = get_frame_info(skb);
1004
1005 /* do not exceed aggregation limit */
1006 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
1007 if (nframes) {
1008 if (aggr_limit < al + bpad + al_delta ||
1009 ath_lookup_legacy(bf) || nframes >= h_baw)
1010 goto stop;
1011
1012 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1013 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
1014 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
1015 goto stop;
1016 }
1017
1018 /* add padding for previous frame to aggregation length */
1019 al += bpad + al_delta;
1020
1021 /*
1022 * Get the delimiters needed to meet the MPDU
1023 * density for this node.
1024 */
1025 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
1026 !nframes);
1027 bpad = PADBYTES(al_delta) + (ndelim << 2);
1028
1029 nframes++;
1030 bf->bf_next = NULL;
1031
1032 /* link buffers of this frame to the aggregate */
1033 bf->bf_state.ndelim = ndelim;
1034
1035 list_add_tail(&bf->list, bf_q);
1036 if (bf_prev)
1037 bf_prev->bf_next = bf;
1038
1039 bf_prev = bf;
1040
1041 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1042 if (ret < 0)
1043 break;
1044 }
1045 goto finish;
1046 stop:
1047 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1048 finish:
1049 bf = bf_first;
1050 bf->bf_lastbf = bf_prev;
1051
1052 if (bf == bf_prev) {
1053 al = get_frame_info(bf->bf_mpdu)->framelen;
1054 bf->bf_state.bf_type = BUF_AMPDU;
1055 } else {
1056 TX_STAT_INC(sc, txq->axq_qnum, a_aggr);
1057 }
1058
1059 return al;
1060 #undef PADBYTES
1061 }
1062
1063 /*
1064 * rix - rate index
1065 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1066 * width - 0 for 20 MHz, 1 for 40 MHz
1067 * half_gi - to use 4us v/s 3.6 us for symbol time
1068 */
ath_pkt_duration(struct ath_softc * sc,u8 rix,int pktlen,int width,int half_gi,bool shortPreamble)1069 u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1070 int width, int half_gi, bool shortPreamble)
1071 {
1072 u32 nbits, nsymbits, duration, nsymbols;
1073 int streams;
1074
1075 /* find number of symbols: PLCP + data */
1076 streams = HT_RC_2_STREAMS(rix);
1077 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1078 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1079 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1080
1081 if (!half_gi)
1082 duration = SYMBOL_TIME(nsymbols);
1083 else
1084 duration = SYMBOL_TIME_HALFGI(nsymbols);
1085
1086 /* addup duration for legacy/ht training and signal fields */
1087 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1088
1089 return duration;
1090 }
1091
ath_max_framelen(int usec,int mcs,bool ht40,bool sgi)1092 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1093 {
1094 int streams = HT_RC_2_STREAMS(mcs);
1095 int symbols, bits;
1096 int bytes = 0;
1097
1098 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1099 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1100 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1101 bits -= OFDM_PLCP_BITS;
1102 bytes = bits / 8;
1103 if (bytes > 65532)
1104 bytes = 65532;
1105
1106 return bytes;
1107 }
1108
ath_update_max_aggr_framelen(struct ath_softc * sc,int queue,int txop)1109 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1110 {
1111 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1112 int mcs;
1113
1114 /* 4ms is the default (and maximum) duration */
1115 if (!txop || txop > 4096)
1116 txop = 4096;
1117
1118 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1119 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1120 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1121 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1122 for (mcs = 0; mcs < 32; mcs++) {
1123 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1124 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1125 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1126 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1127 }
1128 }
1129
ath_get_rate_txpower(struct ath_softc * sc,struct ath_buf * bf,u8 rateidx,bool is_40,bool is_cck)1130 static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf,
1131 u8 rateidx, bool is_40, bool is_cck)
1132 {
1133 u8 max_power;
1134 struct sk_buff *skb;
1135 struct ath_frame_info *fi;
1136 struct ieee80211_tx_info *info;
1137 struct ath_hw *ah = sc->sc_ah;
1138
1139 if (sc->tx99_state || !ah->tpc_enabled)
1140 return MAX_RATE_POWER;
1141
1142 skb = bf->bf_mpdu;
1143 fi = get_frame_info(skb);
1144 info = IEEE80211_SKB_CB(skb);
1145
1146 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1147 int txpower = fi->tx_power;
1148
1149 if (is_40) {
1150 u8 power_ht40delta;
1151 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1152 u16 eeprom_rev = ah->eep_ops->get_eeprom_rev(ah);
1153
1154 if (eeprom_rev >= AR5416_EEP_MINOR_VER_2) {
1155 bool is_2ghz;
1156 struct modal_eep_header *pmodal;
1157
1158 is_2ghz = info->band == NL80211_BAND_2GHZ;
1159 pmodal = &eep->modalHeader[is_2ghz];
1160 power_ht40delta = pmodal->ht40PowerIncForPdadc;
1161 } else {
1162 power_ht40delta = 2;
1163 }
1164 txpower += power_ht40delta;
1165 }
1166
1167 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) ||
1168 AR_SREV_9271(ah)) {
1169 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB;
1170 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
1171 s8 power_offset;
1172
1173 power_offset = ah->eep_ops->get_eeprom(ah,
1174 EEP_PWR_TABLE_OFFSET);
1175 txpower -= 2 * power_offset;
1176 }
1177
1178 if (OLC_FOR_AR9280_20_LATER && is_cck)
1179 txpower -= 2;
1180
1181 txpower = max(txpower, 0);
1182 max_power = min_t(u8, ah->tx_power[rateidx], txpower);
1183
1184 /* XXX: clamp minimum TX power at 1 for AR9160 since if
1185 * max_power is set to 0, frames are transmitted at max
1186 * TX power
1187 */
1188 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah))
1189 max_power = 1;
1190 } else if (!bf->bf_state.bfs_paprd) {
1191 if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC))
1192 max_power = min_t(u8, ah->tx_power_stbc[rateidx],
1193 fi->tx_power);
1194 else
1195 max_power = min_t(u8, ah->tx_power[rateidx],
1196 fi->tx_power);
1197 } else {
1198 max_power = ah->paprd_training_power;
1199 }
1200
1201 return max_power;
1202 }
1203
ath_buf_set_rate(struct ath_softc * sc,struct ath_buf * bf,struct ath_tx_info * info,int len,bool rts)1204 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1205 struct ath_tx_info *info, int len, bool rts)
1206 {
1207 struct ath_hw *ah = sc->sc_ah;
1208 struct ath_common *common = ath9k_hw_common(ah);
1209 struct sk_buff *skb;
1210 struct ieee80211_tx_info *tx_info;
1211 struct ieee80211_tx_rate *rates;
1212 const struct ieee80211_rate *rate;
1213 struct ieee80211_hdr *hdr;
1214 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1215 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1216 int i;
1217 u8 rix = 0;
1218
1219 skb = bf->bf_mpdu;
1220 tx_info = IEEE80211_SKB_CB(skb);
1221 rates = bf->rates;
1222 hdr = (struct ieee80211_hdr *)skb->data;
1223
1224 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1225 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1226 info->rtscts_rate = fi->rtscts_rate;
1227
1228 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1229 bool is_40, is_sgi, is_sp, is_cck;
1230 int phy;
1231
1232 if (!rates[i].count || (rates[i].idx < 0))
1233 continue;
1234
1235 rix = rates[i].idx;
1236 info->rates[i].Tries = rates[i].count;
1237
1238 /*
1239 * Handle RTS threshold for unaggregated HT frames.
1240 */
1241 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1242 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1243 unlikely(rts_thresh != (u32) -1)) {
1244 if (!rts_thresh || (len > rts_thresh))
1245 rts = true;
1246 }
1247
1248 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1249 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1250 info->flags |= ATH9K_TXDESC_RTSENA;
1251 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1252 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1253 info->flags |= ATH9K_TXDESC_CTSENA;
1254 }
1255
1256 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1257 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1258 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1259 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1260
1261 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1262 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1263 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1264
1265 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1266 /* MCS rates */
1267 info->rates[i].Rate = rix | 0x80;
1268 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1269 ah->txchainmask, info->rates[i].Rate);
1270 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1271 is_40, is_sgi, is_sp);
1272 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1273 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1274 if (rix >= 8 && fi->dyn_smps) {
1275 info->rates[i].RateFlags |=
1276 ATH9K_RATESERIES_RTS_CTS;
1277 info->flags |= ATH9K_TXDESC_CTSENA;
1278 }
1279
1280 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix,
1281 is_40, false);
1282 continue;
1283 }
1284
1285 /* legacy rates */
1286 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1287 if ((tx_info->band == NL80211_BAND_2GHZ) &&
1288 !(rate->flags & IEEE80211_RATE_ERP_G))
1289 phy = WLAN_RC_PHY_CCK;
1290 else
1291 phy = WLAN_RC_PHY_OFDM;
1292
1293 info->rates[i].Rate = rate->hw_value;
1294 if (rate->hw_value_short) {
1295 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1296 info->rates[i].Rate |= rate->hw_value_short;
1297 } else {
1298 is_sp = false;
1299 }
1300
1301 if (bf->bf_state.bfs_paprd)
1302 info->rates[i].ChSel = ah->txchainmask;
1303 else
1304 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1305 ah->txchainmask, info->rates[i].Rate);
1306
1307 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1308 phy, rate->bitrate * 100, len, rix, is_sp);
1309
1310 is_cck = IS_CCK_RATE(info->rates[i].Rate);
1311 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false,
1312 is_cck);
1313 }
1314
1315 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1316 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1317 info->flags &= ~ATH9K_TXDESC_RTSENA;
1318
1319 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1320 if (info->flags & ATH9K_TXDESC_RTSENA)
1321 info->flags &= ~ATH9K_TXDESC_CTSENA;
1322 }
1323
get_hw_packet_type(struct sk_buff * skb)1324 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1325 {
1326 struct ieee80211_hdr *hdr;
1327 enum ath9k_pkt_type htype;
1328 __le16 fc;
1329
1330 hdr = (struct ieee80211_hdr *)skb->data;
1331 fc = hdr->frame_control;
1332
1333 if (ieee80211_is_beacon(fc))
1334 htype = ATH9K_PKT_TYPE_BEACON;
1335 else if (ieee80211_is_probe_resp(fc))
1336 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1337 else if (ieee80211_is_atim(fc))
1338 htype = ATH9K_PKT_TYPE_ATIM;
1339 else if (ieee80211_is_pspoll(fc))
1340 htype = ATH9K_PKT_TYPE_PSPOLL;
1341 else
1342 htype = ATH9K_PKT_TYPE_NORMAL;
1343
1344 return htype;
1345 }
1346
ath_tx_fill_desc(struct ath_softc * sc,struct ath_buf * bf,struct ath_txq * txq,int len)1347 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1348 struct ath_txq *txq, int len)
1349 {
1350 struct ath_hw *ah = sc->sc_ah;
1351 struct ath_buf *bf_first = NULL;
1352 struct ath_tx_info info;
1353 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1354 bool rts = false;
1355
1356 memset(&info, 0, sizeof(info));
1357 info.is_first = true;
1358 info.is_last = true;
1359 info.qcu = txq->axq_qnum;
1360
1361 while (bf) {
1362 struct sk_buff *skb = bf->bf_mpdu;
1363 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1364 struct ath_frame_info *fi = get_frame_info(skb);
1365 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1366
1367 info.type = get_hw_packet_type(skb);
1368 if (bf->bf_next)
1369 info.link = bf->bf_next->bf_daddr;
1370 else
1371 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1372
1373 if (!bf_first) {
1374 bf_first = bf;
1375
1376 if (!sc->tx99_state)
1377 info.flags = ATH9K_TXDESC_INTREQ;
1378 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1379 txq == sc->tx.uapsdq)
1380 info.flags |= ATH9K_TXDESC_CLRDMASK;
1381
1382 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1383 info.flags |= ATH9K_TXDESC_NOACK;
1384 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1385 info.flags |= ATH9K_TXDESC_LDPC;
1386
1387 if (bf->bf_state.bfs_paprd)
1388 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1389 ATH9K_TXDESC_PAPRD_S;
1390
1391 /*
1392 * mac80211 doesn't handle RTS threshold for HT because
1393 * the decision has to be taken based on AMPDU length
1394 * and aggregation is done entirely inside ath9k.
1395 * Set the RTS/CTS flag for the first subframe based
1396 * on the threshold.
1397 */
1398 if (aggr && (bf == bf_first) &&
1399 unlikely(rts_thresh != (u32) -1)) {
1400 /*
1401 * "len" is the size of the entire AMPDU.
1402 */
1403 if (!rts_thresh || (len > rts_thresh))
1404 rts = true;
1405 }
1406
1407 if (!aggr)
1408 len = fi->framelen;
1409
1410 ath_buf_set_rate(sc, bf, &info, len, rts);
1411 }
1412
1413 info.buf_addr[0] = bf->bf_buf_addr;
1414 info.buf_len[0] = skb->len;
1415 info.pkt_len = fi->framelen;
1416 info.keyix = fi->keyix;
1417 info.keytype = fi->keytype;
1418
1419 if (aggr) {
1420 if (bf == bf_first)
1421 info.aggr = AGGR_BUF_FIRST;
1422 else if (bf == bf_first->bf_lastbf)
1423 info.aggr = AGGR_BUF_LAST;
1424 else
1425 info.aggr = AGGR_BUF_MIDDLE;
1426
1427 info.ndelim = bf->bf_state.ndelim;
1428 info.aggr_len = len;
1429 }
1430
1431 if (bf == bf_first->bf_lastbf)
1432 bf_first = NULL;
1433
1434 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1435 bf = bf->bf_next;
1436 }
1437 }
1438
1439 static void
ath_tx_form_burst(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid,struct list_head * bf_q,struct ath_buf * bf_first)1440 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1441 struct ath_atx_tid *tid, struct list_head *bf_q,
1442 struct ath_buf *bf_first)
1443 {
1444 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1445 int nframes = 0, ret;
1446
1447 do {
1448 struct ieee80211_tx_info *tx_info;
1449
1450 nframes++;
1451 list_add_tail(&bf->list, bf_q);
1452 if (bf_prev)
1453 bf_prev->bf_next = bf;
1454 bf_prev = bf;
1455
1456 if (nframes >= 2)
1457 break;
1458
1459 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1460 if (ret < 0)
1461 break;
1462
1463 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1464 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1465 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1466 break;
1467 }
1468
1469 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1470 } while (1);
1471 }
1472
ath_tx_sched_aggr(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid)1473 static int ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1474 struct ath_atx_tid *tid)
1475 {
1476 struct ath_buf *bf = NULL;
1477 struct ieee80211_tx_info *tx_info;
1478 struct list_head bf_q;
1479 int aggr_len = 0, ret;
1480 bool aggr;
1481
1482 INIT_LIST_HEAD(&bf_q);
1483
1484 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf);
1485 if (ret < 0)
1486 return ret;
1487
1488 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1489 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1490 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1491 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1492 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1493 return -EBUSY;
1494 }
1495
1496 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1497 if (aggr)
1498 aggr_len = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf);
1499 else
1500 ath_tx_form_burst(sc, txq, tid, &bf_q, bf);
1501
1502 if (list_empty(&bf_q))
1503 return -EAGAIN;
1504
1505 if (tid->clear_ps_filter || tid->an->no_ps_filter) {
1506 tid->clear_ps_filter = false;
1507 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1508 }
1509
1510 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1511 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1512 return 0;
1513 }
1514
ath_tx_aggr_start(struct ath_softc * sc,struct ieee80211_sta * sta,u16 tid,u16 * ssn)1515 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1516 u16 tid, u16 *ssn)
1517 {
1518 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1519 struct ath_atx_tid *txtid;
1520 struct ath_txq *txq;
1521 struct ath_node *an;
1522 u8 density;
1523
1524 ath_dbg(common, XMIT, "%s called\n", __func__);
1525
1526 an = (struct ath_node *)sta->drv_priv;
1527 txtid = ATH_AN_2_TID(an, tid);
1528 txq = txtid->txq;
1529
1530 ath_txq_lock(sc, txq);
1531
1532 /* update ampdu factor/density, they may have changed. This may happen
1533 * in HT IBSS when a beacon with HT-info is received after the station
1534 * has already been added.
1535 */
1536 if (sta->ht_cap.ht_supported) {
1537 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1538 sta->ht_cap.ampdu_factor)) - 1;
1539 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1540 an->mpdudensity = density;
1541 }
1542
1543 txtid->active = true;
1544 *ssn = txtid->seq_start = txtid->seq_next;
1545 txtid->bar_index = -1;
1546
1547 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1548 txtid->baw_head = txtid->baw_tail = 0;
1549
1550 ath_txq_unlock_complete(sc, txq);
1551
1552 return 0;
1553 }
1554
ath_tx_aggr_stop(struct ath_softc * sc,struct ieee80211_sta * sta,u16 tid)1555 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1556 {
1557 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1558 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1559 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1560 struct ath_txq *txq = txtid->txq;
1561
1562 ath_dbg(common, XMIT, "%s called\n", __func__);
1563
1564 ath_txq_lock(sc, txq);
1565 txtid->active = false;
1566 ath_tx_flush_tid(sc, txtid);
1567 ath_txq_unlock_complete(sc, txq);
1568 }
1569
ath_tx_aggr_sleep(struct ieee80211_sta * sta,struct ath_softc * sc,struct ath_node * an)1570 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1571 struct ath_node *an)
1572 {
1573 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1574 struct ath_atx_tid *tid;
1575 int tidno;
1576
1577 ath_dbg(common, XMIT, "%s called\n", __func__);
1578
1579 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1580 tid = ath_node_to_tid(an, tidno);
1581
1582 if (!skb_queue_empty(&tid->retry_q))
1583 ieee80211_sta_set_buffered(sta, tid->tidno, true);
1584
1585 }
1586 }
1587
ath_tx_aggr_wakeup(struct ath_softc * sc,struct ath_node * an)1588 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1589 {
1590 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1591 struct ath_atx_tid *tid;
1592 struct ath_txq *txq;
1593 int tidno;
1594
1595 ath_dbg(common, XMIT, "%s called\n", __func__);
1596
1597 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1598 tid = ath_node_to_tid(an, tidno);
1599 txq = tid->txq;
1600
1601 ath_txq_lock(sc, txq);
1602 tid->clear_ps_filter = true;
1603 if (!skb_queue_empty(&tid->retry_q)) {
1604 ath_tx_queue_tid(sc, tid);
1605 ath_txq_schedule(sc, txq);
1606 }
1607 ath_txq_unlock_complete(sc, txq);
1608
1609 }
1610 }
1611
1612
1613 static void
ath9k_set_moredata(struct ath_softc * sc,struct ath_buf * bf,bool val)1614 ath9k_set_moredata(struct ath_softc *sc, struct ath_buf *bf, bool val)
1615 {
1616 struct ieee80211_hdr *hdr;
1617 u16 mask = cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1618 u16 mask_val = mask * val;
1619
1620 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
1621 if ((hdr->frame_control & mask) != mask_val) {
1622 hdr->frame_control = (hdr->frame_control & ~mask) | mask_val;
1623 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
1624 sizeof(*hdr), DMA_TO_DEVICE);
1625 }
1626 }
1627
ath9k_release_buffered_frames(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u16 tids,int nframes,enum ieee80211_frame_release_type reason,bool more_data)1628 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1629 struct ieee80211_sta *sta,
1630 u16 tids, int nframes,
1631 enum ieee80211_frame_release_type reason,
1632 bool more_data)
1633 {
1634 struct ath_softc *sc = hw->priv;
1635 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1636 struct ath_txq *txq = sc->tx.uapsdq;
1637 struct ieee80211_tx_info *info;
1638 struct list_head bf_q;
1639 struct ath_buf *bf_tail = NULL, *bf = NULL;
1640 int sent = 0;
1641 int i, ret;
1642
1643 INIT_LIST_HEAD(&bf_q);
1644 for (i = 0; tids && nframes; i++, tids >>= 1) {
1645 struct ath_atx_tid *tid;
1646
1647 if (!(tids & 1))
1648 continue;
1649
1650 tid = ATH_AN_2_TID(an, i);
1651
1652 ath_txq_lock(sc, tid->txq);
1653 while (nframes > 0) {
1654 ret = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq,
1655 tid, &bf);
1656 if (ret < 0)
1657 break;
1658
1659 ath9k_set_moredata(sc, bf, true);
1660 list_add_tail(&bf->list, &bf_q);
1661 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1662 if (bf_isampdu(bf))
1663 bf->bf_state.bf_type &= ~BUF_AGGR;
1664 if (bf_tail)
1665 bf_tail->bf_next = bf;
1666
1667 bf_tail = bf;
1668 nframes--;
1669 sent++;
1670 TX_STAT_INC(sc, txq->axq_qnum, a_queued_hw);
1671
1672 if (an->sta && skb_queue_empty(&tid->retry_q))
1673 ieee80211_sta_set_buffered(an->sta, i, false);
1674 }
1675 ath_txq_unlock_complete(sc, tid->txq);
1676 }
1677
1678 if (list_empty(&bf_q))
1679 return;
1680
1681 if (!more_data)
1682 ath9k_set_moredata(sc, bf_tail, false);
1683
1684 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1685 info->flags |= IEEE80211_TX_STATUS_EOSP;
1686
1687 bf = list_first_entry(&bf_q, struct ath_buf, list);
1688 ath_txq_lock(sc, txq);
1689 ath_tx_fill_desc(sc, bf, txq, 0);
1690 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1691 ath_txq_unlock(sc, txq);
1692 }
1693
1694 /********************/
1695 /* Queue Management */
1696 /********************/
1697
ath_txq_setup(struct ath_softc * sc,int qtype,int subtype)1698 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1699 {
1700 struct ath_hw *ah = sc->sc_ah;
1701 struct ath9k_tx_queue_info qi;
1702 static const int subtype_txq_to_hwq[] = {
1703 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1704 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1705 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1706 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1707 };
1708 int axq_qnum, i;
1709
1710 memset(&qi, 0, sizeof(qi));
1711 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1712 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1713 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1714 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1715 qi.tqi_physCompBuf = 0;
1716
1717 /*
1718 * Enable interrupts only for EOL and DESC conditions.
1719 * We mark tx descriptors to receive a DESC interrupt
1720 * when a tx queue gets deep; otherwise waiting for the
1721 * EOL to reap descriptors. Note that this is done to
1722 * reduce interrupt load and this only defers reaping
1723 * descriptors, never transmitting frames. Aside from
1724 * reducing interrupts this also permits more concurrency.
1725 * The only potential downside is if the tx queue backs
1726 * up in which case the top half of the kernel may backup
1727 * due to a lack of tx descriptors.
1728 *
1729 * The UAPSD queue is an exception, since we take a desc-
1730 * based intr on the EOSP frames.
1731 */
1732 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1733 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1734 } else {
1735 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1736 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1737 else
1738 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1739 TXQ_FLAG_TXDESCINT_ENABLE;
1740 }
1741 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1742 if (axq_qnum == -1) {
1743 /*
1744 * NB: don't print a message, this happens
1745 * normally on parts with too few tx queues
1746 */
1747 return NULL;
1748 }
1749 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1750 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1751
1752 txq->axq_qnum = axq_qnum;
1753 txq->mac80211_qnum = -1;
1754 txq->axq_link = NULL;
1755 __skb_queue_head_init(&txq->complete_q);
1756 INIT_LIST_HEAD(&txq->axq_q);
1757 spin_lock_init(&txq->axq_lock);
1758 txq->axq_depth = 0;
1759 txq->axq_ampdu_depth = 0;
1760 txq->axq_tx_inprogress = false;
1761 sc->tx.txqsetup |= 1<<axq_qnum;
1762
1763 txq->txq_headidx = txq->txq_tailidx = 0;
1764 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1765 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1766 }
1767 return &sc->tx.txq[axq_qnum];
1768 }
1769
ath_txq_update(struct ath_softc * sc,int qnum,struct ath9k_tx_queue_info * qinfo)1770 int ath_txq_update(struct ath_softc *sc, int qnum,
1771 struct ath9k_tx_queue_info *qinfo)
1772 {
1773 struct ath_hw *ah = sc->sc_ah;
1774 int error = 0;
1775 struct ath9k_tx_queue_info qi;
1776
1777 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1778
1779 ath9k_hw_get_txq_props(ah, qnum, &qi);
1780 qi.tqi_aifs = qinfo->tqi_aifs;
1781 qi.tqi_cwmin = qinfo->tqi_cwmin;
1782 qi.tqi_cwmax = qinfo->tqi_cwmax;
1783 qi.tqi_burstTime = qinfo->tqi_burstTime;
1784 qi.tqi_readyTime = qinfo->tqi_readyTime;
1785
1786 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1787 ath_err(ath9k_hw_common(sc->sc_ah),
1788 "Unable to update hardware queue %u!\n", qnum);
1789 error = -EIO;
1790 } else {
1791 ath9k_hw_resettxqueue(ah, qnum);
1792 }
1793
1794 return error;
1795 }
1796
ath_cabq_update(struct ath_softc * sc)1797 int ath_cabq_update(struct ath_softc *sc)
1798 {
1799 struct ath9k_tx_queue_info qi;
1800 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1801 int qnum = sc->beacon.cabq->axq_qnum;
1802
1803 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1804
1805 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1806 ATH_CABQ_READY_TIME) / 100;
1807 ath_txq_update(sc, qnum, &qi);
1808
1809 return 0;
1810 }
1811
ath_drain_txq_list(struct ath_softc * sc,struct ath_txq * txq,struct list_head * list)1812 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1813 struct list_head *list)
1814 {
1815 struct ath_buf *bf, *lastbf;
1816 struct list_head bf_head;
1817 struct ath_tx_status ts;
1818
1819 memset(&ts, 0, sizeof(ts));
1820 ts.ts_status = ATH9K_TX_FLUSH;
1821 INIT_LIST_HEAD(&bf_head);
1822
1823 while (!list_empty(list)) {
1824 bf = list_first_entry(list, struct ath_buf, list);
1825
1826 if (bf->bf_state.stale) {
1827 list_del(&bf->list);
1828
1829 ath_tx_return_buffer(sc, bf);
1830 continue;
1831 }
1832
1833 lastbf = bf->bf_lastbf;
1834 list_cut_position(&bf_head, list, &lastbf->list);
1835 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1836 }
1837 }
1838
1839 /*
1840 * Drain a given TX queue (could be Beacon or Data)
1841 *
1842 * This assumes output has been stopped and
1843 * we do not need to block ath_tx_tasklet.
1844 */
ath_draintxq(struct ath_softc * sc,struct ath_txq * txq)1845 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1846 {
1847 rcu_read_lock();
1848 ath_txq_lock(sc, txq);
1849
1850 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1851 int idx = txq->txq_tailidx;
1852
1853 while (!list_empty(&txq->txq_fifo[idx])) {
1854 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1855
1856 INCR(idx, ATH_TXFIFO_DEPTH);
1857 }
1858 txq->txq_tailidx = idx;
1859 }
1860
1861 txq->axq_link = NULL;
1862 txq->axq_tx_inprogress = false;
1863 ath_drain_txq_list(sc, txq, &txq->axq_q);
1864
1865 ath_txq_unlock_complete(sc, txq);
1866 rcu_read_unlock();
1867 }
1868
ath_drain_all_txq(struct ath_softc * sc)1869 bool ath_drain_all_txq(struct ath_softc *sc)
1870 {
1871 struct ath_hw *ah = sc->sc_ah;
1872 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1873 struct ath_txq *txq;
1874 int i;
1875 u32 npend = 0;
1876
1877 if (test_bit(ATH_OP_INVALID, &common->op_flags))
1878 return true;
1879
1880 ath9k_hw_abort_tx_dma(ah);
1881
1882 /* Check if any queue remains active */
1883 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1884 if (!ATH_TXQ_SETUP(sc, i))
1885 continue;
1886
1887 if (!sc->tx.txq[i].axq_depth)
1888 continue;
1889
1890 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1891 npend |= BIT(i);
1892 }
1893
1894 if (npend) {
1895 RESET_STAT_INC(sc, RESET_TX_DMA_ERROR);
1896 ath_dbg(common, RESET,
1897 "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1898 }
1899
1900 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1901 if (!ATH_TXQ_SETUP(sc, i))
1902 continue;
1903
1904 txq = &sc->tx.txq[i];
1905 ath_draintxq(sc, txq);
1906 }
1907
1908 return !npend;
1909 }
1910
ath_tx_cleanupq(struct ath_softc * sc,struct ath_txq * txq)1911 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1912 {
1913 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1914 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1915 }
1916
1917 /* For each acq entry, for each tid, try to schedule packets
1918 * for transmit until ampdu_depth has reached min Q depth.
1919 */
ath_txq_schedule(struct ath_softc * sc,struct ath_txq * txq)1920 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1921 {
1922 struct ieee80211_hw *hw = sc->hw;
1923 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1924 struct ieee80211_txq *queue;
1925 struct ath_atx_tid *tid;
1926 int ret;
1927
1928 if (txq->mac80211_qnum < 0)
1929 return;
1930
1931 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
1932 return;
1933
1934 ieee80211_txq_schedule_start(hw, txq->mac80211_qnum);
1935 spin_lock_bh(&sc->chan_lock);
1936 rcu_read_lock();
1937
1938 if (sc->cur_chan->stopped)
1939 goto out;
1940
1941 while ((queue = ieee80211_next_txq(hw, txq->mac80211_qnum))) {
1942 bool force;
1943
1944 tid = (struct ath_atx_tid *)queue->drv_priv;
1945
1946 ret = ath_tx_sched_aggr(sc, txq, tid);
1947 ath_dbg(common, QUEUE, "ath_tx_sched_aggr returned %d\n", ret);
1948
1949 force = !skb_queue_empty(&tid->retry_q);
1950 ieee80211_return_txq(hw, queue, force);
1951 }
1952
1953 out:
1954 rcu_read_unlock();
1955 spin_unlock_bh(&sc->chan_lock);
1956 ieee80211_txq_schedule_end(hw, txq->mac80211_qnum);
1957 }
1958
ath_txq_schedule_all(struct ath_softc * sc)1959 void ath_txq_schedule_all(struct ath_softc *sc)
1960 {
1961 struct ath_txq *txq;
1962 int i;
1963
1964 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
1965 txq = sc->tx.txq_map[i];
1966
1967 spin_lock_bh(&txq->axq_lock);
1968 ath_txq_schedule(sc, txq);
1969 spin_unlock_bh(&txq->axq_lock);
1970 }
1971 }
1972
1973 /***********/
1974 /* TX, DMA */
1975 /***********/
1976
1977 /*
1978 * Insert a chain of ath_buf (descriptors) on a txq and
1979 * assume the descriptors are already chained together by caller.
1980 */
ath_tx_txqaddbuf(struct ath_softc * sc,struct ath_txq * txq,struct list_head * head,bool internal)1981 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1982 struct list_head *head, bool internal)
1983 {
1984 struct ath_hw *ah = sc->sc_ah;
1985 struct ath_common *common = ath9k_hw_common(ah);
1986 struct ath_buf *bf, *bf_last;
1987 bool puttxbuf = false;
1988 bool edma;
1989
1990 /*
1991 * Insert the frame on the outbound list and
1992 * pass it on to the hardware.
1993 */
1994
1995 if (list_empty(head))
1996 return;
1997
1998 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1999 bf = list_first_entry(head, struct ath_buf, list);
2000 bf_last = list_entry(head->prev, struct ath_buf, list);
2001
2002 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
2003 txq->axq_qnum, txq->axq_depth);
2004
2005 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
2006 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
2007 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
2008 puttxbuf = true;
2009 } else {
2010 list_splice_tail_init(head, &txq->axq_q);
2011
2012 if (txq->axq_link) {
2013 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
2014 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
2015 txq->axq_qnum, txq->axq_link,
2016 ito64(bf->bf_daddr), bf->bf_desc);
2017 } else if (!edma)
2018 puttxbuf = true;
2019
2020 txq->axq_link = bf_last->bf_desc;
2021 }
2022
2023 if (puttxbuf) {
2024 TX_STAT_INC(sc, txq->axq_qnum, puttxbuf);
2025 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
2026 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
2027 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
2028 }
2029
2030 if (!edma || sc->tx99_state) {
2031 TX_STAT_INC(sc, txq->axq_qnum, txstart);
2032 ath9k_hw_txstart(ah, txq->axq_qnum);
2033 }
2034
2035 if (!internal) {
2036 while (bf) {
2037 txq->axq_depth++;
2038 if (bf_is_ampdu_not_probing(bf))
2039 txq->axq_ampdu_depth++;
2040
2041 bf_last = bf->bf_lastbf;
2042 bf = bf_last->bf_next;
2043 bf_last->bf_next = NULL;
2044 }
2045 }
2046 }
2047
ath_tx_send_normal(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid,struct sk_buff * skb)2048 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
2049 struct ath_atx_tid *tid, struct sk_buff *skb)
2050 {
2051 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2052 struct ath_frame_info *fi = get_frame_info(skb);
2053 struct list_head bf_head;
2054 struct ath_buf *bf = fi->bf;
2055
2056 INIT_LIST_HEAD(&bf_head);
2057 list_add_tail(&bf->list, &bf_head);
2058 bf->bf_state.bf_type = 0;
2059 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2060 bf->bf_state.bf_type = BUF_AMPDU;
2061 ath_tx_addto_baw(sc, tid, bf);
2062 }
2063
2064 bf->bf_next = NULL;
2065 bf->bf_lastbf = bf;
2066 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2067 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2068 TX_STAT_INC(sc, txq->axq_qnum, queued);
2069 }
2070
setup_frame_info(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb,int framelen)2071 static void setup_frame_info(struct ieee80211_hw *hw,
2072 struct ieee80211_sta *sta,
2073 struct sk_buff *skb,
2074 int framelen)
2075 {
2076 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2077 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2078 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2079 const struct ieee80211_rate *rate;
2080 struct ath_frame_info *fi = get_frame_info(skb);
2081 struct ath_node *an = NULL;
2082 enum ath9k_key_type keytype;
2083 bool short_preamble = false;
2084 u8 txpower;
2085
2086 /*
2087 * We check if Short Preamble is needed for the CTS rate by
2088 * checking the BSS's global flag.
2089 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2090 */
2091 if (tx_info->control.vif &&
2092 tx_info->control.vif->bss_conf.use_short_preamble)
2093 short_preamble = true;
2094
2095 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2096 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2097
2098 if (sta)
2099 an = (struct ath_node *) sta->drv_priv;
2100
2101 if (tx_info->control.vif) {
2102 struct ieee80211_vif *vif = tx_info->control.vif;
2103 if (vif->bss_conf.txpower == INT_MIN)
2104 goto nonvifpower;
2105 txpower = 2 * vif->bss_conf.txpower;
2106 } else {
2107 struct ath_softc *sc;
2108 nonvifpower:
2109 sc = hw->priv;
2110
2111 txpower = sc->cur_chan->cur_txpower;
2112 }
2113
2114 memset(fi, 0, sizeof(*fi));
2115 fi->txq = -1;
2116 if (hw_key)
2117 fi->keyix = hw_key->hw_key_idx;
2118 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2119 fi->keyix = an->ps_key;
2120 else
2121 fi->keyix = ATH9K_TXKEYIX_INVALID;
2122 fi->dyn_smps = sta && sta->smps_mode == IEEE80211_SMPS_DYNAMIC;
2123 fi->keytype = keytype;
2124 fi->framelen = framelen;
2125 fi->tx_power = txpower;
2126
2127 if (!rate)
2128 return;
2129 fi->rtscts_rate = rate->hw_value;
2130 if (short_preamble)
2131 fi->rtscts_rate |= rate->hw_value_short;
2132 }
2133
ath_txchainmask_reduction(struct ath_softc * sc,u8 chainmask,u32 rate)2134 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2135 {
2136 struct ath_hw *ah = sc->sc_ah;
2137 struct ath9k_channel *curchan = ah->curchan;
2138
2139 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2140 (chainmask == 0x7) && (rate < 0x90))
2141 return 0x3;
2142 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2143 IS_CCK_RATE(rate))
2144 return 0x2;
2145 else
2146 return chainmask;
2147 }
2148
2149 /*
2150 * Assign a descriptor (and sequence number if necessary,
2151 * and map buffer for DMA. Frees skb on error
2152 */
ath_tx_setup_buffer(struct ath_softc * sc,struct ath_txq * txq,struct ath_atx_tid * tid,struct sk_buff * skb)2153 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2154 struct ath_txq *txq,
2155 struct ath_atx_tid *tid,
2156 struct sk_buff *skb)
2157 {
2158 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2159 struct ath_frame_info *fi = get_frame_info(skb);
2160 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2161 struct ath_buf *bf;
2162 int fragno;
2163 u16 seqno;
2164
2165 bf = ath_tx_get_buffer(sc);
2166 if (!bf) {
2167 ath_dbg(common, XMIT, "TX buffers are full\n");
2168 return NULL;
2169 }
2170
2171 ATH_TXBUF_RESET(bf);
2172
2173 if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2174 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2175 seqno = tid->seq_next;
2176 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2177
2178 if (fragno)
2179 hdr->seq_ctrl |= cpu_to_le16(fragno);
2180
2181 if (!ieee80211_has_morefrags(hdr->frame_control))
2182 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2183
2184 bf->bf_state.seqno = seqno;
2185 }
2186
2187 bf->bf_mpdu = skb;
2188
2189 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2190 skb->len, DMA_TO_DEVICE);
2191 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2192 bf->bf_mpdu = NULL;
2193 bf->bf_buf_addr = 0;
2194 ath_err(ath9k_hw_common(sc->sc_ah),
2195 "dma_mapping_error() on TX\n");
2196 ath_tx_return_buffer(sc, bf);
2197 return NULL;
2198 }
2199
2200 fi->bf = bf;
2201
2202 return bf;
2203 }
2204
ath_assign_seq(struct ath_common * common,struct sk_buff * skb)2205 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb)
2206 {
2207 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2208 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2209 struct ieee80211_vif *vif = info->control.vif;
2210 struct ath_vif *avp;
2211
2212 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
2213 return;
2214
2215 if (!vif)
2216 return;
2217
2218 avp = (struct ath_vif *)vif->drv_priv;
2219
2220 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2221 avp->seq_no += 0x10;
2222
2223 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2224 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
2225 }
2226
ath_tx_prepare(struct ieee80211_hw * hw,struct sk_buff * skb,struct ath_tx_control * txctl)2227 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2228 struct ath_tx_control *txctl)
2229 {
2230 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2231 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2232 struct ieee80211_sta *sta = txctl->sta;
2233 struct ieee80211_vif *vif = info->control.vif;
2234 struct ath_vif *avp;
2235 struct ath_softc *sc = hw->priv;
2236 int frmlen = skb->len + FCS_LEN;
2237 int padpos, padsize;
2238
2239 /* NOTE: sta can be NULL according to net/mac80211.h */
2240 if (sta)
2241 txctl->an = (struct ath_node *)sta->drv_priv;
2242 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2243 avp = (void *)vif->drv_priv;
2244 txctl->an = &avp->mcast_node;
2245 }
2246
2247 if (info->control.hw_key)
2248 frmlen += info->control.hw_key->icv_len;
2249
2250 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb);
2251
2252 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2253 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2254 !ieee80211_is_data(hdr->frame_control))
2255 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2256
2257 /* Add the padding after the header if this is not already done */
2258 padpos = ieee80211_hdrlen(hdr->frame_control);
2259 padsize = padpos & 3;
2260 if (padsize && skb->len > padpos) {
2261 if (skb_headroom(skb) < padsize)
2262 return -ENOMEM;
2263
2264 skb_push(skb, padsize);
2265 memmove(skb->data, skb->data + padsize, padpos);
2266 }
2267
2268 setup_frame_info(hw, sta, skb, frmlen);
2269 return 0;
2270 }
2271
2272
2273 /* Upon failure caller should free skb */
ath_tx_start(struct ieee80211_hw * hw,struct sk_buff * skb,struct ath_tx_control * txctl)2274 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2275 struct ath_tx_control *txctl)
2276 {
2277 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2278 struct ieee80211_sta *sta = txctl->sta;
2279 struct ieee80211_vif *vif = info->control.vif;
2280 struct ath_frame_info *fi = get_frame_info(skb);
2281 struct ath_softc *sc = hw->priv;
2282 struct ath_txq *txq = txctl->txq;
2283 struct ath_atx_tid *tid = NULL;
2284 struct ath_node *an = NULL;
2285 struct ath_buf *bf;
2286 bool ps_resp;
2287 int q, ret;
2288
2289 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE);
2290
2291 ret = ath_tx_prepare(hw, skb, txctl);
2292 if (ret)
2293 return ret;
2294
2295 /*
2296 * At this point, the vif, hw_key and sta pointers in the tx control
2297 * info are no longer valid (overwritten by the ath_frame_info data.
2298 */
2299
2300 q = skb_get_queue_mapping(skb);
2301
2302 if (ps_resp)
2303 txq = sc->tx.uapsdq;
2304
2305 if (txctl->sta) {
2306 an = (struct ath_node *) sta->drv_priv;
2307 tid = ath_get_skb_tid(sc, an, skb);
2308 }
2309
2310 ath_txq_lock(sc, txq);
2311 if (txq == sc->tx.txq_map[q]) {
2312 fi->txq = q;
2313 ++txq->pending_frames;
2314 }
2315
2316 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2317 if (!bf) {
2318 ath_txq_skb_done(sc, txq, skb);
2319 if (txctl->paprd)
2320 dev_kfree_skb_any(skb);
2321 else
2322 ieee80211_free_txskb(sc->hw, skb);
2323 goto out;
2324 }
2325
2326 bf->bf_state.bfs_paprd = txctl->paprd;
2327
2328 if (txctl->paprd)
2329 bf->bf_state.bfs_paprd_timestamp = jiffies;
2330
2331 ath_set_rates(vif, sta, bf);
2332 ath_tx_send_normal(sc, txq, tid, skb);
2333
2334 out:
2335 ath_txq_unlock(sc, txq);
2336
2337 return 0;
2338 }
2339
ath_tx_cabq(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct sk_buff * skb)2340 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2341 struct sk_buff *skb)
2342 {
2343 struct ath_softc *sc = hw->priv;
2344 struct ath_tx_control txctl = {
2345 .txq = sc->beacon.cabq
2346 };
2347 struct ath_tx_info info = {};
2348 struct ath_buf *bf_tail = NULL;
2349 struct ath_buf *bf;
2350 LIST_HEAD(bf_q);
2351 int duration = 0;
2352 int max_duration;
2353
2354 max_duration =
2355 sc->cur_chan->beacon.beacon_interval * 1000 *
2356 sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2357
2358 do {
2359 struct ath_frame_info *fi = get_frame_info(skb);
2360
2361 if (ath_tx_prepare(hw, skb, &txctl))
2362 break;
2363
2364 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2365 if (!bf)
2366 break;
2367
2368 bf->bf_lastbf = bf;
2369 ath_set_rates(vif, NULL, bf);
2370 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2371 duration += info.rates[0].PktDuration;
2372 if (bf_tail)
2373 bf_tail->bf_next = bf;
2374
2375 list_add_tail(&bf->list, &bf_q);
2376 bf_tail = bf;
2377 skb = NULL;
2378
2379 if (duration > max_duration)
2380 break;
2381
2382 skb = ieee80211_get_buffered_bc(hw, vif);
2383 } while(skb);
2384
2385 if (skb)
2386 ieee80211_free_txskb(hw, skb);
2387
2388 if (list_empty(&bf_q))
2389 return;
2390
2391 bf = list_last_entry(&bf_q, struct ath_buf, list);
2392 ath9k_set_moredata(sc, bf, false);
2393
2394 bf = list_first_entry(&bf_q, struct ath_buf, list);
2395 ath_txq_lock(sc, txctl.txq);
2396 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2397 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2398 TX_STAT_INC(sc, txctl.txq->axq_qnum, queued);
2399 ath_txq_unlock(sc, txctl.txq);
2400 }
2401
2402 /*****************/
2403 /* TX Completion */
2404 /*****************/
2405
ath_tx_complete(struct ath_softc * sc,struct sk_buff * skb,int tx_flags,struct ath_txq * txq,struct ieee80211_sta * sta)2406 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2407 int tx_flags, struct ath_txq *txq,
2408 struct ieee80211_sta *sta)
2409 {
2410 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2411 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2412 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2413 int padpos, padsize;
2414 unsigned long flags;
2415
2416 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2417
2418 if (sc->sc_ah->caldata)
2419 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2420
2421 if (!(tx_flags & ATH_TX_ERROR)) {
2422 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
2423 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
2424 else
2425 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2426 }
2427
2428 if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) {
2429 padpos = ieee80211_hdrlen(hdr->frame_control);
2430 padsize = padpos & 3;
2431 if (padsize && skb->len>padpos+padsize) {
2432 /*
2433 * Remove MAC header padding before giving the frame back to
2434 * mac80211.
2435 */
2436 memmove(skb->data + padsize, skb->data, padpos);
2437 skb_pull(skb, padsize);
2438 }
2439 }
2440
2441 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2442 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2443 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2444 ath_dbg(common, PS,
2445 "Going back to sleep after having received TX status (0x%lx)\n",
2446 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2447 PS_WAIT_FOR_CAB |
2448 PS_WAIT_FOR_PSPOLL_DATA |
2449 PS_WAIT_FOR_TX_ACK));
2450 }
2451 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2452
2453 ath_txq_skb_done(sc, txq, skb);
2454 tx_info->status.status_driver_data[0] = sta;
2455 __skb_queue_tail(&txq->complete_q, skb);
2456 }
2457
ath_tx_complete_buf(struct ath_softc * sc,struct ath_buf * bf,struct ath_txq * txq,struct list_head * bf_q,struct ieee80211_sta * sta,struct ath_tx_status * ts,int txok)2458 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2459 struct ath_txq *txq, struct list_head *bf_q,
2460 struct ieee80211_sta *sta,
2461 struct ath_tx_status *ts, int txok)
2462 {
2463 struct sk_buff *skb = bf->bf_mpdu;
2464 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2465 unsigned long flags;
2466 int tx_flags = 0;
2467
2468 if (!txok)
2469 tx_flags |= ATH_TX_ERROR;
2470
2471 if (ts->ts_status & ATH9K_TXERR_FILT)
2472 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2473
2474 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2475 bf->bf_buf_addr = 0;
2476 if (sc->tx99_state)
2477 goto skip_tx_complete;
2478
2479 if (bf->bf_state.bfs_paprd) {
2480 if (time_after(jiffies,
2481 bf->bf_state.bfs_paprd_timestamp +
2482 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2483 dev_kfree_skb_any(skb);
2484 else
2485 complete(&sc->paprd_complete);
2486 } else {
2487 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2488 ath_tx_complete(sc, skb, tx_flags, txq, sta);
2489 }
2490 skip_tx_complete:
2491 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2492 * accidentally reference it later.
2493 */
2494 bf->bf_mpdu = NULL;
2495
2496 /*
2497 * Return the list of ath_buf of this mpdu to free queue
2498 */
2499 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2500 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2501 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2502 }
2503
ath_clear_tx_status(struct ieee80211_tx_info * tx_info)2504 static void ath_clear_tx_status(struct ieee80211_tx_info *tx_info)
2505 {
2506 void *ptr = &tx_info->status;
2507
2508 memset(ptr + sizeof(tx_info->status.rates), 0,
2509 sizeof(tx_info->status) -
2510 sizeof(tx_info->status.rates) -
2511 sizeof(tx_info->status.status_driver_data));
2512 }
2513
ath_tx_rc_status(struct ath_softc * sc,struct ath_buf * bf,struct ath_tx_status * ts,int nframes,int nbad,int txok)2514 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2515 struct ath_tx_status *ts, int nframes, int nbad,
2516 int txok)
2517 {
2518 struct sk_buff *skb = bf->bf_mpdu;
2519 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2520 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2521 struct ieee80211_hw *hw = sc->hw;
2522 struct ath_hw *ah = sc->sc_ah;
2523 u8 i, tx_rateindex;
2524
2525 ath_clear_tx_status(tx_info);
2526
2527 if (txok)
2528 tx_info->status.ack_signal = ts->ts_rssi;
2529
2530 tx_rateindex = ts->ts_rateindex;
2531 WARN_ON(tx_rateindex >= hw->max_rates);
2532
2533 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2534 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2535
2536 BUG_ON(nbad > nframes);
2537 }
2538 tx_info->status.ampdu_len = nframes;
2539 tx_info->status.ampdu_ack_len = nframes - nbad;
2540
2541 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2542
2543 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2544 tx_info->status.rates[i].count = 0;
2545 tx_info->status.rates[i].idx = -1;
2546 }
2547
2548 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2549 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2550 /*
2551 * If an underrun error is seen assume it as an excessive
2552 * retry only if max frame trigger level has been reached
2553 * (2 KB for single stream, and 4 KB for dual stream).
2554 * Adjust the long retry as if the frame was tried
2555 * hw->max_rate_tries times to affect how rate control updates
2556 * PER for the failed rate.
2557 * In case of congestion on the bus penalizing this type of
2558 * underruns should help hardware actually transmit new frames
2559 * successfully by eventually preferring slower rates.
2560 * This itself should also alleviate congestion on the bus.
2561 */
2562 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2563 ATH9K_TX_DELIM_UNDERRUN)) &&
2564 ieee80211_is_data(hdr->frame_control) &&
2565 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2566 tx_info->status.rates[tx_rateindex].count =
2567 hw->max_rate_tries;
2568 }
2569 }
2570
ath_tx_processq(struct ath_softc * sc,struct ath_txq * txq)2571 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2572 {
2573 struct ath_hw *ah = sc->sc_ah;
2574 struct ath_common *common = ath9k_hw_common(ah);
2575 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2576 struct list_head bf_head;
2577 struct ath_desc *ds;
2578 struct ath_tx_status ts;
2579 int status;
2580
2581 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2582 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2583 txq->axq_link);
2584
2585 ath_txq_lock(sc, txq);
2586 for (;;) {
2587 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2588 break;
2589
2590 if (list_empty(&txq->axq_q)) {
2591 txq->axq_link = NULL;
2592 ath_txq_schedule(sc, txq);
2593 break;
2594 }
2595 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2596
2597 /*
2598 * There is a race condition that a BH gets scheduled
2599 * after sw writes TxE and before hw re-load the last
2600 * descriptor to get the newly chained one.
2601 * Software must keep the last DONE descriptor as a
2602 * holding descriptor - software does so by marking
2603 * it with the STALE flag.
2604 */
2605 bf_held = NULL;
2606 if (bf->bf_state.stale) {
2607 bf_held = bf;
2608 if (list_is_last(&bf_held->list, &txq->axq_q))
2609 break;
2610
2611 bf = list_entry(bf_held->list.next, struct ath_buf,
2612 list);
2613 }
2614
2615 lastbf = bf->bf_lastbf;
2616 ds = lastbf->bf_desc;
2617
2618 memset(&ts, 0, sizeof(ts));
2619 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2620 if (status == -EINPROGRESS)
2621 break;
2622
2623 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc);
2624
2625 /*
2626 * Remove ath_buf's of the same transmit unit from txq,
2627 * however leave the last descriptor back as the holding
2628 * descriptor for hw.
2629 */
2630 lastbf->bf_state.stale = true;
2631 INIT_LIST_HEAD(&bf_head);
2632 if (!list_is_singular(&lastbf->list))
2633 list_cut_position(&bf_head,
2634 &txq->axq_q, lastbf->list.prev);
2635
2636 if (bf_held) {
2637 list_del(&bf_held->list);
2638 ath_tx_return_buffer(sc, bf_held);
2639 }
2640
2641 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2642 }
2643 ath_txq_unlock_complete(sc, txq);
2644 }
2645
ath_tx_tasklet(struct ath_softc * sc)2646 void ath_tx_tasklet(struct ath_softc *sc)
2647 {
2648 struct ath_hw *ah = sc->sc_ah;
2649 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2650 int i;
2651
2652 rcu_read_lock();
2653 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2654 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2655 ath_tx_processq(sc, &sc->tx.txq[i]);
2656 }
2657 rcu_read_unlock();
2658 }
2659
ath_tx_edma_tasklet(struct ath_softc * sc)2660 void ath_tx_edma_tasklet(struct ath_softc *sc)
2661 {
2662 struct ath_tx_status ts;
2663 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2664 struct ath_hw *ah = sc->sc_ah;
2665 struct ath_txq *txq;
2666 struct ath_buf *bf, *lastbf;
2667 struct list_head bf_head;
2668 struct list_head *fifo_list;
2669 int status;
2670
2671 rcu_read_lock();
2672 for (;;) {
2673 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2674 break;
2675
2676 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2677 if (status == -EINPROGRESS)
2678 break;
2679 if (status == -EIO) {
2680 ath_dbg(common, XMIT, "Error processing tx status\n");
2681 break;
2682 }
2683
2684 /* Process beacon completions separately */
2685 if (ts.qid == sc->beacon.beaconq) {
2686 sc->beacon.tx_processed = true;
2687 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2688
2689 if (ath9k_is_chanctx_enabled()) {
2690 ath_chanctx_event(sc, NULL,
2691 ATH_CHANCTX_EVENT_BEACON_SENT);
2692 }
2693
2694 ath9k_csa_update(sc);
2695 continue;
2696 }
2697
2698 txq = &sc->tx.txq[ts.qid];
2699
2700 ath_txq_lock(sc, txq);
2701
2702 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc);
2703
2704 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2705 if (list_empty(fifo_list)) {
2706 ath_txq_unlock(sc, txq);
2707 break;
2708 }
2709
2710 bf = list_first_entry(fifo_list, struct ath_buf, list);
2711 if (bf->bf_state.stale) {
2712 list_del(&bf->list);
2713 ath_tx_return_buffer(sc, bf);
2714 bf = list_first_entry(fifo_list, struct ath_buf, list);
2715 }
2716
2717 lastbf = bf->bf_lastbf;
2718
2719 INIT_LIST_HEAD(&bf_head);
2720 if (list_is_last(&lastbf->list, fifo_list)) {
2721 list_splice_tail_init(fifo_list, &bf_head);
2722 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2723
2724 if (!list_empty(&txq->axq_q)) {
2725 struct list_head bf_q;
2726
2727 INIT_LIST_HEAD(&bf_q);
2728 txq->axq_link = NULL;
2729 list_splice_tail_init(&txq->axq_q, &bf_q);
2730 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2731 }
2732 } else {
2733 lastbf->bf_state.stale = true;
2734 if (bf != lastbf)
2735 list_cut_position(&bf_head, fifo_list,
2736 lastbf->list.prev);
2737 }
2738
2739 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2740 ath_txq_unlock_complete(sc, txq);
2741 }
2742 rcu_read_unlock();
2743 }
2744
2745 /*****************/
2746 /* Init, Cleanup */
2747 /*****************/
2748
ath_txstatus_setup(struct ath_softc * sc,int size)2749 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2750 {
2751 struct ath_descdma *dd = &sc->txsdma;
2752 u8 txs_len = sc->sc_ah->caps.txs_len;
2753
2754 dd->dd_desc_len = size * txs_len;
2755 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2756 &dd->dd_desc_paddr, GFP_KERNEL);
2757 if (!dd->dd_desc)
2758 return -ENOMEM;
2759
2760 return 0;
2761 }
2762
ath_tx_edma_init(struct ath_softc * sc)2763 static int ath_tx_edma_init(struct ath_softc *sc)
2764 {
2765 int err;
2766
2767 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2768 if (!err)
2769 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2770 sc->txsdma.dd_desc_paddr,
2771 ATH_TXSTATUS_RING_SIZE);
2772
2773 return err;
2774 }
2775
ath_tx_init(struct ath_softc * sc,int nbufs)2776 int ath_tx_init(struct ath_softc *sc, int nbufs)
2777 {
2778 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2779 int error = 0;
2780
2781 spin_lock_init(&sc->tx.txbuflock);
2782
2783 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2784 "tx", nbufs, 1, 1);
2785 if (error != 0) {
2786 ath_err(common,
2787 "Failed to allocate tx descriptors: %d\n", error);
2788 return error;
2789 }
2790
2791 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2792 "beacon", ATH_BCBUF, 1, 1);
2793 if (error != 0) {
2794 ath_err(common,
2795 "Failed to allocate beacon descriptors: %d\n", error);
2796 return error;
2797 }
2798
2799 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2800 error = ath_tx_edma_init(sc);
2801
2802 return error;
2803 }
2804
ath_tx_node_init(struct ath_softc * sc,struct ath_node * an)2805 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2806 {
2807 struct ath_atx_tid *tid;
2808 int tidno, acno;
2809
2810 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2811 tid = ath_node_to_tid(an, tidno);
2812 tid->an = an;
2813 tid->tidno = tidno;
2814 tid->seq_start = tid->seq_next = 0;
2815 tid->baw_size = WME_MAX_BA;
2816 tid->baw_head = tid->baw_tail = 0;
2817 tid->active = false;
2818 tid->clear_ps_filter = true;
2819 __skb_queue_head_init(&tid->retry_q);
2820 INIT_LIST_HEAD(&tid->list);
2821 acno = TID_TO_WME_AC(tidno);
2822 tid->txq = sc->tx.txq_map[acno];
2823
2824 if (!an->sta)
2825 break; /* just one multicast ath_atx_tid */
2826 }
2827 }
2828
ath_tx_node_cleanup(struct ath_softc * sc,struct ath_node * an)2829 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2830 {
2831 struct ath_atx_tid *tid;
2832 struct ath_txq *txq;
2833 int tidno;
2834
2835 rcu_read_lock();
2836
2837 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2838 tid = ath_node_to_tid(an, tidno);
2839 txq = tid->txq;
2840
2841 ath_txq_lock(sc, txq);
2842
2843 if (!list_empty(&tid->list))
2844 list_del_init(&tid->list);
2845
2846 ath_tid_drain(sc, txq, tid);
2847 tid->active = false;
2848
2849 ath_txq_unlock(sc, txq);
2850
2851 if (!an->sta)
2852 break; /* just one multicast ath_atx_tid */
2853 }
2854
2855 rcu_read_unlock();
2856 }
2857
2858 #ifdef CONFIG_ATH9K_TX99
2859
ath9k_tx99_send(struct ath_softc * sc,struct sk_buff * skb,struct ath_tx_control * txctl)2860 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2861 struct ath_tx_control *txctl)
2862 {
2863 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2864 struct ath_frame_info *fi = get_frame_info(skb);
2865 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2866 struct ath_buf *bf;
2867 int padpos, padsize;
2868
2869 padpos = ieee80211_hdrlen(hdr->frame_control);
2870 padsize = padpos & 3;
2871
2872 if (padsize && skb->len > padpos) {
2873 if (skb_headroom(skb) < padsize) {
2874 ath_dbg(common, XMIT,
2875 "tx99 padding failed\n");
2876 return -EINVAL;
2877 }
2878
2879 skb_push(skb, padsize);
2880 memmove(skb->data, skb->data + padsize, padpos);
2881 }
2882
2883 fi->keyix = ATH9K_TXKEYIX_INVALID;
2884 fi->framelen = skb->len + FCS_LEN;
2885 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2886
2887 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2888 if (!bf) {
2889 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2890 return -EINVAL;
2891 }
2892
2893 ath_set_rates(sc->tx99_vif, NULL, bf);
2894
2895 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2896 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2897
2898 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2899
2900 return 0;
2901 }
2902
2903 #endif /* CONFIG_ATH9K_TX99 */
2904