| /drivers/net/wireless/quantenna/qtnfmac/pcie/ |
| D | pearl_pcie_regs.h | 8 #define PCIE_HDP_CTRL(base) ((base) + 0x2c00) argument
9 #define PCIE_HDP_AXI_CTRL(base) ((base) + 0x2c04) argument
10 #define PCIE_HDP_HOST_WR_DESC0(base) ((base) + 0x2c10) argument
11 #define PCIE_HDP_HOST_WR_DESC0_H(base) ((base) + 0x2c14) argument
12 #define PCIE_HDP_HOST_WR_DESC1(base) ((base) + 0x2c18) argument
13 #define PCIE_HDP_HOST_WR_DESC1_H(base) ((base) + 0x2c1c) argument
14 #define PCIE_HDP_HOST_WR_DESC2(base) ((base) + 0x2c20) argument
15 #define PCIE_HDP_HOST_WR_DESC2_H(base) ((base) + 0x2c24) argument
16 #define PCIE_HDP_HOST_WR_DESC3(base) ((base) + 0x2c28) argument
17 #define PCIE_HDP_HOST_WR_DESC4_H(base) ((base) + 0x2c2c) argument
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| D | topaz_pcie_regs.h | 8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc) argument
9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4) argument
10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8) argument
11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc) argument
12 #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base) + 0x9D0) argument
13 #define PCIE_DMA_WR_DONE_IMWR_ADDR_HIGH(base) ((base) + 0x9d4) argument
15 #define PCIE_DMA_RD_INTR_STATUS(base) ((base) + 0x310) argument
16 #define PCIE_DMA_RD_INTR_MASK(base) ((base) + 0x319) argument
17 #define PCIE_DMA_RD_INTR_CLR(base) ((base) + 0x31c) argument
18 #define PCIE_DMA_RD_ERR_STATUS_LOW(base) ((base) + 0x324) argument
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| /drivers/gpu/drm/sun4i/ |
| D | sun8i_vi_scaler.h | 30 #define SUN8I_SCALER_VSU_CTRL(base) ((base) + 0x0) argument
31 #define SUN50I_SCALER_VSU_SCALE_MODE(base) ((base) + 0x10) argument
32 #define SUN50I_SCALER_VSU_DIR_THR(base) ((base) + 0x20) argument
33 #define SUN50I_SCALER_VSU_EDGE_THR(base) ((base) + 0x24) argument
34 #define SUN50I_SCALER_VSU_EDSCL_CTRL(base) ((base) + 0x28) argument
35 #define SUN50I_SCALER_VSU_ANGLE_THR(base) ((base) + 0x2c) argument
36 #define SUN8I_SCALER_VSU_OUTSIZE(base) ((base) + 0x40) argument
37 #define SUN8I_SCALER_VSU_YINSIZE(base) ((base) + 0x80) argument
38 #define SUN8I_SCALER_VSU_YHSTEP(base) ((base) + 0x88) argument
39 #define SUN8I_SCALER_VSU_YVSTEP(base) ((base) + 0x8c) argument
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| D | sun8i_ui_layer.h | 17 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR(base, layer) \ argument
19 #define SUN8I_MIXER_CHAN_UI_LAYER_SIZE(base, layer) \ argument
21 #define SUN8I_MIXER_CHAN_UI_LAYER_COORD(base, layer) \ argument
23 #define SUN8I_MIXER_CHAN_UI_LAYER_PITCH(base, layer) \ argument
25 #define SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(base, layer) \ argument
27 #define SUN8I_MIXER_CHAN_UI_LAYER_BOT_LADDR(base, layer) \ argument
29 #define SUN8I_MIXER_CHAN_UI_LAYER_FCOLOR(base, layer) \ argument
31 #define SUN8I_MIXER_CHAN_UI_TOP_HADDR(base) \ argument
33 #define SUN8I_MIXER_CHAN_UI_BOT_HADDR(base) \ argument
35 #define SUN8I_MIXER_CHAN_UI_OVL_SIZE(base) \ argument
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| D | sun8i_vi_layer.h | 11 #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR(base, layer) \ argument
13 #define SUN8I_MIXER_CHAN_VI_LAYER_SIZE(base, layer) \ argument
15 #define SUN8I_MIXER_CHAN_VI_LAYER_COORD(base, layer) \ argument
17 #define SUN8I_MIXER_CHAN_VI_LAYER_PITCH(base, layer, plane) \ argument
19 #define SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(base, layer, plane) \ argument
21 #define SUN8I_MIXER_CHAN_VI_OVL_SIZE(base) \ argument
23 #define SUN8I_MIXER_CHAN_VI_HDS_Y(base) \ argument
25 #define SUN8I_MIXER_CHAN_VI_HDS_UV(base) \ argument
27 #define SUN8I_MIXER_CHAN_VI_VDS_Y(base) \ argument
29 #define SUN8I_MIXER_CHAN_VI_VDS_UV(base) \ argument
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| D | sun8i_ui_scaler.h | 26 #define SUN8I_SCALER_GSU_CTRL(base) ((base) + 0x0) argument
27 #define SUN8I_SCALER_GSU_OUTSIZE(base) ((base) + 0x40) argument
28 #define SUN8I_SCALER_GSU_INSIZE(base) ((base) + 0x80) argument
29 #define SUN8I_SCALER_GSU_HSTEP(base) ((base) + 0x88) argument
30 #define SUN8I_SCALER_GSU_VSTEP(base) ((base) + 0x8c) argument
31 #define SUN8I_SCALER_GSU_HPHASE(base) ((base) + 0x90) argument
32 #define SUN8I_SCALER_GSU_VPHASE(base) ((base) + 0x98) argument
33 #define SUN8I_SCALER_GSU_HCOEFF(base, index) ((base) + 0x200 + 0x4 * (index)) argument
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| D | sun8i_mixer.h | 38 #define SUN8I_MIXER_BLEND_PIPE_CTL(base) ((base) + 0) argument
39 #define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x) ((base) + 0x4 + 0x10 * (x)) argument
40 #define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x) ((base) + 0x8 + 0x10 * (x)) argument
41 #define SUN8I_MIXER_BLEND_ATTR_COORD(base, x) ((base) + 0xc + 0x10 * (x)) argument
42 #define SUN8I_MIXER_BLEND_ROUTE(base) ((base) + 0x80) argument
43 #define SUN8I_MIXER_BLEND_PREMULTIPLY(base) ((base) + 0x84) argument
44 #define SUN8I_MIXER_BLEND_BKCOLOR(base) ((base) + 0x88) argument
45 #define SUN8I_MIXER_BLEND_OUTSIZE(base) ((base) + 0x8c) argument
46 #define SUN8I_MIXER_BLEND_MODE(base, x) ((base) + 0x90 + 0x04 * (x)) argument
47 #define SUN8I_MIXER_BLEND_CK_CTL(base) ((base) + 0xb0) argument
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| /drivers/media/platform/s5p-jpeg/ |
| D | jpeg-hw-exynos4.c | 16 void exynos4_jpeg_sw_reset(void __iomem *base) in exynos4_jpeg_sw_reset()
32 void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode) in exynos4_jpeg_set_enc_dec_mode()
52 void __exynos4_jpeg_set_img_fmt(void __iomem *base, unsigned int img_fmt, in __exynos4_jpeg_set_img_fmt()
136 void __exynos4_jpeg_set_enc_out_fmt(void __iomem *base, unsigned int out_fmt, in __exynos4_jpeg_set_enc_out_fmt()
169 void exynos4_jpeg_set_interrupt(void __iomem *base, unsigned int version) in exynos4_jpeg_set_interrupt()
183 unsigned int exynos4_jpeg_get_int_status(void __iomem *base) in exynos4_jpeg_get_int_status()
188 unsigned int exynos4_jpeg_get_fifo_status(void __iomem *base) in exynos4_jpeg_get_fifo_status()
193 void exynos4_jpeg_set_huf_table_enable(void __iomem *base, int value) in exynos4_jpeg_set_huf_table_enable()
207 void exynos4_jpeg_set_sys_int_enable(void __iomem *base, int value) in exynos4_jpeg_set_sys_int_enable()
219 void exynos4_jpeg_set_stream_buf_address(void __iomem *base, in exynos4_jpeg_set_stream_buf_address()
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| /drivers/scsi/ |
| D | nsp32_io.h | 12 static inline void nsp32_write1(unsigned int base, in nsp32_write1()
19 static inline unsigned char nsp32_read1(unsigned int base, in nsp32_read1()
25 static inline void nsp32_write2(unsigned int base, in nsp32_write2()
32 static inline unsigned short nsp32_read2(unsigned int base, in nsp32_read2()
38 static inline void nsp32_write4(unsigned int base, in nsp32_write4()
45 static inline unsigned long nsp32_read4(unsigned int base, in nsp32_read4()
53 static inline void nsp32_mmio_write1(unsigned long base, in nsp32_mmio_write1()
64 static inline unsigned char nsp32_mmio_read1(unsigned long base, in nsp32_mmio_read1()
74 static inline void nsp32_mmio_write2(unsigned long base, in nsp32_mmio_write2()
85 static inline unsigned short nsp32_mmio_read2(unsigned long base, in nsp32_mmio_read2()
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| D | aha1740.h | 19 #define HID0(base) (base + 0x0) argument
20 #define HID1(base) (base + 0x1) argument
21 #define HID2(base) (base + 0x2) argument
22 #define HID3(base) (base + 0x3) argument
23 #define EBCNTRL(base) (base + 0x4) argument
24 #define PORTADR(base) (base + 0x40) argument
25 #define BIOSADR(base) (base + 0x41) argument
26 #define INTDEF(base) (base + 0x42) argument
27 #define SCSIDEF(base) (base + 0x43) argument
28 #define BUSDEF(base) (base + 0x44) argument
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| D | myrs.c | 106 void __iomem *base = cs->io_base; in myrs_qcmd() local
485 void __iomem *base = cs->io_base; in myrs_enable_mmio_mbox() local
2403 static inline void DAC960_GEM_hw_mbox_new_cmd(void __iomem *base) in DAC960_GEM_hw_mbox_new_cmd()
2410 static inline void DAC960_GEM_ack_hw_mbox_status(void __iomem *base) in DAC960_GEM_ack_hw_mbox_status()
2417 static inline void DAC960_GEM_gen_intr(void __iomem *base) in DAC960_GEM_gen_intr()
2424 static inline void DAC960_GEM_reset_ctrl(void __iomem *base) in DAC960_GEM_reset_ctrl()
2431 static inline void DAC960_GEM_mem_mbox_new_cmd(void __iomem *base) in DAC960_GEM_mem_mbox_new_cmd()
2438 static inline bool DAC960_GEM_hw_mbox_is_full(void __iomem *base) in DAC960_GEM_hw_mbox_is_full()
2446 static inline bool DAC960_GEM_init_in_progress(void __iomem *base) in DAC960_GEM_init_in_progress()
2454 static inline void DAC960_GEM_ack_hw_mbox_intr(void __iomem *base) in DAC960_GEM_ack_hw_mbox_intr()
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| D | myrb.c | 165 void __iomem *base = cb->io_base; in myrb_qcmd() local
810 void __iomem *base = cb->io_base; in myrb_enable_mmio() local
2548 static inline void DAC960_LA_hw_mbox_new_cmd(void __iomem *base) in DAC960_LA_hw_mbox_new_cmd()
2553 static inline void DAC960_LA_ack_hw_mbox_status(void __iomem *base) in DAC960_LA_ack_hw_mbox_status()
2558 static inline void DAC960_LA_gen_intr(void __iomem *base) in DAC960_LA_gen_intr()
2563 static inline void DAC960_LA_reset_ctrl(void __iomem *base) in DAC960_LA_reset_ctrl()
2568 static inline void DAC960_LA_mem_mbox_new_cmd(void __iomem *base) in DAC960_LA_mem_mbox_new_cmd()
2573 static inline bool DAC960_LA_hw_mbox_is_full(void __iomem *base) in DAC960_LA_hw_mbox_is_full()
2580 static inline bool DAC960_LA_init_in_progress(void __iomem *base) in DAC960_LA_init_in_progress()
2587 static inline void DAC960_LA_ack_hw_mbox_intr(void __iomem *base) in DAC960_LA_ack_hw_mbox_intr()
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| /drivers/media/platform/mtk-jpeg/ |
| D | mtk_jpeg_dec_hw.c | 192 u32 mtk_jpeg_dec_get_int_status(void __iomem *base) in mtk_jpeg_dec_get_int_status()
219 void mtk_jpeg_dec_start(void __iomem *base) in mtk_jpeg_dec_start()
224 static void mtk_jpeg_dec_soft_reset(void __iomem *base) in mtk_jpeg_dec_soft_reset()
231 static void mtk_jpeg_dec_hard_reset(void __iomem *base) in mtk_jpeg_dec_hard_reset()
237 void mtk_jpeg_dec_reset(void __iomem *base) in mtk_jpeg_dec_reset()
243 static void mtk_jpeg_dec_set_brz_factor(void __iomem *base, u8 yscale_w, in mtk_jpeg_dec_set_brz_factor()
253 static void mtk_jpeg_dec_set_dst_bank0(void __iomem *base, u32 addr_y, in mtk_jpeg_dec_set_dst_bank0()
264 static void mtk_jpeg_dec_set_dst_bank1(void __iomem *base, u32 addr_y, in mtk_jpeg_dec_set_dst_bank1()
272 static void mtk_jpeg_dec_set_mem_stride(void __iomem *base, u32 stride_y, in mtk_jpeg_dec_set_mem_stride()
279 static void mtk_jpeg_dec_set_img_stride(void __iomem *base, u32 stride_y, in mtk_jpeg_dec_set_img_stride()
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| /drivers/scsi/pcmcia/ |
| D | nsp_io.h | 30 static inline void nsp_write(unsigned int base, in nsp_write()
37 static inline unsigned char nsp_read(unsigned int base, in nsp_read()
75 static inline void nsp_fifo8_read(unsigned int base, in nsp_fifo8_read()
94 static inline void nsp_fifo16_read(unsigned int base, in nsp_fifo16_read()
113 static inline void nsp_fifo32_read(unsigned int base, in nsp_fifo32_read()
132 static inline void nsp_fifo8_write(unsigned int base, in nsp_fifo8_write()
150 static inline void nsp_fifo16_write(unsigned int base, in nsp_fifo16_write()
168 static inline void nsp_fifo32_write(unsigned int base, in nsp_fifo32_write()
178 static inline void nsp_mmio_write(unsigned long base, in nsp_mmio_write()
187 static inline unsigned char nsp_mmio_read(unsigned long base, in nsp_mmio_read()
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| /drivers/s390/block/ |
| D | dasd_ioctl.c | 47 struct dasd_device *base; in dasd_ioctl_enable() local
70 struct dasd_device *base; in dasd_ioctl_disable() local
102 struct dasd_device *base; in dasd_ioctl_quiesce() local
123 struct dasd_device *base; in dasd_ioctl_resume() local
146 struct dasd_device *base; in dasd_ioctl_abortio() local
181 struct dasd_device *base; in dasd_ioctl_allowio() local
202 struct dasd_device *base; in dasd_format() local
241 struct dasd_device *base; in dasd_check_format() local
261 struct dasd_device *base; in dasd_ioctl_format() local
299 struct dasd_device *base; in dasd_ioctl_check_format() local
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| /drivers/gpu/drm/nouveau/nvkm/subdev/bar/ |
| D | nv50.c | 32 nv50_bar_flush(struct nvkm_bar *base) in nv50_bar_flush()
47 nv50_bar_bar1_vmm(struct nvkm_bar *base) in nv50_bar_bar1_vmm()
53 nv50_bar_bar1_wait(struct nvkm_bar *base) in nv50_bar_bar1_wait()
65 nv50_bar_bar1_init(struct nvkm_bar *base) in nv50_bar_bar1_init()
73 nv50_bar_bar2_vmm(struct nvkm_bar *base) in nv50_bar_bar2_vmm()
85 nv50_bar_bar2_init(struct nvkm_bar *base) in nv50_bar_bar2_init()
95 nv50_bar_init(struct nvkm_bar *base) in nv50_bar_init()
106 nv50_bar_oneinit(struct nvkm_bar *base) in nv50_bar_oneinit()
204 nv50_bar_dtor(struct nvkm_bar *base) in nv50_bar_dtor()
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| /drivers/block/ |
| D | swim.c | 62 #define swim_write(base, reg, v) out_8(&(base)->write_##reg, (v)) argument
63 #define swim_read(base, reg) in_8(&(base)->read_##reg) argument
86 #define iwm_write(base, reg, v) out_8(&(base)->reg, (v)) argument
87 #define iwm_read(base, reg) in_8(&(base)->reg) argument
209 struct swim __iomem *base; member
221 static inline void set_swim_mode(struct swim __iomem *base, int enable) in set_swim_mode()
246 static inline int get_swim_mode(struct swim __iomem *base) in get_swim_mode()
268 static inline void swim_select(struct swim __iomem *base, int sel) in swim_select()
277 static inline void swim_action(struct swim __iomem *base, int action) in swim_action()
293 static inline int swim_readbit(struct swim __iomem *base, int bit) in swim_readbit()
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| /drivers/gpu/drm/hisilicon/kirin/ |
| D | kirin_drm_ade.c | 43 void __iomem *base; member
94 static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val) in ade_update_reload_bit()
105 static u32 ade_read_reload_bit(void __iomem *base, u32 bit_num) in ade_read_reload_bit()
118 void __iomem *base = ctx->base; in ade_init() local
174 void __iomem *base = ctx->base; in ade_ldi_set_mode() local
248 void __iomem *base = ctx->base; in ade_power_down() local
279 void __iomem *base = ctx->base; in ade_crtc_enable_vblank() local
294 void __iomem *base = ctx->base; in ade_crtc_disable_vblank() local
309 void __iomem *base = ctx->base; in ade_irq_handler() local
327 void __iomem *base = ctx->base; in ade_display_enable() local
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| /drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| D | channv50.c | 46 nv50_fifo_chan_engine_fini(struct nvkm_fifo_chan *base, in nv50_fifo_chan_engine_fini()
102 nv50_fifo_chan_engine_init(struct nvkm_fifo_chan *base, in nv50_fifo_chan_engine_init()
129 nv50_fifo_chan_engine_dtor(struct nvkm_fifo_chan *base, in nv50_fifo_chan_engine_dtor()
137 nv50_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base, in nv50_fifo_chan_engine_ctor()
151 nv50_fifo_chan_object_dtor(struct nvkm_fifo_chan *base, int cookie) in nv50_fifo_chan_object_dtor()
158 nv50_fifo_chan_object_ctor(struct nvkm_fifo_chan *base, in nv50_fifo_chan_object_ctor()
179 nv50_fifo_chan_fini(struct nvkm_fifo_chan *base) in nv50_fifo_chan_fini()
193 nv50_fifo_chan_init(struct nvkm_fifo_chan *base) in nv50_fifo_chan_init()
206 nv50_fifo_chan_dtor(struct nvkm_fifo_chan *base) in nv50_fifo_chan_dtor()
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| /drivers/gpio/ |
| D | gpio-winbond.c | 131 unsigned long base; member
142 static int winbond_sio_enter(unsigned long base) in winbond_sio_enter()
157 static void winbond_sio_select_logical(unsigned long base, u8 dev) in winbond_sio_select_logical()
163 static void winbond_sio_leave(unsigned long base) in winbond_sio_leave()
170 static void winbond_sio_reg_write(unsigned long base, u8 reg, u8 data) in winbond_sio_reg_write()
176 static u8 winbond_sio_reg_read(unsigned long base, u8 reg) in winbond_sio_reg_read()
182 static void winbond_sio_reg_bset(unsigned long base, u8 reg, u8 bit) in winbond_sio_reg_bset()
191 static void winbond_sio_reg_bclear(unsigned long base, u8 reg, u8 bit) in winbond_sio_reg_bclear()
200 static bool winbond_sio_reg_btest(unsigned long base, u8 reg, u8 bit) in winbond_sio_reg_btest()
385 unsigned long *base = gpiochip_get_data(gc); in winbond_gpio_get() local
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| /drivers/clocksource/ |
| D | timer-gx6605s.c | 28 void __iomem *base = timer_of_base(to_timer_of(ce)); in gx6605s_timer_interrupt() local
40 void __iomem *base = timer_of_base(to_timer_of(ce)); in gx6605s_timer_set_oneshot() local
55 void __iomem *base = timer_of_base(to_timer_of(ce)); in gx6605s_timer_set_next_event() local
69 void __iomem *base = timer_of_base(to_timer_of(ce)); in gx6605s_timer_shutdown() local
96 void __iomem *base; in gx6605s_sched_clock_read() local
103 static void gx6605s_clkevt_init(void __iomem *base) in gx6605s_clkevt_init()
112 static int gx6605s_clksrc_init(void __iomem *base) in gx6605s_clksrc_init()
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| /drivers/fpga/ |
| D | dfl-fme-error.c | 46 void __iomem *base; in pcie0_errors_show() local
63 void __iomem *base; in pcie0_errors_store() local
91 void __iomem *base; in pcie1_errors_show() local
108 void __iomem *base; in pcie1_errors_store() local
135 void __iomem *base; in nonfatal_errors_show() local
147 void __iomem *base; in catfatal_errors_show() local
160 void __iomem *base; in inject_errors_show() local
178 void __iomem *base; in inject_errors_store() local
205 void __iomem *base; in fme_errors_show() local
222 void __iomem *base; in fme_errors_store() local
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| /drivers/gpu/drm/i915/gt/ |
| D | intel_lrc.h | 38 #define RING_ELSP(base) _MMIO((base) + 0x230) argument
39 #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234) argument
40 #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4) argument
41 #define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244) argument
47 #define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0) argument
48 #define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510) argument
49 #define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550) argument
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| /drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy_28nm_8960.c | 14 void __iomem *base = phy->base; in dsi_28nm_dphy_set_timing() local
44 void __iomem *base = phy->reg_base; in dsi_28nm_phy_regulator_init() local
56 void __iomem *base = phy->reg_base; in dsi_28nm_phy_regulator_ctrl() local
67 void __iomem *base = phy->reg_base; in dsi_28nm_phy_calibration() local
97 void __iomem *base = phy->base; in dsi_28nm_phy_lane_config() local
124 void __iomem *base = phy->base; in dsi_28nm_phy_enable() local
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | hdmi5_core.c | 41 void __iomem *base = core->base; in hdmi_core_ddc_init() local
120 void __iomem *base = core->base; in hdmi_core_ddc_uninit() local
130 void __iomem *base = core->base; in hdmi_core_ddc_edid() local
309 void __iomem *base = core->base; in hdmi_core_video_config() local
373 void __iomem *base = core->base; in hdmi_core_config_video_packetizer() local
411 void __iomem *base = core->base; in hdmi_core_write_avi_infoframe() local
467 void __iomem *base = core->base; in hdmi_core_csc_config() local
509 void __iomem *base = core->base; in hdmi_core_enable_video_path() local
525 void __iomem *base = core->base; in hdmi_core_mask_interrupts() local
574 void __iomem *base = core->base; in hdmi5_core_handle_irqs() local
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