1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 47 #define AMDGPU_DM_MAX_CRTC 6 48 49 /* 50 #include "include/amdgpu_dal_power_if.h" 51 #include "amdgpu_dm_irq.h" 52 */ 53 54 #include "irq_types.h" 55 #include "signal_types.h" 56 #include "amdgpu_dm_crc.h" 57 58 /* Forward declarations */ 59 struct amdgpu_device; 60 struct drm_device; 61 struct amdgpu_dm_irq_handler_data; 62 struct dc; 63 struct amdgpu_bo; 64 struct dmub_srv; 65 66 struct common_irq_params { 67 struct amdgpu_device *adev; 68 enum dc_irq_source irq_src; 69 }; 70 71 /** 72 * struct dm_compressor_info - Buffer info used by frame buffer compression 73 * @cpu_addr: MMIO cpu addr 74 * @bo_ptr: Pointer to the buffer object 75 * @gpu_addr: MMIO gpu addr 76 */ 77 struct dm_compressor_info { 78 void *cpu_addr; 79 struct amdgpu_bo *bo_ptr; 80 uint64_t gpu_addr; 81 }; 82 83 /** 84 * struct amdgpu_dm_backlight_caps - Information about backlight 85 * 86 * Describe the backlight support for ACPI or eDP AUX. 87 */ 88 struct amdgpu_dm_backlight_caps { 89 /** 90 * @ext_caps: Keep the data struct with all the information about the 91 * display support for HDR. 92 */ 93 union dpcd_sink_ext_caps *ext_caps; 94 /** 95 * @aux_min_input_signal: Min brightness value supported by the display 96 */ 97 u32 aux_min_input_signal; 98 /** 99 * @aux_max_input_signal: Max brightness value supported by the display 100 * in nits. 101 */ 102 u32 aux_max_input_signal; 103 /** 104 * @min_input_signal: minimum possible input in range 0-255. 105 */ 106 int min_input_signal; 107 /** 108 * @max_input_signal: maximum possible input in range 0-255. 109 */ 110 int max_input_signal; 111 /** 112 * @caps_valid: true if these values are from the ACPI interface. 113 */ 114 bool caps_valid; 115 /** 116 * @aux_support: Describes if the display supports AUX backlight. 117 */ 118 bool aux_support; 119 }; 120 121 /** 122 * struct amdgpu_display_manager - Central amdgpu display manager device 123 * 124 * @dc: Display Core control structure 125 * @adev: AMDGPU base driver structure 126 * @ddev: DRM base driver structure 127 * @display_indexes_num: Max number of display streams supported 128 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 129 * @backlight_dev: Backlight control device 130 * @backlight_link: Link on which to control backlight 131 * @backlight_caps: Capabilities of the backlight device 132 * @freesync_module: Module handling freesync calculations 133 * @hdcp_workqueue: AMDGPU content protection queue 134 * @fw_dmcu: Reference to DMCU firmware 135 * @dmcu_fw_version: Version of the DMCU firmware 136 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 137 * @cached_state: Caches device atomic state for suspend/resume 138 * @cached_dc_state: Cached state of content streams 139 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 140 * @force_timing_sync: set via debugfs. When set, indicates that all connected 141 * displays will be forced to synchronize. 142 */ 143 struct amdgpu_display_manager { 144 145 struct dc *dc; 146 147 /** 148 * @dmub_srv: 149 * 150 * DMUB service, used for controlling the DMUB on hardware 151 * that supports it. The pointer to the dmub_srv will be 152 * NULL on hardware that does not support it. 153 */ 154 struct dmub_srv *dmub_srv; 155 156 /** 157 * @dmub_fb_info: 158 * 159 * Framebuffer regions for the DMUB. 160 */ 161 struct dmub_srv_fb_info *dmub_fb_info; 162 163 /** 164 * @dmub_fw: 165 * 166 * DMUB firmware, required on hardware that has DMUB support. 167 */ 168 const struct firmware *dmub_fw; 169 170 /** 171 * @dmub_bo: 172 * 173 * Buffer object for the DMUB. 174 */ 175 struct amdgpu_bo *dmub_bo; 176 177 /** 178 * @dmub_bo_gpu_addr: 179 * 180 * GPU virtual address for the DMUB buffer object. 181 */ 182 u64 dmub_bo_gpu_addr; 183 184 /** 185 * @dmub_bo_cpu_addr: 186 * 187 * CPU address for the DMUB buffer object. 188 */ 189 void *dmub_bo_cpu_addr; 190 191 /** 192 * @dmcub_fw_version: 193 * 194 * DMCUB firmware version. 195 */ 196 uint32_t dmcub_fw_version; 197 198 /** 199 * @cgs_device: 200 * 201 * The Common Graphics Services device. It provides an interface for 202 * accessing registers. 203 */ 204 struct cgs_device *cgs_device; 205 206 struct amdgpu_device *adev; 207 struct drm_device *ddev; 208 u16 display_indexes_num; 209 210 /** 211 * @atomic_obj: 212 * 213 * In combination with &dm_atomic_state it helps manage 214 * global atomic state that doesn't map cleanly into existing 215 * drm resources, like &dc_context. 216 */ 217 struct drm_private_obj atomic_obj; 218 219 /** 220 * @dc_lock: 221 * 222 * Guards access to DC functions that can issue register write 223 * sequences. 224 */ 225 struct mutex dc_lock; 226 227 /** 228 * @audio_lock: 229 * 230 * Guards access to audio instance changes. 231 */ 232 struct mutex audio_lock; 233 234 /** 235 * @audio_component: 236 * 237 * Used to notify ELD changes to sound driver. 238 */ 239 struct drm_audio_component *audio_component; 240 241 /** 242 * @audio_registered: 243 * 244 * True if the audio component has been registered 245 * successfully, false otherwise. 246 */ 247 bool audio_registered; 248 249 /** 250 * @irq_handler_list_low_tab: 251 * 252 * Low priority IRQ handler table. 253 * 254 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 255 * source. Low priority IRQ handlers are deferred to a workqueue to be 256 * processed. Hence, they can sleep. 257 * 258 * Note that handlers are called in the same order as they were 259 * registered (FIFO). 260 */ 261 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 262 263 /** 264 * @irq_handler_list_high_tab: 265 * 266 * High priority IRQ handler table. 267 * 268 * It is a n*m table, same as &irq_handler_list_low_tab. However, 269 * handlers in this table are not deferred and are called immediately. 270 */ 271 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 272 273 /** 274 * @pflip_params: 275 * 276 * Page flip IRQ parameters, passed to registered handlers when 277 * triggered. 278 */ 279 struct common_irq_params 280 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 281 282 /** 283 * @vblank_params: 284 * 285 * Vertical blanking IRQ parameters, passed to registered handlers when 286 * triggered. 287 */ 288 struct common_irq_params 289 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 290 291 /** 292 * @vupdate_params: 293 * 294 * Vertical update IRQ parameters, passed to registered handlers when 295 * triggered. 296 */ 297 struct common_irq_params 298 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 299 300 spinlock_t irq_handler_list_table_lock; 301 302 struct backlight_device *backlight_dev; 303 304 const struct dc_link *backlight_link; 305 struct amdgpu_dm_backlight_caps backlight_caps; 306 307 struct mod_freesync *freesync_module; 308 #ifdef CONFIG_DRM_AMD_DC_HDCP 309 struct hdcp_workqueue *hdcp_workqueue; 310 #endif 311 312 struct drm_atomic_state *cached_state; 313 struct dc_state *cached_dc_state; 314 315 struct dm_compressor_info compressor; 316 317 const struct firmware *fw_dmcu; 318 uint32_t dmcu_fw_version; 319 /** 320 * @soc_bounding_box: 321 * 322 * gpu_info FW provided soc bounding box struct or 0 if not 323 * available in FW 324 */ 325 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 326 327 /** 328 * @mst_encoders: 329 * 330 * fake encoders used for DP MST. 331 */ 332 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 333 bool force_timing_sync; 334 }; 335 336 enum dsc_clock_force_state { 337 DSC_CLK_FORCE_DEFAULT = 0, 338 DSC_CLK_FORCE_ENABLE, 339 DSC_CLK_FORCE_DISABLE, 340 }; 341 342 struct dsc_preferred_settings { 343 enum dsc_clock_force_state dsc_force_enable; 344 uint32_t dsc_num_slices_v; 345 uint32_t dsc_num_slices_h; 346 uint32_t dsc_bits_per_pixel; 347 }; 348 349 struct amdgpu_dm_connector { 350 351 struct drm_connector base; 352 uint32_t connector_id; 353 354 /* we need to mind the EDID between detect 355 and get modes due to analog/digital/tvencoder */ 356 struct edid *edid; 357 358 /* shared with amdgpu */ 359 struct amdgpu_hpd hpd; 360 361 /* number of modes generated from EDID at 'dc_sink' */ 362 int num_modes; 363 364 /* The 'old' sink - before an HPD. 365 * The 'current' sink is in dc_link->sink. */ 366 struct dc_sink *dc_sink; 367 struct dc_link *dc_link; 368 struct dc_sink *dc_em_sink; 369 370 /* DM only */ 371 struct drm_dp_mst_topology_mgr mst_mgr; 372 struct amdgpu_dm_dp_aux dm_dp_aux; 373 struct drm_dp_mst_port *port; 374 struct amdgpu_dm_connector *mst_port; 375 struct drm_dp_aux *dsc_aux; 376 377 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 378 struct amdgpu_i2c_adapter *i2c; 379 380 /* Monitor range limits */ 381 int min_vfreq ; 382 int max_vfreq ; 383 int pixel_clock_mhz; 384 385 /* Audio instance - protected by audio_lock. */ 386 int audio_inst; 387 388 struct mutex hpd_lock; 389 390 bool fake_enable; 391 #ifdef CONFIG_DEBUG_FS 392 uint32_t debugfs_dpcd_address; 393 uint32_t debugfs_dpcd_size; 394 #endif 395 bool force_yuv420_output; 396 struct dsc_preferred_settings dsc_settings; 397 }; 398 399 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 400 401 extern const struct amdgpu_ip_block_version dm_ip_block; 402 403 struct amdgpu_framebuffer; 404 struct amdgpu_display_manager; 405 struct dc_validation_set; 406 struct dc_plane_state; 407 408 struct dm_plane_state { 409 struct drm_plane_state base; 410 struct dc_plane_state *dc_state; 411 uint64_t tiling_flags; 412 bool tmz_surface; 413 }; 414 415 struct dm_crtc_state { 416 struct drm_crtc_state base; 417 struct dc_stream_state *stream; 418 419 bool cm_has_degamma; 420 bool cm_is_degamma_srgb; 421 422 int update_type; 423 int active_planes; 424 425 int crc_skip_count; 426 enum amdgpu_dm_pipe_crc_source crc_src; 427 428 bool freesync_timing_changed; 429 bool freesync_vrr_info_changed; 430 431 bool vrr_supported; 432 struct mod_freesync_config freesync_config; 433 struct dc_info_packet vrr_infopacket; 434 435 int abm_level; 436 }; 437 438 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 439 440 struct dm_atomic_state { 441 struct drm_private_state base; 442 443 struct dc_state *context; 444 }; 445 446 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 447 448 struct dm_connector_state { 449 struct drm_connector_state base; 450 451 enum amdgpu_rmx_type scaling; 452 uint8_t underscan_vborder; 453 uint8_t underscan_hborder; 454 bool underscan_enable; 455 bool freesync_capable; 456 uint8_t abm_level; 457 int vcpi_slots; 458 uint64_t pbn; 459 }; 460 461 #define to_dm_connector_state(x)\ 462 container_of((x), struct dm_connector_state, base) 463 464 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 465 struct drm_connector_state * 466 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 467 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 468 struct drm_connector_state *state, 469 struct drm_property *property, 470 uint64_t val); 471 472 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 473 const struct drm_connector_state *state, 474 struct drm_property *property, 475 uint64_t *val); 476 477 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 478 479 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 480 struct amdgpu_dm_connector *aconnector, 481 int connector_type, 482 struct dc_link *link, 483 int link_index); 484 485 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 486 struct drm_display_mode *mode); 487 488 void dm_restore_drm_connector_state(struct drm_device *dev, 489 struct drm_connector *connector); 490 491 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 492 struct edid *edid); 493 494 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 495 496 #define MAX_COLOR_LUT_ENTRIES 4096 497 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 498 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 499 500 void amdgpu_dm_init_color_mod(void); 501 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 502 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 503 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 504 struct dc_plane_state *dc_plane_state); 505 506 void amdgpu_dm_update_connector_after_detect( 507 struct amdgpu_dm_connector *aconnector); 508 509 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 510 511 #endif /* __AMDGPU_DM_H__ */ 512