1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "atom.h"
29
30 #include "include/bios_parser_types.h"
31
32 #include "../command_table_helper.h"
33
phy_id_to_atom(enum transmitter t)34 static uint8_t phy_id_to_atom(enum transmitter t)
35 {
36 uint8_t atom_phy_id;
37
38 switch (t) {
39 case TRANSMITTER_UNIPHY_A:
40 atom_phy_id = ATOM_PHY_ID_UNIPHYA;
41 break;
42 case TRANSMITTER_UNIPHY_B:
43 atom_phy_id = ATOM_PHY_ID_UNIPHYB;
44 break;
45 case TRANSMITTER_UNIPHY_C:
46 atom_phy_id = ATOM_PHY_ID_UNIPHYC;
47 break;
48 case TRANSMITTER_UNIPHY_D:
49 atom_phy_id = ATOM_PHY_ID_UNIPHYD;
50 break;
51 case TRANSMITTER_UNIPHY_E:
52 atom_phy_id = ATOM_PHY_ID_UNIPHYE;
53 break;
54 case TRANSMITTER_UNIPHY_F:
55 atom_phy_id = ATOM_PHY_ID_UNIPHYF;
56 break;
57 case TRANSMITTER_UNIPHY_G:
58 atom_phy_id = ATOM_PHY_ID_UNIPHYG;
59 break;
60 default:
61 atom_phy_id = ATOM_PHY_ID_UNIPHYA;
62 break;
63 }
64 return atom_phy_id;
65 }
66
signal_type_to_atom_dig_mode(enum signal_type s)67 static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
68 {
69 uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
70
71 switch (s) {
72 case SIGNAL_TYPE_DISPLAY_PORT:
73 case SIGNAL_TYPE_EDP:
74 atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
75 break;
76 case SIGNAL_TYPE_LVDS:
77 atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_LVDS;
78 break;
79 case SIGNAL_TYPE_DVI_SINGLE_LINK:
80 case SIGNAL_TYPE_DVI_DUAL_LINK:
81 atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
82 break;
83 case SIGNAL_TYPE_HDMI_TYPE_A:
84 atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_HDMI;
85 break;
86 case SIGNAL_TYPE_DISPLAY_PORT_MST:
87 atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP_MST;
88 break;
89 default:
90 atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
91 break;
92 }
93
94 return atom_dig_mode;
95 }
96
clock_source_id_to_atom_phy_clk_src_id(enum clock_source_id id)97 static uint8_t clock_source_id_to_atom_phy_clk_src_id(
98 enum clock_source_id id)
99 {
100 uint8_t atom_phy_clk_src_id = 0;
101
102 switch (id) {
103 case CLOCK_SOURCE_ID_PLL0:
104 atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P0PLL;
105 break;
106 case CLOCK_SOURCE_ID_PLL1:
107 atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
108 break;
109 case CLOCK_SOURCE_ID_PLL2:
110 atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P2PLL;
111 break;
112 case CLOCK_SOURCE_ID_EXTERNAL:
113 atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT;
114 break;
115 default:
116 atom_phy_clk_src_id = ATOM_TRANSMITTER_CONFIG_V5_P1PLL;
117 break;
118 }
119
120 return atom_phy_clk_src_id >> 2;
121 }
122
hpd_sel_to_atom(enum hpd_source_id id)123 static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
124 {
125 uint8_t atom_hpd_sel = 0;
126
127 switch (id) {
128 case HPD_SOURCEID1:
129 atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL;
130 break;
131 case HPD_SOURCEID2:
132 atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL;
133 break;
134 case HPD_SOURCEID3:
135 atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL;
136 break;
137 case HPD_SOURCEID4:
138 atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL;
139 break;
140 case HPD_SOURCEID5:
141 atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL;
142 break;
143 case HPD_SOURCEID6:
144 atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL;
145 break;
146 case HPD_SOURCEID_UNKNOWN:
147 default:
148 atom_hpd_sel = 0;
149 break;
150 }
151 return atom_hpd_sel >> 4;
152 }
153
dig_encoder_sel_to_atom(enum engine_id id)154 static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
155 {
156 /* On any ASIC after DCE80, we manually program the DIG_FE
157 * selection (see connect_dig_be_to_fe function of the link
158 * encoder), so translation should always return 0 (no FE).
159 */
160
161 return 0;
162 }
163
clock_source_id_to_atom(enum clock_source_id id,uint32_t * atom_pll_id)164 static bool clock_source_id_to_atom(
165 enum clock_source_id id,
166 uint32_t *atom_pll_id)
167 {
168 bool result = true;
169
170 if (atom_pll_id != NULL)
171 switch (id) {
172 case CLOCK_SOURCE_ID_PLL0:
173 *atom_pll_id = ATOM_PPLL0;
174 break;
175 case CLOCK_SOURCE_ID_PLL1:
176 *atom_pll_id = ATOM_PPLL1;
177 break;
178 case CLOCK_SOURCE_ID_PLL2:
179 *atom_pll_id = ATOM_PPLL2;
180 break;
181 case CLOCK_SOURCE_ID_EXTERNAL:
182 *atom_pll_id = ATOM_PPLL_INVALID;
183 break;
184 case CLOCK_SOURCE_ID_DFS:
185 *atom_pll_id = ATOM_EXT_PLL1;
186 break;
187 case CLOCK_SOURCE_ID_VCE:
188 /* for VCE encoding,
189 * we need to pass in ATOM_PPLL_INVALID
190 */
191 *atom_pll_id = ATOM_PPLL_INVALID;
192 break;
193 case CLOCK_SOURCE_ID_DP_DTO:
194 /* When programming DP DTO PLL ID should be invalid */
195 *atom_pll_id = ATOM_PPLL_INVALID;
196 break;
197 case CLOCK_SOURCE_ID_UNDEFINED:
198 /* Should not happen */
199 *atom_pll_id = ATOM_PPLL_INVALID;
200 result = false;
201 break;
202 default:
203 result = false;
204 break;
205 }
206
207 return result;
208 }
209
engine_bp_to_atom(enum engine_id id,uint32_t * atom_engine_id)210 static bool engine_bp_to_atom(enum engine_id id, uint32_t *atom_engine_id)
211 {
212 bool result = false;
213
214 if (atom_engine_id != NULL)
215 switch (id) {
216 case ENGINE_ID_DIGA:
217 *atom_engine_id = ASIC_INT_DIG1_ENCODER_ID;
218 result = true;
219 break;
220 case ENGINE_ID_DIGB:
221 *atom_engine_id = ASIC_INT_DIG2_ENCODER_ID;
222 result = true;
223 break;
224 case ENGINE_ID_DIGC:
225 *atom_engine_id = ASIC_INT_DIG3_ENCODER_ID;
226 result = true;
227 break;
228 case ENGINE_ID_DIGD:
229 *atom_engine_id = ASIC_INT_DIG4_ENCODER_ID;
230 result = true;
231 break;
232 case ENGINE_ID_DIGE:
233 *atom_engine_id = ASIC_INT_DIG5_ENCODER_ID;
234 result = true;
235 break;
236 case ENGINE_ID_DIGF:
237 *atom_engine_id = ASIC_INT_DIG6_ENCODER_ID;
238 result = true;
239 break;
240 case ENGINE_ID_DIGG:
241 *atom_engine_id = ASIC_INT_DIG7_ENCODER_ID;
242 result = true;
243 break;
244 case ENGINE_ID_DACA:
245 *atom_engine_id = ASIC_INT_DAC1_ENCODER_ID;
246 result = true;
247 break;
248 default:
249 break;
250 }
251
252 return result;
253 }
254
encoder_action_to_atom(enum bp_encoder_control_action action)255 static uint8_t encoder_action_to_atom(enum bp_encoder_control_action action)
256 {
257 uint8_t atom_action = 0;
258
259 switch (action) {
260 case ENCODER_CONTROL_ENABLE:
261 atom_action = ATOM_ENABLE;
262 break;
263 case ENCODER_CONTROL_DISABLE:
264 atom_action = ATOM_DISABLE;
265 break;
266 case ENCODER_CONTROL_SETUP:
267 atom_action = ATOM_ENCODER_CMD_SETUP;
268 break;
269 case ENCODER_CONTROL_INIT:
270 atom_action = ATOM_ENCODER_INIT;
271 break;
272 default:
273 BREAK_TO_DEBUGGER(); /* Unhandle action in driver.!! */
274 break;
275 }
276
277 return atom_action;
278 }
279
disp_power_gating_action_to_atom(enum bp_pipe_control_action action)280 static uint8_t disp_power_gating_action_to_atom(
281 enum bp_pipe_control_action action)
282 {
283 uint8_t atom_pipe_action = 0;
284
285 switch (action) {
286 case ASIC_PIPE_DISABLE:
287 atom_pipe_action = ATOM_DISABLE;
288 break;
289 case ASIC_PIPE_ENABLE:
290 atom_pipe_action = ATOM_ENABLE;
291 break;
292 case ASIC_PIPE_INIT:
293 atom_pipe_action = ATOM_INIT;
294 break;
295 default:
296 ASSERT_CRITICAL(false); /* Unhandle action in driver! */
297 break;
298 }
299
300 return atom_pipe_action;
301 }
302
303 /* function table */
304 static const struct command_table_helper command_table_helper_funcs = {
305 .controller_id_to_atom = dal_cmd_table_helper_controller_id_to_atom,
306 .encoder_action_to_atom = encoder_action_to_atom,
307 .engine_bp_to_atom = engine_bp_to_atom,
308 .clock_source_id_to_atom = clock_source_id_to_atom,
309 .clock_source_id_to_atom_phy_clk_src_id =
310 clock_source_id_to_atom_phy_clk_src_id,
311 .signal_type_to_atom_dig_mode = signal_type_to_atom_dig_mode,
312 .hpd_sel_to_atom = hpd_sel_to_atom,
313 .dig_encoder_sel_to_atom = dig_encoder_sel_to_atom,
314 .phy_id_to_atom = phy_id_to_atom,
315 .disp_power_gating_action_to_atom = disp_power_gating_action_to_atom,
316 .assign_control_parameter = NULL,
317 .clock_source_id_to_ref_clk_src = NULL,
318 .transmitter_bp_to_atom = NULL,
319 .encoder_id_to_atom = dal_cmd_table_helper_encoder_id_to_atom,
320 .encoder_mode_bp_to_atom = dal_cmd_table_helper_encoder_mode_bp_to_atom,
321 };
322
323 /*
324 * dal_cmd_tbl_helper_dce110_get_table
325 *
326 * @brief
327 * Initialize command table helper functions
328 *
329 * @param
330 * const struct command_table_helper **h - [out] struct of functions
331 *
332 */
dal_cmd_tbl_helper_dce110_get_table(void)333 const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table(void)
334 {
335 return &command_table_helper_funcs;
336 }
337