1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * TI Camera Access Layer (CAL) - CAMERARX
4 *
5 * Copyright (c) 2015-2020 Texas Instruments Inc.
6 *
7 * Authors:
8 * Benoit Parrot <bparrot@ti.com>
9 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 */
11
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of_graph.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-subdev.h>
24
25 #include "cal.h"
26 #include "cal_regs.h"
27
28 /* ------------------------------------------------------------------
29 * I/O Register Accessors
30 * ------------------------------------------------------------------
31 */
32
camerarx_read(struct cal_camerarx * phy,u32 offset)33 static inline u32 camerarx_read(struct cal_camerarx *phy, u32 offset)
34 {
35 return ioread32(phy->base + offset);
36 }
37
camerarx_write(struct cal_camerarx * phy,u32 offset,u32 val)38 static inline void camerarx_write(struct cal_camerarx *phy, u32 offset, u32 val)
39 {
40 iowrite32(val, phy->base + offset);
41 }
42
43 /* ------------------------------------------------------------------
44 * CAMERARX Management
45 * ------------------------------------------------------------------
46 */
47
cal_camerarx_get_external_rate(struct cal_camerarx * phy)48 static s64 cal_camerarx_get_external_rate(struct cal_camerarx *phy)
49 {
50 struct v4l2_ctrl *ctrl;
51 s64 rate;
52
53 ctrl = v4l2_ctrl_find(phy->sensor->ctrl_handler, V4L2_CID_PIXEL_RATE);
54 if (!ctrl) {
55 phy_err(phy, "no pixel rate control in subdev: %s\n",
56 phy->sensor->name);
57 return -EPIPE;
58 }
59
60 rate = v4l2_ctrl_g_ctrl_int64(ctrl);
61 phy_dbg(3, phy, "sensor Pixel Rate: %llu\n", rate);
62
63 return rate;
64 }
65
cal_camerarx_lane_config(struct cal_camerarx * phy)66 static void cal_camerarx_lane_config(struct cal_camerarx *phy)
67 {
68 u32 val = cal_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance));
69 u32 lane_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK;
70 u32 polarity_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK;
71 struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 =
72 &phy->endpoint.bus.mipi_csi2;
73 int lane;
74
75 cal_set_field(&val, mipi_csi2->clock_lane + 1, lane_mask);
76 cal_set_field(&val, mipi_csi2->lane_polarities[0], polarity_mask);
77 for (lane = 0; lane < mipi_csi2->num_data_lanes; lane++) {
78 /*
79 * Every lane are one nibble apart starting with the
80 * clock followed by the data lanes so shift masks by 4.
81 */
82 lane_mask <<= 4;
83 polarity_mask <<= 4;
84 cal_set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask);
85 cal_set_field(&val, mipi_csi2->lane_polarities[lane + 1],
86 polarity_mask);
87 }
88
89 cal_write(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance), val);
90 phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x\n",
91 phy->instance, val);
92 }
93
cal_camerarx_enable(struct cal_camerarx * phy)94 static void cal_camerarx_enable(struct cal_camerarx *phy)
95 {
96 u32 num_lanes = phy->cal->data->camerarx[phy->instance].num_lanes;
97
98 regmap_field_write(phy->fields[F_CAMMODE], 0);
99 /* Always enable all lanes at the phy control level */
100 regmap_field_write(phy->fields[F_LANEENABLE], (1 << num_lanes) - 1);
101 /* F_CSI_MODE is not present on every architecture */
102 if (phy->fields[F_CSI_MODE])
103 regmap_field_write(phy->fields[F_CSI_MODE], 1);
104 regmap_field_write(phy->fields[F_CTRLCLKEN], 1);
105 }
106
cal_camerarx_disable(struct cal_camerarx * phy)107 void cal_camerarx_disable(struct cal_camerarx *phy)
108 {
109 regmap_field_write(phy->fields[F_CTRLCLKEN], 0);
110 }
111
112 /*
113 * TCLK values are OK at their reset values
114 */
115 #define TCLK_TERM 0
116 #define TCLK_MISS 1
117 #define TCLK_SETTLE 14
118
cal_camerarx_config(struct cal_camerarx * phy,s64 external_rate,const struct cal_fmt * fmt)119 static void cal_camerarx_config(struct cal_camerarx *phy, s64 external_rate,
120 const struct cal_fmt *fmt)
121 {
122 unsigned int reg0, reg1;
123 unsigned int ths_term, ths_settle;
124 unsigned int csi2_ddrclk_khz;
125 struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 =
126 &phy->endpoint.bus.mipi_csi2;
127 u32 num_lanes = mipi_csi2->num_data_lanes;
128
129 /* DPHY timing configuration */
130
131 /*
132 * CSI-2 is DDR and we only count used lanes.
133 *
134 * csi2_ddrclk_khz = external_rate / 1000
135 * / (2 * num_lanes) * fmt->bpp;
136 */
137 csi2_ddrclk_khz = div_s64(external_rate * fmt->bpp,
138 2 * num_lanes * 1000);
139
140 phy_dbg(1, phy, "csi2_ddrclk_khz: %d\n", csi2_ddrclk_khz);
141
142 /* THS_TERM: Programmed value = floor(20 ns/DDRClk period) */
143 ths_term = 20 * csi2_ddrclk_khz / 1000000;
144 phy_dbg(1, phy, "ths_term: %d (0x%02x)\n", ths_term, ths_term);
145
146 /* THS_SETTLE: Programmed value = floor(105 ns/DDRClk period) + 4 */
147 ths_settle = (105 * csi2_ddrclk_khz / 1000000) + 4;
148 phy_dbg(1, phy, "ths_settle: %d (0x%02x)\n", ths_settle, ths_settle);
149
150 reg0 = camerarx_read(phy, CAL_CSI2_PHY_REG0);
151 cal_set_field(®0, CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE,
152 CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK);
153 cal_set_field(®0, ths_term, CAL_CSI2_PHY_REG0_THS_TERM_MASK);
154 cal_set_field(®0, ths_settle, CAL_CSI2_PHY_REG0_THS_SETTLE_MASK);
155
156 phy_dbg(1, phy, "CSI2_%d_REG0 = 0x%08x\n", phy->instance, reg0);
157 camerarx_write(phy, CAL_CSI2_PHY_REG0, reg0);
158
159 reg1 = camerarx_read(phy, CAL_CSI2_PHY_REG1);
160 cal_set_field(®1, TCLK_TERM, CAL_CSI2_PHY_REG1_TCLK_TERM_MASK);
161 cal_set_field(®1, 0xb8, CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK);
162 cal_set_field(®1, TCLK_MISS,
163 CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK);
164 cal_set_field(®1, TCLK_SETTLE, CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK);
165
166 phy_dbg(1, phy, "CSI2_%d_REG1 = 0x%08x\n", phy->instance, reg1);
167 camerarx_write(phy, CAL_CSI2_PHY_REG1, reg1);
168 }
169
cal_camerarx_power(struct cal_camerarx * phy,bool enable)170 static void cal_camerarx_power(struct cal_camerarx *phy, bool enable)
171 {
172 u32 target_state;
173 unsigned int i;
174
175 target_state = enable ? CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON :
176 CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF;
177
178 cal_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
179 target_state, CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK);
180
181 for (i = 0; i < 10; i++) {
182 u32 current_state;
183
184 current_state = cal_read_field(phy->cal,
185 CAL_CSI2_COMPLEXIO_CFG(phy->instance),
186 CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK);
187
188 if (current_state == target_state)
189 break;
190
191 usleep_range(1000, 1100);
192 }
193
194 if (i == 10)
195 phy_err(phy, "Failed to power %s complexio\n",
196 enable ? "up" : "down");
197 }
198
cal_camerarx_wait_reset(struct cal_camerarx * phy)199 static void cal_camerarx_wait_reset(struct cal_camerarx *phy)
200 {
201 unsigned long timeout;
202
203 timeout = jiffies + msecs_to_jiffies(750);
204 while (time_before(jiffies, timeout)) {
205 if (cal_read_field(phy->cal,
206 CAL_CSI2_COMPLEXIO_CFG(phy->instance),
207 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==
208 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
209 break;
210 usleep_range(500, 5000);
211 }
212
213 if (cal_read_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
214 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) !=
215 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
216 phy_err(phy, "Timeout waiting for Complex IO reset done\n");
217 }
218
cal_camerarx_wait_stop_state(struct cal_camerarx * phy)219 static void cal_camerarx_wait_stop_state(struct cal_camerarx *phy)
220 {
221 unsigned long timeout;
222
223 timeout = jiffies + msecs_to_jiffies(750);
224 while (time_before(jiffies, timeout)) {
225 if (cal_read_field(phy->cal,
226 CAL_CSI2_TIMING(phy->instance),
227 CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) == 0)
228 break;
229 usleep_range(500, 5000);
230 }
231
232 if (cal_read_field(phy->cal, CAL_CSI2_TIMING(phy->instance),
233 CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) != 0)
234 phy_err(phy, "Timeout waiting for stop state\n");
235 }
236
cal_camerarx_start(struct cal_camerarx * phy,const struct cal_fmt * fmt)237 int cal_camerarx_start(struct cal_camerarx *phy, const struct cal_fmt *fmt)
238 {
239 s64 external_rate;
240 u32 sscounter;
241 u32 val;
242 int ret;
243
244 external_rate = cal_camerarx_get_external_rate(phy);
245 if (external_rate < 0)
246 return external_rate;
247
248 ret = v4l2_subdev_call(phy->sensor, core, s_power, 1);
249 if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV) {
250 phy_err(phy, "power on failed in subdev\n");
251 return ret;
252 }
253
254 /*
255 * CSI-2 PHY Link Initialization Sequence, according to the DRA74xP /
256 * DRA75xP / DRA76xP / DRA77xP TRM. The DRA71x / DRA72x and the AM65x /
257 * DRA80xM TRMs have a a slightly simplified sequence.
258 */
259
260 /*
261 * 1. Configure all CSI-2 low level protocol registers to be ready to
262 * receive signals/data from the CSI-2 PHY.
263 *
264 * i.-v. Configure the lanes position and polarity.
265 */
266 cal_camerarx_lane_config(phy);
267
268 /*
269 * vi.-vii. Configure D-PHY mode, enable the required lanes and
270 * enable the CAMERARX clock.
271 */
272 cal_camerarx_enable(phy);
273
274 /*
275 * 2. CSI PHY and link initialization sequence.
276 *
277 * a. Deassert the CSI-2 PHY reset. Do not wait for reset completion
278 * at this point, as it requires the external sensor to send the
279 * CSI-2 HS clock.
280 */
281 cal_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
282 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL,
283 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK);
284 phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x De-assert Complex IO Reset\n",
285 phy->instance,
286 cal_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance)));
287
288 /* Dummy read to allow SCP reset to complete. */
289 camerarx_read(phy, CAL_CSI2_PHY_REG0);
290
291 /* Program the PHY timing parameters. */
292 cal_camerarx_config(phy, external_rate, fmt);
293
294 /*
295 * b. Assert the FORCERXMODE signal.
296 *
297 * The stop-state-counter is based on fclk cycles, and we always use
298 * the x16 and x4 settings, so stop-state-timeout =
299 * fclk-cycle * 16 * 4 * counter.
300 *
301 * Stop-state-timeout must be more than 100us as per CSI-2 spec, so we
302 * calculate a timeout that's 100us (rounding up).
303 */
304 sscounter = DIV_ROUND_UP(clk_get_rate(phy->cal->fclk), 10000 * 16 * 4);
305
306 val = cal_read(phy->cal, CAL_CSI2_TIMING(phy->instance));
307 cal_set_field(&val, 1, CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK);
308 cal_set_field(&val, 1, CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK);
309 cal_set_field(&val, sscounter,
310 CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK);
311 cal_write(phy->cal, CAL_CSI2_TIMING(phy->instance), val);
312 phy_dbg(3, phy, "CAL_CSI2_TIMING(%d) = 0x%08x Stop States\n",
313 phy->instance,
314 cal_read(phy->cal, CAL_CSI2_TIMING(phy->instance)));
315
316 /* Assert the FORCERXMODE signal. */
317 cal_write_field(phy->cal, CAL_CSI2_TIMING(phy->instance),
318 1, CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK);
319 phy_dbg(3, phy, "CAL_CSI2_TIMING(%d) = 0x%08x Force RXMODE\n",
320 phy->instance,
321 cal_read(phy->cal, CAL_CSI2_TIMING(phy->instance)));
322
323 /*
324 * c. Connect pull-down on CSI-2 PHY link (using pad control).
325 *
326 * This is not required on DRA71x, DRA72x, AM65x and DRA80xM. Not
327 * implemented.
328 */
329
330 /*
331 * d. Power up the CSI-2 PHY.
332 * e. Check whether the state status reaches the ON state.
333 */
334 cal_camerarx_power(phy, true);
335
336 /*
337 * Start the sensor to enable the CSI-2 HS clock. We can now wait for
338 * CSI-2 PHY reset to complete.
339 */
340 ret = v4l2_subdev_call(phy->sensor, video, s_stream, 1);
341 if (ret) {
342 v4l2_subdev_call(phy->sensor, core, s_power, 0);
343 phy_err(phy, "stream on failed in subdev\n");
344 return ret;
345 }
346
347 cal_camerarx_wait_reset(phy);
348
349 /* f. Wait for STOPSTATE=1 for all enabled lane modules. */
350 cal_camerarx_wait_stop_state(phy);
351
352 phy_dbg(1, phy, "CSI2_%u_REG1 = 0x%08x (bits 31-28 should be set)\n",
353 phy->instance, camerarx_read(phy, CAL_CSI2_PHY_REG1));
354
355 /*
356 * g. Disable pull-down on CSI-2 PHY link (using pad control).
357 *
358 * This is not required on DRA71x, DRA72x, AM65x and DRA80xM. Not
359 * implemented.
360 */
361
362 return 0;
363 }
364
cal_camerarx_stop(struct cal_camerarx * phy)365 void cal_camerarx_stop(struct cal_camerarx *phy)
366 {
367 unsigned int i;
368 int ret;
369
370 cal_camerarx_power(phy, false);
371
372 /* Assert Complex IO Reset */
373 cal_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance),
374 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL,
375 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK);
376
377 /* Wait for power down completion */
378 for (i = 0; i < 10; i++) {
379 if (cal_read_field(phy->cal,
380 CAL_CSI2_COMPLEXIO_CFG(phy->instance),
381 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) ==
382 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETONGOING)
383 break;
384 usleep_range(1000, 1100);
385 }
386 phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO in Reset (%d) %s\n",
387 phy->instance,
388 cal_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance)), i,
389 (i >= 10) ? "(timeout)" : "");
390
391 /* Disable the phy */
392 cal_camerarx_disable(phy);
393
394 if (v4l2_subdev_call(phy->sensor, video, s_stream, 0))
395 phy_err(phy, "stream off failed in subdev\n");
396
397 ret = v4l2_subdev_call(phy->sensor, core, s_power, 0);
398 if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
399 phy_err(phy, "power off failed in subdev\n");
400 }
401
402 /*
403 * Errata i913: CSI2 LDO Needs to be disabled when module is powered on
404 *
405 * Enabling CSI2 LDO shorts it to core supply. It is crucial the 2 CSI2
406 * LDOs on the device are disabled if CSI-2 module is powered on
407 * (0x4845 B304 | 0x4845 B384 [28:27] = 0x1) or in ULPS (0x4845 B304
408 * | 0x4845 B384 [28:27] = 0x2) mode. Common concerns include: high
409 * current draw on the module supply in active mode.
410 *
411 * Errata does not apply when CSI-2 module is powered off
412 * (0x4845 B304 | 0x4845 B384 [28:27] = 0x0).
413 *
414 * SW Workaround:
415 * Set the following register bits to disable the LDO,
416 * which is essentially CSI2 REG10 bit 6:
417 *
418 * Core 0: 0x4845 B828 = 0x0000 0040
419 * Core 1: 0x4845 B928 = 0x0000 0040
420 */
cal_camerarx_i913_errata(struct cal_camerarx * phy)421 void cal_camerarx_i913_errata(struct cal_camerarx *phy)
422 {
423 u32 reg10 = camerarx_read(phy, CAL_CSI2_PHY_REG10);
424
425 cal_set_field(®10, 1, CAL_CSI2_PHY_REG10_I933_LDO_DISABLE_MASK);
426
427 phy_dbg(1, phy, "CSI2_%d_REG10 = 0x%08x\n", phy->instance, reg10);
428 camerarx_write(phy, CAL_CSI2_PHY_REG10, reg10);
429 }
430
431 /*
432 * Enable the expected IRQ sources
433 */
cal_camerarx_enable_irqs(struct cal_camerarx * phy)434 void cal_camerarx_enable_irqs(struct cal_camerarx *phy)
435 {
436 u32 val;
437
438 const u32 cio_err_mask =
439 CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK |
440 CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK |
441 CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK |
442 CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK;
443
444 /* Enable CIO error irqs */
445 cal_write(phy->cal, CAL_HL_IRQENABLE_SET(0),
446 CAL_HL_IRQ_CIO_MASK(phy->instance));
447 cal_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance),
448 cio_err_mask);
449
450 /* Always enable OCPO error */
451 cal_write(phy->cal, CAL_HL_IRQENABLE_SET(0), CAL_HL_IRQ_OCPO_ERR_MASK);
452
453 /* Enable IRQ_WDMA_END 0/1 */
454 val = 0;
455 cal_set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance));
456 cal_write(phy->cal, CAL_HL_IRQENABLE_SET(1), val);
457 /* Enable IRQ_WDMA_START 0/1 */
458 val = 0;
459 cal_set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance));
460 cal_write(phy->cal, CAL_HL_IRQENABLE_SET(2), val);
461 /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */
462 cal_write(phy->cal, CAL_CSI2_VC_IRQENABLE(0), 0xFF000000);
463 }
464
cal_camerarx_disable_irqs(struct cal_camerarx * phy)465 void cal_camerarx_disable_irqs(struct cal_camerarx *phy)
466 {
467 u32 val;
468
469 /* Disable CIO error irqs */
470 cal_write(phy->cal, CAL_HL_IRQENABLE_CLR(0),
471 CAL_HL_IRQ_CIO_MASK(phy->instance));
472 cal_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance), 0);
473
474 /* Disable IRQ_WDMA_END 0/1 */
475 val = 0;
476 cal_set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance));
477 cal_write(phy->cal, CAL_HL_IRQENABLE_CLR(1), val);
478 /* Disable IRQ_WDMA_START 0/1 */
479 val = 0;
480 cal_set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance));
481 cal_write(phy->cal, CAL_HL_IRQENABLE_CLR(2), val);
482 /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */
483 cal_write(phy->cal, CAL_CSI2_VC_IRQENABLE(0), 0);
484 }
485
cal_camerarx_ppi_enable(struct cal_camerarx * phy)486 void cal_camerarx_ppi_enable(struct cal_camerarx *phy)
487 {
488 cal_write(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance), BIT(3));
489 cal_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance),
490 1, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
491 }
492
cal_camerarx_ppi_disable(struct cal_camerarx * phy)493 void cal_camerarx_ppi_disable(struct cal_camerarx *phy)
494 {
495 cal_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance),
496 0, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
497 }
498
cal_camerarx_regmap_init(struct cal_dev * cal,struct cal_camerarx * phy)499 static int cal_camerarx_regmap_init(struct cal_dev *cal,
500 struct cal_camerarx *phy)
501 {
502 const struct cal_camerarx_data *phy_data;
503 unsigned int i;
504
505 if (!cal->data)
506 return -EINVAL;
507
508 phy_data = &cal->data->camerarx[phy->instance];
509
510 for (i = 0; i < F_MAX_FIELDS; i++) {
511 struct reg_field field = {
512 .reg = cal->syscon_camerrx_offset,
513 .lsb = phy_data->fields[i].lsb,
514 .msb = phy_data->fields[i].msb,
515 };
516
517 /*
518 * Here we update the reg offset with the
519 * value found in DT
520 */
521 phy->fields[i] = devm_regmap_field_alloc(cal->dev,
522 cal->syscon_camerrx,
523 field);
524 if (IS_ERR(phy->fields[i])) {
525 cal_err(cal, "Unable to allocate regmap fields\n");
526 return PTR_ERR(phy->fields[i]);
527 }
528 }
529
530 return 0;
531 }
532
cal_camerarx_parse_dt(struct cal_camerarx * phy)533 static int cal_camerarx_parse_dt(struct cal_camerarx *phy)
534 {
535 struct v4l2_fwnode_endpoint *endpoint = &phy->endpoint;
536 struct device_node *ep_node;
537 char data_lanes[V4L2_FWNODE_CSI2_MAX_DATA_LANES * 2];
538 unsigned int i;
539 int ret;
540
541 /*
542 * Find the endpoint node for the port corresponding to the PHY
543 * instance, and parse its CSI-2-related properties.
544 */
545 ep_node = of_graph_get_endpoint_by_regs(phy->cal->dev->of_node,
546 phy->instance, 0);
547 if (!ep_node) {
548 /*
549 * The endpoint is not mandatory, not all PHY instances need to
550 * be connected in DT.
551 */
552 phy_dbg(3, phy, "Port has no endpoint\n");
553 return 0;
554 }
555
556 endpoint->bus_type = V4L2_MBUS_CSI2_DPHY;
557 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), endpoint);
558 if (ret < 0) {
559 phy_err(phy, "Failed to parse endpoint\n");
560 goto done;
561 }
562
563 for (i = 0; i < endpoint->bus.mipi_csi2.num_data_lanes; i++) {
564 unsigned int lane = endpoint->bus.mipi_csi2.data_lanes[i];
565
566 if (lane > 4) {
567 phy_err(phy, "Invalid position %u for data lane %u\n",
568 lane, i);
569 ret = -EINVAL;
570 goto done;
571 }
572
573 data_lanes[i*2] = '0' + lane;
574 data_lanes[i*2+1] = ' ';
575 }
576
577 data_lanes[i*2-1] = '\0';
578
579 phy_dbg(3, phy,
580 "CSI-2 bus: clock lane <%u>, data lanes <%s>, flags 0x%08x\n",
581 endpoint->bus.mipi_csi2.clock_lane, data_lanes,
582 endpoint->bus.mipi_csi2.flags);
583
584 /* Retrieve the connected device and store it for later use. */
585 phy->sensor_node = of_graph_get_remote_port_parent(ep_node);
586 if (!phy->sensor_node) {
587 phy_dbg(3, phy, "Can't get remote parent\n");
588 ret = -EINVAL;
589 goto done;
590 }
591
592 phy_dbg(1, phy, "Found connected device %pOFn\n", phy->sensor_node);
593
594 done:
595 of_node_put(ep_node);
596 return ret;
597 }
598
cal_camerarx_create(struct cal_dev * cal,unsigned int instance)599 struct cal_camerarx *cal_camerarx_create(struct cal_dev *cal,
600 unsigned int instance)
601 {
602 struct platform_device *pdev = to_platform_device(cal->dev);
603 struct cal_camerarx *phy;
604 int ret;
605
606 phy = kzalloc(sizeof(*phy), GFP_KERNEL);
607 if (!phy)
608 return ERR_PTR(-ENOMEM);
609
610 phy->cal = cal;
611 phy->instance = instance;
612
613 phy->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
614 (instance == 0) ?
615 "cal_rx_core0" :
616 "cal_rx_core1");
617 phy->base = devm_ioremap_resource(cal->dev, phy->res);
618 if (IS_ERR(phy->base)) {
619 cal_err(cal, "failed to ioremap\n");
620 ret = PTR_ERR(phy->base);
621 goto error;
622 }
623
624 cal_dbg(1, cal, "ioresource %s at %pa - %pa\n",
625 phy->res->name, &phy->res->start, &phy->res->end);
626
627 ret = cal_camerarx_regmap_init(cal, phy);
628 if (ret)
629 goto error;
630
631 ret = cal_camerarx_parse_dt(phy);
632 if (ret)
633 goto error;
634
635 return phy;
636
637 error:
638 kfree(phy);
639 return ERR_PTR(ret);
640 }
641
cal_camerarx_destroy(struct cal_camerarx * phy)642 void cal_camerarx_destroy(struct cal_camerarx *phy)
643 {
644 if (!phy)
645 return;
646
647 of_node_put(phy->sensor_node);
648 kfree(phy);
649 }
650