1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.cls
3 *
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include <linux/slab.h>
28
29 #include "dm_services.h"
30
31
32 #include "stream_encoder.h"
33 #include "resource.h"
34 #include "include/irq_service_interface.h"
35 #include "dce120_resource.h"
36
37 #include "dce112/dce112_resource.h"
38
39 #include "dce110/dce110_resource.h"
40 #include "../virtual/virtual_stream_encoder.h"
41 #include "dce120_timing_generator.h"
42 #include "irq/dce120/irq_service_dce120.h"
43 #include "dce/dce_opp.h"
44 #include "dce/dce_clock_source.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_mem_input.h"
47 #include "dce/dce_panel_cntl.h"
48
49 #include "dce110/dce110_hw_sequencer.h"
50 #include "dce120/dce120_hw_sequencer.h"
51 #include "dce/dce_transform.h"
52 #include "clk_mgr.h"
53 #include "dce/dce_audio.h"
54 #include "dce/dce_link_encoder.h"
55 #include "dce/dce_stream_encoder.h"
56 #include "dce/dce_hwseq.h"
57 #include "dce/dce_abm.h"
58 #include "dce/dce_dmcu.h"
59 #include "dce/dce_aux.h"
60 #include "dce/dce_i2c.h"
61
62 #include "dce/dce_12_0_offset.h"
63 #include "dce/dce_12_0_sh_mask.h"
64 #include "soc15_hw_ip.h"
65 #include "vega10_ip_offset.h"
66 #include "nbio/nbio_6_1_offset.h"
67 #include "mmhub/mmhub_1_0_offset.h"
68 #include "mmhub/mmhub_1_0_sh_mask.h"
69 #include "reg_helper.h"
70
71 #include "dce100/dce100_resource.h"
72
73 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
74 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
75 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
76 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
77 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
78 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
79 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
80 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
81 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
82 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
83 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
84 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
85 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
86 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
87 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
88 #endif
89
90 enum dce120_clk_src_array_id {
91 DCE120_CLK_SRC_PLL0,
92 DCE120_CLK_SRC_PLL1,
93 DCE120_CLK_SRC_PLL2,
94 DCE120_CLK_SRC_PLL3,
95 DCE120_CLK_SRC_PLL4,
96 DCE120_CLK_SRC_PLL5,
97
98 DCE120_CLK_SRC_TOTAL
99 };
100
101 static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = {
102 {
103 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
104 },
105 {
106 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
107 },
108 {
109 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
110 },
111 {
112 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
113 },
114 {
115 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
116 },
117 {
118 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC0_CRTC_CONTROL),
119 }
120 };
121
122 /* begin *********************
123 * macros to expend register list macro defined in HW object header file */
124
125 #define BASE_INNER(seg) \
126 DCE_BASE__INST0_SEG ## seg
127
128 #define NBIO_BASE_INNER(seg) \
129 NBIF_BASE__INST0_SEG ## seg
130
131 #define NBIO_BASE(seg) \
132 NBIO_BASE_INNER(seg)
133
134 /* compile time expand base address. */
135 #define BASE(seg) \
136 BASE_INNER(seg)
137
138 #define SR(reg_name)\
139 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
140 mm ## reg_name
141
142 #define SRI(reg_name, block, id)\
143 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
144 mm ## block ## id ## _ ## reg_name
145
146 /* MMHUB */
147 #define MMHUB_BASE_INNER(seg) \
148 MMHUB_BASE__INST0_SEG ## seg
149
150 #define MMHUB_BASE(seg) \
151 MMHUB_BASE_INNER(seg)
152
153 #define MMHUB_SR(reg_name)\
154 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
155 mm ## reg_name
156
157 /* macros to expend register list macro defined in HW object header file
158 * end *********************/
159
160
161 static const struct dce_dmcu_registers dmcu_regs = {
162 DMCU_DCE110_COMMON_REG_LIST()
163 };
164
165 static const struct dce_dmcu_shift dmcu_shift = {
166 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
167 };
168
169 static const struct dce_dmcu_mask dmcu_mask = {
170 DMCU_MASK_SH_LIST_DCE110(_MASK)
171 };
172
173 static const struct dce_abm_registers abm_regs = {
174 ABM_DCE110_COMMON_REG_LIST()
175 };
176
177 static const struct dce_abm_shift abm_shift = {
178 ABM_MASK_SH_LIST_DCE110(__SHIFT)
179 };
180
181 static const struct dce_abm_mask abm_mask = {
182 ABM_MASK_SH_LIST_DCE110(_MASK)
183 };
184
185 #define ipp_regs(id)\
186 [id] = {\
187 IPP_DCE110_REG_LIST_DCE_BASE(id)\
188 }
189
190 static const struct dce_ipp_registers ipp_regs[] = {
191 ipp_regs(0),
192 ipp_regs(1),
193 ipp_regs(2),
194 ipp_regs(3),
195 ipp_regs(4),
196 ipp_regs(5)
197 };
198
199 static const struct dce_ipp_shift ipp_shift = {
200 IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT)
201 };
202
203 static const struct dce_ipp_mask ipp_mask = {
204 IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK)
205 };
206
207 #define transform_regs(id)\
208 [id] = {\
209 XFM_COMMON_REG_LIST_DCE110(id)\
210 }
211
212 static const struct dce_transform_registers xfm_regs[] = {
213 transform_regs(0),
214 transform_regs(1),
215 transform_regs(2),
216 transform_regs(3),
217 transform_regs(4),
218 transform_regs(5)
219 };
220
221 static const struct dce_transform_shift xfm_shift = {
222 XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT)
223 };
224
225 static const struct dce_transform_mask xfm_mask = {
226 XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK)
227 };
228
229 #define aux_regs(id)\
230 [id] = {\
231 AUX_REG_LIST(id)\
232 }
233
234 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
235 aux_regs(0),
236 aux_regs(1),
237 aux_regs(2),
238 aux_regs(3),
239 aux_regs(4),
240 aux_regs(5)
241 };
242
243 #define hpd_regs(id)\
244 [id] = {\
245 HPD_REG_LIST(id)\
246 }
247
248 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
249 hpd_regs(0),
250 hpd_regs(1),
251 hpd_regs(2),
252 hpd_regs(3),
253 hpd_regs(4),
254 hpd_regs(5)
255 };
256
257 #define link_regs(id)\
258 [id] = {\
259 LE_DCE120_REG_LIST(id), \
260 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
261 }
262
263 static const struct dce110_link_enc_registers link_enc_regs[] = {
264 link_regs(0),
265 link_regs(1),
266 link_regs(2),
267 link_regs(3),
268 link_regs(4),
269 link_regs(5),
270 link_regs(6),
271 };
272
273
274 #define stream_enc_regs(id)\
275 [id] = {\
276 SE_COMMON_REG_LIST(id),\
277 .TMDS_CNTL = 0,\
278 }
279
280 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
281 stream_enc_regs(0),
282 stream_enc_regs(1),
283 stream_enc_regs(2),
284 stream_enc_regs(3),
285 stream_enc_regs(4),
286 stream_enc_regs(5)
287 };
288
289 static const struct dce_stream_encoder_shift se_shift = {
290 SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT)
291 };
292
293 static const struct dce_stream_encoder_mask se_mask = {
294 SE_COMMON_MASK_SH_LIST_DCE120(_MASK)
295 };
296
297 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
298 { DCE_PANEL_CNTL_REG_LIST() }
299 };
300
301 static const struct dce_panel_cntl_shift panel_cntl_shift = {
302 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
303 };
304
305 static const struct dce_panel_cntl_mask panel_cntl_mask = {
306 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
307 };
308
309 static const struct dce110_aux_registers_shift aux_shift = {
310 DCE12_AUX_MASK_SH_LIST(__SHIFT)
311 };
312
313 static const struct dce110_aux_registers_mask aux_mask = {
314 DCE12_AUX_MASK_SH_LIST(_MASK)
315 };
316
317 #define opp_regs(id)\
318 [id] = {\
319 OPP_DCE_120_REG_LIST(id),\
320 }
321
322 static const struct dce_opp_registers opp_regs[] = {
323 opp_regs(0),
324 opp_regs(1),
325 opp_regs(2),
326 opp_regs(3),
327 opp_regs(4),
328 opp_regs(5)
329 };
330
331 static const struct dce_opp_shift opp_shift = {
332 OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT)
333 };
334
335 static const struct dce_opp_mask opp_mask = {
336 OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK)
337 };
338 #define aux_engine_regs(id)\
339 [id] = {\
340 AUX_COMMON_REG_LIST(id), \
341 .AUX_RESET_MASK = 0 \
342 }
343
344 static const struct dce110_aux_registers aux_engine_regs[] = {
345 aux_engine_regs(0),
346 aux_engine_regs(1),
347 aux_engine_regs(2),
348 aux_engine_regs(3),
349 aux_engine_regs(4),
350 aux_engine_regs(5)
351 };
352
353 #define audio_regs(id)\
354 [id] = {\
355 AUD_COMMON_REG_LIST(id)\
356 }
357
358 static const struct dce_audio_registers audio_regs[] = {
359 audio_regs(0),
360 audio_regs(1),
361 audio_regs(2),
362 audio_regs(3),
363 audio_regs(4),
364 audio_regs(5),
365 audio_regs(6),
366 };
367
368 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
369 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
370 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
371 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
372
373 static const struct dce_audio_shift audio_shift = {
374 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
375 };
376
377 static const struct dce_audio_mask audio_mask = {
378 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
379 };
380
map_transmitter_id_to_phy_instance(enum transmitter transmitter)381 static int map_transmitter_id_to_phy_instance(
382 enum transmitter transmitter)
383 {
384 switch (transmitter) {
385 case TRANSMITTER_UNIPHY_A:
386 return 0;
387 break;
388 case TRANSMITTER_UNIPHY_B:
389 return 1;
390 break;
391 case TRANSMITTER_UNIPHY_C:
392 return 2;
393 break;
394 case TRANSMITTER_UNIPHY_D:
395 return 3;
396 break;
397 case TRANSMITTER_UNIPHY_E:
398 return 4;
399 break;
400 case TRANSMITTER_UNIPHY_F:
401 return 5;
402 break;
403 case TRANSMITTER_UNIPHY_G:
404 return 6;
405 break;
406 default:
407 ASSERT(0);
408 return 0;
409 }
410 }
411
412 #define clk_src_regs(index, id)\
413 [index] = {\
414 CS_COMMON_REG_LIST_DCE_112(id),\
415 }
416
417 static const struct dce110_clk_src_regs clk_src_regs[] = {
418 clk_src_regs(0, A),
419 clk_src_regs(1, B),
420 clk_src_regs(2, C),
421 clk_src_regs(3, D),
422 clk_src_regs(4, E),
423 clk_src_regs(5, F)
424 };
425
426 static const struct dce110_clk_src_shift cs_shift = {
427 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
428 };
429
430 static const struct dce110_clk_src_mask cs_mask = {
431 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
432 };
433
dce120_opp_create(struct dc_context * ctx,uint32_t inst)434 struct output_pixel_processor *dce120_opp_create(
435 struct dc_context *ctx,
436 uint32_t inst)
437 {
438 struct dce110_opp *opp =
439 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
440
441 if (!opp)
442 return NULL;
443
444 dce110_opp_construct(opp,
445 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
446 return &opp->base;
447 }
dce120_aux_engine_create(struct dc_context * ctx,uint32_t inst)448 struct dce_aux *dce120_aux_engine_create(
449 struct dc_context *ctx,
450 uint32_t inst)
451 {
452 struct aux_engine_dce110 *aux_engine =
453 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
454
455 if (!aux_engine)
456 return NULL;
457
458 dce110_aux_engine_construct(aux_engine, ctx, inst,
459 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
460 &aux_engine_regs[inst],
461 &aux_mask,
462 &aux_shift,
463 ctx->dc->caps.extended_aux_timeout_support);
464
465 return &aux_engine->base;
466 }
467 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
468
469 static const struct dce_i2c_registers i2c_hw_regs[] = {
470 i2c_inst_regs(1),
471 i2c_inst_regs(2),
472 i2c_inst_regs(3),
473 i2c_inst_regs(4),
474 i2c_inst_regs(5),
475 i2c_inst_regs(6),
476 };
477
478 static const struct dce_i2c_shift i2c_shifts = {
479 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
480 };
481
482 static const struct dce_i2c_mask i2c_masks = {
483 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
484 };
485
dce120_i2c_hw_create(struct dc_context * ctx,uint32_t inst)486 struct dce_i2c_hw *dce120_i2c_hw_create(
487 struct dc_context *ctx,
488 uint32_t inst)
489 {
490 struct dce_i2c_hw *dce_i2c_hw =
491 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
492
493 if (!dce_i2c_hw)
494 return NULL;
495
496 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
497 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
498
499 return dce_i2c_hw;
500 }
501 static const struct bios_registers bios_regs = {
502 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX),
503 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
504 };
505
506 static const struct resource_caps res_cap = {
507 .num_timing_generator = 6,
508 .num_audio = 7,
509 .num_stream_encoder = 6,
510 .num_pll = 6,
511 .num_ddc = 6,
512 };
513
514 static const struct dc_plane_cap plane_cap = {
515 .type = DC_PLANE_TYPE_DCE_RGB,
516
517 .pixel_format_support = {
518 .argb8888 = true,
519 .nv12 = false,
520 .fp16 = true
521 },
522
523 .max_upscale_factor = {
524 .argb8888 = 16000,
525 .nv12 = 1,
526 .fp16 = 1
527 },
528
529 .max_downscale_factor = {
530 .argb8888 = 250,
531 .nv12 = 1,
532 .fp16 = 1
533 }
534 };
535
536 static const struct dc_debug_options debug_defaults = {
537 .disable_clock_gate = true,
538 };
539
dce120_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)540 static struct clock_source *dce120_clock_source_create(
541 struct dc_context *ctx,
542 struct dc_bios *bios,
543 enum clock_source_id id,
544 const struct dce110_clk_src_regs *regs,
545 bool dp_clk_src)
546 {
547 struct dce110_clk_src *clk_src =
548 kzalloc(sizeof(*clk_src), GFP_KERNEL);
549
550 if (!clk_src)
551 return NULL;
552
553 if (dce112_clk_src_construct(clk_src, ctx, bios, id,
554 regs, &cs_shift, &cs_mask)) {
555 clk_src->base.dp_clk_src = dp_clk_src;
556 return &clk_src->base;
557 }
558
559 kfree(clk_src);
560 BREAK_TO_DEBUGGER();
561 return NULL;
562 }
563
dce120_clock_source_destroy(struct clock_source ** clk_src)564 static void dce120_clock_source_destroy(struct clock_source **clk_src)
565 {
566 kfree(TO_DCE110_CLK_SRC(*clk_src));
567 *clk_src = NULL;
568 }
569
570
dce120_hw_sequencer_create(struct dc * dc)571 static bool dce120_hw_sequencer_create(struct dc *dc)
572 {
573 /* All registers used by dce11.2 match those in dce11 in offset and
574 * structure
575 */
576 dce120_hw_sequencer_construct(dc);
577
578 /*TODO Move to separate file and Override what is needed */
579
580 return true;
581 }
582
dce120_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)583 static struct timing_generator *dce120_timing_generator_create(
584 struct dc_context *ctx,
585 uint32_t instance,
586 const struct dce110_timing_generator_offsets *offsets)
587 {
588 struct dce110_timing_generator *tg110 =
589 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
590
591 if (!tg110)
592 return NULL;
593
594 dce120_timing_generator_construct(tg110, ctx, instance, offsets);
595 return &tg110->base;
596 }
597
dce120_transform_destroy(struct transform ** xfm)598 static void dce120_transform_destroy(struct transform **xfm)
599 {
600 kfree(TO_DCE_TRANSFORM(*xfm));
601 *xfm = NULL;
602 }
603
dce120_resource_destruct(struct dce110_resource_pool * pool)604 static void dce120_resource_destruct(struct dce110_resource_pool *pool)
605 {
606 unsigned int i;
607
608 for (i = 0; i < pool->base.pipe_count; i++) {
609 if (pool->base.opps[i] != NULL)
610 dce110_opp_destroy(&pool->base.opps[i]);
611
612 if (pool->base.transforms[i] != NULL)
613 dce120_transform_destroy(&pool->base.transforms[i]);
614
615 if (pool->base.ipps[i] != NULL)
616 dce_ipp_destroy(&pool->base.ipps[i]);
617
618 if (pool->base.mis[i] != NULL) {
619 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
620 pool->base.mis[i] = NULL;
621 }
622
623 if (pool->base.irqs != NULL) {
624 dal_irq_service_destroy(&pool->base.irqs);
625 }
626
627 if (pool->base.timing_generators[i] != NULL) {
628 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
629 pool->base.timing_generators[i] = NULL;
630 }
631 }
632
633 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
634 if (pool->base.engines[i] != NULL)
635 dce110_engine_destroy(&pool->base.engines[i]);
636 if (pool->base.hw_i2cs[i] != NULL) {
637 kfree(pool->base.hw_i2cs[i]);
638 pool->base.hw_i2cs[i] = NULL;
639 }
640 if (pool->base.sw_i2cs[i] != NULL) {
641 kfree(pool->base.sw_i2cs[i]);
642 pool->base.sw_i2cs[i] = NULL;
643 }
644 }
645
646 for (i = 0; i < pool->base.audio_count; i++) {
647 if (pool->base.audios[i])
648 dce_aud_destroy(&pool->base.audios[i]);
649 }
650
651 for (i = 0; i < pool->base.stream_enc_count; i++) {
652 if (pool->base.stream_enc[i] != NULL)
653 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
654 }
655
656 for (i = 0; i < pool->base.clk_src_count; i++) {
657 if (pool->base.clock_sources[i] != NULL)
658 dce120_clock_source_destroy(
659 &pool->base.clock_sources[i]);
660 }
661
662 if (pool->base.dp_clock_source != NULL)
663 dce120_clock_source_destroy(&pool->base.dp_clock_source);
664
665 if (pool->base.abm != NULL)
666 dce_abm_destroy(&pool->base.abm);
667
668 if (pool->base.dmcu != NULL)
669 dce_dmcu_destroy(&pool->base.dmcu);
670 }
671
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)672 static void read_dce_straps(
673 struct dc_context *ctx,
674 struct resource_straps *straps)
675 {
676 uint32_t reg_val = dm_read_reg_soc15(ctx, mmCC_DC_MISC_STRAPS, 0);
677
678 straps->audio_stream_number = get_reg_field_value(reg_val,
679 CC_DC_MISC_STRAPS,
680 AUDIO_STREAM_NUMBER);
681 straps->hdmi_disable = get_reg_field_value(reg_val,
682 CC_DC_MISC_STRAPS,
683 HDMI_DISABLE);
684
685 reg_val = dm_read_reg_soc15(ctx, mmDC_PINSTRAPS, 0);
686 straps->dc_pinstraps_audio = get_reg_field_value(reg_val,
687 DC_PINSTRAPS,
688 DC_PINSTRAPS_AUDIO);
689 }
690
create_audio(struct dc_context * ctx,unsigned int inst)691 static struct audio *create_audio(
692 struct dc_context *ctx, unsigned int inst)
693 {
694 return dce_audio_create(ctx, inst,
695 &audio_regs[inst], &audio_shift, &audio_mask);
696 }
697
698 static const struct encoder_feature_support link_enc_feature = {
699 .max_hdmi_deep_color = COLOR_DEPTH_121212,
700 .max_hdmi_pixel_clock = 600000,
701 .hdmi_ycbcr420_supported = true,
702 .dp_ycbcr420_supported = false,
703 .flags.bits.IS_HBR2_CAPABLE = true,
704 .flags.bits.IS_HBR3_CAPABLE = true,
705 .flags.bits.IS_TPS3_CAPABLE = true,
706 .flags.bits.IS_TPS4_CAPABLE = true,
707 };
708
dce120_link_encoder_create(const struct encoder_init_data * enc_init_data)709 static struct link_encoder *dce120_link_encoder_create(
710 const struct encoder_init_data *enc_init_data)
711 {
712 struct dce110_link_encoder *enc110 =
713 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
714 int link_regs_id;
715
716 if (!enc110)
717 return NULL;
718
719 link_regs_id =
720 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
721
722 dce110_link_encoder_construct(enc110,
723 enc_init_data,
724 &link_enc_feature,
725 &link_enc_regs[link_regs_id],
726 &link_enc_aux_regs[enc_init_data->channel - 1],
727 &link_enc_hpd_regs[enc_init_data->hpd_source]);
728
729 return &enc110->base;
730 }
731
dce120_panel_cntl_create(const struct panel_cntl_init_data * init_data)732 static struct panel_cntl *dce120_panel_cntl_create(const struct panel_cntl_init_data *init_data)
733 {
734 struct dce_panel_cntl *panel_cntl =
735 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
736
737 if (!panel_cntl)
738 return NULL;
739
740 dce_panel_cntl_construct(panel_cntl,
741 init_data,
742 &panel_cntl_regs[init_data->inst],
743 &panel_cntl_shift,
744 &panel_cntl_mask);
745
746 return &panel_cntl->base;
747 }
748
dce120_ipp_create(struct dc_context * ctx,uint32_t inst)749 static struct input_pixel_processor *dce120_ipp_create(
750 struct dc_context *ctx, uint32_t inst)
751 {
752 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
753
754 if (!ipp) {
755 BREAK_TO_DEBUGGER();
756 return NULL;
757 }
758
759 dce_ipp_construct(ipp, ctx, inst,
760 &ipp_regs[inst], &ipp_shift, &ipp_mask);
761 return &ipp->base;
762 }
763
dce120_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)764 static struct stream_encoder *dce120_stream_encoder_create(
765 enum engine_id eng_id,
766 struct dc_context *ctx)
767 {
768 struct dce110_stream_encoder *enc110 =
769 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
770
771 if (!enc110)
772 return NULL;
773
774 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
775 &stream_enc_regs[eng_id],
776 &se_shift, &se_mask);
777 return &enc110->base;
778 }
779
780 #define SRII(reg_name, block, id)\
781 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
782 mm ## block ## id ## _ ## reg_name
783
784 static const struct dce_hwseq_registers hwseq_reg = {
785 HWSEQ_DCE120_REG_LIST()
786 };
787
788 static const struct dce_hwseq_shift hwseq_shift = {
789 HWSEQ_DCE12_MASK_SH_LIST(__SHIFT)
790 };
791
792 static const struct dce_hwseq_mask hwseq_mask = {
793 HWSEQ_DCE12_MASK_SH_LIST(_MASK)
794 };
795
796 /* HWSEQ regs for VG20 */
797 static const struct dce_hwseq_registers dce121_hwseq_reg = {
798 HWSEQ_VG20_REG_LIST()
799 };
800
801 static const struct dce_hwseq_shift dce121_hwseq_shift = {
802 HWSEQ_VG20_MASK_SH_LIST(__SHIFT)
803 };
804
805 static const struct dce_hwseq_mask dce121_hwseq_mask = {
806 HWSEQ_VG20_MASK_SH_LIST(_MASK)
807 };
808
dce120_hwseq_create(struct dc_context * ctx)809 static struct dce_hwseq *dce120_hwseq_create(
810 struct dc_context *ctx)
811 {
812 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
813
814 if (hws) {
815 hws->ctx = ctx;
816 hws->regs = &hwseq_reg;
817 hws->shifts = &hwseq_shift;
818 hws->masks = &hwseq_mask;
819 }
820 return hws;
821 }
822
dce121_hwseq_create(struct dc_context * ctx)823 static struct dce_hwseq *dce121_hwseq_create(
824 struct dc_context *ctx)
825 {
826 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
827
828 if (hws) {
829 hws->ctx = ctx;
830 hws->regs = &dce121_hwseq_reg;
831 hws->shifts = &dce121_hwseq_shift;
832 hws->masks = &dce121_hwseq_mask;
833 }
834 return hws;
835 }
836
837 static const struct resource_create_funcs res_create_funcs = {
838 .read_dce_straps = read_dce_straps,
839 .create_audio = create_audio,
840 .create_stream_encoder = dce120_stream_encoder_create,
841 .create_hwseq = dce120_hwseq_create,
842 };
843
844 static const struct resource_create_funcs dce121_res_create_funcs = {
845 .read_dce_straps = read_dce_straps,
846 .create_audio = create_audio,
847 .create_stream_encoder = dce120_stream_encoder_create,
848 .create_hwseq = dce121_hwseq_create,
849 };
850
851
852 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) }
853 static const struct dce_mem_input_registers mi_regs[] = {
854 mi_inst_regs(0),
855 mi_inst_regs(1),
856 mi_inst_regs(2),
857 mi_inst_regs(3),
858 mi_inst_regs(4),
859 mi_inst_regs(5),
860 };
861
862 static const struct dce_mem_input_shift mi_shifts = {
863 MI_DCE12_MASK_SH_LIST(__SHIFT)
864 };
865
866 static const struct dce_mem_input_mask mi_masks = {
867 MI_DCE12_MASK_SH_LIST(_MASK)
868 };
869
dce120_mem_input_create(struct dc_context * ctx,uint32_t inst)870 static struct mem_input *dce120_mem_input_create(
871 struct dc_context *ctx,
872 uint32_t inst)
873 {
874 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
875 GFP_KERNEL);
876
877 if (!dce_mi) {
878 BREAK_TO_DEBUGGER();
879 return NULL;
880 }
881
882 dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
883 return &dce_mi->base;
884 }
885
dce120_transform_create(struct dc_context * ctx,uint32_t inst)886 static struct transform *dce120_transform_create(
887 struct dc_context *ctx,
888 uint32_t inst)
889 {
890 struct dce_transform *transform =
891 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
892
893 if (!transform)
894 return NULL;
895
896 dce_transform_construct(transform, ctx, inst,
897 &xfm_regs[inst], &xfm_shift, &xfm_mask);
898 transform->lb_memory_size = 0x1404; /*5124*/
899 return &transform->base;
900 }
901
dce120_destroy_resource_pool(struct resource_pool ** pool)902 static void dce120_destroy_resource_pool(struct resource_pool **pool)
903 {
904 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
905
906 dce120_resource_destruct(dce110_pool);
907 kfree(dce110_pool);
908 *pool = NULL;
909 }
910
911 static const struct resource_funcs dce120_res_pool_funcs = {
912 .destroy = dce120_destroy_resource_pool,
913 .link_enc_create = dce120_link_encoder_create,
914 .panel_cntl_create = dce120_panel_cntl_create,
915 .validate_bandwidth = dce112_validate_bandwidth,
916 .validate_plane = dce100_validate_plane,
917 .add_stream_to_ctx = dce112_add_stream_to_ctx,
918 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
919 };
920
bw_calcs_data_update_from_pplib(struct dc * dc)921 static void bw_calcs_data_update_from_pplib(struct dc *dc)
922 {
923 struct dm_pp_clock_levels_with_latency eng_clks = {0};
924 struct dm_pp_clock_levels_with_latency mem_clks = {0};
925 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
926 int i;
927 unsigned int clk;
928 unsigned int latency;
929 /*original logic in dal3*/
930 int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
931
932 /*do system clock*/
933 if (!dm_pp_get_clock_levels_by_type_with_latency(
934 dc->ctx,
935 DM_PP_CLOCK_TYPE_ENGINE_CLK,
936 &eng_clks) || eng_clks.num_levels == 0) {
937
938 eng_clks.num_levels = 8;
939 clk = 300000;
940
941 for (i = 0; i < eng_clks.num_levels; i++) {
942 eng_clks.data[i].clocks_in_khz = clk;
943 clk += 100000;
944 }
945 }
946
947 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */
948 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
949 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
950 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed(
951 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
952 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed(
953 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
954 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed(
955 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
956 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed(
957 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
958 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed(
959 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
960 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed(
961 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
962 dc->bw_vbios->low_sclk = bw_frc_to_fixed(
963 eng_clks.data[0].clocks_in_khz, 1000);
964
965 /*do memory clock*/
966 if (!dm_pp_get_clock_levels_by_type_with_latency(
967 dc->ctx,
968 DM_PP_CLOCK_TYPE_MEMORY_CLK,
969 &mem_clks) || mem_clks.num_levels == 0) {
970
971 mem_clks.num_levels = 3;
972 clk = 250000;
973 latency = 45;
974
975 for (i = 0; i < eng_clks.num_levels; i++) {
976 mem_clks.data[i].clocks_in_khz = clk;
977 mem_clks.data[i].latency_in_us = latency;
978 clk += 500000;
979 latency -= 5;
980 }
981
982 }
983
984 /* we don't need to call PPLIB for validation clock since they
985 * also give us the highest sclk and highest mclk (UMA clock).
986 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula):
987 * YCLK = UMACLK*m_memoryTypeMultiplier
988 */
989 if (dc->bw_vbios->memory_type == bw_def_hbm)
990 memory_type_multiplier = MEMORY_TYPE_HBM;
991
992 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
993 mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000);
994 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
995 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier,
996 1000);
997 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
998 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier,
999 1000);
1000
1001 /* Now notify PPLib/SMU about which Watermarks sets they should select
1002 * depending on DPM state they are in. And update BW MGR GFX Engine and
1003 * Memory clock member variables for Watermarks calculations for each
1004 * Watermark Set
1005 */
1006 clk_ranges.num_wm_sets = 4;
1007 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1008 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1009 eng_clks.data[0].clocks_in_khz;
1010 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1011 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1012 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1013 mem_clks.data[0].clocks_in_khz;
1014 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1015 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1016
1017 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1018 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1019 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1020 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1021 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1022 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1023 mem_clks.data[0].clocks_in_khz;
1024 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1025 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1026
1027 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1028 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1029 eng_clks.data[0].clocks_in_khz;
1030 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1031 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1032 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1033 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1034 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1035 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1036
1037 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1038 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1039 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1040 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1041 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1042 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1043 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1044 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1045 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1046
1047 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1048 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1049 }
1050
read_pipe_fuses(struct dc_context * ctx)1051 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1052 {
1053 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1054 /* VG20 support max 6 pipes */
1055 value = value & 0x3f;
1056 return value;
1057 }
1058
dce120_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1059 static bool dce120_resource_construct(
1060 uint8_t num_virtual_links,
1061 struct dc *dc,
1062 struct dce110_resource_pool *pool)
1063 {
1064 unsigned int i;
1065 int j;
1066 struct dc_context *ctx = dc->ctx;
1067 struct irq_service_init_data irq_init_data;
1068 static const struct resource_create_funcs *res_funcs;
1069 bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
1070 uint32_t pipe_fuses;
1071
1072 ctx->dc_bios->regs = &bios_regs;
1073
1074 pool->base.res_cap = &res_cap;
1075 pool->base.funcs = &dce120_res_pool_funcs;
1076
1077 /* TODO: Fill more data from GreenlandAsicCapability.cpp */
1078 pool->base.pipe_count = res_cap.num_timing_generator;
1079 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1080 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1081
1082 dc->caps.max_downscale_ratio = 200;
1083 dc->caps.i2c_speed_in_khz = 100;
1084 dc->caps.max_cursor_size = 128;
1085 dc->caps.dual_link_dvi = true;
1086 dc->caps.psp_setup_panel_mode = true;
1087 dc->caps.extended_aux_timeout_support = false;
1088 dc->debug = debug_defaults;
1089
1090 /*************************************************
1091 * Create resources *
1092 *************************************************/
1093
1094 pool->base.clock_sources[DCE120_CLK_SRC_PLL0] =
1095 dce120_clock_source_create(ctx, ctx->dc_bios,
1096 CLOCK_SOURCE_COMBO_PHY_PLL0,
1097 &clk_src_regs[0], false);
1098 pool->base.clock_sources[DCE120_CLK_SRC_PLL1] =
1099 dce120_clock_source_create(ctx, ctx->dc_bios,
1100 CLOCK_SOURCE_COMBO_PHY_PLL1,
1101 &clk_src_regs[1], false);
1102 pool->base.clock_sources[DCE120_CLK_SRC_PLL2] =
1103 dce120_clock_source_create(ctx, ctx->dc_bios,
1104 CLOCK_SOURCE_COMBO_PHY_PLL2,
1105 &clk_src_regs[2], false);
1106 pool->base.clock_sources[DCE120_CLK_SRC_PLL3] =
1107 dce120_clock_source_create(ctx, ctx->dc_bios,
1108 CLOCK_SOURCE_COMBO_PHY_PLL3,
1109 &clk_src_regs[3], false);
1110 pool->base.clock_sources[DCE120_CLK_SRC_PLL4] =
1111 dce120_clock_source_create(ctx, ctx->dc_bios,
1112 CLOCK_SOURCE_COMBO_PHY_PLL4,
1113 &clk_src_regs[4], false);
1114 pool->base.clock_sources[DCE120_CLK_SRC_PLL5] =
1115 dce120_clock_source_create(ctx, ctx->dc_bios,
1116 CLOCK_SOURCE_COMBO_PHY_PLL5,
1117 &clk_src_regs[5], false);
1118 pool->base.clk_src_count = DCE120_CLK_SRC_TOTAL;
1119
1120 pool->base.dp_clock_source =
1121 dce120_clock_source_create(ctx, ctx->dc_bios,
1122 CLOCK_SOURCE_ID_DP_DTO,
1123 &clk_src_regs[0], true);
1124
1125 for (i = 0; i < pool->base.clk_src_count; i++) {
1126 if (pool->base.clock_sources[i] == NULL) {
1127 dm_error("DC: failed to create clock sources!\n");
1128 BREAK_TO_DEBUGGER();
1129 goto clk_src_create_fail;
1130 }
1131 }
1132
1133 pool->base.dmcu = dce_dmcu_create(ctx,
1134 &dmcu_regs,
1135 &dmcu_shift,
1136 &dmcu_mask);
1137 if (pool->base.dmcu == NULL) {
1138 dm_error("DC: failed to create dmcu!\n");
1139 BREAK_TO_DEBUGGER();
1140 goto res_create_fail;
1141 }
1142
1143 pool->base.abm = dce_abm_create(ctx,
1144 &abm_regs,
1145 &abm_shift,
1146 &abm_mask);
1147 if (pool->base.abm == NULL) {
1148 dm_error("DC: failed to create abm!\n");
1149 BREAK_TO_DEBUGGER();
1150 goto res_create_fail;
1151 }
1152
1153
1154 irq_init_data.ctx = dc->ctx;
1155 pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data);
1156 if (!pool->base.irqs)
1157 goto irqs_create_fail;
1158
1159 /* VG20: Pipe harvesting enabled, retrieve valid pipe fuses */
1160 if (is_vg20)
1161 pipe_fuses = read_pipe_fuses(ctx);
1162
1163 /* index to valid pipe resource */
1164 j = 0;
1165 for (i = 0; i < pool->base.pipe_count; i++) {
1166 if (is_vg20) {
1167 if ((pipe_fuses & (1 << i)) != 0) {
1168 dm_error("DC: skip invalid pipe %d!\n", i);
1169 continue;
1170 }
1171 }
1172
1173 pool->base.timing_generators[j] =
1174 dce120_timing_generator_create(
1175 ctx,
1176 i,
1177 &dce120_tg_offsets[i]);
1178 if (pool->base.timing_generators[j] == NULL) {
1179 BREAK_TO_DEBUGGER();
1180 dm_error("DC: failed to create tg!\n");
1181 goto controller_create_fail;
1182 }
1183
1184 pool->base.mis[j] = dce120_mem_input_create(ctx, i);
1185
1186 if (pool->base.mis[j] == NULL) {
1187 BREAK_TO_DEBUGGER();
1188 dm_error(
1189 "DC: failed to create memory input!\n");
1190 goto controller_create_fail;
1191 }
1192
1193 pool->base.ipps[j] = dce120_ipp_create(ctx, i);
1194 if (pool->base.ipps[i] == NULL) {
1195 BREAK_TO_DEBUGGER();
1196 dm_error(
1197 "DC: failed to create input pixel processor!\n");
1198 goto controller_create_fail;
1199 }
1200
1201 pool->base.transforms[j] = dce120_transform_create(ctx, i);
1202 if (pool->base.transforms[i] == NULL) {
1203 BREAK_TO_DEBUGGER();
1204 dm_error(
1205 "DC: failed to create transform!\n");
1206 goto res_create_fail;
1207 }
1208
1209 pool->base.opps[j] = dce120_opp_create(
1210 ctx,
1211 i);
1212 if (pool->base.opps[j] == NULL) {
1213 BREAK_TO_DEBUGGER();
1214 dm_error(
1215 "DC: failed to create output pixel processor!\n");
1216 }
1217
1218 /* check next valid pipe */
1219 j++;
1220 }
1221
1222 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1223 pool->base.engines[i] = dce120_aux_engine_create(ctx, i);
1224 if (pool->base.engines[i] == NULL) {
1225 BREAK_TO_DEBUGGER();
1226 dm_error(
1227 "DC:failed to create aux engine!!\n");
1228 goto res_create_fail;
1229 }
1230 pool->base.hw_i2cs[i] = dce120_i2c_hw_create(ctx, i);
1231 if (pool->base.hw_i2cs[i] == NULL) {
1232 BREAK_TO_DEBUGGER();
1233 dm_error(
1234 "DC:failed to create i2c engine!!\n");
1235 goto res_create_fail;
1236 }
1237 pool->base.sw_i2cs[i] = NULL;
1238 }
1239
1240 /* valid pipe num */
1241 pool->base.pipe_count = j;
1242 pool->base.timing_generator_count = j;
1243
1244 if (is_vg20)
1245 res_funcs = &dce121_res_create_funcs;
1246 else
1247 res_funcs = &res_create_funcs;
1248
1249 if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs))
1250 goto res_create_fail;
1251
1252 /* Create hardware sequencer */
1253 if (!dce120_hw_sequencer_create(dc))
1254 goto controller_create_fail;
1255
1256 dc->caps.max_planes = pool->base.pipe_count;
1257
1258 for (i = 0; i < dc->caps.max_planes; ++i)
1259 dc->caps.planes[i] = plane_cap;
1260
1261 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1262
1263 bw_calcs_data_update_from_pplib(dc);
1264
1265 return true;
1266
1267 irqs_create_fail:
1268 controller_create_fail:
1269 clk_src_create_fail:
1270 res_create_fail:
1271
1272 dce120_resource_destruct(pool);
1273
1274 return false;
1275 }
1276
dce120_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1277 struct resource_pool *dce120_create_resource_pool(
1278 uint8_t num_virtual_links,
1279 struct dc *dc)
1280 {
1281 struct dce110_resource_pool *pool =
1282 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1283
1284 if (!pool)
1285 return NULL;
1286
1287 if (dce120_resource_construct(num_virtual_links, dc, pool))
1288 return &pool->base;
1289
1290 kfree(pool);
1291 BREAK_TO_DEBUGGER();
1292 return NULL;
1293 }
1294