1 /*
2 * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dce/dce_6_0_d.h"
29 #include "dce/dce_6_0_sh_mask.h"
30
31 #include "dm_services.h"
32
33 #include "link_encoder.h"
34 #include "stream_encoder.h"
35
36 #include "resource.h"
37 #include "include/irq_service_interface.h"
38 #include "irq/dce60/irq_service_dce60.h"
39 #include "dce110/dce110_timing_generator.h"
40 #include "dce110/dce110_resource.h"
41 #include "dce60/dce60_timing_generator.h"
42 #include "dce/dce_mem_input.h"
43 #include "dce/dce_link_encoder.h"
44 #include "dce/dce_stream_encoder.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_transform.h"
47 #include "dce/dce_opp.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
50 #include "dce/dce_hwseq.h"
51 #include "dce60/dce60_hw_sequencer.h"
52 #include "dce100/dce100_resource.h"
53 #include "dce/dce_panel_cntl.h"
54
55 #include "reg_helper.h"
56
57 #include "dce/dce_dmcu.h"
58 #include "dce/dce_aux.h"
59 #include "dce/dce_abm.h"
60 #include "dce/dce_i2c.h"
61 /* TODO remove this include */
62
63 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
64 #include "gmc/gmc_6_0_d.h"
65 #include "gmc/gmc_6_0_sh_mask.h"
66 #endif
67
68 #ifndef mmDP_DPHY_INTERNAL_CTRL
69 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE
70 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE
71 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE
72 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE
73 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE
74 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE
75 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE
76 #endif
77
78
79 #ifndef mmBIOS_SCRATCH_2
80 #define mmBIOS_SCRATCH_2 0x05CB
81 #define mmBIOS_SCRATCH_3 0x05CC
82 #define mmBIOS_SCRATCH_6 0x05CF
83 #endif
84
85 #ifndef mmDP_DPHY_FAST_TRAINING
86 #define mmDP_DPHY_FAST_TRAINING 0x1CCE
87 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE
88 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE
89 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE
90 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE
91 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE
92 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE
93 #endif
94
95
96 #ifndef mmHPD_DC_HPD_CONTROL
97 #define mmHPD_DC_HPD_CONTROL 0x189A
98 #define mmHPD0_DC_HPD_CONTROL 0x189A
99 #define mmHPD1_DC_HPD_CONTROL 0x18A2
100 #define mmHPD2_DC_HPD_CONTROL 0x18AA
101 #define mmHPD3_DC_HPD_CONTROL 0x18B2
102 #define mmHPD4_DC_HPD_CONTROL 0x18BA
103 #define mmHPD5_DC_HPD_CONTROL 0x18C2
104 #endif
105
106 #define DCE11_DIG_FE_CNTL 0x4a00
107 #define DCE11_DIG_BE_CNTL 0x4a47
108 #define DCE11_DP_SEC 0x4ac3
109
110 static const struct dce110_timing_generator_offsets dce60_tg_offsets[] = {
111 {
112 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
113 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
114 .dmif = (mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL3
115 - mmDPG_PIPE_ARBITRATION_CONTROL3),
116 },
117 {
118 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
119 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
120 .dmif = (mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL3
121 - mmDPG_PIPE_ARBITRATION_CONTROL3),
122 },
123 {
124 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
125 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
126 .dmif = (mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL3
127 - mmDPG_PIPE_ARBITRATION_CONTROL3),
128 },
129 {
130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
132 .dmif = (mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL3
133 - mmDPG_PIPE_ARBITRATION_CONTROL3),
134 },
135 {
136 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
137 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
138 .dmif = (mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL3
139 - mmDPG_PIPE_ARBITRATION_CONTROL3),
140 },
141 {
142 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
143 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
144 .dmif = (mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL3
145 - mmDPG_PIPE_ARBITRATION_CONTROL3),
146 }
147 };
148
149 /* set register offset */
150 #define SR(reg_name)\
151 .reg_name = mm ## reg_name
152
153 /* set register offset with instance */
154 #define SRI(reg_name, block, id)\
155 .reg_name = mm ## block ## id ## _ ## reg_name
156
157 #define ipp_regs(id)\
158 [id] = {\
159 IPP_COMMON_REG_LIST_DCE_BASE(id)\
160 }
161
162 static const struct dce_ipp_registers ipp_regs[] = {
163 ipp_regs(0),
164 ipp_regs(1),
165 ipp_regs(2),
166 ipp_regs(3),
167 ipp_regs(4),
168 ipp_regs(5)
169 };
170
171 static const struct dce_ipp_shift ipp_shift = {
172 IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
173 };
174
175 static const struct dce_ipp_mask ipp_mask = {
176 IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
177 };
178
179 #define transform_regs(id)\
180 [id] = {\
181 XFM_COMMON_REG_LIST_DCE60(id)\
182 }
183
184 static const struct dce_transform_registers xfm_regs[] = {
185 transform_regs(0),
186 transform_regs(1),
187 transform_regs(2),
188 transform_regs(3),
189 transform_regs(4),
190 transform_regs(5)
191 };
192
193 static const struct dce_transform_shift xfm_shift = {
194 XFM_COMMON_MASK_SH_LIST_DCE60(__SHIFT)
195 };
196
197 static const struct dce_transform_mask xfm_mask = {
198 XFM_COMMON_MASK_SH_LIST_DCE60(_MASK)
199 };
200
201 #define aux_regs(id)\
202 [id] = {\
203 AUX_REG_LIST(id)\
204 }
205
206 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
207 aux_regs(0),
208 aux_regs(1),
209 aux_regs(2),
210 aux_regs(3),
211 aux_regs(4),
212 aux_regs(5)
213 };
214
215 #define hpd_regs(id)\
216 [id] = {\
217 HPD_REG_LIST(id)\
218 }
219
220 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
221 hpd_regs(0),
222 hpd_regs(1),
223 hpd_regs(2),
224 hpd_regs(3),
225 hpd_regs(4),
226 hpd_regs(5)
227 };
228
229 #define link_regs(id)\
230 [id] = {\
231 LE_DCE60_REG_LIST(id)\
232 }
233
234 static const struct dce110_link_enc_registers link_enc_regs[] = {
235 link_regs(0),
236 link_regs(1),
237 link_regs(2),
238 link_regs(3),
239 link_regs(4),
240 link_regs(5)
241 };
242
243 #define stream_enc_regs(id)\
244 [id] = {\
245 SE_COMMON_REG_LIST_DCE_BASE(id),\
246 .AFMT_CNTL = 0,\
247 }
248
249 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
250 stream_enc_regs(0),
251 stream_enc_regs(1),
252 stream_enc_regs(2),
253 stream_enc_regs(3),
254 stream_enc_regs(4),
255 stream_enc_regs(5)
256 };
257
258 static const struct dce_stream_encoder_shift se_shift = {
259 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
260 };
261
262 static const struct dce_stream_encoder_mask se_mask = {
263 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
264 };
265
266 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
267 { DCE_PANEL_CNTL_REG_LIST() }
268 };
269
270 static const struct dce_panel_cntl_shift panel_cntl_shift = {
271 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
272 };
273
274 static const struct dce_panel_cntl_mask panel_cntl_mask = {
275 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
276 };
277
278 #define opp_regs(id)\
279 [id] = {\
280 OPP_DCE_60_REG_LIST(id),\
281 }
282
283 static const struct dce_opp_registers opp_regs[] = {
284 opp_regs(0),
285 opp_regs(1),
286 opp_regs(2),
287 opp_regs(3),
288 opp_regs(4),
289 opp_regs(5)
290 };
291
292 static const struct dce_opp_shift opp_shift = {
293 OPP_COMMON_MASK_SH_LIST_DCE_60(__SHIFT)
294 };
295
296 static const struct dce_opp_mask opp_mask = {
297 OPP_COMMON_MASK_SH_LIST_DCE_60(_MASK)
298 };
299
300 static const struct dce110_aux_registers_shift aux_shift = {
301 DCE10_AUX_MASK_SH_LIST(__SHIFT)
302 };
303
304 static const struct dce110_aux_registers_mask aux_mask = {
305 DCE10_AUX_MASK_SH_LIST(_MASK)
306 };
307
308 #define aux_engine_regs(id)\
309 [id] = {\
310 AUX_COMMON_REG_LIST(id), \
311 .AUX_RESET_MASK = 0 \
312 }
313
314 static const struct dce110_aux_registers aux_engine_regs[] = {
315 aux_engine_regs(0),
316 aux_engine_regs(1),
317 aux_engine_regs(2),
318 aux_engine_regs(3),
319 aux_engine_regs(4),
320 aux_engine_regs(5)
321 };
322
323 #define audio_regs(id)\
324 [id] = {\
325 AUD_COMMON_REG_LIST(id)\
326 }
327
328 static const struct dce_audio_registers audio_regs[] = {
329 audio_regs(0),
330 audio_regs(1),
331 audio_regs(2),
332 audio_regs(3),
333 audio_regs(4),
334 audio_regs(5),
335 };
336
337 static const struct dce_audio_shift audio_shift = {
338 AUD_DCE60_MASK_SH_LIST(__SHIFT)
339 };
340
341 static const struct dce_audio_mask audio_mask = {
342 AUD_DCE60_MASK_SH_LIST(_MASK)
343 };
344
345 #define clk_src_regs(id)\
346 [id] = {\
347 CS_COMMON_REG_LIST_DCE_80(id),\
348 }
349
350
351 static const struct dce110_clk_src_regs clk_src_regs[] = {
352 clk_src_regs(0),
353 clk_src_regs(1),
354 clk_src_regs(2)
355 };
356
357 static const struct dce110_clk_src_shift cs_shift = {
358 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
359 };
360
361 static const struct dce110_clk_src_mask cs_mask = {
362 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
363 };
364
365 static const struct bios_registers bios_regs = {
366 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
367 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
368 };
369
370 static const struct resource_caps res_cap = {
371 .num_timing_generator = 6,
372 .num_audio = 6,
373 .num_stream_encoder = 6,
374 .num_pll = 2,
375 .num_ddc = 6,
376 };
377
378 static const struct resource_caps res_cap_61 = {
379 .num_timing_generator = 4,
380 .num_audio = 6,
381 .num_stream_encoder = 6,
382 .num_pll = 3,
383 .num_ddc = 6,
384 };
385
386 static const struct resource_caps res_cap_64 = {
387 .num_timing_generator = 2,
388 .num_audio = 2,
389 .num_stream_encoder = 2,
390 .num_pll = 2,
391 .num_ddc = 2,
392 };
393
394 static const struct dc_plane_cap plane_cap = {
395 .type = DC_PLANE_TYPE_DCE_RGB,
396
397 .pixel_format_support = {
398 .argb8888 = true,
399 .nv12 = false,
400 .fp16 = false
401 },
402
403 .max_upscale_factor = {
404 .argb8888 = 16000,
405 .nv12 = 1,
406 .fp16 = 1
407 },
408
409 .max_downscale_factor = {
410 .argb8888 = 250,
411 .nv12 = 1,
412 .fp16 = 1
413 }
414 };
415
416 static const struct dce_dmcu_registers dmcu_regs = {
417 DMCU_DCE60_REG_LIST()
418 };
419
420 static const struct dce_dmcu_shift dmcu_shift = {
421 DMCU_MASK_SH_LIST_DCE60(__SHIFT)
422 };
423
424 static const struct dce_dmcu_mask dmcu_mask = {
425 DMCU_MASK_SH_LIST_DCE60(_MASK)
426 };
427 static const struct dce_abm_registers abm_regs = {
428 ABM_DCE110_COMMON_REG_LIST()
429 };
430
431 static const struct dce_abm_shift abm_shift = {
432 ABM_MASK_SH_LIST_DCE110(__SHIFT)
433 };
434
435 static const struct dce_abm_mask abm_mask = {
436 ABM_MASK_SH_LIST_DCE110(_MASK)
437 };
438
439 #define CTX ctx
440 #define REG(reg) mm ## reg
441
442 #ifndef mmCC_DC_HDMI_STRAPS
443 #define mmCC_DC_HDMI_STRAPS 0x1918
444 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
445 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
446 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
447 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
448 #endif
449
map_transmitter_id_to_phy_instance(enum transmitter transmitter)450 static int map_transmitter_id_to_phy_instance(
451 enum transmitter transmitter)
452 {
453 switch (transmitter) {
454 case TRANSMITTER_UNIPHY_A:
455 return 0;
456 break;
457 case TRANSMITTER_UNIPHY_B:
458 return 1;
459 break;
460 case TRANSMITTER_UNIPHY_C:
461 return 2;
462 break;
463 case TRANSMITTER_UNIPHY_D:
464 return 3;
465 break;
466 case TRANSMITTER_UNIPHY_E:
467 return 4;
468 break;
469 case TRANSMITTER_UNIPHY_F:
470 return 5;
471 break;
472 case TRANSMITTER_UNIPHY_G:
473 return 6;
474 break;
475 default:
476 ASSERT(0);
477 return 0;
478 }
479 }
480
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)481 static void read_dce_straps(
482 struct dc_context *ctx,
483 struct resource_straps *straps)
484 {
485 REG_GET_2(CC_DC_HDMI_STRAPS,
486 HDMI_DISABLE, &straps->hdmi_disable,
487 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
488
489 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
490 }
491
create_audio(struct dc_context * ctx,unsigned int inst)492 static struct audio *create_audio(
493 struct dc_context *ctx, unsigned int inst)
494 {
495 return dce60_audio_create(ctx, inst,
496 &audio_regs[inst], &audio_shift, &audio_mask);
497 }
498
dce60_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)499 static struct timing_generator *dce60_timing_generator_create(
500 struct dc_context *ctx,
501 uint32_t instance,
502 const struct dce110_timing_generator_offsets *offsets)
503 {
504 struct dce110_timing_generator *tg110 =
505 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
506
507 if (!tg110)
508 return NULL;
509
510 dce60_timing_generator_construct(tg110, ctx, instance, offsets);
511 return &tg110->base;
512 }
513
dce60_opp_create(struct dc_context * ctx,uint32_t inst)514 static struct output_pixel_processor *dce60_opp_create(
515 struct dc_context *ctx,
516 uint32_t inst)
517 {
518 struct dce110_opp *opp =
519 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
520
521 if (!opp)
522 return NULL;
523
524 dce60_opp_construct(opp,
525 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
526 return &opp->base;
527 }
528
dce60_aux_engine_create(struct dc_context * ctx,uint32_t inst)529 struct dce_aux *dce60_aux_engine_create(
530 struct dc_context *ctx,
531 uint32_t inst)
532 {
533 struct aux_engine_dce110 *aux_engine =
534 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
535
536 if (!aux_engine)
537 return NULL;
538
539 dce110_aux_engine_construct(aux_engine, ctx, inst,
540 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
541 &aux_engine_regs[inst],
542 &aux_mask,
543 &aux_shift,
544 ctx->dc->caps.extended_aux_timeout_support);
545
546 return &aux_engine->base;
547 }
548 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
549
550 static const struct dce_i2c_registers i2c_hw_regs[] = {
551 i2c_inst_regs(1),
552 i2c_inst_regs(2),
553 i2c_inst_regs(3),
554 i2c_inst_regs(4),
555 i2c_inst_regs(5),
556 i2c_inst_regs(6),
557 };
558
559 static const struct dce_i2c_shift i2c_shifts = {
560 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
561 };
562
563 static const struct dce_i2c_mask i2c_masks = {
564 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
565 };
566
dce60_i2c_hw_create(struct dc_context * ctx,uint32_t inst)567 struct dce_i2c_hw *dce60_i2c_hw_create(
568 struct dc_context *ctx,
569 uint32_t inst)
570 {
571 struct dce_i2c_hw *dce_i2c_hw =
572 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
573
574 if (!dce_i2c_hw)
575 return NULL;
576
577 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
578 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
579
580 return dce_i2c_hw;
581 }
582
dce60_i2c_sw_create(struct dc_context * ctx)583 struct dce_i2c_sw *dce60_i2c_sw_create(
584 struct dc_context *ctx)
585 {
586 struct dce_i2c_sw *dce_i2c_sw =
587 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
588
589 if (!dce_i2c_sw)
590 return NULL;
591
592 dce_i2c_sw_construct(dce_i2c_sw, ctx);
593
594 return dce_i2c_sw;
595 }
dce60_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)596 static struct stream_encoder *dce60_stream_encoder_create(
597 enum engine_id eng_id,
598 struct dc_context *ctx)
599 {
600 struct dce110_stream_encoder *enc110 =
601 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
602
603 if (!enc110)
604 return NULL;
605
606 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
607 &stream_enc_regs[eng_id],
608 &se_shift, &se_mask);
609 return &enc110->base;
610 }
611
612 #define SRII(reg_name, block, id)\
613 .reg_name[id] = mm ## block ## id ## _ ## reg_name
614
615 static const struct dce_hwseq_registers hwseq_reg = {
616 HWSEQ_DCE6_REG_LIST()
617 };
618
619 static const struct dce_hwseq_shift hwseq_shift = {
620 HWSEQ_DCE6_MASK_SH_LIST(__SHIFT)
621 };
622
623 static const struct dce_hwseq_mask hwseq_mask = {
624 HWSEQ_DCE6_MASK_SH_LIST(_MASK)
625 };
626
dce60_hwseq_create(struct dc_context * ctx)627 static struct dce_hwseq *dce60_hwseq_create(
628 struct dc_context *ctx)
629 {
630 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
631
632 if (hws) {
633 hws->ctx = ctx;
634 hws->regs = &hwseq_reg;
635 hws->shifts = &hwseq_shift;
636 hws->masks = &hwseq_mask;
637 }
638 return hws;
639 }
640
641 static const struct resource_create_funcs res_create_funcs = {
642 .read_dce_straps = read_dce_straps,
643 .create_audio = create_audio,
644 .create_stream_encoder = dce60_stream_encoder_create,
645 .create_hwseq = dce60_hwseq_create,
646 };
647
648 #define mi_inst_regs(id) { \
649 MI_DCE6_REG_LIST(id), \
650 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
651 }
652 static const struct dce_mem_input_registers mi_regs[] = {
653 mi_inst_regs(0),
654 mi_inst_regs(1),
655 mi_inst_regs(2),
656 mi_inst_regs(3),
657 mi_inst_regs(4),
658 mi_inst_regs(5),
659 };
660
661 static const struct dce_mem_input_shift mi_shifts = {
662 MI_DCE6_MASK_SH_LIST(__SHIFT),
663 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
664 };
665
666 static const struct dce_mem_input_mask mi_masks = {
667 MI_DCE6_MASK_SH_LIST(_MASK),
668 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
669 };
670
dce60_mem_input_create(struct dc_context * ctx,uint32_t inst)671 static struct mem_input *dce60_mem_input_create(
672 struct dc_context *ctx,
673 uint32_t inst)
674 {
675 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
676 GFP_KERNEL);
677
678 if (!dce_mi) {
679 BREAK_TO_DEBUGGER();
680 return NULL;
681 }
682
683 dce60_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
684 dce_mi->wa.single_head_rdreq_dmif_limit = 2;
685 return &dce_mi->base;
686 }
687
dce60_transform_destroy(struct transform ** xfm)688 static void dce60_transform_destroy(struct transform **xfm)
689 {
690 kfree(TO_DCE_TRANSFORM(*xfm));
691 *xfm = NULL;
692 }
693
dce60_transform_create(struct dc_context * ctx,uint32_t inst)694 static struct transform *dce60_transform_create(
695 struct dc_context *ctx,
696 uint32_t inst)
697 {
698 struct dce_transform *transform =
699 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
700
701 if (!transform)
702 return NULL;
703
704 dce60_transform_construct(transform, ctx, inst,
705 &xfm_regs[inst], &xfm_shift, &xfm_mask);
706 transform->prescaler_on = false;
707 return &transform->base;
708 }
709
710 static const struct encoder_feature_support link_enc_feature = {
711 .max_hdmi_deep_color = COLOR_DEPTH_121212,
712 .max_hdmi_pixel_clock = 297000,
713 .flags.bits.IS_HBR2_CAPABLE = true,
714 .flags.bits.IS_TPS3_CAPABLE = true
715 };
716
dce60_link_encoder_create(const struct encoder_init_data * enc_init_data)717 struct link_encoder *dce60_link_encoder_create(
718 const struct encoder_init_data *enc_init_data)
719 {
720 struct dce110_link_encoder *enc110 =
721 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
722 int link_regs_id;
723
724 if (!enc110)
725 return NULL;
726
727 link_regs_id =
728 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
729
730 dce60_link_encoder_construct(enc110,
731 enc_init_data,
732 &link_enc_feature,
733 &link_enc_regs[link_regs_id],
734 &link_enc_aux_regs[enc_init_data->channel - 1],
735 &link_enc_hpd_regs[enc_init_data->hpd_source]);
736 return &enc110->base;
737 }
738
dce60_panel_cntl_create(const struct panel_cntl_init_data * init_data)739 static struct panel_cntl *dce60_panel_cntl_create(const struct panel_cntl_init_data *init_data)
740 {
741 struct dce_panel_cntl *panel_cntl =
742 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
743
744 if (!panel_cntl)
745 return NULL;
746
747 dce_panel_cntl_construct(panel_cntl,
748 init_data,
749 &panel_cntl_regs[init_data->inst],
750 &panel_cntl_shift,
751 &panel_cntl_mask);
752
753 return &panel_cntl->base;
754 }
755
dce60_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)756 struct clock_source *dce60_clock_source_create(
757 struct dc_context *ctx,
758 struct dc_bios *bios,
759 enum clock_source_id id,
760 const struct dce110_clk_src_regs *regs,
761 bool dp_clk_src)
762 {
763 struct dce110_clk_src *clk_src =
764 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
765
766 if (!clk_src)
767 return NULL;
768
769 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
770 regs, &cs_shift, &cs_mask)) {
771 clk_src->base.dp_clk_src = dp_clk_src;
772 return &clk_src->base;
773 }
774
775 kfree(clk_src);
776 BREAK_TO_DEBUGGER();
777 return NULL;
778 }
779
dce60_clock_source_destroy(struct clock_source ** clk_src)780 void dce60_clock_source_destroy(struct clock_source **clk_src)
781 {
782 kfree(TO_DCE110_CLK_SRC(*clk_src));
783 *clk_src = NULL;
784 }
785
dce60_ipp_create(struct dc_context * ctx,uint32_t inst)786 static struct input_pixel_processor *dce60_ipp_create(
787 struct dc_context *ctx, uint32_t inst)
788 {
789 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
790
791 if (!ipp) {
792 BREAK_TO_DEBUGGER();
793 return NULL;
794 }
795
796 dce60_ipp_construct(ipp, ctx, inst,
797 &ipp_regs[inst], &ipp_shift, &ipp_mask);
798 return &ipp->base;
799 }
800
dce60_resource_destruct(struct dce110_resource_pool * pool)801 static void dce60_resource_destruct(struct dce110_resource_pool *pool)
802 {
803 unsigned int i;
804
805 for (i = 0; i < pool->base.pipe_count; i++) {
806 if (pool->base.opps[i] != NULL)
807 dce110_opp_destroy(&pool->base.opps[i]);
808
809 if (pool->base.transforms[i] != NULL)
810 dce60_transform_destroy(&pool->base.transforms[i]);
811
812 if (pool->base.ipps[i] != NULL)
813 dce_ipp_destroy(&pool->base.ipps[i]);
814
815 if (pool->base.mis[i] != NULL) {
816 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
817 pool->base.mis[i] = NULL;
818 }
819
820 if (pool->base.timing_generators[i] != NULL) {
821 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
822 pool->base.timing_generators[i] = NULL;
823 }
824 }
825
826 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
827 if (pool->base.engines[i] != NULL)
828 dce110_engine_destroy(&pool->base.engines[i]);
829 if (pool->base.hw_i2cs[i] != NULL) {
830 kfree(pool->base.hw_i2cs[i]);
831 pool->base.hw_i2cs[i] = NULL;
832 }
833 if (pool->base.sw_i2cs[i] != NULL) {
834 kfree(pool->base.sw_i2cs[i]);
835 pool->base.sw_i2cs[i] = NULL;
836 }
837 }
838
839 for (i = 0; i < pool->base.stream_enc_count; i++) {
840 if (pool->base.stream_enc[i] != NULL)
841 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
842 }
843
844 for (i = 0; i < pool->base.clk_src_count; i++) {
845 if (pool->base.clock_sources[i] != NULL) {
846 dce60_clock_source_destroy(&pool->base.clock_sources[i]);
847 }
848 }
849
850 if (pool->base.abm != NULL)
851 dce_abm_destroy(&pool->base.abm);
852
853 if (pool->base.dmcu != NULL)
854 dce_dmcu_destroy(&pool->base.dmcu);
855
856 if (pool->base.dp_clock_source != NULL)
857 dce60_clock_source_destroy(&pool->base.dp_clock_source);
858
859 for (i = 0; i < pool->base.audio_count; i++) {
860 if (pool->base.audios[i] != NULL) {
861 dce_aud_destroy(&pool->base.audios[i]);
862 }
863 }
864
865 if (pool->base.irqs != NULL) {
866 dal_irq_service_destroy(&pool->base.irqs);
867 }
868 }
869
dce60_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)870 bool dce60_validate_bandwidth(
871 struct dc *dc,
872 struct dc_state *context,
873 bool fast_validate)
874 {
875 int i;
876 bool at_least_one_pipe = false;
877
878 for (i = 0; i < dc->res_pool->pipe_count; i++) {
879 if (context->res_ctx.pipe_ctx[i].stream)
880 at_least_one_pipe = true;
881 }
882
883 if (at_least_one_pipe) {
884 /* TODO implement when needed but for now hardcode max value*/
885 context->bw_ctx.bw.dce.dispclk_khz = 681000;
886 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
887 } else {
888 context->bw_ctx.bw.dce.dispclk_khz = 0;
889 context->bw_ctx.bw.dce.yclk_khz = 0;
890 }
891
892 return true;
893 }
894
dce60_validate_surface_sets(struct dc_state * context)895 static bool dce60_validate_surface_sets(
896 struct dc_state *context)
897 {
898 int i;
899
900 for (i = 0; i < context->stream_count; i++) {
901 if (context->stream_status[i].plane_count == 0)
902 continue;
903
904 if (context->stream_status[i].plane_count > 1)
905 return false;
906
907 if (context->stream_status[i].plane_states[0]->format
908 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
909 return false;
910 }
911
912 return true;
913 }
914
dce60_validate_global(struct dc * dc,struct dc_state * context)915 enum dc_status dce60_validate_global(
916 struct dc *dc,
917 struct dc_state *context)
918 {
919 if (!dce60_validate_surface_sets(context))
920 return DC_FAIL_SURFACE_VALIDATE;
921
922 return DC_OK;
923 }
924
dce60_destroy_resource_pool(struct resource_pool ** pool)925 static void dce60_destroy_resource_pool(struct resource_pool **pool)
926 {
927 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
928
929 dce60_resource_destruct(dce110_pool);
930 kfree(dce110_pool);
931 *pool = NULL;
932 }
933
934 static const struct resource_funcs dce60_res_pool_funcs = {
935 .destroy = dce60_destroy_resource_pool,
936 .link_enc_create = dce60_link_encoder_create,
937 .panel_cntl_create = dce60_panel_cntl_create,
938 .validate_bandwidth = dce60_validate_bandwidth,
939 .validate_plane = dce100_validate_plane,
940 .add_stream_to_ctx = dce100_add_stream_to_ctx,
941 .validate_global = dce60_validate_global,
942 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
943 };
944
dce60_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)945 static bool dce60_construct(
946 uint8_t num_virtual_links,
947 struct dc *dc,
948 struct dce110_resource_pool *pool)
949 {
950 unsigned int i;
951 struct dc_context *ctx = dc->ctx;
952 struct dc_bios *bp;
953
954 ctx->dc_bios->regs = &bios_regs;
955
956 pool->base.res_cap = &res_cap;
957 pool->base.funcs = &dce60_res_pool_funcs;
958
959
960 /*************************************************
961 * Resource + asic cap harcoding *
962 *************************************************/
963 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
964 pool->base.pipe_count = res_cap.num_timing_generator;
965 pool->base.timing_generator_count = res_cap.num_timing_generator;
966 dc->caps.max_downscale_ratio = 200;
967 dc->caps.i2c_speed_in_khz = 40;
968 dc->caps.max_cursor_size = 64;
969 dc->caps.dual_link_dvi = true;
970 dc->caps.extended_aux_timeout_support = false;
971
972 /*************************************************
973 * Create resources *
974 *************************************************/
975
976 bp = ctx->dc_bios;
977
978 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
979 pool->base.dp_clock_source =
980 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
981
982 pool->base.clock_sources[0] =
983 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
984 pool->base.clock_sources[1] =
985 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
986 pool->base.clk_src_count = 2;
987
988 } else {
989 pool->base.dp_clock_source =
990 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
991
992 pool->base.clock_sources[0] =
993 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
994 pool->base.clk_src_count = 1;
995 }
996
997 if (pool->base.dp_clock_source == NULL) {
998 dm_error("DC: failed to create dp clock source!\n");
999 BREAK_TO_DEBUGGER();
1000 goto res_create_fail;
1001 }
1002
1003 for (i = 0; i < pool->base.clk_src_count; i++) {
1004 if (pool->base.clock_sources[i] == NULL) {
1005 dm_error("DC: failed to create clock sources!\n");
1006 BREAK_TO_DEBUGGER();
1007 goto res_create_fail;
1008 }
1009 }
1010
1011 pool->base.dmcu = dce_dmcu_create(ctx,
1012 &dmcu_regs,
1013 &dmcu_shift,
1014 &dmcu_mask);
1015 if (pool->base.dmcu == NULL) {
1016 dm_error("DC: failed to create dmcu!\n");
1017 BREAK_TO_DEBUGGER();
1018 goto res_create_fail;
1019 }
1020
1021 pool->base.abm = dce_abm_create(ctx,
1022 &abm_regs,
1023 &abm_shift,
1024 &abm_mask);
1025 if (pool->base.abm == NULL) {
1026 dm_error("DC: failed to create abm!\n");
1027 BREAK_TO_DEBUGGER();
1028 goto res_create_fail;
1029 }
1030
1031 {
1032 struct irq_service_init_data init_data;
1033 init_data.ctx = dc->ctx;
1034 pool->base.irqs = dal_irq_service_dce60_create(&init_data);
1035 if (!pool->base.irqs)
1036 goto res_create_fail;
1037 }
1038
1039 for (i = 0; i < pool->base.pipe_count; i++) {
1040 pool->base.timing_generators[i] = dce60_timing_generator_create(
1041 ctx, i, &dce60_tg_offsets[i]);
1042 if (pool->base.timing_generators[i] == NULL) {
1043 BREAK_TO_DEBUGGER();
1044 dm_error("DC: failed to create tg!\n");
1045 goto res_create_fail;
1046 }
1047
1048 pool->base.mis[i] = dce60_mem_input_create(ctx, i);
1049 if (pool->base.mis[i] == NULL) {
1050 BREAK_TO_DEBUGGER();
1051 dm_error("DC: failed to create memory input!\n");
1052 goto res_create_fail;
1053 }
1054
1055 pool->base.ipps[i] = dce60_ipp_create(ctx, i);
1056 if (pool->base.ipps[i] == NULL) {
1057 BREAK_TO_DEBUGGER();
1058 dm_error("DC: failed to create input pixel processor!\n");
1059 goto res_create_fail;
1060 }
1061
1062 pool->base.transforms[i] = dce60_transform_create(ctx, i);
1063 if (pool->base.transforms[i] == NULL) {
1064 BREAK_TO_DEBUGGER();
1065 dm_error("DC: failed to create transform!\n");
1066 goto res_create_fail;
1067 }
1068
1069 pool->base.opps[i] = dce60_opp_create(ctx, i);
1070 if (pool->base.opps[i] == NULL) {
1071 BREAK_TO_DEBUGGER();
1072 dm_error("DC: failed to create output pixel processor!\n");
1073 goto res_create_fail;
1074 }
1075 }
1076
1077 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1078 pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
1079 if (pool->base.engines[i] == NULL) {
1080 BREAK_TO_DEBUGGER();
1081 dm_error(
1082 "DC:failed to create aux engine!!\n");
1083 goto res_create_fail;
1084 }
1085 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
1086 if (pool->base.hw_i2cs[i] == NULL) {
1087 BREAK_TO_DEBUGGER();
1088 dm_error(
1089 "DC:failed to create i2c engine!!\n");
1090 goto res_create_fail;
1091 }
1092 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
1093 if (pool->base.sw_i2cs[i] == NULL) {
1094 BREAK_TO_DEBUGGER();
1095 dm_error(
1096 "DC:failed to create sw i2c!!\n");
1097 goto res_create_fail;
1098 }
1099 }
1100
1101 dc->caps.max_planes = pool->base.pipe_count;
1102
1103 for (i = 0; i < dc->caps.max_planes; ++i)
1104 dc->caps.planes[i] = plane_cap;
1105
1106 dc->caps.disable_dp_clk_share = true;
1107
1108 if (!resource_construct(num_virtual_links, dc, &pool->base,
1109 &res_create_funcs))
1110 goto res_create_fail;
1111
1112 /* Create hardware sequencer */
1113 dce60_hw_sequencer_construct(dc);
1114
1115 return true;
1116
1117 res_create_fail:
1118 dce60_resource_destruct(pool);
1119 return false;
1120 }
1121
dce60_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1122 struct resource_pool *dce60_create_resource_pool(
1123 uint8_t num_virtual_links,
1124 struct dc *dc)
1125 {
1126 struct dce110_resource_pool *pool =
1127 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1128
1129 if (!pool)
1130 return NULL;
1131
1132 if (dce60_construct(num_virtual_links, dc, pool))
1133 return &pool->base;
1134
1135 kfree(pool);
1136 BREAK_TO_DEBUGGER();
1137 return NULL;
1138 }
1139
dce61_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1140 static bool dce61_construct(
1141 uint8_t num_virtual_links,
1142 struct dc *dc,
1143 struct dce110_resource_pool *pool)
1144 {
1145 unsigned int i;
1146 struct dc_context *ctx = dc->ctx;
1147 struct dc_bios *bp;
1148
1149 ctx->dc_bios->regs = &bios_regs;
1150
1151 pool->base.res_cap = &res_cap_61;
1152 pool->base.funcs = &dce60_res_pool_funcs;
1153
1154
1155 /*************************************************
1156 * Resource + asic cap harcoding *
1157 *************************************************/
1158 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1159 pool->base.pipe_count = res_cap_61.num_timing_generator;
1160 pool->base.timing_generator_count = res_cap_61.num_timing_generator;
1161 dc->caps.max_downscale_ratio = 200;
1162 dc->caps.i2c_speed_in_khz = 40;
1163 dc->caps.max_cursor_size = 64;
1164 dc->caps.is_apu = true;
1165
1166 /*************************************************
1167 * Create resources *
1168 *************************************************/
1169
1170 bp = ctx->dc_bios;
1171
1172 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1173 pool->base.dp_clock_source =
1174 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1175
1176 pool->base.clock_sources[0] =
1177 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1178 pool->base.clock_sources[1] =
1179 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1180 pool->base.clock_sources[2] =
1181 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1182 pool->base.clk_src_count = 3;
1183
1184 } else {
1185 pool->base.dp_clock_source =
1186 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1187
1188 pool->base.clock_sources[0] =
1189 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1190 pool->base.clock_sources[1] =
1191 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1192 pool->base.clk_src_count = 2;
1193 }
1194
1195 if (pool->base.dp_clock_source == NULL) {
1196 dm_error("DC: failed to create dp clock source!\n");
1197 BREAK_TO_DEBUGGER();
1198 goto res_create_fail;
1199 }
1200
1201 for (i = 0; i < pool->base.clk_src_count; i++) {
1202 if (pool->base.clock_sources[i] == NULL) {
1203 dm_error("DC: failed to create clock sources!\n");
1204 BREAK_TO_DEBUGGER();
1205 goto res_create_fail;
1206 }
1207 }
1208
1209 pool->base.dmcu = dce_dmcu_create(ctx,
1210 &dmcu_regs,
1211 &dmcu_shift,
1212 &dmcu_mask);
1213 if (pool->base.dmcu == NULL) {
1214 dm_error("DC: failed to create dmcu!\n");
1215 BREAK_TO_DEBUGGER();
1216 goto res_create_fail;
1217 }
1218
1219 pool->base.abm = dce_abm_create(ctx,
1220 &abm_regs,
1221 &abm_shift,
1222 &abm_mask);
1223 if (pool->base.abm == NULL) {
1224 dm_error("DC: failed to create abm!\n");
1225 BREAK_TO_DEBUGGER();
1226 goto res_create_fail;
1227 }
1228
1229 {
1230 struct irq_service_init_data init_data;
1231 init_data.ctx = dc->ctx;
1232 pool->base.irqs = dal_irq_service_dce60_create(&init_data);
1233 if (!pool->base.irqs)
1234 goto res_create_fail;
1235 }
1236
1237 for (i = 0; i < pool->base.pipe_count; i++) {
1238 pool->base.timing_generators[i] = dce60_timing_generator_create(
1239 ctx, i, &dce60_tg_offsets[i]);
1240 if (pool->base.timing_generators[i] == NULL) {
1241 BREAK_TO_DEBUGGER();
1242 dm_error("DC: failed to create tg!\n");
1243 goto res_create_fail;
1244 }
1245
1246 pool->base.mis[i] = dce60_mem_input_create(ctx, i);
1247 if (pool->base.mis[i] == NULL) {
1248 BREAK_TO_DEBUGGER();
1249 dm_error("DC: failed to create memory input!\n");
1250 goto res_create_fail;
1251 }
1252
1253 pool->base.ipps[i] = dce60_ipp_create(ctx, i);
1254 if (pool->base.ipps[i] == NULL) {
1255 BREAK_TO_DEBUGGER();
1256 dm_error("DC: failed to create input pixel processor!\n");
1257 goto res_create_fail;
1258 }
1259
1260 pool->base.transforms[i] = dce60_transform_create(ctx, i);
1261 if (pool->base.transforms[i] == NULL) {
1262 BREAK_TO_DEBUGGER();
1263 dm_error("DC: failed to create transform!\n");
1264 goto res_create_fail;
1265 }
1266
1267 pool->base.opps[i] = dce60_opp_create(ctx, i);
1268 if (pool->base.opps[i] == NULL) {
1269 BREAK_TO_DEBUGGER();
1270 dm_error("DC: failed to create output pixel processor!\n");
1271 goto res_create_fail;
1272 }
1273 }
1274
1275 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1276 pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
1277 if (pool->base.engines[i] == NULL) {
1278 BREAK_TO_DEBUGGER();
1279 dm_error(
1280 "DC:failed to create aux engine!!\n");
1281 goto res_create_fail;
1282 }
1283 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
1284 if (pool->base.hw_i2cs[i] == NULL) {
1285 BREAK_TO_DEBUGGER();
1286 dm_error(
1287 "DC:failed to create i2c engine!!\n");
1288 goto res_create_fail;
1289 }
1290 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
1291 if (pool->base.sw_i2cs[i] == NULL) {
1292 BREAK_TO_DEBUGGER();
1293 dm_error(
1294 "DC:failed to create sw i2c!!\n");
1295 goto res_create_fail;
1296 }
1297 }
1298
1299 dc->caps.max_planes = pool->base.pipe_count;
1300
1301 for (i = 0; i < dc->caps.max_planes; ++i)
1302 dc->caps.planes[i] = plane_cap;
1303
1304 dc->caps.disable_dp_clk_share = true;
1305
1306 if (!resource_construct(num_virtual_links, dc, &pool->base,
1307 &res_create_funcs))
1308 goto res_create_fail;
1309
1310 /* Create hardware sequencer */
1311 dce60_hw_sequencer_construct(dc);
1312
1313 return true;
1314
1315 res_create_fail:
1316 dce60_resource_destruct(pool);
1317 return false;
1318 }
1319
dce61_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1320 struct resource_pool *dce61_create_resource_pool(
1321 uint8_t num_virtual_links,
1322 struct dc *dc)
1323 {
1324 struct dce110_resource_pool *pool =
1325 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1326
1327 if (!pool)
1328 return NULL;
1329
1330 if (dce61_construct(num_virtual_links, dc, pool))
1331 return &pool->base;
1332
1333 kfree(pool);
1334 BREAK_TO_DEBUGGER();
1335 return NULL;
1336 }
1337
dce64_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1338 static bool dce64_construct(
1339 uint8_t num_virtual_links,
1340 struct dc *dc,
1341 struct dce110_resource_pool *pool)
1342 {
1343 unsigned int i;
1344 struct dc_context *ctx = dc->ctx;
1345 struct dc_bios *bp;
1346
1347 ctx->dc_bios->regs = &bios_regs;
1348
1349 pool->base.res_cap = &res_cap_64;
1350 pool->base.funcs = &dce60_res_pool_funcs;
1351
1352
1353 /*************************************************
1354 * Resource + asic cap harcoding *
1355 *************************************************/
1356 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1357 pool->base.pipe_count = res_cap_64.num_timing_generator;
1358 pool->base.timing_generator_count = res_cap_64.num_timing_generator;
1359 dc->caps.max_downscale_ratio = 200;
1360 dc->caps.i2c_speed_in_khz = 40;
1361 dc->caps.max_cursor_size = 64;
1362 dc->caps.is_apu = true;
1363
1364 /*************************************************
1365 * Create resources *
1366 *************************************************/
1367
1368 bp = ctx->dc_bios;
1369
1370 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1371 pool->base.dp_clock_source =
1372 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1373
1374 pool->base.clock_sources[0] =
1375 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1376 pool->base.clock_sources[1] =
1377 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1378 pool->base.clk_src_count = 2;
1379
1380 } else {
1381 pool->base.dp_clock_source =
1382 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1383
1384 pool->base.clock_sources[0] =
1385 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1386 pool->base.clk_src_count = 1;
1387 }
1388
1389 if (pool->base.dp_clock_source == NULL) {
1390 dm_error("DC: failed to create dp clock source!\n");
1391 BREAK_TO_DEBUGGER();
1392 goto res_create_fail;
1393 }
1394
1395 for (i = 0; i < pool->base.clk_src_count; i++) {
1396 if (pool->base.clock_sources[i] == NULL) {
1397 dm_error("DC: failed to create clock sources!\n");
1398 BREAK_TO_DEBUGGER();
1399 goto res_create_fail;
1400 }
1401 }
1402
1403 pool->base.dmcu = dce_dmcu_create(ctx,
1404 &dmcu_regs,
1405 &dmcu_shift,
1406 &dmcu_mask);
1407 if (pool->base.dmcu == NULL) {
1408 dm_error("DC: failed to create dmcu!\n");
1409 BREAK_TO_DEBUGGER();
1410 goto res_create_fail;
1411 }
1412
1413 pool->base.abm = dce_abm_create(ctx,
1414 &abm_regs,
1415 &abm_shift,
1416 &abm_mask);
1417 if (pool->base.abm == NULL) {
1418 dm_error("DC: failed to create abm!\n");
1419 BREAK_TO_DEBUGGER();
1420 goto res_create_fail;
1421 }
1422
1423 {
1424 struct irq_service_init_data init_data;
1425 init_data.ctx = dc->ctx;
1426 pool->base.irqs = dal_irq_service_dce60_create(&init_data);
1427 if (!pool->base.irqs)
1428 goto res_create_fail;
1429 }
1430
1431 for (i = 0; i < pool->base.pipe_count; i++) {
1432 pool->base.timing_generators[i] = dce60_timing_generator_create(
1433 ctx, i, &dce60_tg_offsets[i]);
1434 if (pool->base.timing_generators[i] == NULL) {
1435 BREAK_TO_DEBUGGER();
1436 dm_error("DC: failed to create tg!\n");
1437 goto res_create_fail;
1438 }
1439
1440 pool->base.mis[i] = dce60_mem_input_create(ctx, i);
1441 if (pool->base.mis[i] == NULL) {
1442 BREAK_TO_DEBUGGER();
1443 dm_error("DC: failed to create memory input!\n");
1444 goto res_create_fail;
1445 }
1446
1447 pool->base.ipps[i] = dce60_ipp_create(ctx, i);
1448 if (pool->base.ipps[i] == NULL) {
1449 BREAK_TO_DEBUGGER();
1450 dm_error("DC: failed to create input pixel processor!\n");
1451 goto res_create_fail;
1452 }
1453
1454 pool->base.transforms[i] = dce60_transform_create(ctx, i);
1455 if (pool->base.transforms[i] == NULL) {
1456 BREAK_TO_DEBUGGER();
1457 dm_error("DC: failed to create transform!\n");
1458 goto res_create_fail;
1459 }
1460
1461 pool->base.opps[i] = dce60_opp_create(ctx, i);
1462 if (pool->base.opps[i] == NULL) {
1463 BREAK_TO_DEBUGGER();
1464 dm_error("DC: failed to create output pixel processor!\n");
1465 goto res_create_fail;
1466 }
1467 }
1468
1469 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1470 pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
1471 if (pool->base.engines[i] == NULL) {
1472 BREAK_TO_DEBUGGER();
1473 dm_error(
1474 "DC:failed to create aux engine!!\n");
1475 goto res_create_fail;
1476 }
1477 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
1478 if (pool->base.hw_i2cs[i] == NULL) {
1479 BREAK_TO_DEBUGGER();
1480 dm_error(
1481 "DC:failed to create i2c engine!!\n");
1482 goto res_create_fail;
1483 }
1484 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
1485 if (pool->base.sw_i2cs[i] == NULL) {
1486 BREAK_TO_DEBUGGER();
1487 dm_error(
1488 "DC:failed to create sw i2c!!\n");
1489 goto res_create_fail;
1490 }
1491 }
1492
1493 dc->caps.max_planes = pool->base.pipe_count;
1494
1495 for (i = 0; i < dc->caps.max_planes; ++i)
1496 dc->caps.planes[i] = plane_cap;
1497
1498 dc->caps.disable_dp_clk_share = true;
1499
1500 if (!resource_construct(num_virtual_links, dc, &pool->base,
1501 &res_create_funcs))
1502 goto res_create_fail;
1503
1504 /* Create hardware sequencer */
1505 dce60_hw_sequencer_construct(dc);
1506
1507 return true;
1508
1509 res_create_fail:
1510 dce60_resource_destruct(pool);
1511 return false;
1512 }
1513
dce64_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1514 struct resource_pool *dce64_create_resource_pool(
1515 uint8_t num_virtual_links,
1516 struct dc *dc)
1517 {
1518 struct dce110_resource_pool *pool =
1519 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1520
1521 if (!pool)
1522 return NULL;
1523
1524 if (dce64_construct(num_virtual_links, dc, pool))
1525 return &pool->base;
1526
1527 kfree(pool);
1528 BREAK_TO_DEBUGGER();
1529 return NULL;
1530 }
1531