1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/version.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_dp_mst_helper.h>
29 #include <drm/drm_dp_helper.h>
30 #include "dm_services.h"
31 #include "amdgpu.h"
32 #include "amdgpu_dm.h"
33 #include "amdgpu_dm_mst_types.h"
34
35 #include "dc.h"
36 #include "dm_helpers.h"
37
38 #include "dc_link_ddc.h"
39 #include "ddc_service_types.h"
40 #include "dpcd_defs.h"
41
42 #include "i2caux_interface.h"
43 #if defined(CONFIG_DEBUG_FS)
44 #include "amdgpu_dm_debugfs.h"
45 #endif
46
47 #if defined(CONFIG_DRM_AMD_DC_DCN)
48 #include "dc/dcn20/dcn20_resource.h"
49 #endif
50
dm_dp_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)51 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
52 struct drm_dp_aux_msg *msg)
53 {
54 ssize_t result = 0;
55 struct aux_payload payload;
56 enum aux_channel_operation_result operation_result;
57
58 if (WARN_ON(msg->size > 16))
59 return -E2BIG;
60
61 payload.address = msg->address;
62 payload.data = msg->buffer;
63 payload.length = msg->size;
64 payload.reply = &msg->reply;
65 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
66 payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
67 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
68 payload.defer_delay = 0;
69
70 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
71 &operation_result);
72
73 if (payload.write && result >= 0)
74 result = msg->size;
75
76 if (result < 0)
77 switch (operation_result) {
78 case AUX_CHANNEL_OPERATION_SUCCEEDED:
79 break;
80 case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
81 case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
82 result = -EIO;
83 break;
84 case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
85 case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
86 result = -EBUSY;
87 break;
88 case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
89 result = -ETIMEDOUT;
90 break;
91 }
92
93 return result;
94 }
95
96 static void
dm_dp_mst_connector_destroy(struct drm_connector * connector)97 dm_dp_mst_connector_destroy(struct drm_connector *connector)
98 {
99 struct amdgpu_dm_connector *aconnector =
100 to_amdgpu_dm_connector(connector);
101
102 if (aconnector->dc_sink) {
103 dc_link_remove_remote_sink(aconnector->dc_link,
104 aconnector->dc_sink);
105 dc_sink_release(aconnector->dc_sink);
106 }
107
108 kfree(aconnector->edid);
109
110 drm_connector_cleanup(connector);
111 drm_dp_mst_put_port_malloc(aconnector->port);
112 kfree(aconnector);
113 }
114
115 static int
amdgpu_dm_mst_connector_late_register(struct drm_connector * connector)116 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
117 {
118 struct amdgpu_dm_connector *amdgpu_dm_connector =
119 to_amdgpu_dm_connector(connector);
120 int r;
121
122 r = drm_dp_mst_connector_late_register(connector,
123 amdgpu_dm_connector->port);
124 if (r < 0)
125 return r;
126
127 #if defined(CONFIG_DEBUG_FS)
128 connector_debugfs_init(amdgpu_dm_connector);
129 #endif
130
131 return 0;
132 }
133
134 static void
amdgpu_dm_mst_connector_early_unregister(struct drm_connector * connector)135 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
136 {
137 struct amdgpu_dm_connector *amdgpu_dm_connector =
138 to_amdgpu_dm_connector(connector);
139 struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
140
141 drm_dp_mst_connector_early_unregister(connector, port);
142 }
143
144 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
145 .fill_modes = drm_helper_probe_single_connector_modes,
146 .destroy = dm_dp_mst_connector_destroy,
147 .reset = amdgpu_dm_connector_funcs_reset,
148 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
149 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
150 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
151 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
152 .late_register = amdgpu_dm_mst_connector_late_register,
153 .early_unregister = amdgpu_dm_mst_connector_early_unregister,
154 };
155
156 #if defined(CONFIG_DRM_AMD_DC_DCN)
needs_dsc_aux_workaround(struct dc_link * link)157 static bool needs_dsc_aux_workaround(struct dc_link *link)
158 {
159 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
160 (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) &&
161 link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2)
162 return true;
163
164 return false;
165 }
166
is_synaptics_cascaded_panamera(struct dc_link * link,struct drm_dp_mst_port * port)167 bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_mst_port *port)
168 {
169 u8 branch_vendor_data[4] = { 0 }; // Vendor data 0x50C ~ 0x50F
170
171 if (drm_dp_dpcd_read(port->mgr->aux, DP_BRANCH_VENDOR_SPECIFIC_START, &branch_vendor_data, 4) == 4) {
172 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
173 IS_SYNAPTICS_CASCADED_PANAMERA(link->dpcd_caps.branch_dev_name, branch_vendor_data)) {
174 DRM_INFO("Synaptics Cascaded MST hub\n");
175 return true;
176 }
177 }
178
179 return false;
180 }
181
validate_dsc_caps_on_connector(struct amdgpu_dm_connector * aconnector)182 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
183 {
184 struct dc_sink *dc_sink = aconnector->dc_sink;
185 struct drm_dp_mst_port *port = aconnector->port;
186 u8 dsc_caps[16] = { 0 };
187
188 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
189
190 /*
191 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
192 * because it only check the dsc/fec caps of the "port variable" and not the dock
193 *
194 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
195 *
196 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
197 *
198 */
199 if (!aconnector->dsc_aux && !port->parent->port_parent &&
200 needs_dsc_aux_workaround(aconnector->dc_link))
201 aconnector->dsc_aux = &aconnector->mst_port->dm_dp_aux.aux;
202
203 /* synaptics cascaded MST hub case */
204 if (!aconnector->dsc_aux && is_synaptics_cascaded_panamera(aconnector->dc_link, port))
205 aconnector->dsc_aux = port->mgr->aux;
206
207 if (!aconnector->dsc_aux)
208 return false;
209
210 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
211 return false;
212
213 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
214 dsc_caps, NULL,
215 &dc_sink->dsc_caps.dsc_dec_caps))
216 return false;
217
218 return true;
219 }
220 #endif
221
dm_dp_mst_get_modes(struct drm_connector * connector)222 static int dm_dp_mst_get_modes(struct drm_connector *connector)
223 {
224 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
225 int ret = 0;
226
227 if (!aconnector)
228 return drm_add_edid_modes(connector, NULL);
229
230 if (!aconnector->edid) {
231 struct edid *edid;
232 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
233
234 if (!edid) {
235 drm_connector_update_edid_property(
236 &aconnector->base,
237 NULL);
238 return ret;
239 }
240
241 aconnector->edid = edid;
242 }
243
244 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
245 dc_sink_release(aconnector->dc_sink);
246 aconnector->dc_sink = NULL;
247 }
248
249 if (!aconnector->dc_sink) {
250 struct dc_sink *dc_sink;
251 struct dc_sink_init_data init_params = {
252 .link = aconnector->dc_link,
253 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
254 dc_sink = dc_link_add_remote_sink(
255 aconnector->dc_link,
256 (uint8_t *)aconnector->edid,
257 (aconnector->edid->extensions + 1) * EDID_LENGTH,
258 &init_params);
259
260 dc_sink->priv = aconnector;
261 /* dc_link_add_remote_sink returns a new reference */
262 aconnector->dc_sink = dc_sink;
263
264 if (aconnector->dc_sink) {
265 amdgpu_dm_update_freesync_caps(
266 connector, aconnector->edid);
267
268 #if defined(CONFIG_DRM_AMD_DC_DCN)
269 if (!validate_dsc_caps_on_connector(aconnector))
270 memset(&aconnector->dc_sink->dsc_caps,
271 0, sizeof(aconnector->dc_sink->dsc_caps));
272 #endif
273 }
274 }
275
276 drm_connector_update_edid_property(
277 &aconnector->base, aconnector->edid);
278
279 ret = drm_add_edid_modes(connector, aconnector->edid);
280
281 return ret;
282 }
283
284 static struct drm_encoder *
dm_mst_atomic_best_encoder(struct drm_connector * connector,struct drm_connector_state * connector_state)285 dm_mst_atomic_best_encoder(struct drm_connector *connector,
286 struct drm_connector_state *connector_state)
287 {
288 struct drm_device *dev = connector->dev;
289 struct amdgpu_device *adev = drm_to_adev(dev);
290 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
291
292 return &adev->dm.mst_encoders[acrtc->crtc_id].base;
293 }
294
295 static int
dm_dp_mst_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)296 dm_dp_mst_detect(struct drm_connector *connector,
297 struct drm_modeset_acquire_ctx *ctx, bool force)
298 {
299 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
300 struct amdgpu_dm_connector *master = aconnector->mst_port;
301
302 if (drm_connector_is_unregistered(connector))
303 return connector_status_disconnected;
304
305 return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
306 aconnector->port);
307 }
308
dm_dp_mst_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)309 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
310 struct drm_atomic_state *state)
311 {
312 struct drm_connector_state *new_conn_state =
313 drm_atomic_get_new_connector_state(state, connector);
314 struct drm_connector_state *old_conn_state =
315 drm_atomic_get_old_connector_state(state, connector);
316 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
317 struct drm_crtc_state *new_crtc_state;
318 struct drm_dp_mst_topology_mgr *mst_mgr;
319 struct drm_dp_mst_port *mst_port;
320
321 mst_port = aconnector->port;
322 mst_mgr = &aconnector->mst_port->mst_mgr;
323
324 if (!old_conn_state->crtc)
325 return 0;
326
327 if (new_conn_state->crtc) {
328 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
329 if (!new_crtc_state ||
330 !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
331 new_crtc_state->enable)
332 return 0;
333 }
334
335 return drm_dp_atomic_release_vcpi_slots(state,
336 mst_mgr,
337 mst_port);
338 }
339
340 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
341 .get_modes = dm_dp_mst_get_modes,
342 .mode_valid = amdgpu_dm_connector_mode_valid,
343 .atomic_best_encoder = dm_mst_atomic_best_encoder,
344 .detect_ctx = dm_dp_mst_detect,
345 .atomic_check = dm_dp_mst_atomic_check,
346 };
347
amdgpu_dm_encoder_destroy(struct drm_encoder * encoder)348 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
349 {
350 drm_encoder_cleanup(encoder);
351 kfree(encoder);
352 }
353
354 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
355 .destroy = amdgpu_dm_encoder_destroy,
356 };
357
358 void
dm_dp_create_fake_mst_encoders(struct amdgpu_device * adev)359 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
360 {
361 struct drm_device *dev = adev_to_drm(adev);
362 int i;
363
364 for (i = 0; i < adev->dm.display_indexes_num; i++) {
365 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
366 struct drm_encoder *encoder = &amdgpu_encoder->base;
367
368 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
369
370 drm_encoder_init(
371 dev,
372 &amdgpu_encoder->base,
373 &amdgpu_dm_encoder_funcs,
374 DRM_MODE_ENCODER_DPMST,
375 NULL);
376
377 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
378 }
379 }
380
381 static struct drm_connector *
dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr * mgr,struct drm_dp_mst_port * port,const char * pathprop)382 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
383 struct drm_dp_mst_port *port,
384 const char *pathprop)
385 {
386 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
387 struct drm_device *dev = master->base.dev;
388 struct amdgpu_device *adev = drm_to_adev(dev);
389 struct amdgpu_dm_connector *aconnector;
390 struct drm_connector *connector;
391 int i;
392
393 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
394 if (!aconnector)
395 return NULL;
396
397 connector = &aconnector->base;
398 aconnector->port = port;
399 aconnector->mst_port = master;
400
401 if (drm_connector_init(
402 dev,
403 connector,
404 &dm_dp_mst_connector_funcs,
405 DRM_MODE_CONNECTOR_DisplayPort)) {
406 kfree(aconnector);
407 return NULL;
408 }
409 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
410
411 amdgpu_dm_connector_init_helper(
412 &adev->dm,
413 aconnector,
414 DRM_MODE_CONNECTOR_DisplayPort,
415 master->dc_link,
416 master->connector_id);
417
418 for (i = 0; i < adev->dm.display_indexes_num; i++) {
419 drm_connector_attach_encoder(&aconnector->base,
420 &adev->dm.mst_encoders[i].base);
421 }
422
423 connector->max_bpc_property = master->base.max_bpc_property;
424 if (connector->max_bpc_property)
425 drm_connector_attach_max_bpc_property(connector, 8, 16);
426
427 connector->vrr_capable_property = master->base.vrr_capable_property;
428 if (connector->vrr_capable_property)
429 drm_connector_attach_vrr_capable_property(connector);
430
431 drm_object_attach_property(
432 &connector->base,
433 dev->mode_config.path_property,
434 0);
435 drm_object_attach_property(
436 &connector->base,
437 dev->mode_config.tile_property,
438 0);
439
440 drm_connector_set_path_property(connector, pathprop);
441
442 /*
443 * Initialize connector state before adding the connectror to drm and
444 * framebuffer lists
445 */
446 amdgpu_dm_connector_funcs_reset(connector);
447
448 drm_dp_mst_get_port_malloc(port);
449
450 return connector;
451 }
452
453 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
454 .add_connector = dm_dp_add_mst_connector,
455 };
456
amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager * dm,struct amdgpu_dm_connector * aconnector,int link_index)457 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
458 struct amdgpu_dm_connector *aconnector,
459 int link_index)
460 {
461 aconnector->dm_dp_aux.aux.name =
462 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
463 link_index);
464 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
465 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
466
467 drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
468 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
469 &aconnector->base);
470
471 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
472 return;
473
474 aconnector->mst_mgr.cbs = &dm_mst_cbs;
475 drm_dp_mst_topology_mgr_init(
476 &aconnector->mst_mgr,
477 adev_to_drm(dm->adev),
478 &aconnector->dm_dp_aux.aux,
479 16,
480 4,
481 aconnector->connector_id);
482
483 drm_connector_attach_dp_subconnector_property(&aconnector->base);
484 }
485
dm_mst_get_pbn_divider(struct dc_link * link)486 int dm_mst_get_pbn_divider(struct dc_link *link)
487 {
488 if (!link)
489 return 0;
490
491 return dc_link_bandwidth_kbps(link,
492 dc_link_get_link_cap(link)) / (8 * 1000 * 54);
493 }
494
495 #if defined(CONFIG_DRM_AMD_DC_DCN)
496
497 struct dsc_mst_fairness_params {
498 struct dc_crtc_timing *timing;
499 struct dc_sink *sink;
500 struct dc_dsc_bw_range bw_range;
501 bool compression_possible;
502 struct drm_dp_mst_port *port;
503 enum dsc_clock_force_state clock_force_enable;
504 uint32_t num_slices_h;
505 uint32_t num_slices_v;
506 uint32_t bpp_overwrite;
507 };
508
509 struct dsc_mst_fairness_vars {
510 int pbn;
511 bool dsc_enabled;
512 int bpp_x16;
513 };
514
kbps_to_peak_pbn(int kbps)515 static int kbps_to_peak_pbn(int kbps)
516 {
517 u64 peak_kbps = kbps;
518
519 peak_kbps *= 1006;
520 peak_kbps = div_u64(peak_kbps, 1000);
521 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
522 }
523
set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count)524 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
525 struct dsc_mst_fairness_vars *vars,
526 int count)
527 {
528 int i;
529
530 for (i = 0; i < count; i++) {
531 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
532 if (vars[i].dsc_enabled && dc_dsc_compute_config(
533 params[i].sink->ctx->dc->res_pool->dscs[0],
534 ¶ms[i].sink->dsc_caps.dsc_dec_caps,
535 params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
536 0,
537 params[i].timing,
538 ¶ms[i].timing->dsc_cfg)) {
539 params[i].timing->flags.DSC = 1;
540
541 if (params[i].bpp_overwrite)
542 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
543 else
544 params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
545
546 if (params[i].num_slices_h)
547 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
548
549 if (params[i].num_slices_v)
550 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
551 } else {
552 params[i].timing->flags.DSC = 0;
553 }
554 }
555 }
556
bpp_x16_from_pbn(struct dsc_mst_fairness_params param,int pbn)557 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
558 {
559 struct dc_dsc_config dsc_config;
560 u64 kbps;
561
562 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
563 dc_dsc_compute_config(
564 param.sink->ctx->dc->res_pool->dscs[0],
565 ¶m.sink->dsc_caps.dsc_dec_caps,
566 param.sink->ctx->dc->debug.dsc_min_slice_height_override,
567 (int) kbps, param.timing, &dsc_config);
568
569 return dsc_config.bits_per_pixel;
570 }
571
increase_dsc_bpp(struct drm_atomic_state * state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count)572 static void increase_dsc_bpp(struct drm_atomic_state *state,
573 struct dc_link *dc_link,
574 struct dsc_mst_fairness_params *params,
575 struct dsc_mst_fairness_vars *vars,
576 int count)
577 {
578 int i;
579 bool bpp_increased[MAX_PIPES];
580 int initial_slack[MAX_PIPES];
581 int min_initial_slack;
582 int next_index;
583 int remaining_to_increase = 0;
584 int pbn_per_timeslot;
585 int link_timeslots_used;
586 int fair_pbn_alloc;
587
588 pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link);
589
590 for (i = 0; i < count; i++) {
591 if (vars[i].dsc_enabled) {
592 initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
593 bpp_increased[i] = false;
594 remaining_to_increase += 1;
595 } else {
596 initial_slack[i] = 0;
597 bpp_increased[i] = true;
598 }
599 }
600
601 while (remaining_to_increase) {
602 next_index = -1;
603 min_initial_slack = -1;
604 for (i = 0; i < count; i++) {
605 if (!bpp_increased[i]) {
606 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
607 min_initial_slack = initial_slack[i];
608 next_index = i;
609 }
610 }
611 }
612
613 if (next_index == -1)
614 break;
615
616 link_timeslots_used = 0;
617
618 for (i = 0; i < count; i++)
619 link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
620
621 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
622
623 if (initial_slack[next_index] > fair_pbn_alloc) {
624 vars[next_index].pbn += fair_pbn_alloc;
625 if (drm_dp_atomic_find_vcpi_slots(state,
626 params[next_index].port->mgr,
627 params[next_index].port,
628 vars[next_index].pbn,
629 pbn_per_timeslot) < 0)
630 return;
631 if (!drm_dp_mst_atomic_check(state)) {
632 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
633 } else {
634 vars[next_index].pbn -= fair_pbn_alloc;
635 if (drm_dp_atomic_find_vcpi_slots(state,
636 params[next_index].port->mgr,
637 params[next_index].port,
638 vars[next_index].pbn,
639 pbn_per_timeslot) < 0)
640 return;
641 }
642 } else {
643 vars[next_index].pbn += initial_slack[next_index];
644 if (drm_dp_atomic_find_vcpi_slots(state,
645 params[next_index].port->mgr,
646 params[next_index].port,
647 vars[next_index].pbn,
648 pbn_per_timeslot) < 0)
649 return;
650 if (!drm_dp_mst_atomic_check(state)) {
651 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
652 } else {
653 vars[next_index].pbn -= initial_slack[next_index];
654 if (drm_dp_atomic_find_vcpi_slots(state,
655 params[next_index].port->mgr,
656 params[next_index].port,
657 vars[next_index].pbn,
658 pbn_per_timeslot) < 0)
659 return;
660 }
661 }
662
663 bpp_increased[next_index] = true;
664 remaining_to_increase--;
665 }
666 }
667
try_disable_dsc(struct drm_atomic_state * state,struct dc_link * dc_link,struct dsc_mst_fairness_params * params,struct dsc_mst_fairness_vars * vars,int count)668 static void try_disable_dsc(struct drm_atomic_state *state,
669 struct dc_link *dc_link,
670 struct dsc_mst_fairness_params *params,
671 struct dsc_mst_fairness_vars *vars,
672 int count)
673 {
674 int i;
675 bool tried[MAX_PIPES];
676 int kbps_increase[MAX_PIPES];
677 int max_kbps_increase;
678 int next_index;
679 int remaining_to_try = 0;
680
681 for (i = 0; i < count; i++) {
682 if (vars[i].dsc_enabled
683 && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16
684 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
685 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
686 tried[i] = false;
687 remaining_to_try += 1;
688 } else {
689 kbps_increase[i] = 0;
690 tried[i] = true;
691 }
692 }
693
694 while (remaining_to_try) {
695 next_index = -1;
696 max_kbps_increase = -1;
697 for (i = 0; i < count; i++) {
698 if (!tried[i]) {
699 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
700 max_kbps_increase = kbps_increase[i];
701 next_index = i;
702 }
703 }
704 }
705
706 if (next_index == -1)
707 break;
708
709 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
710 if (drm_dp_atomic_find_vcpi_slots(state,
711 params[next_index].port->mgr,
712 params[next_index].port,
713 vars[next_index].pbn,
714 dm_mst_get_pbn_divider(dc_link)) < 0)
715 return;
716
717 if (!drm_dp_mst_atomic_check(state)) {
718 vars[next_index].dsc_enabled = false;
719 vars[next_index].bpp_x16 = 0;
720 } else {
721 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
722 if (drm_dp_atomic_find_vcpi_slots(state,
723 params[next_index].port->mgr,
724 params[next_index].port,
725 vars[next_index].pbn,
726 dm_mst_get_pbn_divider(dc_link)) < 0)
727 return;
728 }
729
730 tried[next_index] = true;
731 remaining_to_try--;
732 }
733 }
734
compute_mst_dsc_configs_for_link(struct drm_atomic_state * state,struct dc_state * dc_state,struct dc_link * dc_link)735 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
736 struct dc_state *dc_state,
737 struct dc_link *dc_link)
738 {
739 int i;
740 struct dc_stream_state *stream;
741 struct dsc_mst_fairness_params params[MAX_PIPES];
742 struct dsc_mst_fairness_vars vars[MAX_PIPES];
743 struct amdgpu_dm_connector *aconnector;
744 int count = 0;
745 bool debugfs_overwrite = false;
746
747 memset(params, 0, sizeof(params));
748
749 /* Set up params */
750 for (i = 0; i < dc_state->stream_count; i++) {
751 struct dc_dsc_policy dsc_policy = {0};
752
753 stream = dc_state->streams[i];
754
755 if (stream->link != dc_link)
756 continue;
757
758 stream->timing.flags.DSC = 0;
759
760 params[count].timing = &stream->timing;
761 params[count].sink = stream->sink;
762 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
763 params[count].port = aconnector->port;
764 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
765 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
766 debugfs_overwrite = true;
767 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
768 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
769 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
770 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
771 dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);
772 if (!dc_dsc_compute_bandwidth_range(
773 stream->sink->ctx->dc->res_pool->dscs[0],
774 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
775 dsc_policy.min_target_bpp,
776 dsc_policy.max_target_bpp,
777 &stream->sink->dsc_caps.dsc_dec_caps,
778 &stream->timing, ¶ms[count].bw_range))
779 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
780
781 count++;
782 }
783 /* Try no compression */
784 for (i = 0; i < count; i++) {
785 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
786 vars[i].dsc_enabled = false;
787 vars[i].bpp_x16 = 0;
788 if (drm_dp_atomic_find_vcpi_slots(state,
789 params[i].port->mgr,
790 params[i].port,
791 vars[i].pbn,
792 dm_mst_get_pbn_divider(dc_link)) < 0)
793 return false;
794 }
795 if (!drm_dp_mst_atomic_check(state) && !debugfs_overwrite) {
796 set_dsc_configs_from_fairness_vars(params, vars, count);
797 return true;
798 }
799
800 /* Try max compression */
801 for (i = 0; i < count; i++) {
802 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
803 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
804 vars[i].dsc_enabled = true;
805 vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
806 if (drm_dp_atomic_find_vcpi_slots(state,
807 params[i].port->mgr,
808 params[i].port,
809 vars[i].pbn,
810 dm_mst_get_pbn_divider(dc_link)) < 0)
811 return false;
812 } else {
813 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
814 vars[i].dsc_enabled = false;
815 vars[i].bpp_x16 = 0;
816 if (drm_dp_atomic_find_vcpi_slots(state,
817 params[i].port->mgr,
818 params[i].port,
819 vars[i].pbn,
820 dm_mst_get_pbn_divider(dc_link)) < 0)
821 return false;
822 }
823 }
824 if (drm_dp_mst_atomic_check(state))
825 return false;
826
827 /* Optimize degree of compression */
828 increase_dsc_bpp(state, dc_link, params, vars, count);
829
830 try_disable_dsc(state, dc_link, params, vars, count);
831
832 set_dsc_configs_from_fairness_vars(params, vars, count);
833
834 return true;
835 }
836
compute_mst_dsc_configs_for_state(struct drm_atomic_state * state,struct dc_state * dc_state)837 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
838 struct dc_state *dc_state)
839 {
840 int i, j;
841 struct dc_stream_state *stream;
842 bool computed_streams[MAX_PIPES];
843 struct amdgpu_dm_connector *aconnector;
844
845 for (i = 0; i < dc_state->stream_count; i++)
846 computed_streams[i] = false;
847
848 for (i = 0; i < dc_state->stream_count; i++) {
849 stream = dc_state->streams[i];
850
851 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
852 continue;
853
854 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
855
856 if (!aconnector || !aconnector->dc_sink)
857 continue;
858
859 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
860 continue;
861
862 if (computed_streams[i])
863 continue;
864
865 if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
866 return false;
867
868 mutex_lock(&aconnector->mst_mgr.lock);
869 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
870 mutex_unlock(&aconnector->mst_mgr.lock);
871 return false;
872 }
873 mutex_unlock(&aconnector->mst_mgr.lock);
874
875 for (j = 0; j < dc_state->stream_count; j++) {
876 if (dc_state->streams[j]->link == stream->link)
877 computed_streams[j] = true;
878 }
879 }
880
881 for (i = 0; i < dc_state->stream_count; i++) {
882 stream = dc_state->streams[i];
883
884 if (stream->timing.flags.DSC == 1)
885 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK)
886 return false;
887 }
888
889 return true;
890 }
891
892 #endif
893