1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 */
4
5 #include "dpu_hwio.h"
6 #include "dpu_hw_catalog.h"
7 #include "dpu_hw_lm.h"
8 #include "dpu_hw_dspp.h"
9 #include "dpu_kms.h"
10
11
12 /* DSPP_PCC */
13 #define PCC_EN BIT(0)
14 #define PCC_DIS 0
15 #define PCC_RED_R_OFF 0x10
16 #define PCC_RED_G_OFF 0x1C
17 #define PCC_RED_B_OFF 0x28
18 #define PCC_GREEN_R_OFF 0x14
19 #define PCC_GREEN_G_OFF 0x20
20 #define PCC_GREEN_B_OFF 0x2C
21 #define PCC_BLUE_R_OFF 0x18
22 #define PCC_BLUE_G_OFF 0x24
23 #define PCC_BLUE_B_OFF 0x30
24
dpu_setup_dspp_pcc(struct dpu_hw_dspp * ctx,struct dpu_hw_pcc_cfg * cfg)25 static void dpu_setup_dspp_pcc(struct dpu_hw_dspp *ctx,
26 struct dpu_hw_pcc_cfg *cfg)
27 {
28
29 u32 base;
30
31 if (!ctx) {
32 DRM_ERROR("invalid ctx %pK\n", ctx);
33 return;
34 }
35
36 base = ctx->cap->sblk->pcc.base;
37
38 if (!base) {
39 DRM_ERROR("invalid ctx %pK pcc base 0x%x\n", ctx, base);
40 return;
41 }
42
43 if (!cfg) {
44 DRM_DEBUG_DRIVER("disable pcc feature\n");
45 DPU_REG_WRITE(&ctx->hw, base, PCC_DIS);
46 return;
47 }
48
49 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_R_OFF, cfg->r.r);
50 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_G_OFF, cfg->r.g);
51 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_B_OFF, cfg->r.b);
52
53 DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_R_OFF, cfg->g.r);
54 DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_G_OFF, cfg->g.g);
55 DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_B_OFF, cfg->g.b);
56
57 DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_R_OFF, cfg->b.r);
58 DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_G_OFF, cfg->b.g);
59 DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_B_OFF, cfg->b.b);
60
61 DPU_REG_WRITE(&ctx->hw, base, PCC_EN);
62 }
63
_setup_dspp_ops(struct dpu_hw_dspp * c,unsigned long features)64 static void _setup_dspp_ops(struct dpu_hw_dspp *c,
65 unsigned long features)
66 {
67 if (test_bit(DPU_DSPP_PCC, &features) &&
68 IS_SC7180_TARGET(c->hw.hwversion))
69 c->ops.setup_pcc = dpu_setup_dspp_pcc;
70 }
71
_dspp_offset(enum dpu_dspp dspp,const struct dpu_mdss_cfg * m,void __iomem * addr,struct dpu_hw_blk_reg_map * b)72 static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp dspp,
73 const struct dpu_mdss_cfg *m,
74 void __iomem *addr,
75 struct dpu_hw_blk_reg_map *b)
76 {
77 int i;
78
79 if (!m || !addr || !b)
80 return ERR_PTR(-EINVAL);
81
82 for (i = 0; i < m->dspp_count; i++) {
83 if (dspp == m->dspp[i].id) {
84 b->base_off = addr;
85 b->blk_off = m->dspp[i].base;
86 b->length = m->dspp[i].len;
87 b->hwversion = m->hwversion;
88 b->log_mask = DPU_DBG_MASK_DSPP;
89 return &m->dspp[i];
90 }
91 }
92
93 return ERR_PTR(-EINVAL);
94 }
95
96 static struct dpu_hw_blk_ops dpu_hw_ops;
97
dpu_hw_dspp_init(enum dpu_dspp idx,void __iomem * addr,const struct dpu_mdss_cfg * m)98 struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx,
99 void __iomem *addr,
100 const struct dpu_mdss_cfg *m)
101 {
102 struct dpu_hw_dspp *c;
103 const struct dpu_dspp_cfg *cfg;
104
105 if (!addr || !m)
106 return ERR_PTR(-EINVAL);
107
108 c = kzalloc(sizeof(*c), GFP_KERNEL);
109 if (!c)
110 return ERR_PTR(-ENOMEM);
111
112 cfg = _dspp_offset(idx, m, addr, &c->hw);
113 if (IS_ERR_OR_NULL(cfg)) {
114 kfree(c);
115 return ERR_PTR(-EINVAL);
116 }
117
118 /* Assign ops */
119 c->idx = idx;
120 c->cap = cfg;
121 _setup_dspp_ops(c, c->cap->features);
122
123 dpu_hw_blk_init(&c->base, DPU_HW_BLK_DSPP, idx, &dpu_hw_ops);
124
125 return c;
126 }
127
dpu_hw_dspp_destroy(struct dpu_hw_dspp * dspp)128 void dpu_hw_dspp_destroy(struct dpu_hw_dspp *dspp)
129 {
130 if (dspp)
131 dpu_hw_blk_destroy(&dspp->base);
132
133 kfree(dspp);
134 }
135
136
137