1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3 */
4
5 #include "dpu_hwio.h"
6 #include "dpu_hw_catalog.h"
7 #include "dpu_hw_intf.h"
8 #include "dpu_kms.h"
9
10 #define INTF_TIMING_ENGINE_EN 0x000
11 #define INTF_CONFIG 0x004
12 #define INTF_HSYNC_CTL 0x008
13 #define INTF_VSYNC_PERIOD_F0 0x00C
14 #define INTF_VSYNC_PERIOD_F1 0x010
15 #define INTF_VSYNC_PULSE_WIDTH_F0 0x014
16 #define INTF_VSYNC_PULSE_WIDTH_F1 0x018
17 #define INTF_DISPLAY_V_START_F0 0x01C
18 #define INTF_DISPLAY_V_START_F1 0x020
19 #define INTF_DISPLAY_V_END_F0 0x024
20 #define INTF_DISPLAY_V_END_F1 0x028
21 #define INTF_ACTIVE_V_START_F0 0x02C
22 #define INTF_ACTIVE_V_START_F1 0x030
23 #define INTF_ACTIVE_V_END_F0 0x034
24 #define INTF_ACTIVE_V_END_F1 0x038
25 #define INTF_DISPLAY_HCTL 0x03C
26 #define INTF_ACTIVE_HCTL 0x040
27 #define INTF_BORDER_COLOR 0x044
28 #define INTF_UNDERFLOW_COLOR 0x048
29 #define INTF_HSYNC_SKEW 0x04C
30 #define INTF_POLARITY_CTL 0x050
31 #define INTF_TEST_CTL 0x054
32 #define INTF_TP_COLOR0 0x058
33 #define INTF_TP_COLOR1 0x05C
34 #define INTF_FRAME_LINE_COUNT_EN 0x0A8
35 #define INTF_FRAME_COUNT 0x0AC
36 #define INTF_LINE_COUNT 0x0B0
37
38 #define INTF_DEFLICKER_CONFIG 0x0F0
39 #define INTF_DEFLICKER_STRNG_COEFF 0x0F4
40 #define INTF_DEFLICKER_WEAK_COEFF 0x0F8
41
42 #define INTF_DSI_CMD_MODE_TRIGGER_EN 0x084
43 #define INTF_PANEL_FORMAT 0x090
44 #define INTF_TPG_ENABLE 0x100
45 #define INTF_TPG_MAIN_CONTROL 0x104
46 #define INTF_TPG_VIDEO_CONFIG 0x108
47 #define INTF_TPG_COMPONENT_LIMITS 0x10C
48 #define INTF_TPG_RECTANGLE 0x110
49 #define INTF_TPG_INITIAL_VALUE 0x114
50 #define INTF_TPG_BLK_WHITE_PATTERN_FRAMES 0x118
51 #define INTF_TPG_RGB_MAPPING 0x11C
52 #define INTF_PROG_FETCH_START 0x170
53 #define INTF_PROG_ROT_START 0x174
54 #define INTF_MUX 0x25C
55
_intf_offset(enum dpu_intf intf,const struct dpu_mdss_cfg * m,void __iomem * addr,struct dpu_hw_blk_reg_map * b)56 static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
57 const struct dpu_mdss_cfg *m,
58 void __iomem *addr,
59 struct dpu_hw_blk_reg_map *b)
60 {
61 int i;
62
63 for (i = 0; i < m->intf_count; i++) {
64 if ((intf == m->intf[i].id) &&
65 (m->intf[i].type != INTF_NONE)) {
66 b->base_off = addr;
67 b->blk_off = m->intf[i].base;
68 b->length = m->intf[i].len;
69 b->hwversion = m->hwversion;
70 b->log_mask = DPU_DBG_MASK_INTF;
71 return &m->intf[i];
72 }
73 }
74
75 return ERR_PTR(-EINVAL);
76 }
77
dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf * ctx,const struct intf_timing_params * p,const struct dpu_format * fmt)78 static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
79 const struct intf_timing_params *p,
80 const struct dpu_format *fmt)
81 {
82 struct dpu_hw_blk_reg_map *c = &ctx->hw;
83 u32 hsync_period, vsync_period;
84 u32 display_v_start, display_v_end;
85 u32 hsync_start_x, hsync_end_x;
86 u32 active_h_start, active_h_end;
87 u32 active_v_start, active_v_end;
88 u32 active_hctl, display_hctl, hsync_ctl;
89 u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity;
90 u32 panel_format;
91 u32 intf_cfg;
92
93 /* read interface_cfg */
94 intf_cfg = DPU_REG_READ(c, INTF_CONFIG);
95 hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width +
96 p->h_front_porch;
97 vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height +
98 p->v_front_porch;
99
100 display_v_start = ((p->vsync_pulse_width + p->v_back_porch) *
101 hsync_period) + p->hsync_skew;
102 display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) +
103 p->hsync_skew - 1;
104
105 hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
106 hsync_end_x = hsync_period - p->h_front_porch - 1;
107
108 if (p->width != p->xres) {
109 active_h_start = hsync_start_x;
110 active_h_end = active_h_start + p->xres - 1;
111 } else {
112 active_h_start = 0;
113 active_h_end = 0;
114 }
115
116 if (p->height != p->yres) {
117 active_v_start = display_v_start;
118 active_v_end = active_v_start + (p->yres * hsync_period) - 1;
119 } else {
120 active_v_start = 0;
121 active_v_end = 0;
122 }
123
124 if (active_h_end) {
125 active_hctl = (active_h_end << 16) | active_h_start;
126 intf_cfg |= BIT(29); /* ACTIVE_H_ENABLE */
127 } else {
128 active_hctl = 0;
129 }
130
131 if (active_v_end)
132 intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */
133
134 hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
135 display_hctl = (hsync_end_x << 16) | hsync_start_x;
136
137 if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) {
138 active_h_start = hsync_start_x;
139 active_h_end = active_h_start + p->xres - 1;
140 active_v_start = display_v_start;
141 active_v_end = active_v_start + (p->yres * hsync_period) - 1;
142
143 display_v_start += p->hsync_pulse_width + p->h_back_porch;
144 display_v_end -= p->h_front_porch;
145
146 active_hctl = (active_h_end << 16) | active_h_start;
147 display_hctl = active_hctl;
148 }
149
150 den_polarity = 0;
151 if (ctx->cap->type == INTF_HDMI) {
152 hsync_polarity = p->yres >= 720 ? 0 : 1;
153 vsync_polarity = p->yres >= 720 ? 0 : 1;
154 } else if (ctx->cap->type == INTF_DP) {
155 hsync_polarity = p->hsync_polarity;
156 vsync_polarity = p->vsync_polarity;
157 } else {
158 hsync_polarity = 0;
159 vsync_polarity = 0;
160 }
161 polarity_ctl = (den_polarity << 2) | /* DEN Polarity */
162 (vsync_polarity << 1) | /* VSYNC Polarity */
163 (hsync_polarity << 0); /* HSYNC Polarity */
164
165 if (!DPU_FORMAT_IS_YUV(fmt))
166 panel_format = (fmt->bits[C0_G_Y] |
167 (fmt->bits[C1_B_Cb] << 2) |
168 (fmt->bits[C2_R_Cr] << 4) |
169 (0x21 << 8));
170 else
171 /* Interface treats all the pixel data in RGB888 format */
172 panel_format = (COLOR_8BIT |
173 (COLOR_8BIT << 2) |
174 (COLOR_8BIT << 4) |
175 (0x21 << 8));
176
177 DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);
178 DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period);
179 DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0,
180 p->vsync_pulse_width * hsync_period);
181 DPU_REG_WRITE(c, INTF_DISPLAY_HCTL, display_hctl);
182 DPU_REG_WRITE(c, INTF_DISPLAY_V_START_F0, display_v_start);
183 DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end);
184 DPU_REG_WRITE(c, INTF_ACTIVE_HCTL, active_hctl);
185 DPU_REG_WRITE(c, INTF_ACTIVE_V_START_F0, active_v_start);
186 DPU_REG_WRITE(c, INTF_ACTIVE_V_END_F0, active_v_end);
187 DPU_REG_WRITE(c, INTF_BORDER_COLOR, p->border_clr);
188 DPU_REG_WRITE(c, INTF_UNDERFLOW_COLOR, p->underflow_clr);
189 DPU_REG_WRITE(c, INTF_HSYNC_SKEW, p->hsync_skew);
190 DPU_REG_WRITE(c, INTF_POLARITY_CTL, polarity_ctl);
191 DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3);
192 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg);
193 DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
194 }
195
dpu_hw_intf_enable_timing_engine(struct dpu_hw_intf * intf,u8 enable)196 static void dpu_hw_intf_enable_timing_engine(
197 struct dpu_hw_intf *intf,
198 u8 enable)
199 {
200 struct dpu_hw_blk_reg_map *c = &intf->hw;
201 /* Note: Display interface select is handled in top block hw layer */
202 DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0);
203 }
204
dpu_hw_intf_setup_prg_fetch(struct dpu_hw_intf * intf,const struct intf_prog_fetch * fetch)205 static void dpu_hw_intf_setup_prg_fetch(
206 struct dpu_hw_intf *intf,
207 const struct intf_prog_fetch *fetch)
208 {
209 struct dpu_hw_blk_reg_map *c = &intf->hw;
210 int fetch_enable;
211
212 /*
213 * Fetch should always be outside the active lines. If the fetching
214 * is programmed within active region, hardware behavior is unknown.
215 */
216
217 fetch_enable = DPU_REG_READ(c, INTF_CONFIG);
218 if (fetch->enable) {
219 fetch_enable |= BIT(31);
220 DPU_REG_WRITE(c, INTF_PROG_FETCH_START,
221 fetch->fetch_start);
222 } else {
223 fetch_enable &= ~BIT(31);
224 }
225
226 DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable);
227 }
228
dpu_hw_intf_bind_pingpong_blk(struct dpu_hw_intf * intf,bool enable,const enum dpu_pingpong pp)229 static void dpu_hw_intf_bind_pingpong_blk(
230 struct dpu_hw_intf *intf,
231 bool enable,
232 const enum dpu_pingpong pp)
233 {
234 struct dpu_hw_blk_reg_map *c = &intf->hw;
235 u32 mux_cfg;
236
237 mux_cfg = DPU_REG_READ(c, INTF_MUX);
238 mux_cfg &= ~0xf;
239
240 if (enable)
241 mux_cfg |= (pp - PINGPONG_0) & 0x7;
242 else
243 mux_cfg |= 0xf;
244
245 DPU_REG_WRITE(c, INTF_MUX, mux_cfg);
246 }
247
dpu_hw_intf_get_status(struct dpu_hw_intf * intf,struct intf_status * s)248 static void dpu_hw_intf_get_status(
249 struct dpu_hw_intf *intf,
250 struct intf_status *s)
251 {
252 struct dpu_hw_blk_reg_map *c = &intf->hw;
253
254 s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
255 if (s->is_en) {
256 s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT);
257 s->line_count = DPU_REG_READ(c, INTF_LINE_COUNT);
258 } else {
259 s->line_count = 0;
260 s->frame_count = 0;
261 }
262 }
263
dpu_hw_intf_get_line_count(struct dpu_hw_intf * intf)264 static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
265 {
266 struct dpu_hw_blk_reg_map *c;
267
268 if (!intf)
269 return 0;
270
271 c = &intf->hw;
272
273 return DPU_REG_READ(c, INTF_LINE_COUNT);
274 }
275
_setup_intf_ops(struct dpu_hw_intf_ops * ops,unsigned long cap)276 static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
277 unsigned long cap)
278 {
279 ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine;
280 ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch;
281 ops->get_status = dpu_hw_intf_get_status;
282 ops->enable_timing = dpu_hw_intf_enable_timing_engine;
283 ops->get_line_count = dpu_hw_intf_get_line_count;
284 if (cap & BIT(DPU_INTF_INPUT_CTRL))
285 ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
286 }
287
288 static struct dpu_hw_blk_ops dpu_hw_ops;
289
dpu_hw_intf_init(enum dpu_intf idx,void __iomem * addr,const struct dpu_mdss_cfg * m)290 struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx,
291 void __iomem *addr,
292 const struct dpu_mdss_cfg *m)
293 {
294 struct dpu_hw_intf *c;
295 const struct dpu_intf_cfg *cfg;
296
297 c = kzalloc(sizeof(*c), GFP_KERNEL);
298 if (!c)
299 return ERR_PTR(-ENOMEM);
300
301 cfg = _intf_offset(idx, m, addr, &c->hw);
302 if (IS_ERR_OR_NULL(cfg)) {
303 kfree(c);
304 pr_err("failed to create dpu_hw_intf %d\n", idx);
305 return ERR_PTR(-EINVAL);
306 }
307
308 /*
309 * Assign ops
310 */
311 c->idx = idx;
312 c->cap = cfg;
313 c->mdss = m;
314 _setup_intf_ops(&c->ops, c->cap->features);
315
316 dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops);
317
318 return c;
319 }
320
dpu_hw_intf_destroy(struct dpu_hw_intf * intf)321 void dpu_hw_intf_destroy(struct dpu_hw_intf *intf)
322 {
323 if (intf)
324 dpu_hw_blk_destroy(&intf->base);
325 kfree(intf);
326 }
327
328