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1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  Device State Control Registers driver
4  *
5  *  Copyright (C) 2011 Texas Instruments Incorporated
6  *  Author: Mark Salter <msalter@redhat.com>
7  */
8 
9 /*
10  * The Device State Control Registers (DSCR) provide SoC level control over
11  * a number of peripherals. Details vary considerably among the various SoC
12  * parts. In general, the DSCR block will provide one or more configuration
13  * registers often protected by a lock register. One or more key values must
14  * be written to a lock register in order to unlock the configuration register.
15  * The configuration register may be used to enable (and disable in some
16  * cases) SoC pin drivers, peripheral clock sources (internal or pin), etc.
17  * In some cases, a configuration register is write once or the individual
18  * bits are write once. That is, you may be able to enable a device, but
19  * will not be able to disable it.
20  *
21  * In addition to device configuration, the DSCR block may provide registers
22  * which are used to reset SoC peripherals, provide device ID information,
23  * provide MAC addresses, and other miscellaneous functions.
24  */
25 
26 #include <linux/of.h>
27 #include <linux/of_address.h>
28 #include <linux/of_platform.h>
29 #include <linux/module.h>
30 #include <linux/io.h>
31 #include <linux/delay.h>
32 #include <asm/soc.h>
33 #include <asm/dscr.h>
34 
35 #define MAX_DEVSTATE_IDS   32
36 #define MAX_DEVCTL_REGS     8
37 #define MAX_DEVSTAT_REGS    8
38 #define MAX_LOCKED_REGS     4
39 #define MAX_SOC_EMACS       2
40 
41 struct rmii_reset_reg {
42 	u32 reg;
43 	u32 mask;
44 };
45 
46 /*
47  * Some registerd may be locked. In order to write to these
48  * registers, the key value must first be written to the lockreg.
49  */
50 struct locked_reg {
51 	u32 reg;	/* offset from base */
52 	u32 lockreg;	/* offset from base */
53 	u32 key;	/* unlock key */
54 };
55 
56 /*
57  * This describes a contiguous area of like control bits used to enable/disable
58  * SoC devices. Each controllable device is given an ID which is used by the
59  * individual device drivers to control the device state. These IDs start at
60  * zero and are assigned sequentially to the control bitfield ranges described
61  * by this structure.
62  */
63 struct devstate_ctl_reg {
64 	u32 reg;		/* register holding the control bits */
65 	u8  start_id;		/* start id of this range */
66 	u8  num_ids;		/* number of devices in this range */
67 	u8  enable_only;	/* bits are write-once to enable only */
68 	u8  enable;		/* value used to enable device */
69 	u8  disable;		/* value used to disable device */
70 	u8  shift;		/* starting (rightmost) bit in range */
71 	u8  nbits;		/* number of bits per device */
72 };
73 
74 
75 /*
76  * This describes a region of status bits indicating the state of
77  * various devices. This is used internally to wait for status
78  * change completion when enabling/disabling a device. Status is
79  * optional and not all device controls will have a corresponding
80  * status.
81  */
82 struct devstate_stat_reg {
83 	u32 reg;		/* register holding the status bits */
84 	u8  start_id;		/* start id of this range */
85 	u8  num_ids;		/* number of devices in this range */
86 	u8  enable;		/* value indicating enabled state */
87 	u8  disable;		/* value indicating disabled state */
88 	u8  shift;		/* starting (rightmost) bit in range */
89 	u8  nbits;		/* number of bits per device */
90 };
91 
92 struct devstate_info {
93 	struct devstate_ctl_reg *ctl;
94 	struct devstate_stat_reg *stat;
95 };
96 
97 /* These are callbacks to SOC-specific code. */
98 struct dscr_ops {
99 	void (*init)(struct device_node *node);
100 };
101 
102 struct dscr_regs {
103 	spinlock_t		lock;
104 	void __iomem		*base;
105 	u32			kick_reg[2];
106 	u32			kick_key[2];
107 	struct locked_reg	locked[MAX_LOCKED_REGS];
108 	struct devstate_info	devstate_info[MAX_DEVSTATE_IDS];
109 	struct rmii_reset_reg   rmii_resets[MAX_SOC_EMACS];
110 	struct devstate_ctl_reg devctl[MAX_DEVCTL_REGS];
111 	struct devstate_stat_reg devstat[MAX_DEVSTAT_REGS];
112 };
113 
114 static struct dscr_regs	dscr;
115 
find_locked_reg(u32 reg)116 static struct locked_reg *find_locked_reg(u32 reg)
117 {
118 	int i;
119 
120 	for (i = 0; i < MAX_LOCKED_REGS; i++)
121 		if (dscr.locked[i].key && reg == dscr.locked[i].reg)
122 			return &dscr.locked[i];
123 	return NULL;
124 }
125 
126 /*
127  * Write to a register with one lock
128  */
dscr_write_locked1(u32 reg,u32 val,u32 lock,u32 key)129 static void dscr_write_locked1(u32 reg, u32 val,
130 			       u32 lock, u32 key)
131 {
132 	void __iomem *reg_addr = dscr.base + reg;
133 	void __iomem *lock_addr = dscr.base + lock;
134 
135 	/*
136 	 * For some registers, the lock is relocked after a short number
137 	 * of cycles. We have to put the lock write and register write in
138 	 * the same fetch packet to meet this timing. The .align ensures
139 	 * the two stw instructions are in the same fetch packet.
140 	 */
141 	asm volatile ("b	.s2	0f\n"
142 		      "nop	5\n"
143 		      "    .align 5\n"
144 		      "0:\n"
145 		      "stw	.D1T2	%3,*%2\n"
146 		      "stw	.D1T2	%1,*%0\n"
147 		      :
148 		      : "a"(reg_addr), "b"(val), "a"(lock_addr), "b"(key)
149 		);
150 
151 	/* in case the hw doesn't reset the lock */
152 	soc_writel(0, lock_addr);
153 }
154 
155 /*
156  * Write to a register protected by two lock registers
157  */
dscr_write_locked2(u32 reg,u32 val,u32 lock0,u32 key0,u32 lock1,u32 key1)158 static void dscr_write_locked2(u32 reg, u32 val,
159 			       u32 lock0, u32 key0,
160 			       u32 lock1, u32 key1)
161 {
162 	soc_writel(key0, dscr.base + lock0);
163 	soc_writel(key1, dscr.base + lock1);
164 	soc_writel(val, dscr.base + reg);
165 	soc_writel(0, dscr.base + lock0);
166 	soc_writel(0, dscr.base + lock1);
167 }
168 
dscr_write(u32 reg,u32 val)169 static void dscr_write(u32 reg, u32 val)
170 {
171 	struct locked_reg *lock;
172 
173 	lock = find_locked_reg(reg);
174 	if (lock)
175 		dscr_write_locked1(reg, val, lock->lockreg, lock->key);
176 	else if (dscr.kick_key[0])
177 		dscr_write_locked2(reg, val, dscr.kick_reg[0], dscr.kick_key[0],
178 				   dscr.kick_reg[1], dscr.kick_key[1]);
179 	else
180 		soc_writel(val, dscr.base + reg);
181 }
182 
183 
184 /*
185  * Drivers can use this interface to enable/disable SoC IP blocks.
186  */
dscr_set_devstate(int id,enum dscr_devstate_t state)187 void dscr_set_devstate(int id, enum dscr_devstate_t state)
188 {
189 	struct devstate_ctl_reg *ctl;
190 	struct devstate_stat_reg *stat;
191 	struct devstate_info *info;
192 	u32 ctl_val, val;
193 	int ctl_shift, ctl_mask;
194 	unsigned long flags;
195 
196 	if (!dscr.base)
197 		return;
198 
199 	if (id < 0 || id >= MAX_DEVSTATE_IDS)
200 		return;
201 
202 	info = &dscr.devstate_info[id];
203 	ctl = info->ctl;
204 	stat = info->stat;
205 
206 	if (ctl == NULL)
207 		return;
208 
209 	ctl_shift = ctl->shift + ctl->nbits * (id - ctl->start_id);
210 	ctl_mask = ((1 << ctl->nbits) - 1) << ctl_shift;
211 
212 	switch (state) {
213 	case DSCR_DEVSTATE_ENABLED:
214 		ctl_val = ctl->enable << ctl_shift;
215 		break;
216 	case DSCR_DEVSTATE_DISABLED:
217 		if (ctl->enable_only)
218 			return;
219 		ctl_val = ctl->disable << ctl_shift;
220 		break;
221 	default:
222 		return;
223 	}
224 
225 	spin_lock_irqsave(&dscr.lock, flags);
226 
227 	val = soc_readl(dscr.base + ctl->reg);
228 	val &= ~ctl_mask;
229 	val |= ctl_val;
230 
231 	dscr_write(ctl->reg, val);
232 
233 	spin_unlock_irqrestore(&dscr.lock, flags);
234 
235 	if (!stat)
236 		return;
237 
238 	ctl_shift = stat->shift + stat->nbits * (id - stat->start_id);
239 
240 	if (state == DSCR_DEVSTATE_ENABLED)
241 		ctl_val = stat->enable;
242 	else
243 		ctl_val = stat->disable;
244 
245 	do {
246 		val = soc_readl(dscr.base + stat->reg);
247 		val >>= ctl_shift;
248 		val &= ((1 << stat->nbits) - 1);
249 	} while (val != ctl_val);
250 }
251 EXPORT_SYMBOL(dscr_set_devstate);
252 
253 /*
254  * Drivers can use this to reset RMII module.
255  */
dscr_rmii_reset(int id,int assert)256 void dscr_rmii_reset(int id, int assert)
257 {
258 	struct rmii_reset_reg *r;
259 	unsigned long flags;
260 	u32 val;
261 
262 	if (id < 0 || id >= MAX_SOC_EMACS)
263 		return;
264 
265 	r = &dscr.rmii_resets[id];
266 	if (r->mask == 0)
267 		return;
268 
269 	spin_lock_irqsave(&dscr.lock, flags);
270 
271 	val = soc_readl(dscr.base + r->reg);
272 	if (assert)
273 		dscr_write(r->reg, val | r->mask);
274 	else
275 		dscr_write(r->reg, val & ~(r->mask));
276 
277 	spin_unlock_irqrestore(&dscr.lock, flags);
278 }
279 EXPORT_SYMBOL(dscr_rmii_reset);
280 
dscr_parse_devstat(struct device_node * node,void __iomem * base)281 static void __init dscr_parse_devstat(struct device_node *node,
282 				      void __iomem *base)
283 {
284 	u32 val;
285 	int err;
286 
287 	err = of_property_read_u32_array(node, "ti,dscr-devstat", &val, 1);
288 	if (!err)
289 		c6x_devstat = soc_readl(base + val);
290 	printk(KERN_INFO "DEVSTAT: %08x\n", c6x_devstat);
291 }
292 
dscr_parse_silicon_rev(struct device_node * node,void __iomem * base)293 static void __init dscr_parse_silicon_rev(struct device_node *node,
294 					 void __iomem *base)
295 {
296 	u32 vals[3];
297 	int err;
298 
299 	err = of_property_read_u32_array(node, "ti,dscr-silicon-rev", vals, 3);
300 	if (!err) {
301 		c6x_silicon_rev = soc_readl(base + vals[0]);
302 		c6x_silicon_rev >>= vals[1];
303 		c6x_silicon_rev &= vals[2];
304 	}
305 }
306 
307 /*
308  * Some SoCs will have a pair of fuse registers which hold
309  * an ethernet MAC address. The "ti,dscr-mac-fuse-regs"
310  * property is a mapping from fuse register bytes to MAC
311  * address bytes. The expected format is:
312  *
313  *	ti,dscr-mac-fuse-regs = <reg0 b3 b2 b1 b0
314  *				 reg1 b3 b2 b1 b0>
315  *
316  * reg0 and reg1 are the offsets of the two fuse registers.
317  * b3-b0 positionally represent bytes within the fuse register.
318  * b3 is the most significant byte and b0 is the least.
319  * Allowable values for b3-b0 are:
320  *
321  *	  0 = fuse register byte not used in MAC address
322  *      1-6 = index+1 into c6x_fuse_mac[]
323  */
dscr_parse_mac_fuse(struct device_node * node,void __iomem * base)324 static void __init dscr_parse_mac_fuse(struct device_node *node,
325 				       void __iomem *base)
326 {
327 	u32 vals[10], fuse;
328 	int f, i, j, err;
329 
330 	err = of_property_read_u32_array(node, "ti,dscr-mac-fuse-regs",
331 					 vals, 10);
332 	if (err)
333 		return;
334 
335 	for (f = 0; f < 2; f++) {
336 		fuse = soc_readl(base + vals[f * 5]);
337 		for (j = (f * 5) + 1, i = 24; i >= 0; i -= 8, j++)
338 			if (vals[j] && vals[j] <= 6)
339 				c6x_fuse_mac[vals[j] - 1] = fuse >> i;
340 	}
341 }
342 
dscr_parse_rmii_resets(struct device_node * node,void __iomem * base)343 static void __init dscr_parse_rmii_resets(struct device_node *node,
344 					  void __iomem *base)
345 {
346 	const __be32 *p;
347 	int i, size;
348 
349 	/* look for RMII reset registers */
350 	p = of_get_property(node, "ti,dscr-rmii-resets", &size);
351 	if (p) {
352 		/* parse all the reg/mask pairs we can handle */
353 		size /= (sizeof(*p) * 2);
354 		if (size > MAX_SOC_EMACS)
355 			size = MAX_SOC_EMACS;
356 
357 		for (i = 0; i < size; i++) {
358 			dscr.rmii_resets[i].reg = be32_to_cpup(p++);
359 			dscr.rmii_resets[i].mask = be32_to_cpup(p++);
360 		}
361 	}
362 }
363 
364 
dscr_parse_privperm(struct device_node * node,void __iomem * base)365 static void __init dscr_parse_privperm(struct device_node *node,
366 				       void __iomem *base)
367 {
368 	u32 vals[2];
369 	int err;
370 
371 	err = of_property_read_u32_array(node, "ti,dscr-privperm", vals, 2);
372 	if (err)
373 		return;
374 	dscr_write(vals[0], vals[1]);
375 }
376 
377 /*
378  * SoCs may have "locked" DSCR registers which can only be written
379  * to only after writing a key value to a lock registers. These
380  * regisers can be described with the "ti,dscr-locked-regs" property.
381  * This property provides a list of register descriptions with each
382  * description consisting of three values.
383  *
384  *	ti,dscr-locked-regs = <reg0 lockreg0 key0
385  *                               ...
386  *                             regN lockregN keyN>;
387  *
388  * reg is the offset of the locked register
389  * lockreg is the offset of the lock register
390  * key is the unlock key written to lockreg
391  *
392  */
dscr_parse_locked_regs(struct device_node * node,void __iomem * base)393 static void __init dscr_parse_locked_regs(struct device_node *node,
394 					  void __iomem *base)
395 {
396 	struct locked_reg *r;
397 	const __be32 *p;
398 	int i, size;
399 
400 	p = of_get_property(node, "ti,dscr-locked-regs", &size);
401 	if (p) {
402 		/* parse all the register descriptions we can handle */
403 		size /= (sizeof(*p) * 3);
404 		if (size > MAX_LOCKED_REGS)
405 			size = MAX_LOCKED_REGS;
406 
407 		for (i = 0; i < size; i++) {
408 			r = &dscr.locked[i];
409 
410 			r->reg = be32_to_cpup(p++);
411 			r->lockreg = be32_to_cpup(p++);
412 			r->key = be32_to_cpup(p++);
413 		}
414 	}
415 }
416 
417 /*
418  * SoCs may have DSCR registers which are only write enabled after
419  * writing specific key values to two registers. The two key registers
420  * and the key values can be parsed from a "ti,dscr-kick-regs"
421  * propety with the following layout:
422  *
423  *	ti,dscr-kick-regs = <kickreg0 key0 kickreg1 key1>
424  *
425  * kickreg is the offset of the "kick" register
426  * key is the value which unlocks writing for protected regs
427  */
dscr_parse_kick_regs(struct device_node * node,void __iomem * base)428 static void __init dscr_parse_kick_regs(struct device_node *node,
429 					void __iomem *base)
430 {
431 	u32 vals[4];
432 	int err;
433 
434 	err = of_property_read_u32_array(node, "ti,dscr-kick-regs", vals, 4);
435 	if (!err) {
436 		dscr.kick_reg[0] = vals[0];
437 		dscr.kick_key[0] = vals[1];
438 		dscr.kick_reg[1] = vals[2];
439 		dscr.kick_key[1] = vals[3];
440 	}
441 }
442 
443 
444 /*
445  * SoCs may provide controls to enable/disable individual IP blocks. These
446  * controls in the DSCR usually control pin drivers but also may control
447  * clocking and or resets. The device tree is used to describe the bitfields
448  * in registers used to control device state. The number of bits and their
449  * values may vary even within the same register.
450  *
451  * The layout of these bitfields is described by the ti,dscr-devstate-ctl-regs
452  * property. This property is a list where each element describes a contiguous
453  * range of control fields with like properties. Each element of the list
454  * consists of 7 cells with the following values:
455  *
456  *   start_id num_ids reg enable disable start_bit nbits
457  *
458  * start_id is device id for the first device control in the range
459  * num_ids is the number of device controls in the range
460  * reg is the offset of the register holding the control bits
461  * enable is the value to enable a device
462  * disable is the value to disable a device (0xffffffff if cannot disable)
463  * start_bit is the bit number of the first bit in the range
464  * nbits is the number of bits per device control
465  */
dscr_parse_devstate_ctl_regs(struct device_node * node,void __iomem * base)466 static void __init dscr_parse_devstate_ctl_regs(struct device_node *node,
467 						void __iomem *base)
468 {
469 	struct devstate_ctl_reg *r;
470 	const __be32 *p;
471 	int i, j, size;
472 
473 	p = of_get_property(node, "ti,dscr-devstate-ctl-regs", &size);
474 	if (p) {
475 		/* parse all the ranges we can handle */
476 		size /= (sizeof(*p) * 7);
477 		if (size > MAX_DEVCTL_REGS)
478 			size = MAX_DEVCTL_REGS;
479 
480 		for (i = 0; i < size; i++) {
481 			r = &dscr.devctl[i];
482 
483 			r->start_id = be32_to_cpup(p++);
484 			r->num_ids = be32_to_cpup(p++);
485 			r->reg = be32_to_cpup(p++);
486 			r->enable = be32_to_cpup(p++);
487 			r->disable = be32_to_cpup(p++);
488 			if (r->disable == 0xffffffff)
489 				r->enable_only = 1;
490 			r->shift = be32_to_cpup(p++);
491 			r->nbits = be32_to_cpup(p++);
492 
493 			for (j = r->start_id;
494 			     j < (r->start_id + r->num_ids);
495 			     j++)
496 				dscr.devstate_info[j].ctl = r;
497 		}
498 	}
499 }
500 
501 /*
502  * SoCs may provide status registers indicating the state (enabled/disabled) of
503  * devices on the SoC. The device tree is used to describe the bitfields in
504  * registers used to provide device status. The number of bits and their
505  * values used to provide status may vary even within the same register.
506  *
507  * The layout of these bitfields is described by the ti,dscr-devstate-stat-regs
508  * property. This property is a list where each element describes a contiguous
509  * range of status fields with like properties. Each element of the list
510  * consists of 7 cells with the following values:
511  *
512  *   start_id num_ids reg enable disable start_bit nbits
513  *
514  * start_id is device id for the first device status in the range
515  * num_ids is the number of devices covered by the range
516  * reg is the offset of the register holding the status bits
517  * enable is the value indicating device is enabled
518  * disable is the value indicating device is disabled
519  * start_bit is the bit number of the first bit in the range
520  * nbits is the number of bits per device status
521  */
dscr_parse_devstate_stat_regs(struct device_node * node,void __iomem * base)522 static void __init dscr_parse_devstate_stat_regs(struct device_node *node,
523 						 void __iomem *base)
524 {
525 	struct devstate_stat_reg *r;
526 	const __be32 *p;
527 	int i, j, size;
528 
529 	p = of_get_property(node, "ti,dscr-devstate-stat-regs", &size);
530 	if (p) {
531 		/* parse all the ranges we can handle */
532 		size /= (sizeof(*p) * 7);
533 		if (size > MAX_DEVSTAT_REGS)
534 			size = MAX_DEVSTAT_REGS;
535 
536 		for (i = 0; i < size; i++) {
537 			r = &dscr.devstat[i];
538 
539 			r->start_id = be32_to_cpup(p++);
540 			r->num_ids = be32_to_cpup(p++);
541 			r->reg = be32_to_cpup(p++);
542 			r->enable = be32_to_cpup(p++);
543 			r->disable = be32_to_cpup(p++);
544 			r->shift = be32_to_cpup(p++);
545 			r->nbits = be32_to_cpup(p++);
546 
547 			for (j = r->start_id;
548 			     j < (r->start_id + r->num_ids);
549 			     j++)
550 				dscr.devstate_info[j].stat = r;
551 		}
552 	}
553 }
554 
555 static struct of_device_id dscr_ids[] __initdata = {
556 	{ .compatible = "ti,c64x+dscr" },
557 	{}
558 };
559 
560 /*
561  * Probe for DSCR area.
562  *
563  * This has to be done early on in case timer or interrupt controller
564  * needs something. e.g. On C6455 SoC, timer must be enabled through
565  * DSCR before it is functional.
566  */
dscr_probe(void)567 void __init dscr_probe(void)
568 {
569 	struct device_node *node;
570 	void __iomem *base;
571 
572 	spin_lock_init(&dscr.lock);
573 
574 	node = of_find_matching_node(NULL, dscr_ids);
575 	if (!node)
576 		return;
577 
578 	base = of_iomap(node, 0);
579 	if (!base) {
580 		of_node_put(node);
581 		return;
582 	}
583 
584 	dscr.base = base;
585 
586 	dscr_parse_devstat(node, base);
587 	dscr_parse_silicon_rev(node, base);
588 	dscr_parse_mac_fuse(node, base);
589 	dscr_parse_rmii_resets(node, base);
590 	dscr_parse_locked_regs(node, base);
591 	dscr_parse_kick_regs(node, base);
592 	dscr_parse_devstate_ctl_regs(node, base);
593 	dscr_parse_devstate_stat_regs(node, base);
594 	dscr_parse_privperm(node, base);
595 }
596