1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2019 Mellanox Technologies. */
3
4 #include "dr_types.h"
5
6 enum dr_action_domain {
7 DR_ACTION_DOMAIN_NIC_INGRESS,
8 DR_ACTION_DOMAIN_NIC_EGRESS,
9 DR_ACTION_DOMAIN_FDB_INGRESS,
10 DR_ACTION_DOMAIN_FDB_EGRESS,
11 DR_ACTION_DOMAIN_MAX,
12 };
13
14 enum dr_action_valid_state {
15 DR_ACTION_STATE_ERR,
16 DR_ACTION_STATE_NO_ACTION,
17 DR_ACTION_STATE_REFORMAT,
18 DR_ACTION_STATE_MODIFY_HDR,
19 DR_ACTION_STATE_MODIFY_VLAN,
20 DR_ACTION_STATE_NON_TERM,
21 DR_ACTION_STATE_TERM,
22 DR_ACTION_STATE_MAX,
23 };
24
25 static const enum dr_action_valid_state
26 next_action_state[DR_ACTION_DOMAIN_MAX][DR_ACTION_STATE_MAX][DR_ACTION_TYP_MAX] = {
27 [DR_ACTION_DOMAIN_NIC_INGRESS] = {
28 [DR_ACTION_STATE_NO_ACTION] = {
29 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
30 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
31 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
32 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM,
33 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
34 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_REFORMAT,
35 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_REFORMAT,
36 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
37 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
38 },
39 [DR_ACTION_STATE_REFORMAT] = {
40 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
41 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
42 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
43 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_REFORMAT,
44 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_REFORMAT,
45 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
46 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
47 },
48 [DR_ACTION_STATE_MODIFY_HDR] = {
49 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
50 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
51 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
52 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_MODIFY_HDR,
53 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR,
54 },
55 [DR_ACTION_STATE_MODIFY_VLAN] = {
56 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
57 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
58 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
59 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_MODIFY_VLAN,
60 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_VLAN,
61 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
62 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
63 },
64 [DR_ACTION_STATE_NON_TERM] = {
65 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
66 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM,
67 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
68 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM,
69 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
70 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_REFORMAT,
71 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_REFORMAT,
72 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
73 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
74 },
75 [DR_ACTION_STATE_TERM] = {
76 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM,
77 },
78 },
79 [DR_ACTION_DOMAIN_NIC_EGRESS] = {
80 [DR_ACTION_STATE_NO_ACTION] = {
81 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
82 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
83 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
84 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT,
85 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT,
86 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
87 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
88 },
89 [DR_ACTION_STATE_REFORMAT] = {
90 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
91 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
92 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_REFORMAT,
93 },
94 [DR_ACTION_STATE_MODIFY_HDR] = {
95 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
96 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
97 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR,
98 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT,
99 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT,
100 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
101 },
102 [DR_ACTION_STATE_MODIFY_VLAN] = {
103 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
104 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
105 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_VLAN,
106 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
107 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT,
108 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT,
109 },
110 [DR_ACTION_STATE_NON_TERM] = {
111 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
112 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
113 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
114 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT,
115 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT,
116 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
117 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
118 },
119 [DR_ACTION_STATE_TERM] = {
120 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM,
121 },
122 },
123 [DR_ACTION_DOMAIN_FDB_INGRESS] = {
124 [DR_ACTION_STATE_NO_ACTION] = {
125 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
126 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
127 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
128 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_REFORMAT,
129 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_REFORMAT,
130 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
131 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
132 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
133 },
134 [DR_ACTION_STATE_REFORMAT] = {
135 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
136 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
137 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_REFORMAT,
138 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
139 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
140 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
141 },
142 [DR_ACTION_STATE_MODIFY_HDR] = {
143 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
144 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
145 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR,
146 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
147 },
148 [DR_ACTION_STATE_MODIFY_VLAN] = {
149 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
150 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
151 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
152 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_VLAN,
153 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
154 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
155 },
156 [DR_ACTION_STATE_NON_TERM] = {
157 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
158 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
159 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
160 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_REFORMAT,
161 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_REFORMAT,
162 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
163 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
164 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
165 },
166 [DR_ACTION_STATE_TERM] = {
167 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM,
168 },
169 },
170 [DR_ACTION_DOMAIN_FDB_EGRESS] = {
171 [DR_ACTION_STATE_NO_ACTION] = {
172 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
173 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
174 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
175 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
176 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT,
177 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT,
178 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
179 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
180 },
181 [DR_ACTION_STATE_REFORMAT] = {
182 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
183 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
184 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_REFORMAT,
185 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
186 },
187 [DR_ACTION_STATE_MODIFY_HDR] = {
188 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
189 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
190 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR,
191 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT,
192 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT,
193 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
194 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
195 },
196 [DR_ACTION_STATE_MODIFY_VLAN] = {
197 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
198 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
199 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
200 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_VLAN,
201 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT,
202 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT,
203 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
204 },
205 [DR_ACTION_STATE_NON_TERM] = {
206 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM,
207 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM,
208 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM,
209 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR,
210 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_REFORMAT,
211 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_REFORMAT,
212 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_MODIFY_VLAN,
213 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM,
214 },
215 [DR_ACTION_STATE_TERM] = {
216 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM,
217 },
218 },
219 };
220
221 struct dr_action_modify_field_conv {
222 u16 hw_field;
223 u8 start;
224 u8 end;
225 u8 l3_type;
226 u8 l4_type;
227 };
228
229 static const struct dr_action_modify_field_conv dr_action_conv_arr[] = {
230 [MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16] = {
231 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_1, .start = 16, .end = 47,
232 },
233 [MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0] = {
234 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_1, .start = 0, .end = 15,
235 },
236 [MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE] = {
237 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_2, .start = 32, .end = 47,
238 },
239 [MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16] = {
240 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_0, .start = 16, .end = 47,
241 },
242 [MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0] = {
243 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_0, .start = 0, .end = 15,
244 },
245 [MLX5_ACTION_IN_FIELD_OUT_IP_DSCP] = {
246 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_1, .start = 0, .end = 5,
247 },
248 [MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS] = {
249 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 48, .end = 56,
250 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_TCP,
251 },
252 [MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT] = {
253 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 0, .end = 15,
254 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_TCP,
255 },
256 [MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT] = {
257 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 16, .end = 31,
258 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_TCP,
259 },
260 [MLX5_ACTION_IN_FIELD_OUT_IP_TTL] = {
261 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_1, .start = 8, .end = 15,
262 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV4,
263 },
264 [MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT] = {
265 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_1, .start = 8, .end = 15,
266 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
267 },
268 [MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT] = {
269 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 0, .end = 15,
270 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_UDP,
271 },
272 [MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT] = {
273 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 16, .end = 31,
274 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_UDP,
275 },
276 [MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96] = {
277 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_3, .start = 32, .end = 63,
278 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
279 },
280 [MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64] = {
281 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_3, .start = 0, .end = 31,
282 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
283 },
284 [MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32] = {
285 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_4, .start = 32, .end = 63,
286 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
287 },
288 [MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0] = {
289 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_4, .start = 0, .end = 31,
290 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
291 },
292 [MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96] = {
293 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_0, .start = 32, .end = 63,
294 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
295 },
296 [MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64] = {
297 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_0, .start = 0, .end = 31,
298 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
299 },
300 [MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32] = {
301 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_2, .start = 32, .end = 63,
302 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
303 },
304 [MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0] = {
305 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_2, .start = 0, .end = 31,
306 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
307 },
308 [MLX5_ACTION_IN_FIELD_OUT_SIPV4] = {
309 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_0, .start = 0, .end = 31,
310 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV4,
311 },
312 [MLX5_ACTION_IN_FIELD_OUT_DIPV4] = {
313 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_0, .start = 32, .end = 63,
314 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV4,
315 },
316 [MLX5_ACTION_IN_FIELD_METADATA_REG_A] = {
317 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_METADATA, .start = 0, .end = 31,
318 },
319 [MLX5_ACTION_IN_FIELD_METADATA_REG_B] = {
320 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_METADATA, .start = 32, .end = 63,
321 },
322 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_0] = {
323 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_0, .start = 32, .end = 63,
324 },
325 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_1] = {
326 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_0, .start = 0, .end = 31,
327 },
328 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_2] = {
329 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_1, .start = 32, .end = 63,
330 },
331 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_3] = {
332 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_1, .start = 0, .end = 31,
333 },
334 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_4] = {
335 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_2, .start = 32, .end = 63,
336 },
337 [MLX5_ACTION_IN_FIELD_METADATA_REG_C_5] = {
338 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_2, .start = 0, .end = 31,
339 },
340 [MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM] = {
341 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_1, .start = 32, .end = 63,
342 },
343 [MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM] = {
344 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_1, .start = 0, .end = 31,
345 },
346 [MLX5_ACTION_IN_FIELD_OUT_FIRST_VID] = {
347 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_2, .start = 0, .end = 15,
348 },
349 };
350
351 #define MAX_VLANS 2
352 struct dr_action_vlan_info {
353 int count;
354 u32 headers[MAX_VLANS];
355 };
356
357 struct dr_action_apply_attr {
358 u32 modify_index;
359 u16 modify_actions;
360 u32 decap_index;
361 u16 decap_actions;
362 u8 decap_with_vlan:1;
363 u64 final_icm_addr;
364 u32 flow_tag;
365 u32 ctr_id;
366 u16 gvmi;
367 u16 hit_gvmi;
368 u32 reformat_id;
369 u32 reformat_size;
370 struct dr_action_vlan_info vlans;
371 };
372
373 static int
dr_action_reformat_to_action_type(enum mlx5dr_action_reformat_type reformat_type,enum mlx5dr_action_type * action_type)374 dr_action_reformat_to_action_type(enum mlx5dr_action_reformat_type reformat_type,
375 enum mlx5dr_action_type *action_type)
376 {
377 switch (reformat_type) {
378 case DR_ACTION_REFORMAT_TYP_TNL_L2_TO_L2:
379 *action_type = DR_ACTION_TYP_TNL_L2_TO_L2;
380 break;
381 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L2:
382 *action_type = DR_ACTION_TYP_L2_TO_TNL_L2;
383 break;
384 case DR_ACTION_REFORMAT_TYP_TNL_L3_TO_L2:
385 *action_type = DR_ACTION_TYP_TNL_L3_TO_L2;
386 break;
387 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L3:
388 *action_type = DR_ACTION_TYP_L2_TO_TNL_L3;
389 break;
390 default:
391 return -EINVAL;
392 }
393
394 return 0;
395 }
396
dr_actions_init_next_ste(u8 ** last_ste,u32 * added_stes,enum mlx5dr_ste_entry_type entry_type,u16 gvmi)397 static void dr_actions_init_next_ste(u8 **last_ste,
398 u32 *added_stes,
399 enum mlx5dr_ste_entry_type entry_type,
400 u16 gvmi)
401 {
402 (*added_stes)++;
403 *last_ste += DR_STE_SIZE;
404 mlx5dr_ste_init(*last_ste, MLX5DR_STE_LU_TYPE_DONT_CARE, entry_type, gvmi);
405 }
406
dr_actions_apply_tx(struct mlx5dr_domain * dmn,u8 * action_type_set,u8 * last_ste,struct dr_action_apply_attr * attr,u32 * added_stes)407 static void dr_actions_apply_tx(struct mlx5dr_domain *dmn,
408 u8 *action_type_set,
409 u8 *last_ste,
410 struct dr_action_apply_attr *attr,
411 u32 *added_stes)
412 {
413 bool encap = action_type_set[DR_ACTION_TYP_L2_TO_TNL_L2] ||
414 action_type_set[DR_ACTION_TYP_L2_TO_TNL_L3];
415
416 /* We want to make sure the modify header comes before L2
417 * encapsulation. The reason for that is that we support
418 * modify headers for outer headers only
419 */
420 if (action_type_set[DR_ACTION_TYP_MODIFY_HDR]) {
421 mlx5dr_ste_set_entry_type(last_ste, MLX5DR_STE_TYPE_MODIFY_PKT);
422 mlx5dr_ste_set_rewrite_actions(last_ste,
423 attr->modify_actions,
424 attr->modify_index);
425 }
426
427 if (action_type_set[DR_ACTION_TYP_PUSH_VLAN]) {
428 int i;
429
430 for (i = 0; i < attr->vlans.count; i++) {
431 if (i || action_type_set[DR_ACTION_TYP_MODIFY_HDR])
432 dr_actions_init_next_ste(&last_ste,
433 added_stes,
434 MLX5DR_STE_TYPE_TX,
435 attr->gvmi);
436
437 mlx5dr_ste_set_tx_push_vlan(last_ste,
438 attr->vlans.headers[i],
439 encap);
440 }
441 }
442
443 if (encap) {
444 /* Modify header and encapsulation require a different STEs.
445 * Since modify header STE format doesn't support encapsulation
446 * tunneling_action.
447 */
448 if (action_type_set[DR_ACTION_TYP_MODIFY_HDR] ||
449 action_type_set[DR_ACTION_TYP_PUSH_VLAN])
450 dr_actions_init_next_ste(&last_ste,
451 added_stes,
452 MLX5DR_STE_TYPE_TX,
453 attr->gvmi);
454
455 mlx5dr_ste_set_tx_encap(last_ste,
456 attr->reformat_id,
457 attr->reformat_size,
458 action_type_set[DR_ACTION_TYP_L2_TO_TNL_L3]);
459 /* Whenever prio_tag_required enabled, we can be sure that the
460 * previous table (ACL) already push vlan to our packet,
461 * And due to HW limitation we need to set this bit, otherwise
462 * push vlan + reformat will not work.
463 */
464 if (MLX5_CAP_GEN(dmn->mdev, prio_tag_required))
465 mlx5dr_ste_set_go_back_bit(last_ste);
466 }
467
468 if (action_type_set[DR_ACTION_TYP_CTR])
469 mlx5dr_ste_set_counter_id(last_ste, attr->ctr_id);
470 }
471
dr_actions_apply_rx(u8 * action_type_set,u8 * last_ste,struct dr_action_apply_attr * attr,u32 * added_stes)472 static void dr_actions_apply_rx(u8 *action_type_set,
473 u8 *last_ste,
474 struct dr_action_apply_attr *attr,
475 u32 *added_stes)
476 {
477 if (action_type_set[DR_ACTION_TYP_CTR])
478 mlx5dr_ste_set_counter_id(last_ste, attr->ctr_id);
479
480 if (action_type_set[DR_ACTION_TYP_TNL_L3_TO_L2]) {
481 mlx5dr_ste_set_entry_type(last_ste, MLX5DR_STE_TYPE_MODIFY_PKT);
482 mlx5dr_ste_set_rx_decap_l3(last_ste, attr->decap_with_vlan);
483 mlx5dr_ste_set_rewrite_actions(last_ste,
484 attr->decap_actions,
485 attr->decap_index);
486 }
487
488 if (action_type_set[DR_ACTION_TYP_TNL_L2_TO_L2])
489 mlx5dr_ste_set_rx_decap(last_ste);
490
491 if (action_type_set[DR_ACTION_TYP_POP_VLAN]) {
492 int i;
493
494 for (i = 0; i < attr->vlans.count; i++) {
495 if (i ||
496 action_type_set[DR_ACTION_TYP_TNL_L2_TO_L2] ||
497 action_type_set[DR_ACTION_TYP_TNL_L3_TO_L2])
498 dr_actions_init_next_ste(&last_ste,
499 added_stes,
500 MLX5DR_STE_TYPE_RX,
501 attr->gvmi);
502
503 mlx5dr_ste_set_rx_pop_vlan(last_ste);
504 }
505 }
506
507 if (action_type_set[DR_ACTION_TYP_MODIFY_HDR]) {
508 if (mlx5dr_ste_get_entry_type(last_ste) == MLX5DR_STE_TYPE_MODIFY_PKT)
509 dr_actions_init_next_ste(&last_ste,
510 added_stes,
511 MLX5DR_STE_TYPE_MODIFY_PKT,
512 attr->gvmi);
513 else
514 mlx5dr_ste_set_entry_type(last_ste, MLX5DR_STE_TYPE_MODIFY_PKT);
515
516 mlx5dr_ste_set_rewrite_actions(last_ste,
517 attr->modify_actions,
518 attr->modify_index);
519 }
520
521 if (action_type_set[DR_ACTION_TYP_TAG]) {
522 if (mlx5dr_ste_get_entry_type(last_ste) == MLX5DR_STE_TYPE_MODIFY_PKT)
523 dr_actions_init_next_ste(&last_ste,
524 added_stes,
525 MLX5DR_STE_TYPE_RX,
526 attr->gvmi);
527
528 mlx5dr_ste_rx_set_flow_tag(last_ste, attr->flow_tag);
529 }
530 }
531
532 /* Apply the actions on the rule STE array starting from the last_ste.
533 * Actions might require more than one STE, new_num_stes will return
534 * the new size of the STEs array, rule with actions.
535 */
dr_actions_apply(struct mlx5dr_domain * dmn,enum mlx5dr_ste_entry_type ste_type,u8 * action_type_set,u8 * last_ste,struct dr_action_apply_attr * attr,u32 * new_num_stes)536 static void dr_actions_apply(struct mlx5dr_domain *dmn,
537 enum mlx5dr_ste_entry_type ste_type,
538 u8 *action_type_set,
539 u8 *last_ste,
540 struct dr_action_apply_attr *attr,
541 u32 *new_num_stes)
542 {
543 u32 added_stes = 0;
544
545 if (ste_type == MLX5DR_STE_TYPE_RX)
546 dr_actions_apply_rx(action_type_set, last_ste, attr, &added_stes);
547 else
548 dr_actions_apply_tx(dmn, action_type_set, last_ste, attr, &added_stes);
549
550 last_ste += added_stes * DR_STE_SIZE;
551 *new_num_stes += added_stes;
552
553 mlx5dr_ste_set_hit_gvmi(last_ste, attr->hit_gvmi);
554 mlx5dr_ste_set_hit_addr(last_ste, attr->final_icm_addr, 1);
555 }
556
557 static enum dr_action_domain
dr_action_get_action_domain(enum mlx5dr_domain_type domain,enum mlx5dr_ste_entry_type ste_type)558 dr_action_get_action_domain(enum mlx5dr_domain_type domain,
559 enum mlx5dr_ste_entry_type ste_type)
560 {
561 switch (domain) {
562 case MLX5DR_DOMAIN_TYPE_NIC_RX:
563 return DR_ACTION_DOMAIN_NIC_INGRESS;
564 case MLX5DR_DOMAIN_TYPE_NIC_TX:
565 return DR_ACTION_DOMAIN_NIC_EGRESS;
566 case MLX5DR_DOMAIN_TYPE_FDB:
567 if (ste_type == MLX5DR_STE_TYPE_RX)
568 return DR_ACTION_DOMAIN_FDB_INGRESS;
569 return DR_ACTION_DOMAIN_FDB_EGRESS;
570 default:
571 WARN_ON(true);
572 return DR_ACTION_DOMAIN_MAX;
573 }
574 }
575
576 static
dr_action_validate_and_get_next_state(enum dr_action_domain action_domain,u32 action_type,u32 * state)577 int dr_action_validate_and_get_next_state(enum dr_action_domain action_domain,
578 u32 action_type,
579 u32 *state)
580 {
581 u32 cur_state = *state;
582
583 /* Check action state machine is valid */
584 *state = next_action_state[action_domain][cur_state][action_type];
585
586 if (*state == DR_ACTION_STATE_ERR)
587 return -EOPNOTSUPP;
588
589 return 0;
590 }
591
dr_action_handle_cs_recalc(struct mlx5dr_domain * dmn,struct mlx5dr_action * dest_action,u64 * final_icm_addr)592 static int dr_action_handle_cs_recalc(struct mlx5dr_domain *dmn,
593 struct mlx5dr_action *dest_action,
594 u64 *final_icm_addr)
595 {
596 int ret;
597
598 switch (dest_action->action_type) {
599 case DR_ACTION_TYP_FT:
600 /* Allow destination flow table only if table is a terminating
601 * table, since there is an *assumption* that in such case FW
602 * will recalculate the CS.
603 */
604 if (dest_action->dest_tbl.is_fw_tbl) {
605 *final_icm_addr = dest_action->dest_tbl.fw_tbl.rx_icm_addr;
606 } else {
607 mlx5dr_dbg(dmn,
608 "Destination FT should be terminating when modify TTL is used\n");
609 return -EINVAL;
610 }
611 break;
612
613 case DR_ACTION_TYP_VPORT:
614 /* If destination is vport we will get the FW flow table
615 * that recalculates the CS and forwards to the vport.
616 */
617 ret = mlx5dr_domain_cache_get_recalc_cs_ft_addr(dest_action->vport.dmn,
618 dest_action->vport.caps->num,
619 final_icm_addr);
620 if (ret) {
621 mlx5dr_err(dmn, "Failed to get FW cs recalc flow table\n");
622 return ret;
623 }
624 break;
625
626 default:
627 break;
628 }
629
630 return 0;
631 }
632
633 #define WITH_VLAN_NUM_HW_ACTIONS 6
634
mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher * matcher,struct mlx5dr_matcher_rx_tx * nic_matcher,struct mlx5dr_action * actions[],u32 num_actions,u8 * ste_arr,u32 * new_hw_ste_arr_sz)635 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher,
636 struct mlx5dr_matcher_rx_tx *nic_matcher,
637 struct mlx5dr_action *actions[],
638 u32 num_actions,
639 u8 *ste_arr,
640 u32 *new_hw_ste_arr_sz)
641 {
642 struct mlx5dr_domain_rx_tx *nic_dmn = nic_matcher->nic_tbl->nic_dmn;
643 bool rx_rule = nic_dmn->ste_type == MLX5DR_STE_TYPE_RX;
644 struct mlx5dr_domain *dmn = matcher->tbl->dmn;
645 u8 action_type_set[DR_ACTION_TYP_MAX] = {};
646 struct mlx5dr_action *dest_action = NULL;
647 u32 state = DR_ACTION_STATE_NO_ACTION;
648 struct dr_action_apply_attr attr = {};
649 enum dr_action_domain action_domain;
650 bool recalc_cs_required = false;
651 u8 *last_ste;
652 int i, ret;
653
654 attr.gvmi = dmn->info.caps.gvmi;
655 attr.hit_gvmi = dmn->info.caps.gvmi;
656 attr.final_icm_addr = nic_dmn->default_icm_addr;
657 action_domain = dr_action_get_action_domain(dmn->type, nic_dmn->ste_type);
658
659 for (i = 0; i < num_actions; i++) {
660 struct mlx5dr_action *action;
661 int max_actions_type = 1;
662 u32 action_type;
663
664 action = actions[i];
665 action_type = action->action_type;
666
667 switch (action_type) {
668 case DR_ACTION_TYP_DROP:
669 attr.final_icm_addr = nic_dmn->drop_icm_addr;
670 attr.hit_gvmi = nic_dmn->drop_icm_addr >> 48;
671 break;
672 case DR_ACTION_TYP_FT:
673 dest_action = action;
674 if (!action->dest_tbl.is_fw_tbl) {
675 if (action->dest_tbl.tbl->dmn != dmn) {
676 mlx5dr_err(dmn,
677 "Destination table belongs to a different domain\n");
678 goto out_invalid_arg;
679 }
680 if (action->dest_tbl.tbl->level <= matcher->tbl->level) {
681 mlx5_core_warn_once(dmn->mdev,
682 "Connecting table to a lower/same level destination table\n");
683 mlx5dr_dbg(dmn,
684 "Connecting table at level %d to a destination table at level %d\n",
685 matcher->tbl->level,
686 action->dest_tbl.tbl->level);
687 }
688 attr.final_icm_addr = rx_rule ?
689 action->dest_tbl.tbl->rx.s_anchor->chunk->icm_addr :
690 action->dest_tbl.tbl->tx.s_anchor->chunk->icm_addr;
691 } else {
692 struct mlx5dr_cmd_query_flow_table_details output;
693 int ret;
694
695 /* get the relevant addresses */
696 if (!action->dest_tbl.fw_tbl.rx_icm_addr) {
697 ret = mlx5dr_cmd_query_flow_table(dmn->mdev,
698 action->dest_tbl.fw_tbl.type,
699 action->dest_tbl.fw_tbl.id,
700 &output);
701 if (!ret) {
702 action->dest_tbl.fw_tbl.tx_icm_addr =
703 output.sw_owner_icm_root_1;
704 action->dest_tbl.fw_tbl.rx_icm_addr =
705 output.sw_owner_icm_root_0;
706 } else {
707 mlx5dr_err(dmn,
708 "Failed mlx5_cmd_query_flow_table ret: %d\n",
709 ret);
710 return ret;
711 }
712 }
713 attr.final_icm_addr = rx_rule ?
714 action->dest_tbl.fw_tbl.rx_icm_addr :
715 action->dest_tbl.fw_tbl.tx_icm_addr;
716 }
717 break;
718 case DR_ACTION_TYP_QP:
719 mlx5dr_info(dmn, "Domain doesn't support QP\n");
720 goto out_invalid_arg;
721 case DR_ACTION_TYP_CTR:
722 attr.ctr_id = action->ctr.ctr_id +
723 action->ctr.offeset;
724 break;
725 case DR_ACTION_TYP_TAG:
726 attr.flow_tag = action->flow_tag;
727 break;
728 case DR_ACTION_TYP_TNL_L2_TO_L2:
729 break;
730 case DR_ACTION_TYP_TNL_L3_TO_L2:
731 attr.decap_index = action->rewrite.index;
732 attr.decap_actions = action->rewrite.num_of_actions;
733 attr.decap_with_vlan =
734 attr.decap_actions == WITH_VLAN_NUM_HW_ACTIONS;
735 break;
736 case DR_ACTION_TYP_MODIFY_HDR:
737 attr.modify_index = action->rewrite.index;
738 attr.modify_actions = action->rewrite.num_of_actions;
739 recalc_cs_required = action->rewrite.modify_ttl;
740 break;
741 case DR_ACTION_TYP_L2_TO_TNL_L2:
742 case DR_ACTION_TYP_L2_TO_TNL_L3:
743 attr.reformat_size = action->reformat.reformat_size;
744 attr.reformat_id = action->reformat.reformat_id;
745 break;
746 case DR_ACTION_TYP_VPORT:
747 attr.hit_gvmi = action->vport.caps->vhca_gvmi;
748 dest_action = action;
749 if (rx_rule) {
750 /* Loopback on WIRE vport is not supported */
751 if (action->vport.caps->num == WIRE_PORT)
752 goto out_invalid_arg;
753
754 attr.final_icm_addr = action->vport.caps->icm_address_rx;
755 } else {
756 attr.final_icm_addr = action->vport.caps->icm_address_tx;
757 }
758 break;
759 case DR_ACTION_TYP_POP_VLAN:
760 max_actions_type = MAX_VLANS;
761 attr.vlans.count++;
762 break;
763 case DR_ACTION_TYP_PUSH_VLAN:
764 max_actions_type = MAX_VLANS;
765 if (attr.vlans.count == MAX_VLANS)
766 return -EINVAL;
767
768 attr.vlans.headers[attr.vlans.count++] = action->push_vlan.vlan_hdr;
769 break;
770 default:
771 goto out_invalid_arg;
772 }
773
774 /* Check action duplication */
775 if (++action_type_set[action_type] > max_actions_type) {
776 mlx5dr_err(dmn, "Action type %d supports only max %d time(s)\n",
777 action_type, max_actions_type);
778 goto out_invalid_arg;
779 }
780
781 /* Check action state machine is valid */
782 if (dr_action_validate_and_get_next_state(action_domain,
783 action_type,
784 &state)) {
785 mlx5dr_err(dmn, "Invalid action sequence provided\n");
786 return -EOPNOTSUPP;
787 }
788 }
789
790 *new_hw_ste_arr_sz = nic_matcher->num_of_builders;
791 last_ste = ste_arr + DR_STE_SIZE * (nic_matcher->num_of_builders - 1);
792
793 /* Due to a HW bug, modifying TTL on RX flows will cause an incorrect
794 * checksum calculation. In this case we will use a FW table to
795 * recalculate.
796 */
797 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB &&
798 rx_rule && recalc_cs_required && dest_action) {
799 ret = dr_action_handle_cs_recalc(dmn, dest_action, &attr.final_icm_addr);
800 if (ret) {
801 mlx5dr_err(dmn,
802 "Failed to handle checksum recalculation err %d\n",
803 ret);
804 return ret;
805 }
806 }
807
808 dr_actions_apply(dmn,
809 nic_dmn->ste_type,
810 action_type_set,
811 last_ste,
812 &attr,
813 new_hw_ste_arr_sz);
814
815 return 0;
816
817 out_invalid_arg:
818 return -EINVAL;
819 }
820
821 #define CVLAN_ETHERTYPE 0x8100
822 #define SVLAN_ETHERTYPE 0x88a8
823 #define HDR_LEN_L2_ONLY 14
824 #define HDR_LEN_L2_VLAN 18
825 #define REWRITE_HW_ACTION_NUM 6
826
dr_actions_l2_rewrite(struct mlx5dr_domain * dmn,struct mlx5dr_action * action,void * data,size_t data_sz)827 static int dr_actions_l2_rewrite(struct mlx5dr_domain *dmn,
828 struct mlx5dr_action *action,
829 void *data, size_t data_sz)
830 {
831 struct mlx5_ifc_l2_hdr_bits *l2_hdr = data;
832 u64 ops[REWRITE_HW_ACTION_NUM] = {};
833 u32 hdr_fld_4b;
834 u16 hdr_fld_2b;
835 u16 vlan_type;
836 bool vlan;
837 int i = 0;
838 int ret;
839
840 vlan = (data_sz != HDR_LEN_L2_ONLY);
841
842 /* dmac_47_16 */
843 MLX5_SET(dr_action_hw_set, ops + i,
844 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
845 MLX5_SET(dr_action_hw_set, ops + i,
846 destination_length, 0);
847 MLX5_SET(dr_action_hw_set, ops + i,
848 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_0);
849 MLX5_SET(dr_action_hw_set, ops + i,
850 destination_left_shifter, 16);
851 hdr_fld_4b = MLX5_GET(l2_hdr, l2_hdr, dmac_47_16);
852 MLX5_SET(dr_action_hw_set, ops + i,
853 inline_data, hdr_fld_4b);
854 i++;
855
856 /* smac_47_16 */
857 MLX5_SET(dr_action_hw_set, ops + i,
858 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
859 MLX5_SET(dr_action_hw_set, ops + i,
860 destination_length, 0);
861 MLX5_SET(dr_action_hw_set, ops + i,
862 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_1);
863 MLX5_SET(dr_action_hw_set, ops + i,
864 destination_left_shifter, 16);
865 hdr_fld_4b = (MLX5_GET(l2_hdr, l2_hdr, smac_31_0) >> 16 |
866 MLX5_GET(l2_hdr, l2_hdr, smac_47_32) << 16);
867 MLX5_SET(dr_action_hw_set, ops + i,
868 inline_data, hdr_fld_4b);
869 i++;
870
871 /* dmac_15_0 */
872 MLX5_SET(dr_action_hw_set, ops + i,
873 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
874 MLX5_SET(dr_action_hw_set, ops + i,
875 destination_length, 16);
876 MLX5_SET(dr_action_hw_set, ops + i,
877 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_0);
878 MLX5_SET(dr_action_hw_set, ops + i,
879 destination_left_shifter, 0);
880 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, dmac_15_0);
881 MLX5_SET(dr_action_hw_set, ops + i,
882 inline_data, hdr_fld_2b);
883 i++;
884
885 /* ethertype + (optional) vlan */
886 MLX5_SET(dr_action_hw_set, ops + i,
887 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
888 MLX5_SET(dr_action_hw_set, ops + i,
889 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_2);
890 MLX5_SET(dr_action_hw_set, ops + i,
891 destination_left_shifter, 32);
892 if (!vlan) {
893 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, ethertype);
894 MLX5_SET(dr_action_hw_set, ops + i, inline_data, hdr_fld_2b);
895 MLX5_SET(dr_action_hw_set, ops + i, destination_length, 16);
896 } else {
897 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, ethertype);
898 vlan_type = hdr_fld_2b == SVLAN_ETHERTYPE ? DR_STE_SVLAN : DR_STE_CVLAN;
899 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, vlan);
900 hdr_fld_4b = (vlan_type << 16) | hdr_fld_2b;
901 MLX5_SET(dr_action_hw_set, ops + i, inline_data, hdr_fld_4b);
902 MLX5_SET(dr_action_hw_set, ops + i, destination_length, 18);
903 }
904 i++;
905
906 /* smac_15_0 */
907 MLX5_SET(dr_action_hw_set, ops + i,
908 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
909 MLX5_SET(dr_action_hw_set, ops + i,
910 destination_length, 16);
911 MLX5_SET(dr_action_hw_set, ops + i,
912 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_1);
913 MLX5_SET(dr_action_hw_set, ops + i,
914 destination_left_shifter, 0);
915 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, smac_31_0);
916 MLX5_SET(dr_action_hw_set, ops + i,
917 inline_data, hdr_fld_2b);
918 i++;
919
920 if (vlan) {
921 MLX5_SET(dr_action_hw_set, ops + i,
922 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
923 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, vlan_type);
924 MLX5_SET(dr_action_hw_set, ops + i,
925 inline_data, hdr_fld_2b);
926 MLX5_SET(dr_action_hw_set, ops + i,
927 destination_length, 16);
928 MLX5_SET(dr_action_hw_set, ops + i,
929 destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_2);
930 MLX5_SET(dr_action_hw_set, ops + i,
931 destination_left_shifter, 0);
932 i++;
933 }
934
935 action->rewrite.data = (void *)ops;
936 action->rewrite.num_of_actions = i;
937
938 ret = mlx5dr_send_postsend_action(dmn, action);
939 if (ret) {
940 mlx5dr_dbg(dmn, "Writing encapsulation action to ICM failed\n");
941 return ret;
942 }
943
944 return 0;
945 }
946
947 static struct mlx5dr_action *
dr_action_create_generic(enum mlx5dr_action_type action_type)948 dr_action_create_generic(enum mlx5dr_action_type action_type)
949 {
950 struct mlx5dr_action *action;
951
952 action = kzalloc(sizeof(*action), GFP_KERNEL);
953 if (!action)
954 return NULL;
955
956 action->action_type = action_type;
957 refcount_set(&action->refcount, 1);
958
959 return action;
960 }
961
mlx5dr_action_create_drop(void)962 struct mlx5dr_action *mlx5dr_action_create_drop(void)
963 {
964 return dr_action_create_generic(DR_ACTION_TYP_DROP);
965 }
966
967 struct mlx5dr_action *
mlx5dr_action_create_dest_table_num(struct mlx5dr_domain * dmn,u32 table_num)968 mlx5dr_action_create_dest_table_num(struct mlx5dr_domain *dmn, u32 table_num)
969 {
970 struct mlx5dr_action *action;
971
972 action = dr_action_create_generic(DR_ACTION_TYP_FT);
973 if (!action)
974 return NULL;
975
976 action->dest_tbl.is_fw_tbl = true;
977 action->dest_tbl.fw_tbl.dmn = dmn;
978 action->dest_tbl.fw_tbl.id = table_num;
979 action->dest_tbl.fw_tbl.type = FS_FT_FDB;
980 refcount_inc(&dmn->refcount);
981
982 return action;
983 }
984
985 struct mlx5dr_action *
mlx5dr_action_create_dest_table(struct mlx5dr_table * tbl)986 mlx5dr_action_create_dest_table(struct mlx5dr_table *tbl)
987 {
988 struct mlx5dr_action *action;
989
990 refcount_inc(&tbl->refcount);
991
992 action = dr_action_create_generic(DR_ACTION_TYP_FT);
993 if (!action)
994 goto dec_ref;
995
996 action->dest_tbl.tbl = tbl;
997
998 return action;
999
1000 dec_ref:
1001 refcount_dec(&tbl->refcount);
1002 return NULL;
1003 }
1004
1005 struct mlx5dr_action *
mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain * dmn,struct mlx5dr_action_dest * dests,u32 num_of_dests)1006 mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain *dmn,
1007 struct mlx5dr_action_dest *dests,
1008 u32 num_of_dests)
1009 {
1010 struct mlx5dr_cmd_flow_destination_hw_info *hw_dests;
1011 struct mlx5dr_action **ref_actions;
1012 struct mlx5dr_action *action;
1013 bool reformat_req = false;
1014 u32 num_of_ref = 0;
1015 int ret;
1016 int i;
1017
1018 if (dmn->type != MLX5DR_DOMAIN_TYPE_FDB) {
1019 mlx5dr_err(dmn, "Multiple destination support is for FDB only\n");
1020 return NULL;
1021 }
1022
1023 hw_dests = kzalloc(sizeof(*hw_dests) * num_of_dests, GFP_KERNEL);
1024 if (!hw_dests)
1025 return NULL;
1026
1027 ref_actions = kzalloc(sizeof(*ref_actions) * num_of_dests * 2, GFP_KERNEL);
1028 if (!ref_actions)
1029 goto free_hw_dests;
1030
1031 for (i = 0; i < num_of_dests; i++) {
1032 struct mlx5dr_action *reformat_action = dests[i].reformat;
1033 struct mlx5dr_action *dest_action = dests[i].dest;
1034
1035 ref_actions[num_of_ref++] = dest_action;
1036
1037 switch (dest_action->action_type) {
1038 case DR_ACTION_TYP_VPORT:
1039 hw_dests[i].vport.flags = MLX5_FLOW_DEST_VPORT_VHCA_ID;
1040 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1041 hw_dests[i].vport.num = dest_action->vport.caps->num;
1042 hw_dests[i].vport.vhca_id = dest_action->vport.caps->vhca_gvmi;
1043 if (reformat_action) {
1044 reformat_req = true;
1045 hw_dests[i].vport.reformat_id =
1046 reformat_action->reformat.reformat_id;
1047 ref_actions[num_of_ref++] = reformat_action;
1048 hw_dests[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
1049 }
1050 break;
1051
1052 case DR_ACTION_TYP_FT:
1053 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1054 if (dest_action->dest_tbl.is_fw_tbl)
1055 hw_dests[i].ft_id = dest_action->dest_tbl.fw_tbl.id;
1056 else
1057 hw_dests[i].ft_id = dest_action->dest_tbl.tbl->table_id;
1058 break;
1059
1060 default:
1061 mlx5dr_dbg(dmn, "Invalid multiple destinations action\n");
1062 goto free_ref_actions;
1063 }
1064 }
1065
1066 action = dr_action_create_generic(DR_ACTION_TYP_FT);
1067 if (!action)
1068 goto free_ref_actions;
1069
1070 ret = mlx5dr_fw_create_md_tbl(dmn,
1071 hw_dests,
1072 num_of_dests,
1073 reformat_req,
1074 &action->dest_tbl.fw_tbl.id,
1075 &action->dest_tbl.fw_tbl.group_id);
1076 if (ret)
1077 goto free_action;
1078
1079 refcount_inc(&dmn->refcount);
1080
1081 for (i = 0; i < num_of_ref; i++)
1082 refcount_inc(&ref_actions[i]->refcount);
1083
1084 action->dest_tbl.is_fw_tbl = true;
1085 action->dest_tbl.fw_tbl.dmn = dmn;
1086 action->dest_tbl.fw_tbl.type = FS_FT_FDB;
1087 action->dest_tbl.fw_tbl.ref_actions = ref_actions;
1088 action->dest_tbl.fw_tbl.num_of_ref_actions = num_of_ref;
1089
1090 kfree(hw_dests);
1091
1092 return action;
1093
1094 free_action:
1095 kfree(action);
1096 free_ref_actions:
1097 kfree(ref_actions);
1098 free_hw_dests:
1099 kfree(hw_dests);
1100 return NULL;
1101 }
1102
1103 struct mlx5dr_action *
mlx5dr_action_create_dest_flow_fw_table(struct mlx5dr_domain * dmn,struct mlx5_flow_table * ft)1104 mlx5dr_action_create_dest_flow_fw_table(struct mlx5dr_domain *dmn,
1105 struct mlx5_flow_table *ft)
1106 {
1107 struct mlx5dr_action *action;
1108
1109 action = dr_action_create_generic(DR_ACTION_TYP_FT);
1110 if (!action)
1111 return NULL;
1112
1113 action->dest_tbl.is_fw_tbl = 1;
1114 action->dest_tbl.fw_tbl.type = ft->type;
1115 action->dest_tbl.fw_tbl.id = ft->id;
1116 action->dest_tbl.fw_tbl.dmn = dmn;
1117
1118 refcount_inc(&dmn->refcount);
1119
1120 return action;
1121 }
1122
1123 struct mlx5dr_action *
mlx5dr_action_create_flow_counter(u32 counter_id)1124 mlx5dr_action_create_flow_counter(u32 counter_id)
1125 {
1126 struct mlx5dr_action *action;
1127
1128 action = dr_action_create_generic(DR_ACTION_TYP_CTR);
1129 if (!action)
1130 return NULL;
1131
1132 action->ctr.ctr_id = counter_id;
1133
1134 return action;
1135 }
1136
mlx5dr_action_create_tag(u32 tag_value)1137 struct mlx5dr_action *mlx5dr_action_create_tag(u32 tag_value)
1138 {
1139 struct mlx5dr_action *action;
1140
1141 action = dr_action_create_generic(DR_ACTION_TYP_TAG);
1142 if (!action)
1143 return NULL;
1144
1145 action->flow_tag = tag_value & 0xffffff;
1146
1147 return action;
1148 }
1149
1150 static int
dr_action_verify_reformat_params(enum mlx5dr_action_type reformat_type,struct mlx5dr_domain * dmn,size_t data_sz,void * data)1151 dr_action_verify_reformat_params(enum mlx5dr_action_type reformat_type,
1152 struct mlx5dr_domain *dmn,
1153 size_t data_sz,
1154 void *data)
1155 {
1156 if ((!data && data_sz) || (data && !data_sz) || reformat_type >
1157 DR_ACTION_TYP_L2_TO_TNL_L3) {
1158 mlx5dr_dbg(dmn, "Invalid reformat parameter!\n");
1159 goto out_err;
1160 }
1161
1162 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB)
1163 return 0;
1164
1165 if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_RX) {
1166 if (reformat_type != DR_ACTION_TYP_TNL_L2_TO_L2 &&
1167 reformat_type != DR_ACTION_TYP_TNL_L3_TO_L2) {
1168 mlx5dr_dbg(dmn, "Action reformat type not support on RX domain\n");
1169 goto out_err;
1170 }
1171 } else if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_TX) {
1172 if (reformat_type != DR_ACTION_TYP_L2_TO_TNL_L2 &&
1173 reformat_type != DR_ACTION_TYP_L2_TO_TNL_L3) {
1174 mlx5dr_dbg(dmn, "Action reformat type not support on TX domain\n");
1175 goto out_err;
1176 }
1177 }
1178
1179 return 0;
1180
1181 out_err:
1182 return -EINVAL;
1183 }
1184
1185 #define ACTION_CACHE_LINE_SIZE 64
1186
1187 static int
dr_action_create_reformat_action(struct mlx5dr_domain * dmn,size_t data_sz,void * data,struct mlx5dr_action * action)1188 dr_action_create_reformat_action(struct mlx5dr_domain *dmn,
1189 size_t data_sz, void *data,
1190 struct mlx5dr_action *action)
1191 {
1192 u32 reformat_id;
1193 int ret;
1194
1195 switch (action->action_type) {
1196 case DR_ACTION_TYP_L2_TO_TNL_L2:
1197 case DR_ACTION_TYP_L2_TO_TNL_L3:
1198 {
1199 enum mlx5_reformat_ctx_type rt;
1200
1201 if (action->action_type == DR_ACTION_TYP_L2_TO_TNL_L2)
1202 rt = MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL;
1203 else
1204 rt = MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
1205
1206 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev, rt, data_sz, data,
1207 &reformat_id);
1208 if (ret)
1209 return ret;
1210
1211 action->reformat.reformat_id = reformat_id;
1212 action->reformat.reformat_size = data_sz;
1213 return 0;
1214 }
1215 case DR_ACTION_TYP_TNL_L2_TO_L2:
1216 {
1217 return 0;
1218 }
1219 case DR_ACTION_TYP_TNL_L3_TO_L2:
1220 {
1221 /* Only Ethernet frame is supported, with VLAN (18) or without (14) */
1222 if (data_sz != HDR_LEN_L2_ONLY && data_sz != HDR_LEN_L2_VLAN)
1223 return -EINVAL;
1224
1225 action->rewrite.chunk = mlx5dr_icm_alloc_chunk(dmn->action_icm_pool,
1226 DR_CHUNK_SIZE_8);
1227 if (!action->rewrite.chunk)
1228 return -ENOMEM;
1229
1230 action->rewrite.index = (action->rewrite.chunk->icm_addr -
1231 dmn->info.caps.hdr_modify_icm_addr) /
1232 ACTION_CACHE_LINE_SIZE;
1233
1234 ret = dr_actions_l2_rewrite(dmn, action, data, data_sz);
1235 if (ret) {
1236 mlx5dr_icm_free_chunk(action->rewrite.chunk);
1237 return ret;
1238 }
1239 return 0;
1240 }
1241 default:
1242 mlx5dr_info(dmn, "Reformat type is not supported %d\n", action->action_type);
1243 return -EINVAL;
1244 }
1245 }
1246
mlx5dr_action_create_pop_vlan(void)1247 struct mlx5dr_action *mlx5dr_action_create_pop_vlan(void)
1248 {
1249 return dr_action_create_generic(DR_ACTION_TYP_POP_VLAN);
1250 }
1251
mlx5dr_action_create_push_vlan(struct mlx5dr_domain * dmn,__be32 vlan_hdr)1252 struct mlx5dr_action *mlx5dr_action_create_push_vlan(struct mlx5dr_domain *dmn,
1253 __be32 vlan_hdr)
1254 {
1255 u32 vlan_hdr_h = ntohl(vlan_hdr);
1256 u16 ethertype = vlan_hdr_h >> 16;
1257 struct mlx5dr_action *action;
1258
1259 if (ethertype != SVLAN_ETHERTYPE && ethertype != CVLAN_ETHERTYPE) {
1260 mlx5dr_dbg(dmn, "Invalid vlan ethertype\n");
1261 return NULL;
1262 }
1263
1264 action = dr_action_create_generic(DR_ACTION_TYP_PUSH_VLAN);
1265 if (!action)
1266 return NULL;
1267
1268 action->push_vlan.vlan_hdr = vlan_hdr_h;
1269 return action;
1270 }
1271
1272 struct mlx5dr_action *
mlx5dr_action_create_packet_reformat(struct mlx5dr_domain * dmn,enum mlx5dr_action_reformat_type reformat_type,size_t data_sz,void * data)1273 mlx5dr_action_create_packet_reformat(struct mlx5dr_domain *dmn,
1274 enum mlx5dr_action_reformat_type reformat_type,
1275 size_t data_sz,
1276 void *data)
1277 {
1278 enum mlx5dr_action_type action_type;
1279 struct mlx5dr_action *action;
1280 int ret;
1281
1282 refcount_inc(&dmn->refcount);
1283
1284 /* General checks */
1285 ret = dr_action_reformat_to_action_type(reformat_type, &action_type);
1286 if (ret) {
1287 mlx5dr_dbg(dmn, "Invalid reformat_type provided\n");
1288 goto dec_ref;
1289 }
1290
1291 ret = dr_action_verify_reformat_params(action_type, dmn, data_sz, data);
1292 if (ret)
1293 goto dec_ref;
1294
1295 action = dr_action_create_generic(action_type);
1296 if (!action)
1297 goto dec_ref;
1298
1299 action->reformat.dmn = dmn;
1300
1301 ret = dr_action_create_reformat_action(dmn,
1302 data_sz,
1303 data,
1304 action);
1305 if (ret) {
1306 mlx5dr_dbg(dmn, "Failed creating reformat action %d\n", ret);
1307 goto free_action;
1308 }
1309
1310 return action;
1311
1312 free_action:
1313 kfree(action);
1314 dec_ref:
1315 refcount_dec(&dmn->refcount);
1316 return NULL;
1317 }
1318
1319 static const struct dr_action_modify_field_conv *
dr_action_modify_get_hw_info(u16 sw_field)1320 dr_action_modify_get_hw_info(u16 sw_field)
1321 {
1322 const struct dr_action_modify_field_conv *hw_action_info;
1323
1324 if (sw_field >= ARRAY_SIZE(dr_action_conv_arr))
1325 goto not_found;
1326
1327 hw_action_info = &dr_action_conv_arr[sw_field];
1328 if (!hw_action_info->end && !hw_action_info->start)
1329 goto not_found;
1330
1331 return hw_action_info;
1332
1333 not_found:
1334 return NULL;
1335 }
1336
1337 static int
dr_action_modify_sw_to_hw_add(struct mlx5dr_domain * dmn,__be64 * sw_action,__be64 * hw_action,const struct dr_action_modify_field_conv ** ret_hw_info)1338 dr_action_modify_sw_to_hw_add(struct mlx5dr_domain *dmn,
1339 __be64 *sw_action,
1340 __be64 *hw_action,
1341 const struct dr_action_modify_field_conv **ret_hw_info)
1342 {
1343 const struct dr_action_modify_field_conv *hw_action_info;
1344 u8 max_length;
1345 u16 sw_field;
1346 u32 data;
1347
1348 /* Get SW modify action data */
1349 sw_field = MLX5_GET(set_action_in, sw_action, field);
1350 data = MLX5_GET(set_action_in, sw_action, data);
1351
1352 /* Convert SW data to HW modify action format */
1353 hw_action_info = dr_action_modify_get_hw_info(sw_field);
1354 if (!hw_action_info) {
1355 mlx5dr_dbg(dmn, "Modify add action invalid field given\n");
1356 return -EINVAL;
1357 }
1358
1359 max_length = hw_action_info->end - hw_action_info->start + 1;
1360
1361 MLX5_SET(dr_action_hw_set, hw_action,
1362 opcode, MLX5DR_ACTION_MDFY_HW_OP_ADD);
1363
1364 MLX5_SET(dr_action_hw_set, hw_action, destination_field_code,
1365 hw_action_info->hw_field);
1366
1367 MLX5_SET(dr_action_hw_set, hw_action, destination_left_shifter,
1368 hw_action_info->start);
1369
1370 /* PRM defines that length zero specific length of 32bits */
1371 MLX5_SET(dr_action_hw_set, hw_action, destination_length,
1372 max_length == 32 ? 0 : max_length);
1373
1374 MLX5_SET(dr_action_hw_set, hw_action, inline_data, data);
1375
1376 *ret_hw_info = hw_action_info;
1377
1378 return 0;
1379 }
1380
1381 static int
dr_action_modify_sw_to_hw_set(struct mlx5dr_domain * dmn,__be64 * sw_action,__be64 * hw_action,const struct dr_action_modify_field_conv ** ret_hw_info)1382 dr_action_modify_sw_to_hw_set(struct mlx5dr_domain *dmn,
1383 __be64 *sw_action,
1384 __be64 *hw_action,
1385 const struct dr_action_modify_field_conv **ret_hw_info)
1386 {
1387 const struct dr_action_modify_field_conv *hw_action_info;
1388 u8 offset, length, max_length;
1389 u16 sw_field;
1390 u32 data;
1391
1392 /* Get SW modify action data */
1393 length = MLX5_GET(set_action_in, sw_action, length);
1394 offset = MLX5_GET(set_action_in, sw_action, offset);
1395 sw_field = MLX5_GET(set_action_in, sw_action, field);
1396 data = MLX5_GET(set_action_in, sw_action, data);
1397
1398 /* Convert SW data to HW modify action format */
1399 hw_action_info = dr_action_modify_get_hw_info(sw_field);
1400 if (!hw_action_info) {
1401 mlx5dr_dbg(dmn, "Modify set action invalid field given\n");
1402 return -EINVAL;
1403 }
1404
1405 /* PRM defines that length zero specific length of 32bits */
1406 length = length ? length : 32;
1407
1408 max_length = hw_action_info->end - hw_action_info->start + 1;
1409
1410 if (length + offset > max_length) {
1411 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n");
1412 return -EINVAL;
1413 }
1414
1415 MLX5_SET(dr_action_hw_set, hw_action,
1416 opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
1417
1418 MLX5_SET(dr_action_hw_set, hw_action, destination_field_code,
1419 hw_action_info->hw_field);
1420
1421 MLX5_SET(dr_action_hw_set, hw_action, destination_left_shifter,
1422 hw_action_info->start + offset);
1423
1424 MLX5_SET(dr_action_hw_set, hw_action, destination_length,
1425 length == 32 ? 0 : length);
1426
1427 MLX5_SET(dr_action_hw_set, hw_action, inline_data, data);
1428
1429 *ret_hw_info = hw_action_info;
1430
1431 return 0;
1432 }
1433
1434 static int
dr_action_modify_sw_to_hw_copy(struct mlx5dr_domain * dmn,__be64 * sw_action,__be64 * hw_action,const struct dr_action_modify_field_conv ** ret_dst_hw_info,const struct dr_action_modify_field_conv ** ret_src_hw_info)1435 dr_action_modify_sw_to_hw_copy(struct mlx5dr_domain *dmn,
1436 __be64 *sw_action,
1437 __be64 *hw_action,
1438 const struct dr_action_modify_field_conv **ret_dst_hw_info,
1439 const struct dr_action_modify_field_conv **ret_src_hw_info)
1440 {
1441 u8 src_offset, dst_offset, src_max_length, dst_max_length, length;
1442 const struct dr_action_modify_field_conv *hw_dst_action_info;
1443 const struct dr_action_modify_field_conv *hw_src_action_info;
1444 u16 src_field, dst_field;
1445
1446 /* Get SW modify action data */
1447 src_field = MLX5_GET(copy_action_in, sw_action, src_field);
1448 dst_field = MLX5_GET(copy_action_in, sw_action, dst_field);
1449 src_offset = MLX5_GET(copy_action_in, sw_action, src_offset);
1450 dst_offset = MLX5_GET(copy_action_in, sw_action, dst_offset);
1451 length = MLX5_GET(copy_action_in, sw_action, length);
1452
1453 /* Convert SW data to HW modify action format */
1454 hw_src_action_info = dr_action_modify_get_hw_info(src_field);
1455 hw_dst_action_info = dr_action_modify_get_hw_info(dst_field);
1456 if (!hw_src_action_info || !hw_dst_action_info) {
1457 mlx5dr_dbg(dmn, "Modify copy action invalid field given\n");
1458 return -EINVAL;
1459 }
1460
1461 /* PRM defines that length zero specific length of 32bits */
1462 length = length ? length : 32;
1463
1464 src_max_length = hw_src_action_info->end -
1465 hw_src_action_info->start + 1;
1466 dst_max_length = hw_dst_action_info->end -
1467 hw_dst_action_info->start + 1;
1468
1469 if (length + src_offset > src_max_length ||
1470 length + dst_offset > dst_max_length) {
1471 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n");
1472 return -EINVAL;
1473 }
1474
1475 MLX5_SET(dr_action_hw_copy, hw_action,
1476 opcode, MLX5DR_ACTION_MDFY_HW_OP_COPY);
1477
1478 MLX5_SET(dr_action_hw_copy, hw_action, destination_field_code,
1479 hw_dst_action_info->hw_field);
1480
1481 MLX5_SET(dr_action_hw_copy, hw_action, destination_left_shifter,
1482 hw_dst_action_info->start + dst_offset);
1483
1484 MLX5_SET(dr_action_hw_copy, hw_action, destination_length,
1485 length == 32 ? 0 : length);
1486
1487 MLX5_SET(dr_action_hw_copy, hw_action, source_field_code,
1488 hw_src_action_info->hw_field);
1489
1490 MLX5_SET(dr_action_hw_copy, hw_action, source_left_shifter,
1491 hw_src_action_info->start + dst_offset);
1492
1493 *ret_dst_hw_info = hw_dst_action_info;
1494 *ret_src_hw_info = hw_src_action_info;
1495
1496 return 0;
1497 }
1498
1499 static int
dr_action_modify_sw_to_hw(struct mlx5dr_domain * dmn,__be64 * sw_action,__be64 * hw_action,const struct dr_action_modify_field_conv ** ret_dst_hw_info,const struct dr_action_modify_field_conv ** ret_src_hw_info)1500 dr_action_modify_sw_to_hw(struct mlx5dr_domain *dmn,
1501 __be64 *sw_action,
1502 __be64 *hw_action,
1503 const struct dr_action_modify_field_conv **ret_dst_hw_info,
1504 const struct dr_action_modify_field_conv **ret_src_hw_info)
1505 {
1506 u8 action;
1507 int ret;
1508
1509 *hw_action = 0;
1510 *ret_src_hw_info = NULL;
1511
1512 /* Get SW modify action type */
1513 action = MLX5_GET(set_action_in, sw_action, action_type);
1514
1515 switch (action) {
1516 case MLX5_ACTION_TYPE_SET:
1517 ret = dr_action_modify_sw_to_hw_set(dmn, sw_action,
1518 hw_action,
1519 ret_dst_hw_info);
1520 break;
1521
1522 case MLX5_ACTION_TYPE_ADD:
1523 ret = dr_action_modify_sw_to_hw_add(dmn, sw_action,
1524 hw_action,
1525 ret_dst_hw_info);
1526 break;
1527
1528 case MLX5_ACTION_TYPE_COPY:
1529 ret = dr_action_modify_sw_to_hw_copy(dmn, sw_action,
1530 hw_action,
1531 ret_dst_hw_info,
1532 ret_src_hw_info);
1533 break;
1534
1535 default:
1536 mlx5dr_info(dmn, "Unsupported action_type for modify action\n");
1537 ret = -EOPNOTSUPP;
1538 }
1539
1540 return ret;
1541 }
1542
1543 static int
dr_action_modify_check_set_field_limitation(struct mlx5dr_action * action,const __be64 * sw_action)1544 dr_action_modify_check_set_field_limitation(struct mlx5dr_action *action,
1545 const __be64 *sw_action)
1546 {
1547 u16 sw_field = MLX5_GET(set_action_in, sw_action, field);
1548 struct mlx5dr_domain *dmn = action->rewrite.dmn;
1549
1550 if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_A) {
1551 action->rewrite.allow_rx = 0;
1552 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) {
1553 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n",
1554 sw_field);
1555 return -EINVAL;
1556 }
1557 } else if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_B) {
1558 action->rewrite.allow_tx = 0;
1559 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) {
1560 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n",
1561 sw_field);
1562 return -EINVAL;
1563 }
1564 }
1565
1566 if (!action->rewrite.allow_rx && !action->rewrite.allow_tx) {
1567 mlx5dr_dbg(dmn, "Modify SET actions not supported on both RX and TX\n");
1568 return -EINVAL;
1569 }
1570
1571 return 0;
1572 }
1573
1574 static int
dr_action_modify_check_add_field_limitation(struct mlx5dr_action * action,const __be64 * sw_action)1575 dr_action_modify_check_add_field_limitation(struct mlx5dr_action *action,
1576 const __be64 *sw_action)
1577 {
1578 u16 sw_field = MLX5_GET(set_action_in, sw_action, field);
1579 struct mlx5dr_domain *dmn = action->rewrite.dmn;
1580
1581 if (sw_field != MLX5_ACTION_IN_FIELD_OUT_IP_TTL &&
1582 sw_field != MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT &&
1583 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM &&
1584 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM) {
1585 mlx5dr_dbg(dmn, "Unsupported field %d for add action\n",
1586 sw_field);
1587 return -EINVAL;
1588 }
1589
1590 return 0;
1591 }
1592
1593 static int
dr_action_modify_check_copy_field_limitation(struct mlx5dr_action * action,const __be64 * sw_action)1594 dr_action_modify_check_copy_field_limitation(struct mlx5dr_action *action,
1595 const __be64 *sw_action)
1596 {
1597 struct mlx5dr_domain *dmn = action->rewrite.dmn;
1598 u16 sw_fields[2];
1599 int i;
1600
1601 sw_fields[0] = MLX5_GET(copy_action_in, sw_action, src_field);
1602 sw_fields[1] = MLX5_GET(copy_action_in, sw_action, dst_field);
1603
1604 for (i = 0; i < 2; i++) {
1605 if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_A) {
1606 action->rewrite.allow_rx = 0;
1607 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) {
1608 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n",
1609 sw_fields[i]);
1610 return -EINVAL;
1611 }
1612 } else if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_B) {
1613 action->rewrite.allow_tx = 0;
1614 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) {
1615 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n",
1616 sw_fields[i]);
1617 return -EINVAL;
1618 }
1619 }
1620 }
1621
1622 if (!action->rewrite.allow_rx && !action->rewrite.allow_tx) {
1623 mlx5dr_dbg(dmn, "Modify copy actions not supported on both RX and TX\n");
1624 return -EINVAL;
1625 }
1626
1627 return 0;
1628 }
1629
1630 static int
dr_action_modify_check_field_limitation(struct mlx5dr_action * action,const __be64 * sw_action)1631 dr_action_modify_check_field_limitation(struct mlx5dr_action *action,
1632 const __be64 *sw_action)
1633 {
1634 struct mlx5dr_domain *dmn = action->rewrite.dmn;
1635 u8 action_type;
1636 int ret;
1637
1638 action_type = MLX5_GET(set_action_in, sw_action, action_type);
1639
1640 switch (action_type) {
1641 case MLX5_ACTION_TYPE_SET:
1642 ret = dr_action_modify_check_set_field_limitation(action,
1643 sw_action);
1644 break;
1645
1646 case MLX5_ACTION_TYPE_ADD:
1647 ret = dr_action_modify_check_add_field_limitation(action,
1648 sw_action);
1649 break;
1650
1651 case MLX5_ACTION_TYPE_COPY:
1652 ret = dr_action_modify_check_copy_field_limitation(action,
1653 sw_action);
1654 break;
1655
1656 default:
1657 mlx5dr_info(dmn, "Unsupported action %d modify action\n",
1658 action_type);
1659 ret = -EOPNOTSUPP;
1660 }
1661
1662 return ret;
1663 }
1664
1665 static bool
dr_action_modify_check_is_ttl_modify(const void * sw_action)1666 dr_action_modify_check_is_ttl_modify(const void *sw_action)
1667 {
1668 u16 sw_field = MLX5_GET(set_action_in, sw_action, field);
1669
1670 return sw_field == MLX5_ACTION_IN_FIELD_OUT_IP_TTL;
1671 }
1672
dr_actions_convert_modify_header(struct mlx5dr_action * action,u32 max_hw_actions,u32 num_sw_actions,__be64 sw_actions[],__be64 hw_actions[],u32 * num_hw_actions,bool * modify_ttl)1673 static int dr_actions_convert_modify_header(struct mlx5dr_action *action,
1674 u32 max_hw_actions,
1675 u32 num_sw_actions,
1676 __be64 sw_actions[],
1677 __be64 hw_actions[],
1678 u32 *num_hw_actions,
1679 bool *modify_ttl)
1680 {
1681 const struct dr_action_modify_field_conv *hw_dst_action_info;
1682 const struct dr_action_modify_field_conv *hw_src_action_info;
1683 u16 hw_field = MLX5DR_ACTION_MDFY_HW_FLD_RESERVED;
1684 u32 l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_NONE;
1685 u32 l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_NONE;
1686 struct mlx5dr_domain *dmn = action->rewrite.dmn;
1687 int ret, i, hw_idx = 0;
1688 __be64 *sw_action;
1689 __be64 hw_action;
1690
1691 *modify_ttl = false;
1692
1693 action->rewrite.allow_rx = 1;
1694 action->rewrite.allow_tx = 1;
1695
1696 for (i = 0; i < num_sw_actions; i++) {
1697 sw_action = &sw_actions[i];
1698
1699 ret = dr_action_modify_check_field_limitation(action,
1700 sw_action);
1701 if (ret)
1702 return ret;
1703
1704 if (!(*modify_ttl))
1705 *modify_ttl = dr_action_modify_check_is_ttl_modify(sw_action);
1706
1707 /* Convert SW action to HW action */
1708 ret = dr_action_modify_sw_to_hw(dmn,
1709 sw_action,
1710 &hw_action,
1711 &hw_dst_action_info,
1712 &hw_src_action_info);
1713 if (ret)
1714 return ret;
1715
1716 /* Due to a HW limitation we cannot modify 2 different L3 types */
1717 if (l3_type && hw_dst_action_info->l3_type &&
1718 hw_dst_action_info->l3_type != l3_type) {
1719 mlx5dr_dbg(dmn, "Action list can't support two different L3 types\n");
1720 return -EINVAL;
1721 }
1722 if (hw_dst_action_info->l3_type)
1723 l3_type = hw_dst_action_info->l3_type;
1724
1725 /* Due to a HW limitation we cannot modify two different L4 types */
1726 if (l4_type && hw_dst_action_info->l4_type &&
1727 hw_dst_action_info->l4_type != l4_type) {
1728 mlx5dr_dbg(dmn, "Action list can't support two different L4 types\n");
1729 return -EINVAL;
1730 }
1731 if (hw_dst_action_info->l4_type)
1732 l4_type = hw_dst_action_info->l4_type;
1733
1734 /* HW reads and executes two actions at once this means we
1735 * need to create a gap if two actions access the same field
1736 */
1737 if ((hw_idx % 2) && (hw_field == hw_dst_action_info->hw_field ||
1738 (hw_src_action_info &&
1739 hw_field == hw_src_action_info->hw_field))) {
1740 /* Check if after gap insertion the total number of HW
1741 * modify actions doesn't exceeds the limit
1742 */
1743 hw_idx++;
1744 if ((num_sw_actions + hw_idx - i) >= max_hw_actions) {
1745 mlx5dr_dbg(dmn, "Modify header action number exceeds HW limit\n");
1746 return -EINVAL;
1747 }
1748 }
1749 hw_field = hw_dst_action_info->hw_field;
1750
1751 hw_actions[hw_idx] = hw_action;
1752 hw_idx++;
1753 }
1754
1755 *num_hw_actions = hw_idx;
1756
1757 return 0;
1758 }
1759
dr_action_create_modify_action(struct mlx5dr_domain * dmn,size_t actions_sz,__be64 actions[],struct mlx5dr_action * action)1760 static int dr_action_create_modify_action(struct mlx5dr_domain *dmn,
1761 size_t actions_sz,
1762 __be64 actions[],
1763 struct mlx5dr_action *action)
1764 {
1765 struct mlx5dr_icm_chunk *chunk;
1766 u32 max_hw_actions;
1767 u32 num_hw_actions;
1768 u32 num_sw_actions;
1769 __be64 *hw_actions;
1770 bool modify_ttl;
1771 int ret;
1772
1773 num_sw_actions = actions_sz / DR_MODIFY_ACTION_SIZE;
1774 max_hw_actions = mlx5dr_icm_pool_chunk_size_to_entries(DR_CHUNK_SIZE_16);
1775
1776 if (num_sw_actions > max_hw_actions) {
1777 mlx5dr_dbg(dmn, "Max number of actions %d exceeds limit %d\n",
1778 num_sw_actions, max_hw_actions);
1779 return -EINVAL;
1780 }
1781
1782 chunk = mlx5dr_icm_alloc_chunk(dmn->action_icm_pool, DR_CHUNK_SIZE_16);
1783 if (!chunk)
1784 return -ENOMEM;
1785
1786 hw_actions = kcalloc(1, max_hw_actions * DR_MODIFY_ACTION_SIZE, GFP_KERNEL);
1787 if (!hw_actions) {
1788 ret = -ENOMEM;
1789 goto free_chunk;
1790 }
1791
1792 ret = dr_actions_convert_modify_header(action,
1793 max_hw_actions,
1794 num_sw_actions,
1795 actions,
1796 hw_actions,
1797 &num_hw_actions,
1798 &modify_ttl);
1799 if (ret)
1800 goto free_hw_actions;
1801
1802 action->rewrite.chunk = chunk;
1803 action->rewrite.modify_ttl = modify_ttl;
1804 action->rewrite.data = (u8 *)hw_actions;
1805 action->rewrite.num_of_actions = num_hw_actions;
1806 action->rewrite.index = (chunk->icm_addr -
1807 dmn->info.caps.hdr_modify_icm_addr) /
1808 ACTION_CACHE_LINE_SIZE;
1809
1810 ret = mlx5dr_send_postsend_action(dmn, action);
1811 if (ret)
1812 goto free_hw_actions;
1813
1814 return 0;
1815
1816 free_hw_actions:
1817 kfree(hw_actions);
1818 free_chunk:
1819 mlx5dr_icm_free_chunk(chunk);
1820 return ret;
1821 }
1822
1823 struct mlx5dr_action *
mlx5dr_action_create_modify_header(struct mlx5dr_domain * dmn,u32 flags,size_t actions_sz,__be64 actions[])1824 mlx5dr_action_create_modify_header(struct mlx5dr_domain *dmn,
1825 u32 flags,
1826 size_t actions_sz,
1827 __be64 actions[])
1828 {
1829 struct mlx5dr_action *action;
1830 int ret = 0;
1831
1832 refcount_inc(&dmn->refcount);
1833
1834 if (actions_sz % DR_MODIFY_ACTION_SIZE) {
1835 mlx5dr_dbg(dmn, "Invalid modify actions size provided\n");
1836 goto dec_ref;
1837 }
1838
1839 action = dr_action_create_generic(DR_ACTION_TYP_MODIFY_HDR);
1840 if (!action)
1841 goto dec_ref;
1842
1843 action->rewrite.dmn = dmn;
1844
1845 ret = dr_action_create_modify_action(dmn,
1846 actions_sz,
1847 actions,
1848 action);
1849 if (ret) {
1850 mlx5dr_dbg(dmn, "Failed creating modify header action %d\n", ret);
1851 goto free_action;
1852 }
1853
1854 return action;
1855
1856 free_action:
1857 kfree(action);
1858 dec_ref:
1859 refcount_dec(&dmn->refcount);
1860 return NULL;
1861 }
1862
1863 struct mlx5dr_action *
mlx5dr_action_create_dest_vport(struct mlx5dr_domain * dmn,u32 vport,u8 vhca_id_valid,u16 vhca_id)1864 mlx5dr_action_create_dest_vport(struct mlx5dr_domain *dmn,
1865 u32 vport, u8 vhca_id_valid,
1866 u16 vhca_id)
1867 {
1868 struct mlx5dr_cmd_vport_cap *vport_cap;
1869 struct mlx5dr_domain *vport_dmn;
1870 struct mlx5dr_action *action;
1871 u8 peer_vport;
1872
1873 peer_vport = vhca_id_valid && (vhca_id != dmn->info.caps.gvmi);
1874 vport_dmn = peer_vport ? dmn->peer_dmn : dmn;
1875 if (!vport_dmn) {
1876 mlx5dr_dbg(dmn, "No peer vport domain for given vhca_id\n");
1877 return NULL;
1878 }
1879
1880 if (vport_dmn->type != MLX5DR_DOMAIN_TYPE_FDB) {
1881 mlx5dr_dbg(dmn, "Domain doesn't support vport actions\n");
1882 return NULL;
1883 }
1884
1885 vport_cap = mlx5dr_get_vport_cap(&vport_dmn->info.caps, vport);
1886 if (!vport_cap) {
1887 mlx5dr_dbg(dmn, "Failed to get vport %d caps\n", vport);
1888 return NULL;
1889 }
1890
1891 action = dr_action_create_generic(DR_ACTION_TYP_VPORT);
1892 if (!action)
1893 return NULL;
1894
1895 action->vport.dmn = vport_dmn;
1896 action->vport.caps = vport_cap;
1897
1898 return action;
1899 }
1900
mlx5dr_action_destroy(struct mlx5dr_action * action)1901 int mlx5dr_action_destroy(struct mlx5dr_action *action)
1902 {
1903 if (refcount_read(&action->refcount) > 1)
1904 return -EBUSY;
1905
1906 switch (action->action_type) {
1907 case DR_ACTION_TYP_FT:
1908 if (action->dest_tbl.is_fw_tbl)
1909 refcount_dec(&action->dest_tbl.fw_tbl.dmn->refcount);
1910 else
1911 refcount_dec(&action->dest_tbl.tbl->refcount);
1912
1913 if (action->dest_tbl.is_fw_tbl &&
1914 action->dest_tbl.fw_tbl.num_of_ref_actions) {
1915 struct mlx5dr_action **ref_actions;
1916 int i;
1917
1918 ref_actions = action->dest_tbl.fw_tbl.ref_actions;
1919 for (i = 0; i < action->dest_tbl.fw_tbl.num_of_ref_actions; i++)
1920 refcount_dec(&ref_actions[i]->refcount);
1921
1922 kfree(ref_actions);
1923
1924 mlx5dr_fw_destroy_md_tbl(action->dest_tbl.fw_tbl.dmn,
1925 action->dest_tbl.fw_tbl.id,
1926 action->dest_tbl.fw_tbl.group_id);
1927 }
1928 break;
1929 case DR_ACTION_TYP_TNL_L2_TO_L2:
1930 refcount_dec(&action->reformat.dmn->refcount);
1931 break;
1932 case DR_ACTION_TYP_TNL_L3_TO_L2:
1933 mlx5dr_icm_free_chunk(action->rewrite.chunk);
1934 refcount_dec(&action->reformat.dmn->refcount);
1935 break;
1936 case DR_ACTION_TYP_L2_TO_TNL_L2:
1937 case DR_ACTION_TYP_L2_TO_TNL_L3:
1938 mlx5dr_cmd_destroy_reformat_ctx((action->reformat.dmn)->mdev,
1939 action->reformat.reformat_id);
1940 refcount_dec(&action->reformat.dmn->refcount);
1941 break;
1942 case DR_ACTION_TYP_MODIFY_HDR:
1943 mlx5dr_icm_free_chunk(action->rewrite.chunk);
1944 kfree(action->rewrite.data);
1945 refcount_dec(&action->rewrite.dmn->refcount);
1946 break;
1947 default:
1948 break;
1949 }
1950
1951 kfree(action);
1952 return 0;
1953 }
1954