1 /* Copyright 2012-17 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_DWBC_H__ 26 #define __DC_DWBC_H__ 27 28 #include "dal_types.h" 29 #include "dc_hw_types.h" 30 31 #define DWB_SW_V2 1 32 #define DWB_MCIF_BUF_COUNT 4 33 34 /* forward declaration of mcif_wb struct */ 35 struct mcif_wb; 36 37 38 enum dwb_sw_version { 39 dwb_ver_1_0 = 1, 40 dwb_ver_2_0 = 2, 41 }; 42 43 enum dwb_source { 44 dwb_src_scl = 0, /* for DCE7x/9x, DCN won't support. */ 45 dwb_src_blnd, /* for DCE7x/9x */ 46 dwb_src_fmt, /* for DCE7x/9x */ 47 dwb_src_otg0 = 0x100, /* for DCN1.x/DCN2.x, register: mmDWB_SOURCE_SELECT */ 48 dwb_src_otg1, /* for DCN1.x/DCN2.x */ 49 dwb_src_otg2, /* for DCN1.x/DCN2.x */ 50 dwb_src_otg3, /* for DCN1.x/DCN2.x */ 51 }; 52 53 /* DCN1.x, DCN2.x support 2 pipes */ 54 enum dwb_pipe { 55 dwb_pipe0 = 0, 56 #if defined(CONFIG_DRM_AMD_DC_DCN) 57 dwb_pipe1, 58 #endif 59 dwb_pipe_max_num, 60 }; 61 62 enum dwb_frame_capture_enable { 63 DWB_FRAME_CAPTURE_DISABLE = 0, 64 DWB_FRAME_CAPTURE_ENABLE = 1, 65 }; 66 67 enum wbscl_coef_filter_type_sel { 68 WBSCL_COEF_LUMA_VERT_FILTER = 0, 69 WBSCL_COEF_CHROMA_VERT_FILTER = 1, 70 WBSCL_COEF_LUMA_HORZ_FILTER = 2, 71 WBSCL_COEF_CHROMA_HORZ_FILTER = 3 72 }; 73 74 75 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 76 enum dwb_boundary_mode { 77 DWBSCL_BOUNDARY_MODE_EDGE = 0, 78 DWBSCL_BOUNDARY_MODE_BLACK = 1 79 }; 80 #endif 81 82 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 83 enum dwb_output_csc_mode { 84 DWB_OUTPUT_CSC_DISABLE = 0, 85 DWB_OUTPUT_CSC_COEF_A = 1, 86 DWB_OUTPUT_CSC_COEF_B = 2 87 }; 88 89 enum dwb_ogam_lut_mode { 90 DWB_OGAM_MODE_BYPASS, 91 DWB_OGAM_RAMA_LUT, 92 DWB_OGAM_RAMB_LUT 93 }; 94 95 enum dwb_color_volume { 96 DWB_SRGB_BT709 = 0, //SDR 97 DWB_PQ = 1, //HDR 98 DWB_HLG = 2, //HDR 99 }; 100 101 enum dwb_color_space { 102 DWB_SRGB = 0, //SDR 103 DWB_BT709 = 1, //SDR 104 DWB_BT2020 = 2, //HDR 105 }; 106 107 struct dwb_efc_hdr_metadata { 108 /*display chromaticities and white point in units of 0.00001 */ 109 unsigned int chromaticity_green_x; 110 unsigned int chromaticity_green_y; 111 unsigned int chromaticity_blue_x; 112 unsigned int chromaticity_blue_y; 113 unsigned int chromaticity_red_x; 114 unsigned int chromaticity_red_y; 115 unsigned int chromaticity_white_point_x; 116 unsigned int chromaticity_white_point_y; 117 118 /*in units of candelas per square meter */ 119 unsigned int min_luminance; 120 unsigned int max_luminance; 121 122 /*in units of nits */ 123 unsigned int maximum_content_light_level; 124 unsigned int maximum_frame_average_light_level; 125 }; 126 127 struct dwb_efc_display_settings { 128 unsigned int inputColorVolume; 129 unsigned int inputColorSpace; 130 unsigned int inputBitDepthMinus8; 131 struct dwb_efc_hdr_metadata hdr_metadata; 132 unsigned int dwbOutputBlack; // 0 - Normal, 1 - Output Black 133 }; 134 135 #endif 136 struct dwb_warmup_params { 137 bool warmup_en; /* false: normal mode, true: enable pattern generator */ 138 bool warmup_mode; /* false: 420, true: 444 */ 139 bool warmup_depth; /* false: 8bit, true: 10bit */ 140 int warmup_data; /* Data to be sent by pattern generator (same for each pixel component) */ 141 int warmup_width; /* Pattern width (pixels) */ 142 int warmup_height; /* Pattern height (lines) */ 143 }; 144 145 struct dwb_caps { 146 enum dce_version hw_version; /* DCN engine version. */ 147 enum dwb_sw_version sw_version; /* DWB sw implementation version. */ 148 unsigned int reserved[6]; /* Reserved for future use, MUST BE 0. */ 149 unsigned int adapter_id; 150 unsigned int num_pipes; /* number of DWB pipes */ 151 struct { 152 unsigned int support_dwb :1; 153 unsigned int support_ogam :1; 154 unsigned int support_wbscl :1; 155 unsigned int support_ocsc :1; 156 unsigned int support_stereo :1; 157 } caps; 158 unsigned int reserved2[9]; /* Reserved for future use, MUST BE 0. */ 159 }; 160 161 struct dwbc { 162 const struct dwbc_funcs *funcs; 163 struct dc_context *ctx; 164 int inst; 165 struct mcif_wb *mcif; 166 bool status; 167 int inputSrcSelect; 168 bool dwb_output_black; 169 enum dc_transfer_func_predefined tf; 170 enum dc_color_space output_color_space; 171 bool dwb_is_efc_transition; 172 bool dwb_is_drc; 173 int wb_src_plane_inst;/*hubp, mpcc, inst*/ 174 bool update_privacymask; 175 uint32_t mask_id; 176 int otg_inst; 177 bool mvc_cfg; 178 }; 179 180 struct dwbc_funcs { 181 bool (*get_caps)( 182 struct dwbc *dwbc, 183 struct dwb_caps *caps); 184 185 bool (*enable)( 186 struct dwbc *dwbc, 187 struct dc_dwb_params *params); 188 189 bool (*disable)(struct dwbc *dwbc); 190 191 bool (*update)( 192 struct dwbc *dwbc, 193 struct dc_dwb_params *params); 194 195 bool (*is_enabled)( 196 struct dwbc *dwbc); 197 198 void (*set_stereo)( 199 struct dwbc *dwbc, 200 struct dwb_stereo_params *stereo_params); 201 202 void (*set_new_content)( 203 struct dwbc *dwbc, 204 bool is_new_content); 205 206 207 void (*set_warmup)( 208 struct dwbc *dwbc, 209 struct dwb_warmup_params *warmup_params); 210 211 212 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 213 214 void (*dwb_program_output_csc)( 215 struct dwbc *dwbc, 216 enum dc_color_space color_space, 217 enum dwb_output_csc_mode mode); 218 219 bool (*dwb_ogam_set_output_transfer_func)( 220 struct dwbc *dwbc, 221 const struct dc_transfer_func *in_transfer_func_dwb_ogam); 222 223 void (*get_privacy_mask)( 224 struct dwbc *dwbc, uint32_t *mask_id); 225 226 void (*set_privacy_mask)( 227 struct dwbc *dwbc, uint32_t mask_id); 228 229 //TODO: merge with output_transfer_func? 230 bool (*dwb_ogam_set_input_transfer_func)( 231 struct dwbc *dwbc, 232 const struct dc_transfer_func *in_transfer_func_dwb_ogam); 233 #endif 234 bool (*get_dwb_status)( 235 struct dwbc *dwbc); 236 void (*dwb_set_scaler)( 237 struct dwbc *dwbc, 238 struct dc_dwb_params *params); 239 }; 240 241 #endif 242