1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * platform.c - DesignWare HS OTG Controller platform driver
4 *
5 * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41 #include <linux/clk.h>
42 #include <linux/device.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/of_device.h>
45 #include <linux/mutex.h>
46 #include <linux/platform_device.h>
47 #include <linux/phy/phy.h>
48 #include <linux/platform_data/s3c-hsotg.h>
49 #include <linux/reset.h>
50
51 #include <linux/usb/of.h>
52
53 #include "core.h"
54 #include "hcd.h"
55 #include "debug.h"
56
57 static const char dwc2_driver_name[] = "dwc2";
58
59 /*
60 * Check the dr_mode against the module configuration and hardware
61 * capabilities.
62 *
63 * The hardware, module, and dr_mode, can each be set to host, device,
64 * or otg. Check that all these values are compatible and adjust the
65 * value of dr_mode if possible.
66 *
67 * actual
68 * HW MOD dr_mode dr_mode
69 * ------------------------------
70 * HST HST any : HST
71 * HST DEV any : ---
72 * HST OTG any : HST
73 *
74 * DEV HST any : ---
75 * DEV DEV any : DEV
76 * DEV OTG any : DEV
77 *
78 * OTG HST any : HST
79 * OTG DEV any : DEV
80 * OTG OTG any : dr_mode
81 */
dwc2_get_dr_mode(struct dwc2_hsotg * hsotg)82 static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
83 {
84 enum usb_dr_mode mode;
85
86 hsotg->dr_mode = usb_get_dr_mode(hsotg->dev);
87 if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN)
88 hsotg->dr_mode = USB_DR_MODE_OTG;
89
90 mode = hsotg->dr_mode;
91
92 if (dwc2_hw_is_device(hsotg)) {
93 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
94 dev_err(hsotg->dev,
95 "Controller does not support host mode.\n");
96 return -EINVAL;
97 }
98 mode = USB_DR_MODE_PERIPHERAL;
99 } else if (dwc2_hw_is_host(hsotg)) {
100 if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
101 dev_err(hsotg->dev,
102 "Controller does not support device mode.\n");
103 return -EINVAL;
104 }
105 mode = USB_DR_MODE_HOST;
106 } else {
107 if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
108 mode = USB_DR_MODE_HOST;
109 else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
110 mode = USB_DR_MODE_PERIPHERAL;
111 }
112
113 if (mode != hsotg->dr_mode) {
114 dev_warn(hsotg->dev,
115 "Configuration mismatch. dr_mode forced to %s\n",
116 mode == USB_DR_MODE_HOST ? "host" : "device");
117
118 hsotg->dr_mode = mode;
119 }
120
121 return 0;
122 }
123
__dwc2_lowlevel_hw_enable(struct dwc2_hsotg * hsotg)124 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
125 {
126 struct platform_device *pdev = to_platform_device(hsotg->dev);
127 int ret;
128
129 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
130 hsotg->supplies);
131 if (ret)
132 return ret;
133
134 if (hsotg->clk) {
135 ret = clk_prepare_enable(hsotg->clk);
136 if (ret)
137 return ret;
138 }
139
140 if (hsotg->uphy) {
141 ret = usb_phy_init(hsotg->uphy);
142 } else if (hsotg->plat && hsotg->plat->phy_init) {
143 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
144 } else {
145 ret = phy_init(hsotg->phy);
146 if (ret == 0)
147 ret = phy_power_on(hsotg->phy);
148 }
149
150 return ret;
151 }
152
153 /**
154 * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
155 * @hsotg: The driver state
156 *
157 * A wrapper for platform code responsible for controlling
158 * low-level USB platform resources (phy, clock, regulators)
159 */
dwc2_lowlevel_hw_enable(struct dwc2_hsotg * hsotg)160 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
161 {
162 int ret = __dwc2_lowlevel_hw_enable(hsotg);
163
164 if (ret == 0)
165 hsotg->ll_hw_enabled = true;
166 return ret;
167 }
168
__dwc2_lowlevel_hw_disable(struct dwc2_hsotg * hsotg)169 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
170 {
171 struct platform_device *pdev = to_platform_device(hsotg->dev);
172 int ret = 0;
173
174 if (hsotg->uphy) {
175 usb_phy_shutdown(hsotg->uphy);
176 } else if (hsotg->plat && hsotg->plat->phy_exit) {
177 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
178 } else {
179 ret = phy_power_off(hsotg->phy);
180 if (ret == 0)
181 ret = phy_exit(hsotg->phy);
182 }
183 if (ret)
184 return ret;
185
186 if (hsotg->clk)
187 clk_disable_unprepare(hsotg->clk);
188
189 return regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
190 }
191
192 /**
193 * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
194 * @hsotg: The driver state
195 *
196 * A wrapper for platform code responsible for controlling
197 * low-level USB platform resources (phy, clock, regulators)
198 */
dwc2_lowlevel_hw_disable(struct dwc2_hsotg * hsotg)199 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
200 {
201 int ret = __dwc2_lowlevel_hw_disable(hsotg);
202
203 if (ret == 0)
204 hsotg->ll_hw_enabled = false;
205 return ret;
206 }
207
dwc2_lowlevel_hw_init(struct dwc2_hsotg * hsotg)208 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
209 {
210 int i, ret;
211
212 hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
213 if (IS_ERR(hsotg->reset)) {
214 ret = PTR_ERR(hsotg->reset);
215 dev_err(hsotg->dev, "error getting reset control %d\n", ret);
216 return ret;
217 }
218
219 reset_control_deassert(hsotg->reset);
220
221 hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc");
222 if (IS_ERR(hsotg->reset_ecc)) {
223 ret = PTR_ERR(hsotg->reset_ecc);
224 dev_err(hsotg->dev, "error getting reset control for ecc %d\n", ret);
225 return ret;
226 }
227
228 reset_control_deassert(hsotg->reset_ecc);
229
230 /*
231 * Attempt to find a generic PHY, then look for an old style
232 * USB PHY and then fall back to pdata
233 */
234 hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
235 if (IS_ERR(hsotg->phy)) {
236 ret = PTR_ERR(hsotg->phy);
237 switch (ret) {
238 case -ENODEV:
239 case -ENOSYS:
240 hsotg->phy = NULL;
241 break;
242 case -EPROBE_DEFER:
243 return ret;
244 default:
245 dev_err(hsotg->dev, "error getting phy %d\n", ret);
246 return ret;
247 }
248 }
249
250 if (!hsotg->phy) {
251 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
252 if (IS_ERR(hsotg->uphy)) {
253 ret = PTR_ERR(hsotg->uphy);
254 switch (ret) {
255 case -ENODEV:
256 case -ENXIO:
257 hsotg->uphy = NULL;
258 break;
259 case -EPROBE_DEFER:
260 return ret;
261 default:
262 dev_err(hsotg->dev, "error getting usb phy %d\n",
263 ret);
264 return ret;
265 }
266 }
267 }
268
269 hsotg->plat = dev_get_platdata(hsotg->dev);
270
271 /* Clock */
272 hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
273 if (IS_ERR(hsotg->clk)) {
274 dev_err(hsotg->dev, "cannot get otg clock\n");
275 return PTR_ERR(hsotg->clk);
276 }
277
278 /* Regulators */
279 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
280 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
281
282 ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
283 hsotg->supplies);
284 if (ret) {
285 if (ret != -EPROBE_DEFER)
286 dev_err(hsotg->dev, "failed to request supplies: %d\n",
287 ret);
288 return ret;
289 }
290 return 0;
291 }
292
293 /**
294 * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
295 * DWC_otg driver
296 *
297 * @dev: Platform device
298 *
299 * This routine is called, for example, when the rmmod command is executed. The
300 * device may or may not be electrically present. If it is present, the driver
301 * stops device processing. Any resources used on behalf of this device are
302 * freed.
303 */
dwc2_driver_remove(struct platform_device * dev)304 static int dwc2_driver_remove(struct platform_device *dev)
305 {
306 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
307
308 dwc2_debugfs_exit(hsotg);
309 if (hsotg->hcd_enabled)
310 dwc2_hcd_remove(hsotg);
311 if (hsotg->gadget_enabled)
312 dwc2_hsotg_remove(hsotg);
313
314 dwc2_drd_exit(hsotg);
315
316 if (hsotg->params.activate_stm_id_vb_detection)
317 regulator_disable(hsotg->usb33d);
318
319 if (hsotg->ll_hw_enabled)
320 dwc2_lowlevel_hw_disable(hsotg);
321
322 reset_control_assert(hsotg->reset);
323 reset_control_assert(hsotg->reset_ecc);
324
325 return 0;
326 }
327
328 /**
329 * dwc2_driver_shutdown() - Called on device shutdown
330 *
331 * @dev: Platform device
332 *
333 * In specific conditions (involving usb hubs) dwc2 devices can create a
334 * lot of interrupts, even to the point of overwhelming devices running
335 * at low frequencies. Some devices need to do special clock handling
336 * at shutdown-time which may bring the system clock below the threshold
337 * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
338 * prevents reboots/poweroffs from getting stuck in such cases.
339 */
dwc2_driver_shutdown(struct platform_device * dev)340 static void dwc2_driver_shutdown(struct platform_device *dev)
341 {
342 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
343
344 dwc2_disable_global_interrupts(hsotg);
345 synchronize_irq(hsotg->irq);
346 }
347
348 /**
349 * dwc2_check_core_endianness() - Returns true if core and AHB have
350 * opposite endianness.
351 * @hsotg: Programming view of the DWC_otg controller.
352 */
dwc2_check_core_endianness(struct dwc2_hsotg * hsotg)353 static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg)
354 {
355 u32 snpsid;
356
357 snpsid = ioread32(hsotg->regs + GSNPSID);
358 if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID ||
359 (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID ||
360 (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID)
361 return false;
362 return true;
363 }
364
365 /**
366 * Check core version
367 *
368 * @hsotg: Programming view of the DWC_otg controller
369 *
370 */
dwc2_check_core_version(struct dwc2_hsotg * hsotg)371 int dwc2_check_core_version(struct dwc2_hsotg *hsotg)
372 {
373 struct dwc2_hw_params *hw = &hsotg->hw_params;
374
375 /*
376 * Attempt to ensure this device is really a DWC_otg Controller.
377 * Read and verify the GSNPSID register contents. The value should be
378 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
379 */
380
381 hw->snpsid = dwc2_readl(hsotg, GSNPSID);
382 if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
383 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
384 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
385 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
386 hw->snpsid);
387 return -ENODEV;
388 }
389
390 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
391 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
392 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
393 return 0;
394 }
395
396 /**
397 * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
398 * driver
399 *
400 * @dev: Platform device
401 *
402 * This routine creates the driver components required to control the device
403 * (core, HCD, and PCD) and initializes the device. The driver components are
404 * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
405 * in the device private data. This allows the driver to access the dwc2_hsotg
406 * structure on subsequent calls to driver methods for this device.
407 */
dwc2_driver_probe(struct platform_device * dev)408 static int dwc2_driver_probe(struct platform_device *dev)
409 {
410 struct dwc2_hsotg *hsotg;
411 struct resource *res;
412 int retval;
413
414 hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
415 if (!hsotg)
416 return -ENOMEM;
417
418 hsotg->dev = &dev->dev;
419
420 /*
421 * Use reasonable defaults so platforms don't have to provide these.
422 */
423 if (!dev->dev.dma_mask)
424 dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
425 retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
426 if (retval) {
427 dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval);
428 return retval;
429 }
430
431 hsotg->regs = devm_platform_get_and_ioremap_resource(dev, 0, &res);
432 if (IS_ERR(hsotg->regs))
433 return PTR_ERR(hsotg->regs);
434
435 dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
436 (unsigned long)res->start, hsotg->regs);
437
438 retval = dwc2_lowlevel_hw_init(hsotg);
439 if (retval)
440 return retval;
441
442 spin_lock_init(&hsotg->lock);
443
444 hsotg->irq = platform_get_irq(dev, 0);
445 if (hsotg->irq < 0)
446 return hsotg->irq;
447
448 dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
449 hsotg->irq);
450 retval = devm_request_irq(hsotg->dev, hsotg->irq,
451 dwc2_handle_common_intr, IRQF_SHARED,
452 dev_name(hsotg->dev), hsotg);
453 if (retval)
454 return retval;
455
456 hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus");
457 if (IS_ERR(hsotg->vbus_supply)) {
458 retval = PTR_ERR(hsotg->vbus_supply);
459 hsotg->vbus_supply = NULL;
460 if (retval != -ENODEV)
461 return retval;
462 }
463
464 retval = dwc2_lowlevel_hw_enable(hsotg);
465 if (retval)
466 return retval;
467
468 hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
469
470 retval = dwc2_get_dr_mode(hsotg);
471 if (retval)
472 goto error;
473
474 hsotg->need_phy_for_wake =
475 of_property_read_bool(dev->dev.of_node,
476 "snps,need-phy-for-wake");
477
478 /*
479 * Before performing any core related operations
480 * check core version.
481 */
482 retval = dwc2_check_core_version(hsotg);
483 if (retval)
484 goto error;
485
486 /*
487 * Reset before dwc2_get_hwparams() then it could get power-on real
488 * reset value form registers.
489 */
490 retval = dwc2_core_reset(hsotg, false);
491 if (retval)
492 goto error;
493
494 /* Detect config values from hardware */
495 retval = dwc2_get_hwparams(hsotg);
496 if (retval)
497 goto error;
498
499 /*
500 * For OTG cores, set the force mode bits to reflect the value
501 * of dr_mode. Force mode bits should not be touched at any
502 * other time after this.
503 */
504 dwc2_force_dr_mode(hsotg);
505
506 retval = dwc2_init_params(hsotg);
507 if (retval)
508 goto error;
509
510 if (hsotg->params.activate_stm_id_vb_detection) {
511 u32 ggpio;
512
513 hsotg->usb33d = devm_regulator_get(hsotg->dev, "usb33d");
514 if (IS_ERR(hsotg->usb33d)) {
515 retval = PTR_ERR(hsotg->usb33d);
516 if (retval != -EPROBE_DEFER)
517 dev_err(hsotg->dev,
518 "failed to request usb33d supply: %d\n",
519 retval);
520 goto error;
521 }
522 retval = regulator_enable(hsotg->usb33d);
523 if (retval) {
524 dev_err(hsotg->dev,
525 "failed to enable usb33d supply: %d\n", retval);
526 goto error;
527 }
528
529 ggpio = dwc2_readl(hsotg, GGPIO);
530 ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
531 ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
532 dwc2_writel(hsotg, ggpio, GGPIO);
533
534 /* ID/VBUS detection startup time */
535 usleep_range(5000, 7000);
536 }
537
538 retval = dwc2_drd_init(hsotg);
539 if (retval) {
540 if (retval != -EPROBE_DEFER)
541 dev_err(hsotg->dev, "failed to initialize dual-role\n");
542 goto error_init;
543 }
544
545 if (hsotg->dr_mode != USB_DR_MODE_HOST) {
546 retval = dwc2_gadget_init(hsotg);
547 if (retval)
548 goto error_drd;
549 hsotg->gadget_enabled = 1;
550 }
551
552 /*
553 * If we need PHY for wakeup we must be wakeup capable.
554 * When we have a device that can wake without the PHY we
555 * can adjust this condition.
556 */
557 if (hsotg->need_phy_for_wake)
558 device_set_wakeup_capable(&dev->dev, true);
559
560 hsotg->reset_phy_on_wake =
561 of_property_read_bool(dev->dev.of_node,
562 "snps,reset-phy-on-wake");
563 if (hsotg->reset_phy_on_wake && !hsotg->phy) {
564 dev_warn(hsotg->dev,
565 "Quirk reset-phy-on-wake only supports generic PHYs\n");
566 hsotg->reset_phy_on_wake = false;
567 }
568
569 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
570 retval = dwc2_hcd_init(hsotg);
571 if (retval) {
572 if (hsotg->gadget_enabled)
573 dwc2_hsotg_remove(hsotg);
574 goto error_drd;
575 }
576 hsotg->hcd_enabled = 1;
577 }
578
579 platform_set_drvdata(dev, hsotg);
580 hsotg->hibernated = 0;
581
582 dwc2_debugfs_init(hsotg);
583
584 /* Gadget code manages lowlevel hw on its own */
585 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
586 dwc2_lowlevel_hw_disable(hsotg);
587
588 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
589 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
590 /* Postponed adding a new gadget to the udc class driver list */
591 if (hsotg->gadget_enabled) {
592 retval = usb_add_gadget_udc(hsotg->dev, &hsotg->gadget);
593 if (retval) {
594 hsotg->gadget.udc = NULL;
595 dwc2_hsotg_remove(hsotg);
596 goto error_debugfs;
597 }
598 }
599 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
600 return 0;
601
602 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
603 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
604 error_debugfs:
605 dwc2_debugfs_exit(hsotg);
606 if (hsotg->hcd_enabled)
607 dwc2_hcd_remove(hsotg);
608 #endif
609 error_drd:
610 dwc2_drd_exit(hsotg);
611
612 error_init:
613 if (hsotg->params.activate_stm_id_vb_detection)
614 regulator_disable(hsotg->usb33d);
615 error:
616 if (hsotg->ll_hw_enabled)
617 dwc2_lowlevel_hw_disable(hsotg);
618 return retval;
619 }
620
dwc2_suspend(struct device * dev)621 static int __maybe_unused dwc2_suspend(struct device *dev)
622 {
623 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
624 bool is_device_mode = dwc2_is_device_mode(dwc2);
625 int ret = 0;
626
627 if (is_device_mode)
628 dwc2_hsotg_suspend(dwc2);
629
630 dwc2_drd_suspend(dwc2);
631
632 if (dwc2->params.activate_stm_id_vb_detection) {
633 unsigned long flags;
634 u32 ggpio, gotgctl;
635
636 /*
637 * Need to force the mode to the current mode to avoid Mode
638 * Mismatch Interrupt when ID detection will be disabled.
639 */
640 dwc2_force_mode(dwc2, !is_device_mode);
641
642 spin_lock_irqsave(&dwc2->lock, flags);
643 gotgctl = dwc2_readl(dwc2, GOTGCTL);
644 /* bypass debounce filter, enable overrides */
645 gotgctl |= GOTGCTL_DBNCE_FLTR_BYPASS;
646 gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_AVALOEN;
647 /* Force A / B session if needed */
648 if (gotgctl & GOTGCTL_ASESVLD)
649 gotgctl |= GOTGCTL_AVALOVAL;
650 if (gotgctl & GOTGCTL_BSESVLD)
651 gotgctl |= GOTGCTL_BVALOVAL;
652 dwc2_writel(dwc2, gotgctl, GOTGCTL);
653 spin_unlock_irqrestore(&dwc2->lock, flags);
654
655 ggpio = dwc2_readl(dwc2, GGPIO);
656 ggpio &= ~GGPIO_STM32_OTG_GCCFG_IDEN;
657 ggpio &= ~GGPIO_STM32_OTG_GCCFG_VBDEN;
658 dwc2_writel(dwc2, ggpio, GGPIO);
659
660 regulator_disable(dwc2->usb33d);
661 }
662
663 if (dwc2->ll_hw_enabled &&
664 (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) {
665 ret = __dwc2_lowlevel_hw_disable(dwc2);
666 dwc2->phy_off_for_suspend = true;
667 }
668
669 return ret;
670 }
671
dwc2_resume(struct device * dev)672 static int __maybe_unused dwc2_resume(struct device *dev)
673 {
674 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
675 int ret = 0;
676
677 if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) {
678 ret = __dwc2_lowlevel_hw_enable(dwc2);
679 if (ret)
680 return ret;
681 }
682 dwc2->phy_off_for_suspend = false;
683
684 if (dwc2->params.activate_stm_id_vb_detection) {
685 unsigned long flags;
686 u32 ggpio, gotgctl;
687
688 ret = regulator_enable(dwc2->usb33d);
689 if (ret)
690 return ret;
691
692 ggpio = dwc2_readl(dwc2, GGPIO);
693 ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
694 ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
695 dwc2_writel(dwc2, ggpio, GGPIO);
696
697 /* ID/VBUS detection startup time */
698 usleep_range(5000, 7000);
699
700 spin_lock_irqsave(&dwc2->lock, flags);
701 gotgctl = dwc2_readl(dwc2, GOTGCTL);
702 gotgctl &= ~GOTGCTL_DBNCE_FLTR_BYPASS;
703 gotgctl &= ~(GOTGCTL_BVALOEN | GOTGCTL_AVALOEN |
704 GOTGCTL_BVALOVAL | GOTGCTL_AVALOVAL);
705 dwc2_writel(dwc2, gotgctl, GOTGCTL);
706 spin_unlock_irqrestore(&dwc2->lock, flags);
707 }
708
709 /* Need to restore FORCEDEVMODE/FORCEHOSTMODE */
710 dwc2_force_dr_mode(dwc2);
711
712 dwc2_drd_resume(dwc2);
713
714 if (dwc2_is_device_mode(dwc2))
715 ret = dwc2_hsotg_resume(dwc2);
716
717 return ret;
718 }
719
720 static const struct dev_pm_ops dwc2_dev_pm_ops = {
721 SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
722 };
723
724 static struct platform_driver dwc2_platform_driver = {
725 .driver = {
726 .name = dwc2_driver_name,
727 .of_match_table = dwc2_of_match_table,
728 .pm = &dwc2_dev_pm_ops,
729 },
730 .probe = dwc2_driver_probe,
731 .remove = dwc2_driver_remove,
732 .shutdown = dwc2_driver_shutdown,
733 };
734
735 module_platform_driver(dwc2_platform_driver);
736
737 MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
738 MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
739 MODULE_LICENSE("Dual BSD/GPL");
740