1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 /* 82562G 10/100 Network Connection
5 * 82562G-2 10/100 Network Connection
6 * 82562GT 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
8 * 82562V 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
11 * 82566DC Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
13 * 82566DM Gigabit Network Connection
14 * 82566MC Gigabit Network Connection
15 * 82566MM Gigabit Network Connection
16 * 82567LM Gigabit Network Connection
17 * 82567LF Gigabit Network Connection
18 * 82567V Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
22 * 82567LF-3 Gigabit Network Connection
23 * 82567LM-3 Gigabit Network Connection
24 * 82567LM-4 Gigabit Network Connection
25 * 82577LM Gigabit Network Connection
26 * 82577LC Gigabit Network Connection
27 * 82578DM Gigabit Network Connection
28 * 82578DC Gigabit Network Connection
29 * 82579LM Gigabit Network Connection
30 * 82579V Gigabit Network Connection
31 * Ethernet Connection I217-LM
32 * Ethernet Connection I217-V
33 * Ethernet Connection I218-V
34 * Ethernet Connection I218-LM
35 * Ethernet Connection (2) I218-LM
36 * Ethernet Connection (2) I218-V
37 * Ethernet Connection (3) I218-LM
38 * Ethernet Connection (3) I218-V
39 */
40
41 #include "e1000.h"
42
43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
44 /* Offset 04h HSFSTS */
45 union ich8_hws_flash_status {
46 struct ich8_hsfsts {
47 u16 flcdone:1; /* bit 0 Flash Cycle Done */
48 u16 flcerr:1; /* bit 1 Flash Cycle Error */
49 u16 dael:1; /* bit 2 Direct Access error Log */
50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
52 u16 reserved1:2; /* bit 13:6 Reserved */
53 u16 reserved2:6; /* bit 13:6 Reserved */
54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
56 } hsf_status;
57 u16 regval;
58 };
59
60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
61 /* Offset 06h FLCTL */
62 union ich8_hws_flash_ctrl {
63 struct ich8_hsflctl {
64 u16 flcgo:1; /* 0 Flash Cycle Go */
65 u16 flcycle:2; /* 2:1 Flash Cycle */
66 u16 reserved:5; /* 7:3 Reserved */
67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
68 u16 flockdn:6; /* 15:10 Reserved */
69 } hsf_ctrl;
70 u16 regval;
71 };
72
73 /* ICH Flash Region Access Permissions */
74 union ich8_hws_flash_regacc {
75 struct ich8_flracc {
76 u32 grra:8; /* 0:7 GbE region Read Access */
77 u32 grwa:8; /* 8:15 GbE region Write Access */
78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
80 } hsf_flregacc;
81 u16 regval;
82 };
83
84 /* ICH Flash Protected Region */
85 union ich8_flash_protected_range {
86 struct ich8_pr {
87 u32 base:13; /* 0:12 Protected Range Base */
88 u32 reserved1:2; /* 13:14 Reserved */
89 u32 rpe:1; /* 15 Read Protection Enable */
90 u32 limit:13; /* 16:28 Protected Range Limit */
91 u32 reserved2:2; /* 29:30 Reserved */
92 u32 wpe:1; /* 31 Write Protection Enable */
93 } range;
94 u32 regval;
95 };
96
97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
101 u32 offset, u8 byte);
102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
103 u8 *data);
104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
105 u16 *data);
106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
107 u8 size, u16 *data);
108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
109 u32 *data);
110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
111 u32 offset, u32 *data);
112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
113 u32 offset, u32 data);
114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
115 u32 offset, u32 dword);
116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
140
__er16flash(struct e1000_hw * hw,unsigned long reg)141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
142 {
143 return readw(hw->flash_address + reg);
144 }
145
__er32flash(struct e1000_hw * hw,unsigned long reg)146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
147 {
148 return readl(hw->flash_address + reg);
149 }
150
__ew16flash(struct e1000_hw * hw,unsigned long reg,u16 val)151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
152 {
153 writew(val, hw->flash_address + reg);
154 }
155
__ew32flash(struct e1000_hw * hw,unsigned long reg,u32 val)156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
157 {
158 writel(val, hw->flash_address + reg);
159 }
160
161 #define er16flash(reg) __er16flash(hw, (reg))
162 #define er32flash(reg) __er32flash(hw, (reg))
163 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
164 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
165
166 /**
167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
168 * @hw: pointer to the HW structure
169 *
170 * Test access to the PHY registers by reading the PHY ID registers. If
171 * the PHY ID is already known (e.g. resume path) compare it with known ID,
172 * otherwise assume the read PHY ID is correct if it is valid.
173 *
174 * Assumes the sw/fw/hw semaphore is already acquired.
175 **/
e1000_phy_is_accessible_pchlan(struct e1000_hw * hw)176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
177 {
178 u16 phy_reg = 0;
179 u32 phy_id = 0;
180 s32 ret_val = 0;
181 u16 retry_count;
182 u32 mac_reg = 0;
183
184 for (retry_count = 0; retry_count < 2; retry_count++) {
185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
186 if (ret_val || (phy_reg == 0xFFFF))
187 continue;
188 phy_id = (u32)(phy_reg << 16);
189
190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
191 if (ret_val || (phy_reg == 0xFFFF)) {
192 phy_id = 0;
193 continue;
194 }
195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
196 break;
197 }
198
199 if (hw->phy.id) {
200 if (hw->phy.id == phy_id)
201 goto out;
202 } else if (phy_id) {
203 hw->phy.id = phy_id;
204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
205 goto out;
206 }
207
208 /* In case the PHY needs to be in mdio slow mode,
209 * set slow mode and try to get the PHY id again.
210 */
211 if (hw->mac.type < e1000_pch_lpt) {
212 hw->phy.ops.release(hw);
213 ret_val = e1000_set_mdio_slow_mode_hv(hw);
214 if (!ret_val)
215 ret_val = e1000e_get_phy_id(hw);
216 hw->phy.ops.acquire(hw);
217 }
218
219 if (ret_val)
220 return false;
221 out:
222 if (hw->mac.type >= e1000_pch_lpt) {
223 /* Only unforce SMBus if ME is not active */
224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
225 /* Unforce SMBus mode in PHY */
226 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
227 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
228 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
229
230 /* Unforce SMBus mode in MAC */
231 mac_reg = er32(CTRL_EXT);
232 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
233 ew32(CTRL_EXT, mac_reg);
234 }
235 }
236
237 return true;
238 }
239
240 /**
241 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
242 * @hw: pointer to the HW structure
243 *
244 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
245 * used to reset the PHY to a quiescent state when necessary.
246 **/
e1000_toggle_lanphypc_pch_lpt(struct e1000_hw * hw)247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
248 {
249 u32 mac_reg;
250
251 /* Set Phy Config Counter to 50msec */
252 mac_reg = er32(FEXTNVM3);
253 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
254 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
255 ew32(FEXTNVM3, mac_reg);
256
257 /* Toggle LANPHYPC Value bit */
258 mac_reg = er32(CTRL);
259 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
260 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
261 ew32(CTRL, mac_reg);
262 e1e_flush();
263 usleep_range(10, 20);
264 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
265 ew32(CTRL, mac_reg);
266 e1e_flush();
267
268 if (hw->mac.type < e1000_pch_lpt) {
269 msleep(50);
270 } else {
271 u16 count = 20;
272
273 do {
274 usleep_range(5000, 6000);
275 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
276
277 msleep(30);
278 }
279 }
280
281 /**
282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
283 * @hw: pointer to the HW structure
284 *
285 * Workarounds/flow necessary for PHY initialization during driver load
286 * and resume paths.
287 **/
e1000_init_phy_workarounds_pchlan(struct e1000_hw * hw)288 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
289 {
290 struct e1000_adapter *adapter = hw->adapter;
291 u32 mac_reg, fwsm = er32(FWSM);
292 s32 ret_val;
293
294 /* Gate automatic PHY configuration by hardware on managed and
295 * non-managed 82579 and newer adapters.
296 */
297 e1000_gate_hw_phy_config_ich8lan(hw, true);
298
299 /* It is not possible to be certain of the current state of ULP
300 * so forcibly disable it.
301 */
302 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
303 ret_val = e1000_disable_ulp_lpt_lp(hw, true);
304 if (ret_val)
305 e_warn("Failed to disable ULP\n");
306
307 ret_val = hw->phy.ops.acquire(hw);
308 if (ret_val) {
309 e_dbg("Failed to initialize PHY flow\n");
310 goto out;
311 }
312
313 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
314 * inaccessible and resetting the PHY is not blocked, toggle the
315 * LANPHYPC Value bit to force the interconnect to PCIe mode.
316 */
317 switch (hw->mac.type) {
318 case e1000_pch_lpt:
319 case e1000_pch_spt:
320 case e1000_pch_cnp:
321 case e1000_pch_tgp:
322 case e1000_pch_adp:
323 case e1000_pch_mtp:
324 if (e1000_phy_is_accessible_pchlan(hw))
325 break;
326
327 /* Before toggling LANPHYPC, see if PHY is accessible by
328 * forcing MAC to SMBus mode first.
329 */
330 mac_reg = er32(CTRL_EXT);
331 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
332 ew32(CTRL_EXT, mac_reg);
333
334 /* Wait 50 milliseconds for MAC to finish any retries
335 * that it might be trying to perform from previous
336 * attempts to acknowledge any phy read requests.
337 */
338 msleep(50);
339
340 fallthrough;
341 case e1000_pch2lan:
342 if (e1000_phy_is_accessible_pchlan(hw))
343 break;
344
345 fallthrough;
346 case e1000_pchlan:
347 if ((hw->mac.type == e1000_pchlan) &&
348 (fwsm & E1000_ICH_FWSM_FW_VALID))
349 break;
350
351 if (hw->phy.ops.check_reset_block(hw)) {
352 e_dbg("Required LANPHYPC toggle blocked by ME\n");
353 ret_val = -E1000_ERR_PHY;
354 break;
355 }
356
357 /* Toggle LANPHYPC Value bit */
358 e1000_toggle_lanphypc_pch_lpt(hw);
359 if (hw->mac.type >= e1000_pch_lpt) {
360 if (e1000_phy_is_accessible_pchlan(hw))
361 break;
362
363 /* Toggling LANPHYPC brings the PHY out of SMBus mode
364 * so ensure that the MAC is also out of SMBus mode
365 */
366 mac_reg = er32(CTRL_EXT);
367 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
368 ew32(CTRL_EXT, mac_reg);
369
370 if (e1000_phy_is_accessible_pchlan(hw))
371 break;
372
373 ret_val = -E1000_ERR_PHY;
374 }
375 break;
376 default:
377 break;
378 }
379
380 hw->phy.ops.release(hw);
381 if (!ret_val) {
382
383 /* Check to see if able to reset PHY. Print error if not */
384 if (hw->phy.ops.check_reset_block(hw)) {
385 e_err("Reset blocked by ME\n");
386 goto out;
387 }
388
389 /* Reset the PHY before any access to it. Doing so, ensures
390 * that the PHY is in a known good state before we read/write
391 * PHY registers. The generic reset is sufficient here,
392 * because we haven't determined the PHY type yet.
393 */
394 ret_val = e1000e_phy_hw_reset_generic(hw);
395 if (ret_val)
396 goto out;
397
398 /* On a successful reset, possibly need to wait for the PHY
399 * to quiesce to an accessible state before returning control
400 * to the calling function. If the PHY does not quiesce, then
401 * return E1000E_BLK_PHY_RESET, as this is the condition that
402 * the PHY is in.
403 */
404 ret_val = hw->phy.ops.check_reset_block(hw);
405 if (ret_val)
406 e_err("ME blocked access to PHY after reset\n");
407 }
408
409 out:
410 /* Ungate automatic PHY configuration on non-managed 82579 */
411 if ((hw->mac.type == e1000_pch2lan) &&
412 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
413 usleep_range(10000, 11000);
414 e1000_gate_hw_phy_config_ich8lan(hw, false);
415 }
416
417 return ret_val;
418 }
419
420 /**
421 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
422 * @hw: pointer to the HW structure
423 *
424 * Initialize family-specific PHY parameters and function pointers.
425 **/
e1000_init_phy_params_pchlan(struct e1000_hw * hw)426 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
427 {
428 struct e1000_phy_info *phy = &hw->phy;
429 s32 ret_val;
430
431 phy->addr = 1;
432 phy->reset_delay_us = 100;
433
434 phy->ops.set_page = e1000_set_page_igp;
435 phy->ops.read_reg = e1000_read_phy_reg_hv;
436 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
437 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
438 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
439 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
440 phy->ops.write_reg = e1000_write_phy_reg_hv;
441 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
442 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
443 phy->ops.power_up = e1000_power_up_phy_copper;
444 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
445 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
446
447 phy->id = e1000_phy_unknown;
448
449 ret_val = e1000_init_phy_workarounds_pchlan(hw);
450 if (ret_val)
451 return ret_val;
452
453 if (phy->id == e1000_phy_unknown)
454 switch (hw->mac.type) {
455 default:
456 ret_val = e1000e_get_phy_id(hw);
457 if (ret_val)
458 return ret_val;
459 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
460 break;
461 fallthrough;
462 case e1000_pch2lan:
463 case e1000_pch_lpt:
464 case e1000_pch_spt:
465 case e1000_pch_cnp:
466 case e1000_pch_tgp:
467 case e1000_pch_adp:
468 case e1000_pch_mtp:
469 /* In case the PHY needs to be in mdio slow mode,
470 * set slow mode and try to get the PHY id again.
471 */
472 ret_val = e1000_set_mdio_slow_mode_hv(hw);
473 if (ret_val)
474 return ret_val;
475 ret_val = e1000e_get_phy_id(hw);
476 if (ret_val)
477 return ret_val;
478 break;
479 }
480 phy->type = e1000e_get_phy_type_from_id(phy->id);
481
482 switch (phy->type) {
483 case e1000_phy_82577:
484 case e1000_phy_82579:
485 case e1000_phy_i217:
486 phy->ops.check_polarity = e1000_check_polarity_82577;
487 phy->ops.force_speed_duplex =
488 e1000_phy_force_speed_duplex_82577;
489 phy->ops.get_cable_length = e1000_get_cable_length_82577;
490 phy->ops.get_info = e1000_get_phy_info_82577;
491 phy->ops.commit = e1000e_phy_sw_reset;
492 break;
493 case e1000_phy_82578:
494 phy->ops.check_polarity = e1000_check_polarity_m88;
495 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
496 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
497 phy->ops.get_info = e1000e_get_phy_info_m88;
498 break;
499 default:
500 ret_val = -E1000_ERR_PHY;
501 break;
502 }
503
504 return ret_val;
505 }
506
507 /**
508 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
509 * @hw: pointer to the HW structure
510 *
511 * Initialize family-specific PHY parameters and function pointers.
512 **/
e1000_init_phy_params_ich8lan(struct e1000_hw * hw)513 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
514 {
515 struct e1000_phy_info *phy = &hw->phy;
516 s32 ret_val;
517 u16 i = 0;
518
519 phy->addr = 1;
520 phy->reset_delay_us = 100;
521
522 phy->ops.power_up = e1000_power_up_phy_copper;
523 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
524
525 /* We may need to do this twice - once for IGP and if that fails,
526 * we'll set BM func pointers and try again
527 */
528 ret_val = e1000e_determine_phy_address(hw);
529 if (ret_val) {
530 phy->ops.write_reg = e1000e_write_phy_reg_bm;
531 phy->ops.read_reg = e1000e_read_phy_reg_bm;
532 ret_val = e1000e_determine_phy_address(hw);
533 if (ret_val) {
534 e_dbg("Cannot determine PHY addr. Erroring out\n");
535 return ret_val;
536 }
537 }
538
539 phy->id = 0;
540 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
541 (i++ < 100)) {
542 usleep_range(1000, 1100);
543 ret_val = e1000e_get_phy_id(hw);
544 if (ret_val)
545 return ret_val;
546 }
547
548 /* Verify phy id */
549 switch (phy->id) {
550 case IGP03E1000_E_PHY_ID:
551 phy->type = e1000_phy_igp_3;
552 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
553 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
554 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
555 phy->ops.get_info = e1000e_get_phy_info_igp;
556 phy->ops.check_polarity = e1000_check_polarity_igp;
557 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
558 break;
559 case IFE_E_PHY_ID:
560 case IFE_PLUS_E_PHY_ID:
561 case IFE_C_E_PHY_ID:
562 phy->type = e1000_phy_ife;
563 phy->autoneg_mask = E1000_ALL_NOT_GIG;
564 phy->ops.get_info = e1000_get_phy_info_ife;
565 phy->ops.check_polarity = e1000_check_polarity_ife;
566 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
567 break;
568 case BME1000_E_PHY_ID:
569 phy->type = e1000_phy_bm;
570 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
571 phy->ops.read_reg = e1000e_read_phy_reg_bm;
572 phy->ops.write_reg = e1000e_write_phy_reg_bm;
573 phy->ops.commit = e1000e_phy_sw_reset;
574 phy->ops.get_info = e1000e_get_phy_info_m88;
575 phy->ops.check_polarity = e1000_check_polarity_m88;
576 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
577 break;
578 default:
579 return -E1000_ERR_PHY;
580 }
581
582 return 0;
583 }
584
585 /**
586 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
587 * @hw: pointer to the HW structure
588 *
589 * Initialize family-specific NVM parameters and function
590 * pointers.
591 **/
e1000_init_nvm_params_ich8lan(struct e1000_hw * hw)592 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
593 {
594 struct e1000_nvm_info *nvm = &hw->nvm;
595 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
596 u32 gfpreg, sector_base_addr, sector_end_addr;
597 u16 i;
598 u32 nvm_size;
599
600 nvm->type = e1000_nvm_flash_sw;
601
602 if (hw->mac.type >= e1000_pch_spt) {
603 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
604 * STRAP register. This is because in SPT the GbE Flash region
605 * is no longer accessed through the flash registers. Instead,
606 * the mechanism has changed, and the Flash region access
607 * registers are now implemented in GbE memory space.
608 */
609 nvm->flash_base_addr = 0;
610 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
611 * NVM_SIZE_MULTIPLIER;
612 nvm->flash_bank_size = nvm_size / 2;
613 /* Adjust to word count */
614 nvm->flash_bank_size /= sizeof(u16);
615 /* Set the base address for flash register access */
616 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
617 } else {
618 /* Can't read flash registers if register set isn't mapped. */
619 if (!hw->flash_address) {
620 e_dbg("ERROR: Flash registers not mapped\n");
621 return -E1000_ERR_CONFIG;
622 }
623
624 gfpreg = er32flash(ICH_FLASH_GFPREG);
625
626 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
627 * Add 1 to sector_end_addr since this sector is included in
628 * the overall size.
629 */
630 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
631 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
632
633 /* flash_base_addr is byte-aligned */
634 nvm->flash_base_addr = sector_base_addr
635 << FLASH_SECTOR_ADDR_SHIFT;
636
637 /* find total size of the NVM, then cut in half since the total
638 * size represents two separate NVM banks.
639 */
640 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
641 << FLASH_SECTOR_ADDR_SHIFT);
642 nvm->flash_bank_size /= 2;
643 /* Adjust to word count */
644 nvm->flash_bank_size /= sizeof(u16);
645 }
646
647 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
648
649 /* Clear shadow ram */
650 for (i = 0; i < nvm->word_size; i++) {
651 dev_spec->shadow_ram[i].modified = false;
652 dev_spec->shadow_ram[i].value = 0xFFFF;
653 }
654
655 return 0;
656 }
657
658 /**
659 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
660 * @hw: pointer to the HW structure
661 *
662 * Initialize family-specific MAC parameters and function
663 * pointers.
664 **/
e1000_init_mac_params_ich8lan(struct e1000_hw * hw)665 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
666 {
667 struct e1000_mac_info *mac = &hw->mac;
668
669 /* Set media type function pointer */
670 hw->phy.media_type = e1000_media_type_copper;
671
672 /* Set mta register count */
673 mac->mta_reg_count = 32;
674 /* Set rar entry count */
675 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
676 if (mac->type == e1000_ich8lan)
677 mac->rar_entry_count--;
678 /* FWSM register */
679 mac->has_fwsm = true;
680 /* ARC subsystem not supported */
681 mac->arc_subsystem_valid = false;
682 /* Adaptive IFS supported */
683 mac->adaptive_ifs = true;
684
685 /* LED and other operations */
686 switch (mac->type) {
687 case e1000_ich8lan:
688 case e1000_ich9lan:
689 case e1000_ich10lan:
690 /* check management mode */
691 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
692 /* ID LED init */
693 mac->ops.id_led_init = e1000e_id_led_init_generic;
694 /* blink LED */
695 mac->ops.blink_led = e1000e_blink_led_generic;
696 /* setup LED */
697 mac->ops.setup_led = e1000e_setup_led_generic;
698 /* cleanup LED */
699 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
700 /* turn on/off LED */
701 mac->ops.led_on = e1000_led_on_ich8lan;
702 mac->ops.led_off = e1000_led_off_ich8lan;
703 break;
704 case e1000_pch2lan:
705 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
706 mac->ops.rar_set = e1000_rar_set_pch2lan;
707 fallthrough;
708 case e1000_pch_lpt:
709 case e1000_pch_spt:
710 case e1000_pch_cnp:
711 case e1000_pch_tgp:
712 case e1000_pch_adp:
713 case e1000_pch_mtp:
714 case e1000_pchlan:
715 /* check management mode */
716 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
717 /* ID LED init */
718 mac->ops.id_led_init = e1000_id_led_init_pchlan;
719 /* setup LED */
720 mac->ops.setup_led = e1000_setup_led_pchlan;
721 /* cleanup LED */
722 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
723 /* turn on/off LED */
724 mac->ops.led_on = e1000_led_on_pchlan;
725 mac->ops.led_off = e1000_led_off_pchlan;
726 break;
727 default:
728 break;
729 }
730
731 if (mac->type >= e1000_pch_lpt) {
732 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
733 mac->ops.rar_set = e1000_rar_set_pch_lpt;
734 mac->ops.setup_physical_interface =
735 e1000_setup_copper_link_pch_lpt;
736 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
737 }
738
739 /* Enable PCS Lock-loss workaround for ICH8 */
740 if (mac->type == e1000_ich8lan)
741 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
742
743 return 0;
744 }
745
746 /**
747 * __e1000_access_emi_reg_locked - Read/write EMI register
748 * @hw: pointer to the HW structure
749 * @address: EMI address to program
750 * @data: pointer to value to read/write from/to the EMI address
751 * @read: boolean flag to indicate read or write
752 *
753 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
754 **/
__e1000_access_emi_reg_locked(struct e1000_hw * hw,u16 address,u16 * data,bool read)755 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
756 u16 *data, bool read)
757 {
758 s32 ret_val;
759
760 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
761 if (ret_val)
762 return ret_val;
763
764 if (read)
765 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
766 else
767 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
768
769 return ret_val;
770 }
771
772 /**
773 * e1000_read_emi_reg_locked - Read Extended Management Interface register
774 * @hw: pointer to the HW structure
775 * @addr: EMI address to program
776 * @data: value to be read from the EMI address
777 *
778 * Assumes the SW/FW/HW Semaphore is already acquired.
779 **/
e1000_read_emi_reg_locked(struct e1000_hw * hw,u16 addr,u16 * data)780 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
781 {
782 return __e1000_access_emi_reg_locked(hw, addr, data, true);
783 }
784
785 /**
786 * e1000_write_emi_reg_locked - Write Extended Management Interface register
787 * @hw: pointer to the HW structure
788 * @addr: EMI address to program
789 * @data: value to be written to the EMI address
790 *
791 * Assumes the SW/FW/HW Semaphore is already acquired.
792 **/
e1000_write_emi_reg_locked(struct e1000_hw * hw,u16 addr,u16 data)793 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
794 {
795 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
796 }
797
798 /**
799 * e1000_set_eee_pchlan - Enable/disable EEE support
800 * @hw: pointer to the HW structure
801 *
802 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
803 * the link and the EEE capabilities of the link partner. The LPI Control
804 * register bits will remain set only if/when link is up.
805 *
806 * EEE LPI must not be asserted earlier than one second after link is up.
807 * On 82579, EEE LPI should not be enabled until such time otherwise there
808 * can be link issues with some switches. Other devices can have EEE LPI
809 * enabled immediately upon link up since they have a timer in hardware which
810 * prevents LPI from being asserted too early.
811 **/
e1000_set_eee_pchlan(struct e1000_hw * hw)812 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
813 {
814 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
815 s32 ret_val;
816 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
817
818 switch (hw->phy.type) {
819 case e1000_phy_82579:
820 lpa = I82579_EEE_LP_ABILITY;
821 pcs_status = I82579_EEE_PCS_STATUS;
822 adv_addr = I82579_EEE_ADVERTISEMENT;
823 break;
824 case e1000_phy_i217:
825 lpa = I217_EEE_LP_ABILITY;
826 pcs_status = I217_EEE_PCS_STATUS;
827 adv_addr = I217_EEE_ADVERTISEMENT;
828 break;
829 default:
830 return 0;
831 }
832
833 ret_val = hw->phy.ops.acquire(hw);
834 if (ret_val)
835 return ret_val;
836
837 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
838 if (ret_val)
839 goto release;
840
841 /* Clear bits that enable EEE in various speeds */
842 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
843
844 /* Enable EEE if not disabled by user */
845 if (!dev_spec->eee_disable) {
846 /* Save off link partner's EEE ability */
847 ret_val = e1000_read_emi_reg_locked(hw, lpa,
848 &dev_spec->eee_lp_ability);
849 if (ret_val)
850 goto release;
851
852 /* Read EEE advertisement */
853 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
854 if (ret_val)
855 goto release;
856
857 /* Enable EEE only for speeds in which the link partner is
858 * EEE capable and for which we advertise EEE.
859 */
860 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
861 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
862
863 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
864 e1e_rphy_locked(hw, MII_LPA, &data);
865 if (data & LPA_100FULL)
866 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
867 else
868 /* EEE is not supported in 100Half, so ignore
869 * partner's EEE in 100 ability if full-duplex
870 * is not advertised.
871 */
872 dev_spec->eee_lp_ability &=
873 ~I82579_EEE_100_SUPPORTED;
874 }
875 }
876
877 if (hw->phy.type == e1000_phy_82579) {
878 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
879 &data);
880 if (ret_val)
881 goto release;
882
883 data &= ~I82579_LPI_100_PLL_SHUT;
884 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
885 data);
886 }
887
888 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
889 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
890 if (ret_val)
891 goto release;
892
893 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
894 release:
895 hw->phy.ops.release(hw);
896
897 return ret_val;
898 }
899
900 /**
901 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
902 * @hw: pointer to the HW structure
903 * @link: link up bool flag
904 *
905 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
906 * preventing further DMA write requests. Workaround the issue by disabling
907 * the de-assertion of the clock request when in 1Gpbs mode.
908 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
909 * speeds in order to avoid Tx hangs.
910 **/
e1000_k1_workaround_lpt_lp(struct e1000_hw * hw,bool link)911 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
912 {
913 u32 fextnvm6 = er32(FEXTNVM6);
914 u32 status = er32(STATUS);
915 s32 ret_val = 0;
916 u16 reg;
917
918 if (link && (status & E1000_STATUS_SPEED_1000)) {
919 ret_val = hw->phy.ops.acquire(hw);
920 if (ret_val)
921 return ret_val;
922
923 ret_val =
924 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
925 ®);
926 if (ret_val)
927 goto release;
928
929 ret_val =
930 e1000e_write_kmrn_reg_locked(hw,
931 E1000_KMRNCTRLSTA_K1_CONFIG,
932 reg &
933 ~E1000_KMRNCTRLSTA_K1_ENABLE);
934 if (ret_val)
935 goto release;
936
937 usleep_range(10, 20);
938
939 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
940
941 ret_val =
942 e1000e_write_kmrn_reg_locked(hw,
943 E1000_KMRNCTRLSTA_K1_CONFIG,
944 reg);
945 release:
946 hw->phy.ops.release(hw);
947 } else {
948 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
949 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
950
951 if ((hw->phy.revision > 5) || !link ||
952 ((status & E1000_STATUS_SPEED_100) &&
953 (status & E1000_STATUS_FD)))
954 goto update_fextnvm6;
955
956 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®);
957 if (ret_val)
958 return ret_val;
959
960 /* Clear link status transmit timeout */
961 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
962
963 if (status & E1000_STATUS_SPEED_100) {
964 /* Set inband Tx timeout to 5x10us for 100Half */
965 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
966
967 /* Do not extend the K1 entry latency for 100Half */
968 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
969 } else {
970 /* Set inband Tx timeout to 50x10us for 10Full/Half */
971 reg |= 50 <<
972 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
973
974 /* Extend the K1 entry latency for 10 Mbps */
975 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
976 }
977
978 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
979 if (ret_val)
980 return ret_val;
981
982 update_fextnvm6:
983 ew32(FEXTNVM6, fextnvm6);
984 }
985
986 return ret_val;
987 }
988
989 /**
990 * e1000_platform_pm_pch_lpt - Set platform power management values
991 * @hw: pointer to the HW structure
992 * @link: bool indicating link status
993 *
994 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
995 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
996 * when link is up (which must not exceed the maximum latency supported
997 * by the platform), otherwise specify there is no LTR requirement.
998 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
999 * latencies in the LTR Extended Capability Structure in the PCIe Extended
1000 * Capability register set, on this device LTR is set by writing the
1001 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1002 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1003 * message to the PMC.
1004 **/
e1000_platform_pm_pch_lpt(struct e1000_hw * hw,bool link)1005 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1006 {
1007 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1008 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1009 u32 max_ltr_enc_d = 0; /* maximum LTR decoded by platform */
1010 u32 lat_enc_d = 0; /* latency decoded */
1011 u16 lat_enc = 0; /* latency encoded */
1012
1013 if (link) {
1014 u16 speed, duplex, scale = 0;
1015 u16 max_snoop, max_nosnoop;
1016 u16 max_ltr_enc; /* max LTR latency encoded */
1017 u64 value;
1018 u32 rxa;
1019
1020 if (!hw->adapter->max_frame_size) {
1021 e_dbg("max_frame_size not set.\n");
1022 return -E1000_ERR_CONFIG;
1023 }
1024
1025 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1026 if (!speed) {
1027 e_dbg("Speed not set.\n");
1028 return -E1000_ERR_CONFIG;
1029 }
1030
1031 /* Rx Packet Buffer Allocation size (KB) */
1032 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1033
1034 /* Determine the maximum latency tolerated by the device.
1035 *
1036 * Per the PCIe spec, the tolerated latencies are encoded as
1037 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1038 * a 10-bit value (0-1023) to provide a range from 1 ns to
1039 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1040 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1041 */
1042 rxa *= 512;
1043 value = (rxa > hw->adapter->max_frame_size) ?
1044 (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1045 0;
1046
1047 while (value > PCI_LTR_VALUE_MASK) {
1048 scale++;
1049 value = DIV_ROUND_UP(value, BIT(5));
1050 }
1051 if (scale > E1000_LTRV_SCALE_MAX) {
1052 e_dbg("Invalid LTR latency scale %d\n", scale);
1053 return -E1000_ERR_CONFIG;
1054 }
1055 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1056
1057 /* Determine the maximum latency tolerated by the platform */
1058 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1059 &max_snoop);
1060 pci_read_config_word(hw->adapter->pdev,
1061 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1062 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1063
1064 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) *
1065 (1U << (E1000_LTRV_SCALE_FACTOR *
1066 ((lat_enc & E1000_LTRV_SCALE_MASK)
1067 >> E1000_LTRV_SCALE_SHIFT)));
1068
1069 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) *
1070 (1U << (E1000_LTRV_SCALE_FACTOR *
1071 ((max_ltr_enc & E1000_LTRV_SCALE_MASK)
1072 >> E1000_LTRV_SCALE_SHIFT)));
1073
1074 if (lat_enc_d > max_ltr_enc_d)
1075 lat_enc = max_ltr_enc;
1076 }
1077
1078 /* Set Snoop and No-Snoop latencies the same */
1079 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1080 ew32(LTRV, reg);
1081
1082 return 0;
1083 }
1084
1085 /**
1086 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1087 * @hw: pointer to the HW structure
1088 * @to_sx: boolean indicating a system power state transition to Sx
1089 *
1090 * When link is down, configure ULP mode to significantly reduce the power
1091 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1092 * ME firmware to start the ULP configuration. If not on an ME enabled
1093 * system, configure the ULP mode by software.
1094 */
e1000_enable_ulp_lpt_lp(struct e1000_hw * hw,bool to_sx)1095 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1096 {
1097 u32 mac_reg;
1098 s32 ret_val = 0;
1099 u16 phy_reg;
1100 u16 oem_reg = 0;
1101
1102 if ((hw->mac.type < e1000_pch_lpt) ||
1103 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1104 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1105 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1106 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1107 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1108 return 0;
1109
1110 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1111 /* Request ME configure ULP mode in the PHY */
1112 mac_reg = er32(H2ME);
1113 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1114 ew32(H2ME, mac_reg);
1115
1116 goto out;
1117 }
1118
1119 if (!to_sx) {
1120 int i = 0;
1121
1122 /* Poll up to 5 seconds for Cable Disconnected indication */
1123 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1124 /* Bail if link is re-acquired */
1125 if (er32(STATUS) & E1000_STATUS_LU)
1126 return -E1000_ERR_PHY;
1127
1128 if (i++ == 100)
1129 break;
1130
1131 msleep(50);
1132 }
1133 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1134 (er32(FEXT) &
1135 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1136 }
1137
1138 ret_val = hw->phy.ops.acquire(hw);
1139 if (ret_val)
1140 goto out;
1141
1142 /* Force SMBus mode in PHY */
1143 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1144 if (ret_val)
1145 goto release;
1146 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1147 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1148
1149 /* Force SMBus mode in MAC */
1150 mac_reg = er32(CTRL_EXT);
1151 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1152 ew32(CTRL_EXT, mac_reg);
1153
1154 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1155 * LPLU and disable Gig speed when entering ULP
1156 */
1157 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1158 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1159 &oem_reg);
1160 if (ret_val)
1161 goto release;
1162
1163 phy_reg = oem_reg;
1164 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1165
1166 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1167 phy_reg);
1168
1169 if (ret_val)
1170 goto release;
1171 }
1172
1173 /* Set Inband ULP Exit, Reset to SMBus mode and
1174 * Disable SMBus Release on PERST# in PHY
1175 */
1176 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1177 if (ret_val)
1178 goto release;
1179 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1180 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1181 if (to_sx) {
1182 if (er32(WUFC) & E1000_WUFC_LNKC)
1183 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1184 else
1185 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1186
1187 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1188 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1189 } else {
1190 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1191 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1192 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1193 }
1194 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1195
1196 /* Set Disable SMBus Release on PERST# in MAC */
1197 mac_reg = er32(FEXTNVM7);
1198 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1199 ew32(FEXTNVM7, mac_reg);
1200
1201 /* Commit ULP changes in PHY by starting auto ULP configuration */
1202 phy_reg |= I218_ULP_CONFIG1_START;
1203 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1204
1205 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1206 to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1207 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1208 oem_reg);
1209 if (ret_val)
1210 goto release;
1211 }
1212
1213 release:
1214 hw->phy.ops.release(hw);
1215 out:
1216 if (ret_val)
1217 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1218 else
1219 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1220
1221 return ret_val;
1222 }
1223
1224 /**
1225 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1226 * @hw: pointer to the HW structure
1227 * @force: boolean indicating whether or not to force disabling ULP
1228 *
1229 * Un-configure ULP mode when link is up, the system is transitioned from
1230 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1231 * system, poll for an indication from ME that ULP has been un-configured.
1232 * If not on an ME enabled system, un-configure the ULP mode by software.
1233 *
1234 * During nominal operation, this function is called when link is acquired
1235 * to disable ULP mode (force=false); otherwise, for example when unloading
1236 * the driver or during Sx->S0 transitions, this is called with force=true
1237 * to forcibly disable ULP.
1238 */
e1000_disable_ulp_lpt_lp(struct e1000_hw * hw,bool force)1239 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1240 {
1241 s32 ret_val = 0;
1242 u32 mac_reg;
1243 u16 phy_reg;
1244 int i = 0;
1245
1246 if ((hw->mac.type < e1000_pch_lpt) ||
1247 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1248 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1249 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1250 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1251 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1252 return 0;
1253
1254 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1255 struct e1000_adapter *adapter = hw->adapter;
1256 bool firmware_bug = false;
1257
1258 if (force) {
1259 /* Request ME un-configure ULP mode in the PHY */
1260 mac_reg = er32(H2ME);
1261 mac_reg &= ~E1000_H2ME_ULP;
1262 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1263 ew32(H2ME, mac_reg);
1264 }
1265
1266 /* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE.
1267 * If this takes more than 1 second, show a warning indicating a
1268 * firmware bug
1269 */
1270 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1271 if (i++ == 250) {
1272 ret_val = -E1000_ERR_PHY;
1273 goto out;
1274 }
1275 if (i > 100 && !firmware_bug)
1276 firmware_bug = true;
1277
1278 usleep_range(10000, 11000);
1279 }
1280 if (firmware_bug)
1281 e_warn("ULP_CONFIG_DONE took %dmsec. This is a firmware bug\n", i * 10);
1282 else
1283 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1284
1285 if (force) {
1286 mac_reg = er32(H2ME);
1287 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1288 ew32(H2ME, mac_reg);
1289 } else {
1290 /* Clear H2ME.ULP after ME ULP configuration */
1291 mac_reg = er32(H2ME);
1292 mac_reg &= ~E1000_H2ME_ULP;
1293 ew32(H2ME, mac_reg);
1294 }
1295
1296 goto out;
1297 }
1298
1299 ret_val = hw->phy.ops.acquire(hw);
1300 if (ret_val)
1301 goto out;
1302
1303 if (force)
1304 /* Toggle LANPHYPC Value bit */
1305 e1000_toggle_lanphypc_pch_lpt(hw);
1306
1307 /* Unforce SMBus mode in PHY */
1308 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1309 if (ret_val) {
1310 /* The MAC might be in PCIe mode, so temporarily force to
1311 * SMBus mode in order to access the PHY.
1312 */
1313 mac_reg = er32(CTRL_EXT);
1314 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1315 ew32(CTRL_EXT, mac_reg);
1316
1317 msleep(50);
1318
1319 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1320 &phy_reg);
1321 if (ret_val)
1322 goto release;
1323 }
1324 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1325 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1326
1327 /* Unforce SMBus mode in MAC */
1328 mac_reg = er32(CTRL_EXT);
1329 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1330 ew32(CTRL_EXT, mac_reg);
1331
1332 /* When ULP mode was previously entered, K1 was disabled by the
1333 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1334 */
1335 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1336 if (ret_val)
1337 goto release;
1338 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1339 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1340
1341 /* Clear ULP enabled configuration */
1342 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1343 if (ret_val)
1344 goto release;
1345 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1346 I218_ULP_CONFIG1_STICKY_ULP |
1347 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1348 I218_ULP_CONFIG1_WOL_HOST |
1349 I218_ULP_CONFIG1_INBAND_EXIT |
1350 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1351 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1352 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1353 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1354
1355 /* Commit ULP changes by starting auto ULP configuration */
1356 phy_reg |= I218_ULP_CONFIG1_START;
1357 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1358
1359 /* Clear Disable SMBus Release on PERST# in MAC */
1360 mac_reg = er32(FEXTNVM7);
1361 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1362 ew32(FEXTNVM7, mac_reg);
1363
1364 release:
1365 hw->phy.ops.release(hw);
1366 if (force) {
1367 e1000_phy_hw_reset(hw);
1368 msleep(50);
1369 }
1370 out:
1371 if (ret_val)
1372 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1373 else
1374 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1375
1376 return ret_val;
1377 }
1378
1379 /**
1380 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1381 * @hw: pointer to the HW structure
1382 *
1383 * Checks to see of the link status of the hardware has changed. If a
1384 * change in link status has been detected, then we read the PHY registers
1385 * to get the current speed/duplex if link exists.
1386 **/
e1000_check_for_copper_link_ich8lan(struct e1000_hw * hw)1387 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1388 {
1389 struct e1000_mac_info *mac = &hw->mac;
1390 s32 ret_val, tipg_reg = 0;
1391 u16 emi_addr, emi_val = 0;
1392 bool link;
1393 u16 phy_reg;
1394
1395 /* We only want to go out to the PHY registers to see if Auto-Neg
1396 * has completed and/or if our link status has changed. The
1397 * get_link_status flag is set upon receiving a Link Status
1398 * Change or Rx Sequence Error interrupt.
1399 */
1400 if (!mac->get_link_status)
1401 return 0;
1402 mac->get_link_status = false;
1403
1404 /* First we want to see if the MII Status Register reports
1405 * link. If so, then we want to get the current speed/duplex
1406 * of the PHY.
1407 */
1408 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1409 if (ret_val)
1410 goto out;
1411
1412 if (hw->mac.type == e1000_pchlan) {
1413 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1414 if (ret_val)
1415 goto out;
1416 }
1417
1418 /* When connected at 10Mbps half-duplex, some parts are excessively
1419 * aggressive resulting in many collisions. To avoid this, increase
1420 * the IPG and reduce Rx latency in the PHY.
1421 */
1422 if ((hw->mac.type >= e1000_pch2lan) && link) {
1423 u16 speed, duplex;
1424
1425 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1426 tipg_reg = er32(TIPG);
1427 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1428
1429 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1430 tipg_reg |= 0xFF;
1431 /* Reduce Rx latency in analog PHY */
1432 emi_val = 0;
1433 } else if (hw->mac.type >= e1000_pch_spt &&
1434 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1435 tipg_reg |= 0xC;
1436 emi_val = 1;
1437 } else {
1438
1439 /* Roll back the default values */
1440 tipg_reg |= 0x08;
1441 emi_val = 1;
1442 }
1443
1444 ew32(TIPG, tipg_reg);
1445
1446 ret_val = hw->phy.ops.acquire(hw);
1447 if (ret_val)
1448 goto out;
1449
1450 if (hw->mac.type == e1000_pch2lan)
1451 emi_addr = I82579_RX_CONFIG;
1452 else
1453 emi_addr = I217_RX_CONFIG;
1454 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1455
1456 if (hw->mac.type >= e1000_pch_lpt) {
1457 u16 phy_reg;
1458
1459 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1460 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1461 if (speed == SPEED_100 || speed == SPEED_10)
1462 phy_reg |= 0x3E8;
1463 else
1464 phy_reg |= 0xFA;
1465 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1466
1467 if (speed == SPEED_1000) {
1468 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1469 &phy_reg);
1470
1471 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1472
1473 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1474 phy_reg);
1475 }
1476 }
1477 hw->phy.ops.release(hw);
1478
1479 if (ret_val)
1480 goto out;
1481
1482 if (hw->mac.type >= e1000_pch_spt) {
1483 u16 data;
1484 u16 ptr_gap;
1485
1486 if (speed == SPEED_1000) {
1487 ret_val = hw->phy.ops.acquire(hw);
1488 if (ret_val)
1489 goto out;
1490
1491 ret_val = e1e_rphy_locked(hw,
1492 PHY_REG(776, 20),
1493 &data);
1494 if (ret_val) {
1495 hw->phy.ops.release(hw);
1496 goto out;
1497 }
1498
1499 ptr_gap = (data & (0x3FF << 2)) >> 2;
1500 if (ptr_gap < 0x18) {
1501 data &= ~(0x3FF << 2);
1502 data |= (0x18 << 2);
1503 ret_val =
1504 e1e_wphy_locked(hw,
1505 PHY_REG(776, 20),
1506 data);
1507 }
1508 hw->phy.ops.release(hw);
1509 if (ret_val)
1510 goto out;
1511 } else {
1512 ret_val = hw->phy.ops.acquire(hw);
1513 if (ret_val)
1514 goto out;
1515
1516 ret_val = e1e_wphy_locked(hw,
1517 PHY_REG(776, 20),
1518 0xC023);
1519 hw->phy.ops.release(hw);
1520 if (ret_val)
1521 goto out;
1522
1523 }
1524 }
1525 }
1526
1527 /* I217 Packet Loss issue:
1528 * ensure that FEXTNVM4 Beacon Duration is set correctly
1529 * on power up.
1530 * Set the Beacon Duration for I217 to 8 usec
1531 */
1532 if (hw->mac.type >= e1000_pch_lpt) {
1533 u32 mac_reg;
1534
1535 mac_reg = er32(FEXTNVM4);
1536 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1537 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1538 ew32(FEXTNVM4, mac_reg);
1539 }
1540
1541 /* Work-around I218 hang issue */
1542 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1543 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1544 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1545 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1546 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1547 if (ret_val)
1548 goto out;
1549 }
1550 if (hw->mac.type >= e1000_pch_lpt) {
1551 /* Set platform power management values for
1552 * Latency Tolerance Reporting (LTR)
1553 */
1554 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1555 if (ret_val)
1556 goto out;
1557 }
1558
1559 /* Clear link partner's EEE ability */
1560 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1561
1562 if (hw->mac.type >= e1000_pch_lpt) {
1563 u32 fextnvm6 = er32(FEXTNVM6);
1564
1565 if (hw->mac.type == e1000_pch_spt) {
1566 /* FEXTNVM6 K1-off workaround - for SPT only */
1567 u32 pcieanacfg = er32(PCIEANACFG);
1568
1569 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1570 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1571 else
1572 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1573 }
1574
1575 ew32(FEXTNVM6, fextnvm6);
1576 }
1577
1578 if (!link)
1579 goto out;
1580
1581 switch (hw->mac.type) {
1582 case e1000_pch2lan:
1583 ret_val = e1000_k1_workaround_lv(hw);
1584 if (ret_val)
1585 return ret_val;
1586 fallthrough;
1587 case e1000_pchlan:
1588 if (hw->phy.type == e1000_phy_82578) {
1589 ret_val = e1000_link_stall_workaround_hv(hw);
1590 if (ret_val)
1591 return ret_val;
1592 }
1593
1594 /* Workaround for PCHx parts in half-duplex:
1595 * Set the number of preambles removed from the packet
1596 * when it is passed from the PHY to the MAC to prevent
1597 * the MAC from misinterpreting the packet type.
1598 */
1599 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1600 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1601
1602 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1603 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1604
1605 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1606 break;
1607 default:
1608 break;
1609 }
1610
1611 /* Check if there was DownShift, must be checked
1612 * immediately after link-up
1613 */
1614 e1000e_check_downshift(hw);
1615
1616 /* Enable/Disable EEE after link up */
1617 if (hw->phy.type > e1000_phy_82579) {
1618 ret_val = e1000_set_eee_pchlan(hw);
1619 if (ret_val)
1620 return ret_val;
1621 }
1622
1623 /* If we are forcing speed/duplex, then we simply return since
1624 * we have already determined whether we have link or not.
1625 */
1626 if (!mac->autoneg)
1627 return -E1000_ERR_CONFIG;
1628
1629 /* Auto-Neg is enabled. Auto Speed Detection takes care
1630 * of MAC speed/duplex configuration. So we only need to
1631 * configure Collision Distance in the MAC.
1632 */
1633 mac->ops.config_collision_dist(hw);
1634
1635 /* Configure Flow Control now that Auto-Neg has completed.
1636 * First, we need to restore the desired flow control
1637 * settings because we may have had to re-autoneg with a
1638 * different link partner.
1639 */
1640 ret_val = e1000e_config_fc_after_link_up(hw);
1641 if (ret_val)
1642 e_dbg("Error configuring flow control\n");
1643
1644 return ret_val;
1645
1646 out:
1647 mac->get_link_status = true;
1648 return ret_val;
1649 }
1650
e1000_get_variants_ich8lan(struct e1000_adapter * adapter)1651 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1652 {
1653 struct e1000_hw *hw = &adapter->hw;
1654 s32 rc;
1655
1656 rc = e1000_init_mac_params_ich8lan(hw);
1657 if (rc)
1658 return rc;
1659
1660 rc = e1000_init_nvm_params_ich8lan(hw);
1661 if (rc)
1662 return rc;
1663
1664 switch (hw->mac.type) {
1665 case e1000_ich8lan:
1666 case e1000_ich9lan:
1667 case e1000_ich10lan:
1668 rc = e1000_init_phy_params_ich8lan(hw);
1669 break;
1670 case e1000_pchlan:
1671 case e1000_pch2lan:
1672 case e1000_pch_lpt:
1673 case e1000_pch_spt:
1674 case e1000_pch_cnp:
1675 case e1000_pch_tgp:
1676 case e1000_pch_adp:
1677 case e1000_pch_mtp:
1678 rc = e1000_init_phy_params_pchlan(hw);
1679 break;
1680 default:
1681 break;
1682 }
1683 if (rc)
1684 return rc;
1685
1686 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1687 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1688 */
1689 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1690 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1691 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1692 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1693 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1694
1695 hw->mac.ops.blink_led = NULL;
1696 }
1697
1698 if ((adapter->hw.mac.type == e1000_ich8lan) &&
1699 (adapter->hw.phy.type != e1000_phy_ife))
1700 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1701
1702 /* Enable workaround for 82579 w/ ME enabled */
1703 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1704 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1705 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1706
1707 return 0;
1708 }
1709
1710 static DEFINE_MUTEX(nvm_mutex);
1711
1712 /**
1713 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1714 * @hw: pointer to the HW structure
1715 *
1716 * Acquires the mutex for performing NVM operations.
1717 **/
e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused * hw)1718 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1719 {
1720 mutex_lock(&nvm_mutex);
1721
1722 return 0;
1723 }
1724
1725 /**
1726 * e1000_release_nvm_ich8lan - Release NVM mutex
1727 * @hw: pointer to the HW structure
1728 *
1729 * Releases the mutex used while performing NVM operations.
1730 **/
e1000_release_nvm_ich8lan(struct e1000_hw __always_unused * hw)1731 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1732 {
1733 mutex_unlock(&nvm_mutex);
1734 }
1735
1736 /**
1737 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1738 * @hw: pointer to the HW structure
1739 *
1740 * Acquires the software control flag for performing PHY and select
1741 * MAC CSR accesses.
1742 **/
e1000_acquire_swflag_ich8lan(struct e1000_hw * hw)1743 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1744 {
1745 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1746 s32 ret_val = 0;
1747
1748 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1749 &hw->adapter->state)) {
1750 e_dbg("contention for Phy access\n");
1751 return -E1000_ERR_PHY;
1752 }
1753
1754 while (timeout) {
1755 extcnf_ctrl = er32(EXTCNF_CTRL);
1756 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1757 break;
1758
1759 mdelay(1);
1760 timeout--;
1761 }
1762
1763 if (!timeout) {
1764 e_dbg("SW has already locked the resource.\n");
1765 ret_val = -E1000_ERR_CONFIG;
1766 goto out;
1767 }
1768
1769 timeout = SW_FLAG_TIMEOUT;
1770
1771 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1772 ew32(EXTCNF_CTRL, extcnf_ctrl);
1773
1774 while (timeout) {
1775 extcnf_ctrl = er32(EXTCNF_CTRL);
1776 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1777 break;
1778
1779 mdelay(1);
1780 timeout--;
1781 }
1782
1783 if (!timeout) {
1784 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1785 er32(FWSM), extcnf_ctrl);
1786 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1787 ew32(EXTCNF_CTRL, extcnf_ctrl);
1788 ret_val = -E1000_ERR_CONFIG;
1789 goto out;
1790 }
1791
1792 out:
1793 if (ret_val)
1794 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1795
1796 return ret_val;
1797 }
1798
1799 /**
1800 * e1000_release_swflag_ich8lan - Release software control flag
1801 * @hw: pointer to the HW structure
1802 *
1803 * Releases the software control flag for performing PHY and select
1804 * MAC CSR accesses.
1805 **/
e1000_release_swflag_ich8lan(struct e1000_hw * hw)1806 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1807 {
1808 u32 extcnf_ctrl;
1809
1810 extcnf_ctrl = er32(EXTCNF_CTRL);
1811
1812 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1813 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1814 ew32(EXTCNF_CTRL, extcnf_ctrl);
1815 } else {
1816 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1817 }
1818
1819 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1820 }
1821
1822 /**
1823 * e1000_check_mng_mode_ich8lan - Checks management mode
1824 * @hw: pointer to the HW structure
1825 *
1826 * This checks if the adapter has any manageability enabled.
1827 * This is a function pointer entry point only called by read/write
1828 * routines for the PHY and NVM parts.
1829 **/
e1000_check_mng_mode_ich8lan(struct e1000_hw * hw)1830 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1831 {
1832 u32 fwsm;
1833
1834 fwsm = er32(FWSM);
1835 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1836 ((fwsm & E1000_FWSM_MODE_MASK) ==
1837 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1838 }
1839
1840 /**
1841 * e1000_check_mng_mode_pchlan - Checks management mode
1842 * @hw: pointer to the HW structure
1843 *
1844 * This checks if the adapter has iAMT enabled.
1845 * This is a function pointer entry point only called by read/write
1846 * routines for the PHY and NVM parts.
1847 **/
e1000_check_mng_mode_pchlan(struct e1000_hw * hw)1848 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1849 {
1850 u32 fwsm;
1851
1852 fwsm = er32(FWSM);
1853 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1854 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1855 }
1856
1857 /**
1858 * e1000_rar_set_pch2lan - Set receive address register
1859 * @hw: pointer to the HW structure
1860 * @addr: pointer to the receive address
1861 * @index: receive address array register
1862 *
1863 * Sets the receive address array register at index to the address passed
1864 * in by addr. For 82579, RAR[0] is the base address register that is to
1865 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1866 * Use SHRA[0-3] in place of those reserved for ME.
1867 **/
e1000_rar_set_pch2lan(struct e1000_hw * hw,u8 * addr,u32 index)1868 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1869 {
1870 u32 rar_low, rar_high;
1871
1872 /* HW expects these in little endian so we reverse the byte order
1873 * from network order (big endian) to little endian
1874 */
1875 rar_low = ((u32)addr[0] |
1876 ((u32)addr[1] << 8) |
1877 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1878
1879 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1880
1881 /* If MAC address zero, no need to set the AV bit */
1882 if (rar_low || rar_high)
1883 rar_high |= E1000_RAH_AV;
1884
1885 if (index == 0) {
1886 ew32(RAL(index), rar_low);
1887 e1e_flush();
1888 ew32(RAH(index), rar_high);
1889 e1e_flush();
1890 return 0;
1891 }
1892
1893 /* RAR[1-6] are owned by manageability. Skip those and program the
1894 * next address into the SHRA register array.
1895 */
1896 if (index < (u32)(hw->mac.rar_entry_count)) {
1897 s32 ret_val;
1898
1899 ret_val = e1000_acquire_swflag_ich8lan(hw);
1900 if (ret_val)
1901 goto out;
1902
1903 ew32(SHRAL(index - 1), rar_low);
1904 e1e_flush();
1905 ew32(SHRAH(index - 1), rar_high);
1906 e1e_flush();
1907
1908 e1000_release_swflag_ich8lan(hw);
1909
1910 /* verify the register updates */
1911 if ((er32(SHRAL(index - 1)) == rar_low) &&
1912 (er32(SHRAH(index - 1)) == rar_high))
1913 return 0;
1914
1915 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1916 (index - 1), er32(FWSM));
1917 }
1918
1919 out:
1920 e_dbg("Failed to write receive address at index %d\n", index);
1921 return -E1000_ERR_CONFIG;
1922 }
1923
1924 /**
1925 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1926 * @hw: pointer to the HW structure
1927 *
1928 * Get the number of available receive registers that the Host can
1929 * program. SHRA[0-10] are the shared receive address registers
1930 * that are shared between the Host and manageability engine (ME).
1931 * ME can reserve any number of addresses and the host needs to be
1932 * able to tell how many available registers it has access to.
1933 **/
e1000_rar_get_count_pch_lpt(struct e1000_hw * hw)1934 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1935 {
1936 u32 wlock_mac;
1937 u32 num_entries;
1938
1939 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1940 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1941
1942 switch (wlock_mac) {
1943 case 0:
1944 /* All SHRA[0..10] and RAR[0] available */
1945 num_entries = hw->mac.rar_entry_count;
1946 break;
1947 case 1:
1948 /* Only RAR[0] available */
1949 num_entries = 1;
1950 break;
1951 default:
1952 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1953 num_entries = wlock_mac + 1;
1954 break;
1955 }
1956
1957 return num_entries;
1958 }
1959
1960 /**
1961 * e1000_rar_set_pch_lpt - Set receive address registers
1962 * @hw: pointer to the HW structure
1963 * @addr: pointer to the receive address
1964 * @index: receive address array register
1965 *
1966 * Sets the receive address register array at index to the address passed
1967 * in by addr. For LPT, RAR[0] is the base address register that is to
1968 * contain the MAC address. SHRA[0-10] are the shared receive address
1969 * registers that are shared between the Host and manageability engine (ME).
1970 **/
e1000_rar_set_pch_lpt(struct e1000_hw * hw,u8 * addr,u32 index)1971 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1972 {
1973 u32 rar_low, rar_high;
1974 u32 wlock_mac;
1975
1976 /* HW expects these in little endian so we reverse the byte order
1977 * from network order (big endian) to little endian
1978 */
1979 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1980 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1981
1982 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1983
1984 /* If MAC address zero, no need to set the AV bit */
1985 if (rar_low || rar_high)
1986 rar_high |= E1000_RAH_AV;
1987
1988 if (index == 0) {
1989 ew32(RAL(index), rar_low);
1990 e1e_flush();
1991 ew32(RAH(index), rar_high);
1992 e1e_flush();
1993 return 0;
1994 }
1995
1996 /* The manageability engine (ME) can lock certain SHRAR registers that
1997 * it is using - those registers are unavailable for use.
1998 */
1999 if (index < hw->mac.rar_entry_count) {
2000 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
2001 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2002
2003 /* Check if all SHRAR registers are locked */
2004 if (wlock_mac == 1)
2005 goto out;
2006
2007 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2008 s32 ret_val;
2009
2010 ret_val = e1000_acquire_swflag_ich8lan(hw);
2011
2012 if (ret_val)
2013 goto out;
2014
2015 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
2016 e1e_flush();
2017 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
2018 e1e_flush();
2019
2020 e1000_release_swflag_ich8lan(hw);
2021
2022 /* verify the register updates */
2023 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2024 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
2025 return 0;
2026 }
2027 }
2028
2029 out:
2030 e_dbg("Failed to write receive address at index %d\n", index);
2031 return -E1000_ERR_CONFIG;
2032 }
2033
2034 /**
2035 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2036 * @hw: pointer to the HW structure
2037 *
2038 * Checks if firmware is blocking the reset of the PHY.
2039 * This is a function pointer entry point only called by
2040 * reset routines.
2041 **/
e1000_check_reset_block_ich8lan(struct e1000_hw * hw)2042 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2043 {
2044 bool blocked = false;
2045 int i = 0;
2046
2047 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2048 (i++ < 30))
2049 usleep_range(10000, 11000);
2050 return blocked ? E1000_BLK_PHY_RESET : 0;
2051 }
2052
2053 /**
2054 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2055 * @hw: pointer to the HW structure
2056 *
2057 * Assumes semaphore already acquired.
2058 *
2059 **/
e1000_write_smbus_addr(struct e1000_hw * hw)2060 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2061 {
2062 u16 phy_data;
2063 u32 strap = er32(STRAP);
2064 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2065 E1000_STRAP_SMT_FREQ_SHIFT;
2066 s32 ret_val;
2067
2068 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2069
2070 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2071 if (ret_val)
2072 return ret_val;
2073
2074 phy_data &= ~HV_SMB_ADDR_MASK;
2075 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2076 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2077
2078 if (hw->phy.type == e1000_phy_i217) {
2079 /* Restore SMBus frequency */
2080 if (freq--) {
2081 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2082 phy_data |= (freq & BIT(0)) <<
2083 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2084 phy_data |= (freq & BIT(1)) <<
2085 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2086 } else {
2087 e_dbg("Unsupported SMB frequency in PHY\n");
2088 }
2089 }
2090
2091 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2092 }
2093
2094 /**
2095 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2096 * @hw: pointer to the HW structure
2097 *
2098 * SW should configure the LCD from the NVM extended configuration region
2099 * as a workaround for certain parts.
2100 **/
e1000_sw_lcd_config_ich8lan(struct e1000_hw * hw)2101 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2102 {
2103 struct e1000_phy_info *phy = &hw->phy;
2104 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2105 s32 ret_val = 0;
2106 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2107
2108 /* Initialize the PHY from the NVM on ICH platforms. This
2109 * is needed due to an issue where the NVM configuration is
2110 * not properly autoloaded after power transitions.
2111 * Therefore, after each PHY reset, we will load the
2112 * configuration data out of the NVM manually.
2113 */
2114 switch (hw->mac.type) {
2115 case e1000_ich8lan:
2116 if (phy->type != e1000_phy_igp_3)
2117 return ret_val;
2118
2119 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2120 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2121 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2122 break;
2123 }
2124 fallthrough;
2125 case e1000_pchlan:
2126 case e1000_pch2lan:
2127 case e1000_pch_lpt:
2128 case e1000_pch_spt:
2129 case e1000_pch_cnp:
2130 case e1000_pch_tgp:
2131 case e1000_pch_adp:
2132 case e1000_pch_mtp:
2133 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2134 break;
2135 default:
2136 return ret_val;
2137 }
2138
2139 ret_val = hw->phy.ops.acquire(hw);
2140 if (ret_val)
2141 return ret_val;
2142
2143 data = er32(FEXTNVM);
2144 if (!(data & sw_cfg_mask))
2145 goto release;
2146
2147 /* Make sure HW does not configure LCD from PHY
2148 * extended configuration before SW configuration
2149 */
2150 data = er32(EXTCNF_CTRL);
2151 if ((hw->mac.type < e1000_pch2lan) &&
2152 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2153 goto release;
2154
2155 cnf_size = er32(EXTCNF_SIZE);
2156 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2157 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2158 if (!cnf_size)
2159 goto release;
2160
2161 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2162 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2163
2164 if (((hw->mac.type == e1000_pchlan) &&
2165 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2166 (hw->mac.type > e1000_pchlan)) {
2167 /* HW configures the SMBus address and LEDs when the
2168 * OEM and LCD Write Enable bits are set in the NVM.
2169 * When both NVM bits are cleared, SW will configure
2170 * them instead.
2171 */
2172 ret_val = e1000_write_smbus_addr(hw);
2173 if (ret_val)
2174 goto release;
2175
2176 data = er32(LEDCTL);
2177 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2178 (u16)data);
2179 if (ret_val)
2180 goto release;
2181 }
2182
2183 /* Configure LCD from extended configuration region. */
2184
2185 /* cnf_base_addr is in DWORD */
2186 word_addr = (u16)(cnf_base_addr << 1);
2187
2188 for (i = 0; i < cnf_size; i++) {
2189 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data);
2190 if (ret_val)
2191 goto release;
2192
2193 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2194 1, ®_addr);
2195 if (ret_val)
2196 goto release;
2197
2198 /* Save off the PHY page for future writes. */
2199 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2200 phy_page = reg_data;
2201 continue;
2202 }
2203
2204 reg_addr &= PHY_REG_MASK;
2205 reg_addr |= phy_page;
2206
2207 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2208 if (ret_val)
2209 goto release;
2210 }
2211
2212 release:
2213 hw->phy.ops.release(hw);
2214 return ret_val;
2215 }
2216
2217 /**
2218 * e1000_k1_gig_workaround_hv - K1 Si workaround
2219 * @hw: pointer to the HW structure
2220 * @link: link up bool flag
2221 *
2222 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2223 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2224 * If link is down, the function will restore the default K1 setting located
2225 * in the NVM.
2226 **/
e1000_k1_gig_workaround_hv(struct e1000_hw * hw,bool link)2227 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2228 {
2229 s32 ret_val = 0;
2230 u16 status_reg = 0;
2231 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2232
2233 if (hw->mac.type != e1000_pchlan)
2234 return 0;
2235
2236 /* Wrap the whole flow with the sw flag */
2237 ret_val = hw->phy.ops.acquire(hw);
2238 if (ret_val)
2239 return ret_val;
2240
2241 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2242 if (link) {
2243 if (hw->phy.type == e1000_phy_82578) {
2244 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2245 &status_reg);
2246 if (ret_val)
2247 goto release;
2248
2249 status_reg &= (BM_CS_STATUS_LINK_UP |
2250 BM_CS_STATUS_RESOLVED |
2251 BM_CS_STATUS_SPEED_MASK);
2252
2253 if (status_reg == (BM_CS_STATUS_LINK_UP |
2254 BM_CS_STATUS_RESOLVED |
2255 BM_CS_STATUS_SPEED_1000))
2256 k1_enable = false;
2257 }
2258
2259 if (hw->phy.type == e1000_phy_82577) {
2260 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2261 if (ret_val)
2262 goto release;
2263
2264 status_reg &= (HV_M_STATUS_LINK_UP |
2265 HV_M_STATUS_AUTONEG_COMPLETE |
2266 HV_M_STATUS_SPEED_MASK);
2267
2268 if (status_reg == (HV_M_STATUS_LINK_UP |
2269 HV_M_STATUS_AUTONEG_COMPLETE |
2270 HV_M_STATUS_SPEED_1000))
2271 k1_enable = false;
2272 }
2273
2274 /* Link stall fix for link up */
2275 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2276 if (ret_val)
2277 goto release;
2278
2279 } else {
2280 /* Link stall fix for link down */
2281 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2282 if (ret_val)
2283 goto release;
2284 }
2285
2286 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2287
2288 release:
2289 hw->phy.ops.release(hw);
2290
2291 return ret_val;
2292 }
2293
2294 /**
2295 * e1000_configure_k1_ich8lan - Configure K1 power state
2296 * @hw: pointer to the HW structure
2297 * @k1_enable: K1 state to configure
2298 *
2299 * Configure the K1 power state based on the provided parameter.
2300 * Assumes semaphore already acquired.
2301 *
2302 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2303 **/
e1000_configure_k1_ich8lan(struct e1000_hw * hw,bool k1_enable)2304 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2305 {
2306 s32 ret_val;
2307 u32 ctrl_reg = 0;
2308 u32 ctrl_ext = 0;
2309 u32 reg = 0;
2310 u16 kmrn_reg = 0;
2311
2312 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2313 &kmrn_reg);
2314 if (ret_val)
2315 return ret_val;
2316
2317 if (k1_enable)
2318 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2319 else
2320 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2321
2322 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2323 kmrn_reg);
2324 if (ret_val)
2325 return ret_val;
2326
2327 usleep_range(20, 40);
2328 ctrl_ext = er32(CTRL_EXT);
2329 ctrl_reg = er32(CTRL);
2330
2331 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2332 reg |= E1000_CTRL_FRCSPD;
2333 ew32(CTRL, reg);
2334
2335 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2336 e1e_flush();
2337 usleep_range(20, 40);
2338 ew32(CTRL, ctrl_reg);
2339 ew32(CTRL_EXT, ctrl_ext);
2340 e1e_flush();
2341 usleep_range(20, 40);
2342
2343 return 0;
2344 }
2345
2346 /**
2347 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2348 * @hw: pointer to the HW structure
2349 * @d0_state: boolean if entering d0 or d3 device state
2350 *
2351 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2352 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2353 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2354 **/
e1000_oem_bits_config_ich8lan(struct e1000_hw * hw,bool d0_state)2355 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2356 {
2357 s32 ret_val = 0;
2358 u32 mac_reg;
2359 u16 oem_reg;
2360
2361 if (hw->mac.type < e1000_pchlan)
2362 return ret_val;
2363
2364 ret_val = hw->phy.ops.acquire(hw);
2365 if (ret_val)
2366 return ret_val;
2367
2368 if (hw->mac.type == e1000_pchlan) {
2369 mac_reg = er32(EXTCNF_CTRL);
2370 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2371 goto release;
2372 }
2373
2374 mac_reg = er32(FEXTNVM);
2375 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2376 goto release;
2377
2378 mac_reg = er32(PHY_CTRL);
2379
2380 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2381 if (ret_val)
2382 goto release;
2383
2384 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2385
2386 if (d0_state) {
2387 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2388 oem_reg |= HV_OEM_BITS_GBE_DIS;
2389
2390 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2391 oem_reg |= HV_OEM_BITS_LPLU;
2392 } else {
2393 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2394 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2395 oem_reg |= HV_OEM_BITS_GBE_DIS;
2396
2397 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2398 E1000_PHY_CTRL_NOND0A_LPLU))
2399 oem_reg |= HV_OEM_BITS_LPLU;
2400 }
2401
2402 /* Set Restart auto-neg to activate the bits */
2403 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2404 !hw->phy.ops.check_reset_block(hw))
2405 oem_reg |= HV_OEM_BITS_RESTART_AN;
2406
2407 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2408
2409 release:
2410 hw->phy.ops.release(hw);
2411
2412 return ret_val;
2413 }
2414
2415 /**
2416 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2417 * @hw: pointer to the HW structure
2418 **/
e1000_set_mdio_slow_mode_hv(struct e1000_hw * hw)2419 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2420 {
2421 s32 ret_val;
2422 u16 data;
2423
2424 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2425 if (ret_val)
2426 return ret_val;
2427
2428 data |= HV_KMRN_MDIO_SLOW;
2429
2430 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2431
2432 return ret_val;
2433 }
2434
2435 /**
2436 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2437 * @hw: pointer to the HW structure
2438 *
2439 * A series of PHY workarounds to be done after every PHY reset.
2440 **/
e1000_hv_phy_workarounds_ich8lan(struct e1000_hw * hw)2441 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2442 {
2443 s32 ret_val = 0;
2444 u16 phy_data;
2445
2446 if (hw->mac.type != e1000_pchlan)
2447 return 0;
2448
2449 /* Set MDIO slow mode before any other MDIO access */
2450 if (hw->phy.type == e1000_phy_82577) {
2451 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2452 if (ret_val)
2453 return ret_val;
2454 }
2455
2456 if (((hw->phy.type == e1000_phy_82577) &&
2457 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2458 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2459 /* Disable generation of early preamble */
2460 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2461 if (ret_val)
2462 return ret_val;
2463
2464 /* Preamble tuning for SSC */
2465 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2466 if (ret_val)
2467 return ret_val;
2468 }
2469
2470 if (hw->phy.type == e1000_phy_82578) {
2471 /* Return registers to default by doing a soft reset then
2472 * writing 0x3140 to the control register.
2473 */
2474 if (hw->phy.revision < 2) {
2475 e1000e_phy_sw_reset(hw);
2476 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2477 if (ret_val)
2478 return ret_val;
2479 }
2480 }
2481
2482 /* Select page 0 */
2483 ret_val = hw->phy.ops.acquire(hw);
2484 if (ret_val)
2485 return ret_val;
2486
2487 hw->phy.addr = 1;
2488 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2489 hw->phy.ops.release(hw);
2490 if (ret_val)
2491 return ret_val;
2492
2493 /* Configure the K1 Si workaround during phy reset assuming there is
2494 * link so that it disables K1 if link is in 1Gbps.
2495 */
2496 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2497 if (ret_val)
2498 return ret_val;
2499
2500 /* Workaround for link disconnects on a busy hub in half duplex */
2501 ret_val = hw->phy.ops.acquire(hw);
2502 if (ret_val)
2503 return ret_val;
2504 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2505 if (ret_val)
2506 goto release;
2507 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2508 if (ret_val)
2509 goto release;
2510
2511 /* set MSE higher to enable link to stay up when noise is high */
2512 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2513 release:
2514 hw->phy.ops.release(hw);
2515
2516 return ret_val;
2517 }
2518
2519 /**
2520 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2521 * @hw: pointer to the HW structure
2522 **/
e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw * hw)2523 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2524 {
2525 u32 mac_reg;
2526 u16 i, phy_reg = 0;
2527 s32 ret_val;
2528
2529 ret_val = hw->phy.ops.acquire(hw);
2530 if (ret_val)
2531 return;
2532 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2533 if (ret_val)
2534 goto release;
2535
2536 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2537 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2538 mac_reg = er32(RAL(i));
2539 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2540 (u16)(mac_reg & 0xFFFF));
2541 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2542 (u16)((mac_reg >> 16) & 0xFFFF));
2543
2544 mac_reg = er32(RAH(i));
2545 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2546 (u16)(mac_reg & 0xFFFF));
2547 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2548 (u16)((mac_reg & E1000_RAH_AV)
2549 >> 16));
2550 }
2551
2552 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2553
2554 release:
2555 hw->phy.ops.release(hw);
2556 }
2557
2558 /**
2559 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2560 * with 82579 PHY
2561 * @hw: pointer to the HW structure
2562 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2563 **/
e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw * hw,bool enable)2564 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2565 {
2566 s32 ret_val = 0;
2567 u16 phy_reg, data;
2568 u32 mac_reg;
2569 u16 i;
2570
2571 if (hw->mac.type < e1000_pch2lan)
2572 return 0;
2573
2574 /* disable Rx path while enabling/disabling workaround */
2575 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2576 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2577 if (ret_val)
2578 return ret_val;
2579
2580 if (enable) {
2581 /* Write Rx addresses (rar_entry_count for RAL/H, and
2582 * SHRAL/H) and initial CRC values to the MAC
2583 */
2584 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2585 u8 mac_addr[ETH_ALEN] = { 0 };
2586 u32 addr_high, addr_low;
2587
2588 addr_high = er32(RAH(i));
2589 if (!(addr_high & E1000_RAH_AV))
2590 continue;
2591 addr_low = er32(RAL(i));
2592 mac_addr[0] = (addr_low & 0xFF);
2593 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2594 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2595 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2596 mac_addr[4] = (addr_high & 0xFF);
2597 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2598
2599 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2600 }
2601
2602 /* Write Rx addresses to the PHY */
2603 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2604
2605 /* Enable jumbo frame workaround in the MAC */
2606 mac_reg = er32(FFLT_DBG);
2607 mac_reg &= ~BIT(14);
2608 mac_reg |= (7 << 15);
2609 ew32(FFLT_DBG, mac_reg);
2610
2611 mac_reg = er32(RCTL);
2612 mac_reg |= E1000_RCTL_SECRC;
2613 ew32(RCTL, mac_reg);
2614
2615 ret_val = e1000e_read_kmrn_reg(hw,
2616 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2617 &data);
2618 if (ret_val)
2619 return ret_val;
2620 ret_val = e1000e_write_kmrn_reg(hw,
2621 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2622 data | BIT(0));
2623 if (ret_val)
2624 return ret_val;
2625 ret_val = e1000e_read_kmrn_reg(hw,
2626 E1000_KMRNCTRLSTA_HD_CTRL,
2627 &data);
2628 if (ret_val)
2629 return ret_val;
2630 data &= ~(0xF << 8);
2631 data |= (0xB << 8);
2632 ret_val = e1000e_write_kmrn_reg(hw,
2633 E1000_KMRNCTRLSTA_HD_CTRL,
2634 data);
2635 if (ret_val)
2636 return ret_val;
2637
2638 /* Enable jumbo frame workaround in the PHY */
2639 e1e_rphy(hw, PHY_REG(769, 23), &data);
2640 data &= ~(0x7F << 5);
2641 data |= (0x37 << 5);
2642 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2643 if (ret_val)
2644 return ret_val;
2645 e1e_rphy(hw, PHY_REG(769, 16), &data);
2646 data &= ~BIT(13);
2647 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2648 if (ret_val)
2649 return ret_val;
2650 e1e_rphy(hw, PHY_REG(776, 20), &data);
2651 data &= ~(0x3FF << 2);
2652 data |= (E1000_TX_PTR_GAP << 2);
2653 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2654 if (ret_val)
2655 return ret_val;
2656 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2657 if (ret_val)
2658 return ret_val;
2659 e1e_rphy(hw, HV_PM_CTRL, &data);
2660 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2661 if (ret_val)
2662 return ret_val;
2663 } else {
2664 /* Write MAC register values back to h/w defaults */
2665 mac_reg = er32(FFLT_DBG);
2666 mac_reg &= ~(0xF << 14);
2667 ew32(FFLT_DBG, mac_reg);
2668
2669 mac_reg = er32(RCTL);
2670 mac_reg &= ~E1000_RCTL_SECRC;
2671 ew32(RCTL, mac_reg);
2672
2673 ret_val = e1000e_read_kmrn_reg(hw,
2674 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2675 &data);
2676 if (ret_val)
2677 return ret_val;
2678 ret_val = e1000e_write_kmrn_reg(hw,
2679 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2680 data & ~BIT(0));
2681 if (ret_val)
2682 return ret_val;
2683 ret_val = e1000e_read_kmrn_reg(hw,
2684 E1000_KMRNCTRLSTA_HD_CTRL,
2685 &data);
2686 if (ret_val)
2687 return ret_val;
2688 data &= ~(0xF << 8);
2689 data |= (0xB << 8);
2690 ret_val = e1000e_write_kmrn_reg(hw,
2691 E1000_KMRNCTRLSTA_HD_CTRL,
2692 data);
2693 if (ret_val)
2694 return ret_val;
2695
2696 /* Write PHY register values back to h/w defaults */
2697 e1e_rphy(hw, PHY_REG(769, 23), &data);
2698 data &= ~(0x7F << 5);
2699 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2700 if (ret_val)
2701 return ret_val;
2702 e1e_rphy(hw, PHY_REG(769, 16), &data);
2703 data |= BIT(13);
2704 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2705 if (ret_val)
2706 return ret_val;
2707 e1e_rphy(hw, PHY_REG(776, 20), &data);
2708 data &= ~(0x3FF << 2);
2709 data |= (0x8 << 2);
2710 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2711 if (ret_val)
2712 return ret_val;
2713 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2714 if (ret_val)
2715 return ret_val;
2716 e1e_rphy(hw, HV_PM_CTRL, &data);
2717 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2718 if (ret_val)
2719 return ret_val;
2720 }
2721
2722 /* re-enable Rx path after enabling/disabling workaround */
2723 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2724 }
2725
2726 /**
2727 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2728 * @hw: pointer to the HW structure
2729 *
2730 * A series of PHY workarounds to be done after every PHY reset.
2731 **/
e1000_lv_phy_workarounds_ich8lan(struct e1000_hw * hw)2732 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2733 {
2734 s32 ret_val = 0;
2735
2736 if (hw->mac.type != e1000_pch2lan)
2737 return 0;
2738
2739 /* Set MDIO slow mode before any other MDIO access */
2740 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2741 if (ret_val)
2742 return ret_val;
2743
2744 ret_val = hw->phy.ops.acquire(hw);
2745 if (ret_val)
2746 return ret_val;
2747 /* set MSE higher to enable link to stay up when noise is high */
2748 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2749 if (ret_val)
2750 goto release;
2751 /* drop link after 5 times MSE threshold was reached */
2752 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2753 release:
2754 hw->phy.ops.release(hw);
2755
2756 return ret_val;
2757 }
2758
2759 /**
2760 * e1000_k1_gig_workaround_lv - K1 Si workaround
2761 * @hw: pointer to the HW structure
2762 *
2763 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2764 * Disable K1 in 1000Mbps and 100Mbps
2765 **/
e1000_k1_workaround_lv(struct e1000_hw * hw)2766 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2767 {
2768 s32 ret_val = 0;
2769 u16 status_reg = 0;
2770
2771 if (hw->mac.type != e1000_pch2lan)
2772 return 0;
2773
2774 /* Set K1 beacon duration based on 10Mbs speed */
2775 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2776 if (ret_val)
2777 return ret_val;
2778
2779 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2780 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2781 if (status_reg &
2782 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2783 u16 pm_phy_reg;
2784
2785 /* LV 1G/100 Packet drop issue wa */
2786 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2787 if (ret_val)
2788 return ret_val;
2789 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2790 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2791 if (ret_val)
2792 return ret_val;
2793 } else {
2794 u32 mac_reg;
2795
2796 mac_reg = er32(FEXTNVM4);
2797 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2798 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2799 ew32(FEXTNVM4, mac_reg);
2800 }
2801 }
2802
2803 return ret_val;
2804 }
2805
2806 /**
2807 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2808 * @hw: pointer to the HW structure
2809 * @gate: boolean set to true to gate, false to ungate
2810 *
2811 * Gate/ungate the automatic PHY configuration via hardware; perform
2812 * the configuration via software instead.
2813 **/
e1000_gate_hw_phy_config_ich8lan(struct e1000_hw * hw,bool gate)2814 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2815 {
2816 u32 extcnf_ctrl;
2817
2818 if (hw->mac.type < e1000_pch2lan)
2819 return;
2820
2821 extcnf_ctrl = er32(EXTCNF_CTRL);
2822
2823 if (gate)
2824 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2825 else
2826 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2827
2828 ew32(EXTCNF_CTRL, extcnf_ctrl);
2829 }
2830
2831 /**
2832 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2833 * @hw: pointer to the HW structure
2834 *
2835 * Check the appropriate indication the MAC has finished configuring the
2836 * PHY after a software reset.
2837 **/
e1000_lan_init_done_ich8lan(struct e1000_hw * hw)2838 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2839 {
2840 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2841
2842 /* Wait for basic configuration completes before proceeding */
2843 do {
2844 data = er32(STATUS);
2845 data &= E1000_STATUS_LAN_INIT_DONE;
2846 usleep_range(100, 200);
2847 } while ((!data) && --loop);
2848
2849 /* If basic configuration is incomplete before the above loop
2850 * count reaches 0, loading the configuration from NVM will
2851 * leave the PHY in a bad state possibly resulting in no link.
2852 */
2853 if (loop == 0)
2854 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2855
2856 /* Clear the Init Done bit for the next init event */
2857 data = er32(STATUS);
2858 data &= ~E1000_STATUS_LAN_INIT_DONE;
2859 ew32(STATUS, data);
2860 }
2861
2862 /**
2863 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2864 * @hw: pointer to the HW structure
2865 **/
e1000_post_phy_reset_ich8lan(struct e1000_hw * hw)2866 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2867 {
2868 s32 ret_val = 0;
2869 u16 reg;
2870
2871 if (hw->phy.ops.check_reset_block(hw))
2872 return 0;
2873
2874 /* Allow time for h/w to get to quiescent state after reset */
2875 usleep_range(10000, 11000);
2876
2877 /* Perform any necessary post-reset workarounds */
2878 switch (hw->mac.type) {
2879 case e1000_pchlan:
2880 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2881 if (ret_val)
2882 return ret_val;
2883 break;
2884 case e1000_pch2lan:
2885 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2886 if (ret_val)
2887 return ret_val;
2888 break;
2889 default:
2890 break;
2891 }
2892
2893 /* Clear the host wakeup bit after lcd reset */
2894 if (hw->mac.type >= e1000_pchlan) {
2895 e1e_rphy(hw, BM_PORT_GEN_CFG, ®);
2896 reg &= ~BM_WUC_HOST_WU_BIT;
2897 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2898 }
2899
2900 /* Configure the LCD with the extended configuration region in NVM */
2901 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2902 if (ret_val)
2903 return ret_val;
2904
2905 /* Configure the LCD with the OEM bits in NVM */
2906 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2907
2908 if (hw->mac.type == e1000_pch2lan) {
2909 /* Ungate automatic PHY configuration on non-managed 82579 */
2910 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2911 usleep_range(10000, 11000);
2912 e1000_gate_hw_phy_config_ich8lan(hw, false);
2913 }
2914
2915 /* Set EEE LPI Update Timer to 200usec */
2916 ret_val = hw->phy.ops.acquire(hw);
2917 if (ret_val)
2918 return ret_val;
2919 ret_val = e1000_write_emi_reg_locked(hw,
2920 I82579_LPI_UPDATE_TIMER,
2921 0x1387);
2922 hw->phy.ops.release(hw);
2923 }
2924
2925 return ret_val;
2926 }
2927
2928 /**
2929 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2930 * @hw: pointer to the HW structure
2931 *
2932 * Resets the PHY
2933 * This is a function pointer entry point called by drivers
2934 * or other shared routines.
2935 **/
e1000_phy_hw_reset_ich8lan(struct e1000_hw * hw)2936 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2937 {
2938 s32 ret_val = 0;
2939
2940 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2941 if ((hw->mac.type == e1000_pch2lan) &&
2942 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2943 e1000_gate_hw_phy_config_ich8lan(hw, true);
2944
2945 ret_val = e1000e_phy_hw_reset_generic(hw);
2946 if (ret_val)
2947 return ret_val;
2948
2949 return e1000_post_phy_reset_ich8lan(hw);
2950 }
2951
2952 /**
2953 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2954 * @hw: pointer to the HW structure
2955 * @active: true to enable LPLU, false to disable
2956 *
2957 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2958 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2959 * the phy speed. This function will manually set the LPLU bit and restart
2960 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2961 * since it configures the same bit.
2962 **/
e1000_set_lplu_state_pchlan(struct e1000_hw * hw,bool active)2963 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2964 {
2965 s32 ret_val;
2966 u16 oem_reg;
2967
2968 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2969 if (ret_val)
2970 return ret_val;
2971
2972 if (active)
2973 oem_reg |= HV_OEM_BITS_LPLU;
2974 else
2975 oem_reg &= ~HV_OEM_BITS_LPLU;
2976
2977 if (!hw->phy.ops.check_reset_block(hw))
2978 oem_reg |= HV_OEM_BITS_RESTART_AN;
2979
2980 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2981 }
2982
2983 /**
2984 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2985 * @hw: pointer to the HW structure
2986 * @active: true to enable LPLU, false to disable
2987 *
2988 * Sets the LPLU D0 state according to the active flag. When
2989 * activating LPLU this function also disables smart speed
2990 * and vice versa. LPLU will not be activated unless the
2991 * device autonegotiation advertisement meets standards of
2992 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2993 * This is a function pointer entry point only called by
2994 * PHY setup routines.
2995 **/
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw * hw,bool active)2996 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2997 {
2998 struct e1000_phy_info *phy = &hw->phy;
2999 u32 phy_ctrl;
3000 s32 ret_val = 0;
3001 u16 data;
3002
3003 if (phy->type == e1000_phy_ife)
3004 return 0;
3005
3006 phy_ctrl = er32(PHY_CTRL);
3007
3008 if (active) {
3009 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3010 ew32(PHY_CTRL, phy_ctrl);
3011
3012 if (phy->type != e1000_phy_igp_3)
3013 return 0;
3014
3015 /* Call gig speed drop workaround on LPLU before accessing
3016 * any PHY registers
3017 */
3018 if (hw->mac.type == e1000_ich8lan)
3019 e1000e_gig_downshift_workaround_ich8lan(hw);
3020
3021 /* When LPLU is enabled, we should disable SmartSpeed */
3022 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3023 if (ret_val)
3024 return ret_val;
3025 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3026 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3027 if (ret_val)
3028 return ret_val;
3029 } else {
3030 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3031 ew32(PHY_CTRL, phy_ctrl);
3032
3033 if (phy->type != e1000_phy_igp_3)
3034 return 0;
3035
3036 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3037 * during Dx states where the power conservation is most
3038 * important. During driver activity we should enable
3039 * SmartSpeed, so performance is maintained.
3040 */
3041 if (phy->smart_speed == e1000_smart_speed_on) {
3042 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3043 &data);
3044 if (ret_val)
3045 return ret_val;
3046
3047 data |= IGP01E1000_PSCFR_SMART_SPEED;
3048 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3049 data);
3050 if (ret_val)
3051 return ret_val;
3052 } else if (phy->smart_speed == e1000_smart_speed_off) {
3053 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3054 &data);
3055 if (ret_val)
3056 return ret_val;
3057
3058 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3059 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3060 data);
3061 if (ret_val)
3062 return ret_val;
3063 }
3064 }
3065
3066 return 0;
3067 }
3068
3069 /**
3070 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3071 * @hw: pointer to the HW structure
3072 * @active: true to enable LPLU, false to disable
3073 *
3074 * Sets the LPLU D3 state according to the active flag. When
3075 * activating LPLU this function also disables smart speed
3076 * and vice versa. LPLU will not be activated unless the
3077 * device autonegotiation advertisement meets standards of
3078 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3079 * This is a function pointer entry point only called by
3080 * PHY setup routines.
3081 **/
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw * hw,bool active)3082 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3083 {
3084 struct e1000_phy_info *phy = &hw->phy;
3085 u32 phy_ctrl;
3086 s32 ret_val = 0;
3087 u16 data;
3088
3089 phy_ctrl = er32(PHY_CTRL);
3090
3091 if (!active) {
3092 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3093 ew32(PHY_CTRL, phy_ctrl);
3094
3095 if (phy->type != e1000_phy_igp_3)
3096 return 0;
3097
3098 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3099 * during Dx states where the power conservation is most
3100 * important. During driver activity we should enable
3101 * SmartSpeed, so performance is maintained.
3102 */
3103 if (phy->smart_speed == e1000_smart_speed_on) {
3104 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3105 &data);
3106 if (ret_val)
3107 return ret_val;
3108
3109 data |= IGP01E1000_PSCFR_SMART_SPEED;
3110 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3111 data);
3112 if (ret_val)
3113 return ret_val;
3114 } else if (phy->smart_speed == e1000_smart_speed_off) {
3115 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3116 &data);
3117 if (ret_val)
3118 return ret_val;
3119
3120 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3121 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3122 data);
3123 if (ret_val)
3124 return ret_val;
3125 }
3126 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3127 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3128 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3129 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3130 ew32(PHY_CTRL, phy_ctrl);
3131
3132 if (phy->type != e1000_phy_igp_3)
3133 return 0;
3134
3135 /* Call gig speed drop workaround on LPLU before accessing
3136 * any PHY registers
3137 */
3138 if (hw->mac.type == e1000_ich8lan)
3139 e1000e_gig_downshift_workaround_ich8lan(hw);
3140
3141 /* When LPLU is enabled, we should disable SmartSpeed */
3142 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3143 if (ret_val)
3144 return ret_val;
3145
3146 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3147 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3148 }
3149
3150 return ret_val;
3151 }
3152
3153 /**
3154 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3155 * @hw: pointer to the HW structure
3156 * @bank: pointer to the variable that returns the active bank
3157 *
3158 * Reads signature byte from the NVM using the flash access registers.
3159 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3160 **/
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw * hw,u32 * bank)3161 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3162 {
3163 u32 eecd;
3164 struct e1000_nvm_info *nvm = &hw->nvm;
3165 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3166 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3167 u32 nvm_dword = 0;
3168 u8 sig_byte = 0;
3169 s32 ret_val;
3170
3171 switch (hw->mac.type) {
3172 case e1000_pch_spt:
3173 case e1000_pch_cnp:
3174 case e1000_pch_tgp:
3175 case e1000_pch_adp:
3176 case e1000_pch_mtp:
3177 bank1_offset = nvm->flash_bank_size;
3178 act_offset = E1000_ICH_NVM_SIG_WORD;
3179
3180 /* set bank to 0 in case flash read fails */
3181 *bank = 0;
3182
3183 /* Check bank 0 */
3184 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3185 &nvm_dword);
3186 if (ret_val)
3187 return ret_val;
3188 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3189 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3190 E1000_ICH_NVM_SIG_VALUE) {
3191 *bank = 0;
3192 return 0;
3193 }
3194
3195 /* Check bank 1 */
3196 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3197 bank1_offset,
3198 &nvm_dword);
3199 if (ret_val)
3200 return ret_val;
3201 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3202 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3203 E1000_ICH_NVM_SIG_VALUE) {
3204 *bank = 1;
3205 return 0;
3206 }
3207
3208 e_dbg("ERROR: No valid NVM bank present\n");
3209 return -E1000_ERR_NVM;
3210 case e1000_ich8lan:
3211 case e1000_ich9lan:
3212 eecd = er32(EECD);
3213 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3214 E1000_EECD_SEC1VAL_VALID_MASK) {
3215 if (eecd & E1000_EECD_SEC1VAL)
3216 *bank = 1;
3217 else
3218 *bank = 0;
3219
3220 return 0;
3221 }
3222 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3223 fallthrough;
3224 default:
3225 /* set bank to 0 in case flash read fails */
3226 *bank = 0;
3227
3228 /* Check bank 0 */
3229 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3230 &sig_byte);
3231 if (ret_val)
3232 return ret_val;
3233 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3234 E1000_ICH_NVM_SIG_VALUE) {
3235 *bank = 0;
3236 return 0;
3237 }
3238
3239 /* Check bank 1 */
3240 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3241 bank1_offset,
3242 &sig_byte);
3243 if (ret_val)
3244 return ret_val;
3245 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3246 E1000_ICH_NVM_SIG_VALUE) {
3247 *bank = 1;
3248 return 0;
3249 }
3250
3251 e_dbg("ERROR: No valid NVM bank present\n");
3252 return -E1000_ERR_NVM;
3253 }
3254 }
3255
3256 /**
3257 * e1000_read_nvm_spt - NVM access for SPT
3258 * @hw: pointer to the HW structure
3259 * @offset: The offset (in bytes) of the word(s) to read.
3260 * @words: Size of data to read in words.
3261 * @data: pointer to the word(s) to read at offset.
3262 *
3263 * Reads a word(s) from the NVM
3264 **/
e1000_read_nvm_spt(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3265 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3266 u16 *data)
3267 {
3268 struct e1000_nvm_info *nvm = &hw->nvm;
3269 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3270 u32 act_offset;
3271 s32 ret_val = 0;
3272 u32 bank = 0;
3273 u32 dword = 0;
3274 u16 offset_to_read;
3275 u16 i;
3276
3277 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3278 (words == 0)) {
3279 e_dbg("nvm parameter(s) out of bounds\n");
3280 ret_val = -E1000_ERR_NVM;
3281 goto out;
3282 }
3283
3284 nvm->ops.acquire(hw);
3285
3286 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3287 if (ret_val) {
3288 e_dbg("Could not detect valid bank, assuming bank 0\n");
3289 bank = 0;
3290 }
3291
3292 act_offset = (bank) ? nvm->flash_bank_size : 0;
3293 act_offset += offset;
3294
3295 ret_val = 0;
3296
3297 for (i = 0; i < words; i += 2) {
3298 if (words - i == 1) {
3299 if (dev_spec->shadow_ram[offset + i].modified) {
3300 data[i] =
3301 dev_spec->shadow_ram[offset + i].value;
3302 } else {
3303 offset_to_read = act_offset + i -
3304 ((act_offset + i) % 2);
3305 ret_val =
3306 e1000_read_flash_dword_ich8lan(hw,
3307 offset_to_read,
3308 &dword);
3309 if (ret_val)
3310 break;
3311 if ((act_offset + i) % 2 == 0)
3312 data[i] = (u16)(dword & 0xFFFF);
3313 else
3314 data[i] = (u16)((dword >> 16) & 0xFFFF);
3315 }
3316 } else {
3317 offset_to_read = act_offset + i;
3318 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3319 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3320 ret_val =
3321 e1000_read_flash_dword_ich8lan(hw,
3322 offset_to_read,
3323 &dword);
3324 if (ret_val)
3325 break;
3326 }
3327 if (dev_spec->shadow_ram[offset + i].modified)
3328 data[i] =
3329 dev_spec->shadow_ram[offset + i].value;
3330 else
3331 data[i] = (u16)(dword & 0xFFFF);
3332 if (dev_spec->shadow_ram[offset + i].modified)
3333 data[i + 1] =
3334 dev_spec->shadow_ram[offset + i + 1].value;
3335 else
3336 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3337 }
3338 }
3339
3340 nvm->ops.release(hw);
3341
3342 out:
3343 if (ret_val)
3344 e_dbg("NVM read error: %d\n", ret_val);
3345
3346 return ret_val;
3347 }
3348
3349 /**
3350 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3351 * @hw: pointer to the HW structure
3352 * @offset: The offset (in bytes) of the word(s) to read.
3353 * @words: Size of data to read in words
3354 * @data: Pointer to the word(s) to read at offset.
3355 *
3356 * Reads a word(s) from the NVM using the flash access registers.
3357 **/
e1000_read_nvm_ich8lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3358 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3359 u16 *data)
3360 {
3361 struct e1000_nvm_info *nvm = &hw->nvm;
3362 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3363 u32 act_offset;
3364 s32 ret_val = 0;
3365 u32 bank = 0;
3366 u16 i, word;
3367
3368 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3369 (words == 0)) {
3370 e_dbg("nvm parameter(s) out of bounds\n");
3371 ret_val = -E1000_ERR_NVM;
3372 goto out;
3373 }
3374
3375 nvm->ops.acquire(hw);
3376
3377 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3378 if (ret_val) {
3379 e_dbg("Could not detect valid bank, assuming bank 0\n");
3380 bank = 0;
3381 }
3382
3383 act_offset = (bank) ? nvm->flash_bank_size : 0;
3384 act_offset += offset;
3385
3386 ret_val = 0;
3387 for (i = 0; i < words; i++) {
3388 if (dev_spec->shadow_ram[offset + i].modified) {
3389 data[i] = dev_spec->shadow_ram[offset + i].value;
3390 } else {
3391 ret_val = e1000_read_flash_word_ich8lan(hw,
3392 act_offset + i,
3393 &word);
3394 if (ret_val)
3395 break;
3396 data[i] = word;
3397 }
3398 }
3399
3400 nvm->ops.release(hw);
3401
3402 out:
3403 if (ret_val)
3404 e_dbg("NVM read error: %d\n", ret_val);
3405
3406 return ret_val;
3407 }
3408
3409 /**
3410 * e1000_flash_cycle_init_ich8lan - Initialize flash
3411 * @hw: pointer to the HW structure
3412 *
3413 * This function does initial flash setup so that a new read/write/erase cycle
3414 * can be started.
3415 **/
e1000_flash_cycle_init_ich8lan(struct e1000_hw * hw)3416 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3417 {
3418 union ich8_hws_flash_status hsfsts;
3419 s32 ret_val = -E1000_ERR_NVM;
3420
3421 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3422
3423 /* Check if the flash descriptor is valid */
3424 if (!hsfsts.hsf_status.fldesvalid) {
3425 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
3426 return -E1000_ERR_NVM;
3427 }
3428
3429 /* Clear FCERR and DAEL in hw status by writing 1 */
3430 hsfsts.hsf_status.flcerr = 1;
3431 hsfsts.hsf_status.dael = 1;
3432 if (hw->mac.type >= e1000_pch_spt)
3433 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3434 else
3435 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3436
3437 /* Either we should have a hardware SPI cycle in progress
3438 * bit to check against, in order to start a new cycle or
3439 * FDONE bit should be changed in the hardware so that it
3440 * is 1 after hardware reset, which can then be used as an
3441 * indication whether a cycle is in progress or has been
3442 * completed.
3443 */
3444
3445 if (!hsfsts.hsf_status.flcinprog) {
3446 /* There is no cycle running at present,
3447 * so we can start a cycle.
3448 * Begin by setting Flash Cycle Done.
3449 */
3450 hsfsts.hsf_status.flcdone = 1;
3451 if (hw->mac.type >= e1000_pch_spt)
3452 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3453 else
3454 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3455 ret_val = 0;
3456 } else {
3457 s32 i;
3458
3459 /* Otherwise poll for sometime so the current
3460 * cycle has a chance to end before giving up.
3461 */
3462 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3463 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3464 if (!hsfsts.hsf_status.flcinprog) {
3465 ret_val = 0;
3466 break;
3467 }
3468 udelay(1);
3469 }
3470 if (!ret_val) {
3471 /* Successful in waiting for previous cycle to timeout,
3472 * now set the Flash Cycle Done.
3473 */
3474 hsfsts.hsf_status.flcdone = 1;
3475 if (hw->mac.type >= e1000_pch_spt)
3476 ew32flash(ICH_FLASH_HSFSTS,
3477 hsfsts.regval & 0xFFFF);
3478 else
3479 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3480 } else {
3481 e_dbg("Flash controller busy, cannot get access\n");
3482 }
3483 }
3484
3485 return ret_val;
3486 }
3487
3488 /**
3489 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3490 * @hw: pointer to the HW structure
3491 * @timeout: maximum time to wait for completion
3492 *
3493 * This function starts a flash cycle and waits for its completion.
3494 **/
e1000_flash_cycle_ich8lan(struct e1000_hw * hw,u32 timeout)3495 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3496 {
3497 union ich8_hws_flash_ctrl hsflctl;
3498 union ich8_hws_flash_status hsfsts;
3499 u32 i = 0;
3500
3501 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3502 if (hw->mac.type >= e1000_pch_spt)
3503 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3504 else
3505 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3506 hsflctl.hsf_ctrl.flcgo = 1;
3507
3508 if (hw->mac.type >= e1000_pch_spt)
3509 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3510 else
3511 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3512
3513 /* wait till FDONE bit is set to 1 */
3514 do {
3515 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3516 if (hsfsts.hsf_status.flcdone)
3517 break;
3518 udelay(1);
3519 } while (i++ < timeout);
3520
3521 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3522 return 0;
3523
3524 return -E1000_ERR_NVM;
3525 }
3526
3527 /**
3528 * e1000_read_flash_dword_ich8lan - Read dword from flash
3529 * @hw: pointer to the HW structure
3530 * @offset: offset to data location
3531 * @data: pointer to the location for storing the data
3532 *
3533 * Reads the flash dword at offset into data. Offset is converted
3534 * to bytes before read.
3535 **/
e1000_read_flash_dword_ich8lan(struct e1000_hw * hw,u32 offset,u32 * data)3536 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3537 u32 *data)
3538 {
3539 /* Must convert word offset into bytes. */
3540 offset <<= 1;
3541 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3542 }
3543
3544 /**
3545 * e1000_read_flash_word_ich8lan - Read word from flash
3546 * @hw: pointer to the HW structure
3547 * @offset: offset to data location
3548 * @data: pointer to the location for storing the data
3549 *
3550 * Reads the flash word at offset into data. Offset is converted
3551 * to bytes before read.
3552 **/
e1000_read_flash_word_ich8lan(struct e1000_hw * hw,u32 offset,u16 * data)3553 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3554 u16 *data)
3555 {
3556 /* Must convert offset into bytes. */
3557 offset <<= 1;
3558
3559 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3560 }
3561
3562 /**
3563 * e1000_read_flash_byte_ich8lan - Read byte from flash
3564 * @hw: pointer to the HW structure
3565 * @offset: The offset of the byte to read.
3566 * @data: Pointer to a byte to store the value read.
3567 *
3568 * Reads a single byte from the NVM using the flash access registers.
3569 **/
e1000_read_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 * data)3570 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3571 u8 *data)
3572 {
3573 s32 ret_val;
3574 u16 word = 0;
3575
3576 /* In SPT, only 32 bits access is supported,
3577 * so this function should not be called.
3578 */
3579 if (hw->mac.type >= e1000_pch_spt)
3580 return -E1000_ERR_NVM;
3581 else
3582 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3583
3584 if (ret_val)
3585 return ret_val;
3586
3587 *data = (u8)word;
3588
3589 return 0;
3590 }
3591
3592 /**
3593 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3594 * @hw: pointer to the HW structure
3595 * @offset: The offset (in bytes) of the byte or word to read.
3596 * @size: Size of data to read, 1=byte 2=word
3597 * @data: Pointer to the word to store the value read.
3598 *
3599 * Reads a byte or word from the NVM using the flash access registers.
3600 **/
e1000_read_flash_data_ich8lan(struct e1000_hw * hw,u32 offset,u8 size,u16 * data)3601 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3602 u8 size, u16 *data)
3603 {
3604 union ich8_hws_flash_status hsfsts;
3605 union ich8_hws_flash_ctrl hsflctl;
3606 u32 flash_linear_addr;
3607 u32 flash_data = 0;
3608 s32 ret_val = -E1000_ERR_NVM;
3609 u8 count = 0;
3610
3611 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3612 return -E1000_ERR_NVM;
3613
3614 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3615 hw->nvm.flash_base_addr);
3616
3617 do {
3618 udelay(1);
3619 /* Steps */
3620 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3621 if (ret_val)
3622 break;
3623
3624 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3625 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3626 hsflctl.hsf_ctrl.fldbcount = size - 1;
3627 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3628 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3629
3630 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3631
3632 ret_val =
3633 e1000_flash_cycle_ich8lan(hw,
3634 ICH_FLASH_READ_COMMAND_TIMEOUT);
3635
3636 /* Check if FCERR is set to 1, if set to 1, clear it
3637 * and try the whole sequence a few more times, else
3638 * read in (shift in) the Flash Data0, the order is
3639 * least significant byte first msb to lsb
3640 */
3641 if (!ret_val) {
3642 flash_data = er32flash(ICH_FLASH_FDATA0);
3643 if (size == 1)
3644 *data = (u8)(flash_data & 0x000000FF);
3645 else if (size == 2)
3646 *data = (u16)(flash_data & 0x0000FFFF);
3647 break;
3648 } else {
3649 /* If we've gotten here, then things are probably
3650 * completely hosed, but if the error condition is
3651 * detected, it won't hurt to give it another try...
3652 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3653 */
3654 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3655 if (hsfsts.hsf_status.flcerr) {
3656 /* Repeat for some time before giving up. */
3657 continue;
3658 } else if (!hsfsts.hsf_status.flcdone) {
3659 e_dbg("Timeout error - flash cycle did not complete.\n");
3660 break;
3661 }
3662 }
3663 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3664
3665 return ret_val;
3666 }
3667
3668 /**
3669 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3670 * @hw: pointer to the HW structure
3671 * @offset: The offset (in bytes) of the dword to read.
3672 * @data: Pointer to the dword to store the value read.
3673 *
3674 * Reads a byte or word from the NVM using the flash access registers.
3675 **/
3676
e1000_read_flash_data32_ich8lan(struct e1000_hw * hw,u32 offset,u32 * data)3677 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3678 u32 *data)
3679 {
3680 union ich8_hws_flash_status hsfsts;
3681 union ich8_hws_flash_ctrl hsflctl;
3682 u32 flash_linear_addr;
3683 s32 ret_val = -E1000_ERR_NVM;
3684 u8 count = 0;
3685
3686 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3687 return -E1000_ERR_NVM;
3688 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3689 hw->nvm.flash_base_addr);
3690
3691 do {
3692 udelay(1);
3693 /* Steps */
3694 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3695 if (ret_val)
3696 break;
3697 /* In SPT, This register is in Lan memory space, not flash.
3698 * Therefore, only 32 bit access is supported
3699 */
3700 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3701
3702 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3703 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3704 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3705 /* In SPT, This register is in Lan memory space, not flash.
3706 * Therefore, only 32 bit access is supported
3707 */
3708 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3709 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3710
3711 ret_val =
3712 e1000_flash_cycle_ich8lan(hw,
3713 ICH_FLASH_READ_COMMAND_TIMEOUT);
3714
3715 /* Check if FCERR is set to 1, if set to 1, clear it
3716 * and try the whole sequence a few more times, else
3717 * read in (shift in) the Flash Data0, the order is
3718 * least significant byte first msb to lsb
3719 */
3720 if (!ret_val) {
3721 *data = er32flash(ICH_FLASH_FDATA0);
3722 break;
3723 } else {
3724 /* If we've gotten here, then things are probably
3725 * completely hosed, but if the error condition is
3726 * detected, it won't hurt to give it another try...
3727 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3728 */
3729 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3730 if (hsfsts.hsf_status.flcerr) {
3731 /* Repeat for some time before giving up. */
3732 continue;
3733 } else if (!hsfsts.hsf_status.flcdone) {
3734 e_dbg("Timeout error - flash cycle did not complete.\n");
3735 break;
3736 }
3737 }
3738 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3739
3740 return ret_val;
3741 }
3742
3743 /**
3744 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3745 * @hw: pointer to the HW structure
3746 * @offset: The offset (in bytes) of the word(s) to write.
3747 * @words: Size of data to write in words
3748 * @data: Pointer to the word(s) to write at offset.
3749 *
3750 * Writes a byte or word to the NVM using the flash access registers.
3751 **/
e1000_write_nvm_ich8lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3752 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3753 u16 *data)
3754 {
3755 struct e1000_nvm_info *nvm = &hw->nvm;
3756 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3757 u16 i;
3758
3759 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3760 (words == 0)) {
3761 e_dbg("nvm parameter(s) out of bounds\n");
3762 return -E1000_ERR_NVM;
3763 }
3764
3765 nvm->ops.acquire(hw);
3766
3767 for (i = 0; i < words; i++) {
3768 dev_spec->shadow_ram[offset + i].modified = true;
3769 dev_spec->shadow_ram[offset + i].value = data[i];
3770 }
3771
3772 nvm->ops.release(hw);
3773
3774 return 0;
3775 }
3776
3777 /**
3778 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3779 * @hw: pointer to the HW structure
3780 *
3781 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3782 * which writes the checksum to the shadow ram. The changes in the shadow
3783 * ram are then committed to the EEPROM by processing each bank at a time
3784 * checking for the modified bit and writing only the pending changes.
3785 * After a successful commit, the shadow ram is cleared and is ready for
3786 * future writes.
3787 **/
e1000_update_nvm_checksum_spt(struct e1000_hw * hw)3788 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3789 {
3790 struct e1000_nvm_info *nvm = &hw->nvm;
3791 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3792 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3793 s32 ret_val;
3794 u32 dword = 0;
3795
3796 ret_val = e1000e_update_nvm_checksum_generic(hw);
3797 if (ret_val)
3798 goto out;
3799
3800 if (nvm->type != e1000_nvm_flash_sw)
3801 goto out;
3802
3803 nvm->ops.acquire(hw);
3804
3805 /* We're writing to the opposite bank so if we're on bank 1,
3806 * write to bank 0 etc. We also need to erase the segment that
3807 * is going to be written
3808 */
3809 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3810 if (ret_val) {
3811 e_dbg("Could not detect valid bank, assuming bank 0\n");
3812 bank = 0;
3813 }
3814
3815 if (bank == 0) {
3816 new_bank_offset = nvm->flash_bank_size;
3817 old_bank_offset = 0;
3818 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3819 if (ret_val)
3820 goto release;
3821 } else {
3822 old_bank_offset = nvm->flash_bank_size;
3823 new_bank_offset = 0;
3824 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3825 if (ret_val)
3826 goto release;
3827 }
3828 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3829 /* Determine whether to write the value stored
3830 * in the other NVM bank or a modified value stored
3831 * in the shadow RAM
3832 */
3833 ret_val = e1000_read_flash_dword_ich8lan(hw,
3834 i + old_bank_offset,
3835 &dword);
3836
3837 if (dev_spec->shadow_ram[i].modified) {
3838 dword &= 0xffff0000;
3839 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3840 }
3841 if (dev_spec->shadow_ram[i + 1].modified) {
3842 dword &= 0x0000ffff;
3843 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3844 << 16);
3845 }
3846 if (ret_val)
3847 break;
3848
3849 /* If the word is 0x13, then make sure the signature bits
3850 * (15:14) are 11b until the commit has completed.
3851 * This will allow us to write 10b which indicates the
3852 * signature is valid. We want to do this after the write
3853 * has completed so that we don't mark the segment valid
3854 * while the write is still in progress
3855 */
3856 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3857 dword |= E1000_ICH_NVM_SIG_MASK << 16;
3858
3859 /* Convert offset to bytes. */
3860 act_offset = (i + new_bank_offset) << 1;
3861
3862 usleep_range(100, 200);
3863
3864 /* Write the data to the new bank. Offset in words */
3865 act_offset = i + new_bank_offset;
3866 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3867 dword);
3868 if (ret_val)
3869 break;
3870 }
3871
3872 /* Don't bother writing the segment valid bits if sector
3873 * programming failed.
3874 */
3875 if (ret_val) {
3876 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3877 e_dbg("Flash commit failed.\n");
3878 goto release;
3879 }
3880
3881 /* Finally validate the new segment by setting bit 15:14
3882 * to 10b in word 0x13 , this can be done without an
3883 * erase as well since these bits are 11 to start with
3884 * and we need to change bit 14 to 0b
3885 */
3886 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3887
3888 /*offset in words but we read dword */
3889 --act_offset;
3890 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3891
3892 if (ret_val)
3893 goto release;
3894
3895 dword &= 0xBFFFFFFF;
3896 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3897
3898 if (ret_val)
3899 goto release;
3900
3901 /* And invalidate the previously valid segment by setting
3902 * its signature word (0x13) high_byte to 0b. This can be
3903 * done without an erase because flash erase sets all bits
3904 * to 1's. We can write 1's to 0's without an erase
3905 */
3906 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3907
3908 /* offset in words but we read dword */
3909 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3910 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3911
3912 if (ret_val)
3913 goto release;
3914
3915 dword &= 0x00FFFFFF;
3916 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3917
3918 if (ret_val)
3919 goto release;
3920
3921 /* Great! Everything worked, we can now clear the cached entries. */
3922 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3923 dev_spec->shadow_ram[i].modified = false;
3924 dev_spec->shadow_ram[i].value = 0xFFFF;
3925 }
3926
3927 release:
3928 nvm->ops.release(hw);
3929
3930 /* Reload the EEPROM, or else modifications will not appear
3931 * until after the next adapter reset.
3932 */
3933 if (!ret_val) {
3934 nvm->ops.reload(hw);
3935 usleep_range(10000, 11000);
3936 }
3937
3938 out:
3939 if (ret_val)
3940 e_dbg("NVM update error: %d\n", ret_val);
3941
3942 return ret_val;
3943 }
3944
3945 /**
3946 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3947 * @hw: pointer to the HW structure
3948 *
3949 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3950 * which writes the checksum to the shadow ram. The changes in the shadow
3951 * ram are then committed to the EEPROM by processing each bank at a time
3952 * checking for the modified bit and writing only the pending changes.
3953 * After a successful commit, the shadow ram is cleared and is ready for
3954 * future writes.
3955 **/
e1000_update_nvm_checksum_ich8lan(struct e1000_hw * hw)3956 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3957 {
3958 struct e1000_nvm_info *nvm = &hw->nvm;
3959 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3960 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3961 s32 ret_val;
3962 u16 data = 0;
3963
3964 ret_val = e1000e_update_nvm_checksum_generic(hw);
3965 if (ret_val)
3966 goto out;
3967
3968 if (nvm->type != e1000_nvm_flash_sw)
3969 goto out;
3970
3971 nvm->ops.acquire(hw);
3972
3973 /* We're writing to the opposite bank so if we're on bank 1,
3974 * write to bank 0 etc. We also need to erase the segment that
3975 * is going to be written
3976 */
3977 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3978 if (ret_val) {
3979 e_dbg("Could not detect valid bank, assuming bank 0\n");
3980 bank = 0;
3981 }
3982
3983 if (bank == 0) {
3984 new_bank_offset = nvm->flash_bank_size;
3985 old_bank_offset = 0;
3986 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3987 if (ret_val)
3988 goto release;
3989 } else {
3990 old_bank_offset = nvm->flash_bank_size;
3991 new_bank_offset = 0;
3992 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3993 if (ret_val)
3994 goto release;
3995 }
3996 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3997 if (dev_spec->shadow_ram[i].modified) {
3998 data = dev_spec->shadow_ram[i].value;
3999 } else {
4000 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4001 old_bank_offset,
4002 &data);
4003 if (ret_val)
4004 break;
4005 }
4006
4007 /* If the word is 0x13, then make sure the signature bits
4008 * (15:14) are 11b until the commit has completed.
4009 * This will allow us to write 10b which indicates the
4010 * signature is valid. We want to do this after the write
4011 * has completed so that we don't mark the segment valid
4012 * while the write is still in progress
4013 */
4014 if (i == E1000_ICH_NVM_SIG_WORD)
4015 data |= E1000_ICH_NVM_SIG_MASK;
4016
4017 /* Convert offset to bytes. */
4018 act_offset = (i + new_bank_offset) << 1;
4019
4020 usleep_range(100, 200);
4021 /* Write the bytes to the new bank. */
4022 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4023 act_offset,
4024 (u8)data);
4025 if (ret_val)
4026 break;
4027
4028 usleep_range(100, 200);
4029 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4030 act_offset + 1,
4031 (u8)(data >> 8));
4032 if (ret_val)
4033 break;
4034 }
4035
4036 /* Don't bother writing the segment valid bits if sector
4037 * programming failed.
4038 */
4039 if (ret_val) {
4040 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4041 e_dbg("Flash commit failed.\n");
4042 goto release;
4043 }
4044
4045 /* Finally validate the new segment by setting bit 15:14
4046 * to 10b in word 0x13 , this can be done without an
4047 * erase as well since these bits are 11 to start with
4048 * and we need to change bit 14 to 0b
4049 */
4050 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4051 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4052 if (ret_val)
4053 goto release;
4054
4055 data &= 0xBFFF;
4056 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4057 act_offset * 2 + 1,
4058 (u8)(data >> 8));
4059 if (ret_val)
4060 goto release;
4061
4062 /* And invalidate the previously valid segment by setting
4063 * its signature word (0x13) high_byte to 0b. This can be
4064 * done without an erase because flash erase sets all bits
4065 * to 1's. We can write 1's to 0's without an erase
4066 */
4067 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4068 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4069 if (ret_val)
4070 goto release;
4071
4072 /* Great! Everything worked, we can now clear the cached entries. */
4073 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4074 dev_spec->shadow_ram[i].modified = false;
4075 dev_spec->shadow_ram[i].value = 0xFFFF;
4076 }
4077
4078 release:
4079 nvm->ops.release(hw);
4080
4081 /* Reload the EEPROM, or else modifications will not appear
4082 * until after the next adapter reset.
4083 */
4084 if (!ret_val) {
4085 nvm->ops.reload(hw);
4086 usleep_range(10000, 11000);
4087 }
4088
4089 out:
4090 if (ret_val)
4091 e_dbg("NVM update error: %d\n", ret_val);
4092
4093 return ret_val;
4094 }
4095
4096 /**
4097 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4098 * @hw: pointer to the HW structure
4099 *
4100 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4101 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4102 * calculated, in which case we need to calculate the checksum and set bit 6.
4103 **/
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw * hw)4104 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4105 {
4106 s32 ret_val;
4107 u16 data;
4108 u16 word;
4109 u16 valid_csum_mask;
4110
4111 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4112 * the checksum needs to be fixed. This bit is an indication that
4113 * the NVM was prepared by OEM software and did not calculate
4114 * the checksum...a likely scenario.
4115 */
4116 switch (hw->mac.type) {
4117 case e1000_pch_lpt:
4118 case e1000_pch_spt:
4119 case e1000_pch_cnp:
4120 case e1000_pch_tgp:
4121 case e1000_pch_adp:
4122 case e1000_pch_mtp:
4123 word = NVM_COMPAT;
4124 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4125 break;
4126 default:
4127 word = NVM_FUTURE_INIT_WORD1;
4128 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4129 break;
4130 }
4131
4132 ret_val = e1000_read_nvm(hw, word, 1, &data);
4133 if (ret_val)
4134 return ret_val;
4135
4136 if (!(data & valid_csum_mask)) {
4137 e_dbg("NVM Checksum valid bit not set\n");
4138
4139 if (hw->mac.type < e1000_pch_tgp) {
4140 data |= valid_csum_mask;
4141 ret_val = e1000_write_nvm(hw, word, 1, &data);
4142 if (ret_val)
4143 return ret_val;
4144 ret_val = e1000e_update_nvm_checksum(hw);
4145 if (ret_val)
4146 return ret_val;
4147 }
4148 }
4149
4150 return e1000e_validate_nvm_checksum_generic(hw);
4151 }
4152
4153 /**
4154 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4155 * @hw: pointer to the HW structure
4156 *
4157 * To prevent malicious write/erase of the NVM, set it to be read-only
4158 * so that the hardware ignores all write/erase cycles of the NVM via
4159 * the flash control registers. The shadow-ram copy of the NVM will
4160 * still be updated, however any updates to this copy will not stick
4161 * across driver reloads.
4162 **/
e1000e_write_protect_nvm_ich8lan(struct e1000_hw * hw)4163 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4164 {
4165 struct e1000_nvm_info *nvm = &hw->nvm;
4166 union ich8_flash_protected_range pr0;
4167 union ich8_hws_flash_status hsfsts;
4168 u32 gfpreg;
4169
4170 nvm->ops.acquire(hw);
4171
4172 gfpreg = er32flash(ICH_FLASH_GFPREG);
4173
4174 /* Write-protect GbE Sector of NVM */
4175 pr0.regval = er32flash(ICH_FLASH_PR0);
4176 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4177 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4178 pr0.range.wpe = true;
4179 ew32flash(ICH_FLASH_PR0, pr0.regval);
4180
4181 /* Lock down a subset of GbE Flash Control Registers, e.g.
4182 * PR0 to prevent the write-protection from being lifted.
4183 * Once FLOCKDN is set, the registers protected by it cannot
4184 * be written until FLOCKDN is cleared by a hardware reset.
4185 */
4186 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4187 hsfsts.hsf_status.flockdn = true;
4188 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4189
4190 nvm->ops.release(hw);
4191 }
4192
4193 /**
4194 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4195 * @hw: pointer to the HW structure
4196 * @offset: The offset (in bytes) of the byte/word to read.
4197 * @size: Size of data to read, 1=byte 2=word
4198 * @data: The byte(s) to write to the NVM.
4199 *
4200 * Writes one/two bytes to the NVM using the flash access registers.
4201 **/
e1000_write_flash_data_ich8lan(struct e1000_hw * hw,u32 offset,u8 size,u16 data)4202 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4203 u8 size, u16 data)
4204 {
4205 union ich8_hws_flash_status hsfsts;
4206 union ich8_hws_flash_ctrl hsflctl;
4207 u32 flash_linear_addr;
4208 u32 flash_data = 0;
4209 s32 ret_val;
4210 u8 count = 0;
4211
4212 if (hw->mac.type >= e1000_pch_spt) {
4213 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4214 return -E1000_ERR_NVM;
4215 } else {
4216 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4217 return -E1000_ERR_NVM;
4218 }
4219
4220 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4221 hw->nvm.flash_base_addr);
4222
4223 do {
4224 udelay(1);
4225 /* Steps */
4226 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4227 if (ret_val)
4228 break;
4229 /* In SPT, This register is in Lan memory space, not
4230 * flash. Therefore, only 32 bit access is supported
4231 */
4232 if (hw->mac.type >= e1000_pch_spt)
4233 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4234 else
4235 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4236
4237 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4238 hsflctl.hsf_ctrl.fldbcount = size - 1;
4239 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4240 /* In SPT, This register is in Lan memory space,
4241 * not flash. Therefore, only 32 bit access is
4242 * supported
4243 */
4244 if (hw->mac.type >= e1000_pch_spt)
4245 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4246 else
4247 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4248
4249 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4250
4251 if (size == 1)
4252 flash_data = (u32)data & 0x00FF;
4253 else
4254 flash_data = (u32)data;
4255
4256 ew32flash(ICH_FLASH_FDATA0, flash_data);
4257
4258 /* check if FCERR is set to 1 , if set to 1, clear it
4259 * and try the whole sequence a few more times else done
4260 */
4261 ret_val =
4262 e1000_flash_cycle_ich8lan(hw,
4263 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4264 if (!ret_val)
4265 break;
4266
4267 /* If we're here, then things are most likely
4268 * completely hosed, but if the error condition
4269 * is detected, it won't hurt to give it another
4270 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4271 */
4272 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4273 if (hsfsts.hsf_status.flcerr)
4274 /* Repeat for some time before giving up. */
4275 continue;
4276 if (!hsfsts.hsf_status.flcdone) {
4277 e_dbg("Timeout error - flash cycle did not complete.\n");
4278 break;
4279 }
4280 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4281
4282 return ret_val;
4283 }
4284
4285 /**
4286 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4287 * @hw: pointer to the HW structure
4288 * @offset: The offset (in bytes) of the dwords to read.
4289 * @data: The 4 bytes to write to the NVM.
4290 *
4291 * Writes one/two/four bytes to the NVM using the flash access registers.
4292 **/
e1000_write_flash_data32_ich8lan(struct e1000_hw * hw,u32 offset,u32 data)4293 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4294 u32 data)
4295 {
4296 union ich8_hws_flash_status hsfsts;
4297 union ich8_hws_flash_ctrl hsflctl;
4298 u32 flash_linear_addr;
4299 s32 ret_val;
4300 u8 count = 0;
4301
4302 if (hw->mac.type >= e1000_pch_spt) {
4303 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4304 return -E1000_ERR_NVM;
4305 }
4306 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4307 hw->nvm.flash_base_addr);
4308 do {
4309 udelay(1);
4310 /* Steps */
4311 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4312 if (ret_val)
4313 break;
4314
4315 /* In SPT, This register is in Lan memory space, not
4316 * flash. Therefore, only 32 bit access is supported
4317 */
4318 if (hw->mac.type >= e1000_pch_spt)
4319 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4320 >> 16;
4321 else
4322 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4323
4324 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4325 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4326
4327 /* In SPT, This register is in Lan memory space,
4328 * not flash. Therefore, only 32 bit access is
4329 * supported
4330 */
4331 if (hw->mac.type >= e1000_pch_spt)
4332 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4333 else
4334 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4335
4336 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4337
4338 ew32flash(ICH_FLASH_FDATA0, data);
4339
4340 /* check if FCERR is set to 1 , if set to 1, clear it
4341 * and try the whole sequence a few more times else done
4342 */
4343 ret_val =
4344 e1000_flash_cycle_ich8lan(hw,
4345 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4346
4347 if (!ret_val)
4348 break;
4349
4350 /* If we're here, then things are most likely
4351 * completely hosed, but if the error condition
4352 * is detected, it won't hurt to give it another
4353 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4354 */
4355 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4356
4357 if (hsfsts.hsf_status.flcerr)
4358 /* Repeat for some time before giving up. */
4359 continue;
4360 if (!hsfsts.hsf_status.flcdone) {
4361 e_dbg("Timeout error - flash cycle did not complete.\n");
4362 break;
4363 }
4364 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4365
4366 return ret_val;
4367 }
4368
4369 /**
4370 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4371 * @hw: pointer to the HW structure
4372 * @offset: The index of the byte to read.
4373 * @data: The byte to write to the NVM.
4374 *
4375 * Writes a single byte to the NVM using the flash access registers.
4376 **/
e1000_write_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 data)4377 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4378 u8 data)
4379 {
4380 u16 word = (u16)data;
4381
4382 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4383 }
4384
4385 /**
4386 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4387 * @hw: pointer to the HW structure
4388 * @offset: The offset of the word to write.
4389 * @dword: The dword to write to the NVM.
4390 *
4391 * Writes a single dword to the NVM using the flash access registers.
4392 * Goes through a retry algorithm before giving up.
4393 **/
e1000_retry_write_flash_dword_ich8lan(struct e1000_hw * hw,u32 offset,u32 dword)4394 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4395 u32 offset, u32 dword)
4396 {
4397 s32 ret_val;
4398 u16 program_retries;
4399
4400 /* Must convert word offset into bytes. */
4401 offset <<= 1;
4402 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4403
4404 if (!ret_val)
4405 return ret_val;
4406 for (program_retries = 0; program_retries < 100; program_retries++) {
4407 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4408 usleep_range(100, 200);
4409 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4410 if (!ret_val)
4411 break;
4412 }
4413 if (program_retries == 100)
4414 return -E1000_ERR_NVM;
4415
4416 return 0;
4417 }
4418
4419 /**
4420 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4421 * @hw: pointer to the HW structure
4422 * @offset: The offset of the byte to write.
4423 * @byte: The byte to write to the NVM.
4424 *
4425 * Writes a single byte to the NVM using the flash access registers.
4426 * Goes through a retry algorithm before giving up.
4427 **/
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 byte)4428 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4429 u32 offset, u8 byte)
4430 {
4431 s32 ret_val;
4432 u16 program_retries;
4433
4434 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4435 if (!ret_val)
4436 return ret_val;
4437
4438 for (program_retries = 0; program_retries < 100; program_retries++) {
4439 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4440 usleep_range(100, 200);
4441 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4442 if (!ret_val)
4443 break;
4444 }
4445 if (program_retries == 100)
4446 return -E1000_ERR_NVM;
4447
4448 return 0;
4449 }
4450
4451 /**
4452 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4453 * @hw: pointer to the HW structure
4454 * @bank: 0 for first bank, 1 for second bank, etc.
4455 *
4456 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4457 * bank N is 4096 * N + flash_reg_addr.
4458 **/
e1000_erase_flash_bank_ich8lan(struct e1000_hw * hw,u32 bank)4459 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4460 {
4461 struct e1000_nvm_info *nvm = &hw->nvm;
4462 union ich8_hws_flash_status hsfsts;
4463 union ich8_hws_flash_ctrl hsflctl;
4464 u32 flash_linear_addr;
4465 /* bank size is in 16bit words - adjust to bytes */
4466 u32 flash_bank_size = nvm->flash_bank_size * 2;
4467 s32 ret_val;
4468 s32 count = 0;
4469 s32 j, iteration, sector_size;
4470
4471 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4472
4473 /* Determine HW Sector size: Read BERASE bits of hw flash status
4474 * register
4475 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4476 * consecutive sectors. The start index for the nth Hw sector
4477 * can be calculated as = bank * 4096 + n * 256
4478 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4479 * The start index for the nth Hw sector can be calculated
4480 * as = bank * 4096
4481 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4482 * (ich9 only, otherwise error condition)
4483 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4484 */
4485 switch (hsfsts.hsf_status.berasesz) {
4486 case 0:
4487 /* Hw sector size 256 */
4488 sector_size = ICH_FLASH_SEG_SIZE_256;
4489 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4490 break;
4491 case 1:
4492 sector_size = ICH_FLASH_SEG_SIZE_4K;
4493 iteration = 1;
4494 break;
4495 case 2:
4496 sector_size = ICH_FLASH_SEG_SIZE_8K;
4497 iteration = 1;
4498 break;
4499 case 3:
4500 sector_size = ICH_FLASH_SEG_SIZE_64K;
4501 iteration = 1;
4502 break;
4503 default:
4504 return -E1000_ERR_NVM;
4505 }
4506
4507 /* Start with the base address, then add the sector offset. */
4508 flash_linear_addr = hw->nvm.flash_base_addr;
4509 flash_linear_addr += (bank) ? flash_bank_size : 0;
4510
4511 for (j = 0; j < iteration; j++) {
4512 do {
4513 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4514
4515 /* Steps */
4516 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4517 if (ret_val)
4518 return ret_val;
4519
4520 /* Write a value 11 (block Erase) in Flash
4521 * Cycle field in hw flash control
4522 */
4523 if (hw->mac.type >= e1000_pch_spt)
4524 hsflctl.regval =
4525 er32flash(ICH_FLASH_HSFSTS) >> 16;
4526 else
4527 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4528
4529 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4530 if (hw->mac.type >= e1000_pch_spt)
4531 ew32flash(ICH_FLASH_HSFSTS,
4532 hsflctl.regval << 16);
4533 else
4534 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4535
4536 /* Write the last 24 bits of an index within the
4537 * block into Flash Linear address field in Flash
4538 * Address.
4539 */
4540 flash_linear_addr += (j * sector_size);
4541 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4542
4543 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4544 if (!ret_val)
4545 break;
4546
4547 /* Check if FCERR is set to 1. If 1,
4548 * clear it and try the whole sequence
4549 * a few more times else Done
4550 */
4551 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4552 if (hsfsts.hsf_status.flcerr)
4553 /* repeat for some time before giving up */
4554 continue;
4555 else if (!hsfsts.hsf_status.flcdone)
4556 return ret_val;
4557 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4558 }
4559
4560 return 0;
4561 }
4562
4563 /**
4564 * e1000_valid_led_default_ich8lan - Set the default LED settings
4565 * @hw: pointer to the HW structure
4566 * @data: Pointer to the LED settings
4567 *
4568 * Reads the LED default settings from the NVM to data. If the NVM LED
4569 * settings is all 0's or F's, set the LED default to a valid LED default
4570 * setting.
4571 **/
e1000_valid_led_default_ich8lan(struct e1000_hw * hw,u16 * data)4572 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4573 {
4574 s32 ret_val;
4575
4576 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4577 if (ret_val) {
4578 e_dbg("NVM Read Error\n");
4579 return ret_val;
4580 }
4581
4582 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4583 *data = ID_LED_DEFAULT_ICH8LAN;
4584
4585 return 0;
4586 }
4587
4588 /**
4589 * e1000_id_led_init_pchlan - store LED configurations
4590 * @hw: pointer to the HW structure
4591 *
4592 * PCH does not control LEDs via the LEDCTL register, rather it uses
4593 * the PHY LED configuration register.
4594 *
4595 * PCH also does not have an "always on" or "always off" mode which
4596 * complicates the ID feature. Instead of using the "on" mode to indicate
4597 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4598 * use "link_up" mode. The LEDs will still ID on request if there is no
4599 * link based on logic in e1000_led_[on|off]_pchlan().
4600 **/
e1000_id_led_init_pchlan(struct e1000_hw * hw)4601 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4602 {
4603 struct e1000_mac_info *mac = &hw->mac;
4604 s32 ret_val;
4605 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4606 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4607 u16 data, i, temp, shift;
4608
4609 /* Get default ID LED modes */
4610 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4611 if (ret_val)
4612 return ret_val;
4613
4614 mac->ledctl_default = er32(LEDCTL);
4615 mac->ledctl_mode1 = mac->ledctl_default;
4616 mac->ledctl_mode2 = mac->ledctl_default;
4617
4618 for (i = 0; i < 4; i++) {
4619 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4620 shift = (i * 5);
4621 switch (temp) {
4622 case ID_LED_ON1_DEF2:
4623 case ID_LED_ON1_ON2:
4624 case ID_LED_ON1_OFF2:
4625 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4626 mac->ledctl_mode1 |= (ledctl_on << shift);
4627 break;
4628 case ID_LED_OFF1_DEF2:
4629 case ID_LED_OFF1_ON2:
4630 case ID_LED_OFF1_OFF2:
4631 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4632 mac->ledctl_mode1 |= (ledctl_off << shift);
4633 break;
4634 default:
4635 /* Do nothing */
4636 break;
4637 }
4638 switch (temp) {
4639 case ID_LED_DEF1_ON2:
4640 case ID_LED_ON1_ON2:
4641 case ID_LED_OFF1_ON2:
4642 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4643 mac->ledctl_mode2 |= (ledctl_on << shift);
4644 break;
4645 case ID_LED_DEF1_OFF2:
4646 case ID_LED_ON1_OFF2:
4647 case ID_LED_OFF1_OFF2:
4648 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4649 mac->ledctl_mode2 |= (ledctl_off << shift);
4650 break;
4651 default:
4652 /* Do nothing */
4653 break;
4654 }
4655 }
4656
4657 return 0;
4658 }
4659
4660 /**
4661 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4662 * @hw: pointer to the HW structure
4663 *
4664 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4665 * register, so the the bus width is hard coded.
4666 **/
e1000_get_bus_info_ich8lan(struct e1000_hw * hw)4667 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4668 {
4669 struct e1000_bus_info *bus = &hw->bus;
4670 s32 ret_val;
4671
4672 ret_val = e1000e_get_bus_info_pcie(hw);
4673
4674 /* ICH devices are "PCI Express"-ish. They have
4675 * a configuration space, but do not contain
4676 * PCI Express Capability registers, so bus width
4677 * must be hardcoded.
4678 */
4679 if (bus->width == e1000_bus_width_unknown)
4680 bus->width = e1000_bus_width_pcie_x1;
4681
4682 return ret_val;
4683 }
4684
4685 /**
4686 * e1000_reset_hw_ich8lan - Reset the hardware
4687 * @hw: pointer to the HW structure
4688 *
4689 * Does a full reset of the hardware which includes a reset of the PHY and
4690 * MAC.
4691 **/
e1000_reset_hw_ich8lan(struct e1000_hw * hw)4692 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4693 {
4694 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4695 u16 kum_cfg;
4696 u32 ctrl, reg;
4697 s32 ret_val;
4698
4699 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4700 * on the last TLP read/write transaction when MAC is reset.
4701 */
4702 ret_val = e1000e_disable_pcie_master(hw);
4703 if (ret_val)
4704 e_dbg("PCI-E Master disable polling has failed.\n");
4705
4706 e_dbg("Masking off all interrupts\n");
4707 ew32(IMC, 0xffffffff);
4708
4709 /* Disable the Transmit and Receive units. Then delay to allow
4710 * any pending transactions to complete before we hit the MAC
4711 * with the global reset.
4712 */
4713 ew32(RCTL, 0);
4714 ew32(TCTL, E1000_TCTL_PSP);
4715 e1e_flush();
4716
4717 usleep_range(10000, 11000);
4718
4719 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4720 if (hw->mac.type == e1000_ich8lan) {
4721 /* Set Tx and Rx buffer allocation to 8k apiece. */
4722 ew32(PBA, E1000_PBA_8K);
4723 /* Set Packet Buffer Size to 16k. */
4724 ew32(PBS, E1000_PBS_16K);
4725 }
4726
4727 if (hw->mac.type == e1000_pchlan) {
4728 /* Save the NVM K1 bit setting */
4729 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4730 if (ret_val)
4731 return ret_val;
4732
4733 if (kum_cfg & E1000_NVM_K1_ENABLE)
4734 dev_spec->nvm_k1_enabled = true;
4735 else
4736 dev_spec->nvm_k1_enabled = false;
4737 }
4738
4739 ctrl = er32(CTRL);
4740
4741 if (!hw->phy.ops.check_reset_block(hw)) {
4742 /* Full-chip reset requires MAC and PHY reset at the same
4743 * time to make sure the interface between MAC and the
4744 * external PHY is reset.
4745 */
4746 ctrl |= E1000_CTRL_PHY_RST;
4747
4748 /* Gate automatic PHY configuration by hardware on
4749 * non-managed 82579
4750 */
4751 if ((hw->mac.type == e1000_pch2lan) &&
4752 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4753 e1000_gate_hw_phy_config_ich8lan(hw, true);
4754 }
4755 ret_val = e1000_acquire_swflag_ich8lan(hw);
4756 e_dbg("Issuing a global reset to ich8lan\n");
4757 ew32(CTRL, (ctrl | E1000_CTRL_RST));
4758 /* cannot issue a flush here because it hangs the hardware */
4759 msleep(20);
4760
4761 /* Set Phy Config Counter to 50msec */
4762 if (hw->mac.type == e1000_pch2lan) {
4763 reg = er32(FEXTNVM3);
4764 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4765 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4766 ew32(FEXTNVM3, reg);
4767 }
4768
4769 if (!ret_val)
4770 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4771
4772 if (ctrl & E1000_CTRL_PHY_RST) {
4773 ret_val = hw->phy.ops.get_cfg_done(hw);
4774 if (ret_val)
4775 return ret_val;
4776
4777 ret_val = e1000_post_phy_reset_ich8lan(hw);
4778 if (ret_val)
4779 return ret_val;
4780 }
4781
4782 /* For PCH, this write will make sure that any noise
4783 * will be detected as a CRC error and be dropped rather than show up
4784 * as a bad packet to the DMA engine.
4785 */
4786 if (hw->mac.type == e1000_pchlan)
4787 ew32(CRC_OFFSET, 0x65656565);
4788
4789 ew32(IMC, 0xffffffff);
4790 er32(ICR);
4791
4792 reg = er32(KABGTXD);
4793 reg |= E1000_KABGTXD_BGSQLBIAS;
4794 ew32(KABGTXD, reg);
4795
4796 return 0;
4797 }
4798
4799 /**
4800 * e1000_init_hw_ich8lan - Initialize the hardware
4801 * @hw: pointer to the HW structure
4802 *
4803 * Prepares the hardware for transmit and receive by doing the following:
4804 * - initialize hardware bits
4805 * - initialize LED identification
4806 * - setup receive address registers
4807 * - setup flow control
4808 * - setup transmit descriptors
4809 * - clear statistics
4810 **/
e1000_init_hw_ich8lan(struct e1000_hw * hw)4811 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4812 {
4813 struct e1000_mac_info *mac = &hw->mac;
4814 u32 ctrl_ext, txdctl, snoop, fflt_dbg;
4815 s32 ret_val;
4816 u16 i;
4817
4818 e1000_initialize_hw_bits_ich8lan(hw);
4819
4820 /* Initialize identification LED */
4821 ret_val = mac->ops.id_led_init(hw);
4822 /* An error is not fatal and we should not stop init due to this */
4823 if (ret_val)
4824 e_dbg("Error initializing identification LED\n");
4825
4826 /* Setup the receive address. */
4827 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4828
4829 /* Zero out the Multicast HASH table */
4830 e_dbg("Zeroing the MTA\n");
4831 for (i = 0; i < mac->mta_reg_count; i++)
4832 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4833
4834 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4835 * the ME. Disable wakeup by clearing the host wakeup bit.
4836 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4837 */
4838 if (hw->phy.type == e1000_phy_82578) {
4839 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4840 i &= ~BM_WUC_HOST_WU_BIT;
4841 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4842 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4843 if (ret_val)
4844 return ret_val;
4845 }
4846
4847 /* Setup link and flow control */
4848 ret_val = mac->ops.setup_link(hw);
4849
4850 /* Set the transmit descriptor write-back policy for both queues */
4851 txdctl = er32(TXDCTL(0));
4852 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4853 E1000_TXDCTL_FULL_TX_DESC_WB);
4854 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4855 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4856 ew32(TXDCTL(0), txdctl);
4857 txdctl = er32(TXDCTL(1));
4858 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4859 E1000_TXDCTL_FULL_TX_DESC_WB);
4860 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4861 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4862 ew32(TXDCTL(1), txdctl);
4863
4864 /* ICH8 has opposite polarity of no_snoop bits.
4865 * By default, we should use snoop behavior.
4866 */
4867 if (mac->type == e1000_ich8lan)
4868 snoop = PCIE_ICH8_SNOOP_ALL;
4869 else
4870 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4871 e1000e_set_pcie_no_snoop(hw, snoop);
4872
4873 /* Enable workaround for packet loss issue on TGP PCH
4874 * Do not gate DMA clock from the modPHY block
4875 */
4876 if (mac->type >= e1000_pch_tgp) {
4877 fflt_dbg = er32(FFLT_DBG);
4878 fflt_dbg |= E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK;
4879 ew32(FFLT_DBG, fflt_dbg);
4880 }
4881
4882 ctrl_ext = er32(CTRL_EXT);
4883 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4884 ew32(CTRL_EXT, ctrl_ext);
4885
4886 /* Clear all of the statistics registers (clear on read). It is
4887 * important that we do this after we have tried to establish link
4888 * because the symbol error count will increment wildly if there
4889 * is no link.
4890 */
4891 e1000_clear_hw_cntrs_ich8lan(hw);
4892
4893 return ret_val;
4894 }
4895
4896 /**
4897 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4898 * @hw: pointer to the HW structure
4899 *
4900 * Sets/Clears required hardware bits necessary for correctly setting up the
4901 * hardware for transmit and receive.
4902 **/
e1000_initialize_hw_bits_ich8lan(struct e1000_hw * hw)4903 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4904 {
4905 u32 reg;
4906
4907 /* Extended Device Control */
4908 reg = er32(CTRL_EXT);
4909 reg |= BIT(22);
4910 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4911 if (hw->mac.type >= e1000_pchlan)
4912 reg |= E1000_CTRL_EXT_PHYPDEN;
4913 ew32(CTRL_EXT, reg);
4914
4915 /* Transmit Descriptor Control 0 */
4916 reg = er32(TXDCTL(0));
4917 reg |= BIT(22);
4918 ew32(TXDCTL(0), reg);
4919
4920 /* Transmit Descriptor Control 1 */
4921 reg = er32(TXDCTL(1));
4922 reg |= BIT(22);
4923 ew32(TXDCTL(1), reg);
4924
4925 /* Transmit Arbitration Control 0 */
4926 reg = er32(TARC(0));
4927 if (hw->mac.type == e1000_ich8lan)
4928 reg |= BIT(28) | BIT(29);
4929 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4930 ew32(TARC(0), reg);
4931
4932 /* Transmit Arbitration Control 1 */
4933 reg = er32(TARC(1));
4934 if (er32(TCTL) & E1000_TCTL_MULR)
4935 reg &= ~BIT(28);
4936 else
4937 reg |= BIT(28);
4938 reg |= BIT(24) | BIT(26) | BIT(30);
4939 ew32(TARC(1), reg);
4940
4941 /* Device Status */
4942 if (hw->mac.type == e1000_ich8lan) {
4943 reg = er32(STATUS);
4944 reg &= ~BIT(31);
4945 ew32(STATUS, reg);
4946 }
4947
4948 /* work-around descriptor data corruption issue during nfs v2 udp
4949 * traffic, just disable the nfs filtering capability
4950 */
4951 reg = er32(RFCTL);
4952 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4953
4954 /* Disable IPv6 extension header parsing because some malformed
4955 * IPv6 headers can hang the Rx.
4956 */
4957 if (hw->mac.type == e1000_ich8lan)
4958 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4959 ew32(RFCTL, reg);
4960
4961 /* Enable ECC on Lynxpoint */
4962 if (hw->mac.type >= e1000_pch_lpt) {
4963 reg = er32(PBECCSTS);
4964 reg |= E1000_PBECCSTS_ECC_ENABLE;
4965 ew32(PBECCSTS, reg);
4966
4967 reg = er32(CTRL);
4968 reg |= E1000_CTRL_MEHE;
4969 ew32(CTRL, reg);
4970 }
4971 }
4972
4973 /**
4974 * e1000_setup_link_ich8lan - Setup flow control and link settings
4975 * @hw: pointer to the HW structure
4976 *
4977 * Determines which flow control settings to use, then configures flow
4978 * control. Calls the appropriate media-specific link configuration
4979 * function. Assuming the adapter has a valid link partner, a valid link
4980 * should be established. Assumes the hardware has previously been reset
4981 * and the transmitter and receiver are not enabled.
4982 **/
e1000_setup_link_ich8lan(struct e1000_hw * hw)4983 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4984 {
4985 s32 ret_val;
4986
4987 if (hw->phy.ops.check_reset_block(hw))
4988 return 0;
4989
4990 /* ICH parts do not have a word in the NVM to determine
4991 * the default flow control setting, so we explicitly
4992 * set it to full.
4993 */
4994 if (hw->fc.requested_mode == e1000_fc_default) {
4995 /* Workaround h/w hang when Tx flow control enabled */
4996 if (hw->mac.type == e1000_pchlan)
4997 hw->fc.requested_mode = e1000_fc_rx_pause;
4998 else
4999 hw->fc.requested_mode = e1000_fc_full;
5000 }
5001
5002 /* Save off the requested flow control mode for use later. Depending
5003 * on the link partner's capabilities, we may or may not use this mode.
5004 */
5005 hw->fc.current_mode = hw->fc.requested_mode;
5006
5007 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
5008
5009 /* Continue to configure the copper link. */
5010 ret_val = hw->mac.ops.setup_physical_interface(hw);
5011 if (ret_val)
5012 return ret_val;
5013
5014 ew32(FCTTV, hw->fc.pause_time);
5015 if ((hw->phy.type == e1000_phy_82578) ||
5016 (hw->phy.type == e1000_phy_82579) ||
5017 (hw->phy.type == e1000_phy_i217) ||
5018 (hw->phy.type == e1000_phy_82577)) {
5019 ew32(FCRTV_PCH, hw->fc.refresh_time);
5020
5021 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
5022 hw->fc.pause_time);
5023 if (ret_val)
5024 return ret_val;
5025 }
5026
5027 return e1000e_set_fc_watermarks(hw);
5028 }
5029
5030 /**
5031 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5032 * @hw: pointer to the HW structure
5033 *
5034 * Configures the kumeran interface to the PHY to wait the appropriate time
5035 * when polling the PHY, then call the generic setup_copper_link to finish
5036 * configuring the copper link.
5037 **/
e1000_setup_copper_link_ich8lan(struct e1000_hw * hw)5038 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5039 {
5040 u32 ctrl;
5041 s32 ret_val;
5042 u16 reg_data;
5043
5044 ctrl = er32(CTRL);
5045 ctrl |= E1000_CTRL_SLU;
5046 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5047 ew32(CTRL, ctrl);
5048
5049 /* Set the mac to wait the maximum time between each iteration
5050 * and increase the max iterations when polling the phy;
5051 * this fixes erroneous timeouts at 10Mbps.
5052 */
5053 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
5054 if (ret_val)
5055 return ret_val;
5056 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5057 ®_data);
5058 if (ret_val)
5059 return ret_val;
5060 reg_data |= 0x3F;
5061 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5062 reg_data);
5063 if (ret_val)
5064 return ret_val;
5065
5066 switch (hw->phy.type) {
5067 case e1000_phy_igp_3:
5068 ret_val = e1000e_copper_link_setup_igp(hw);
5069 if (ret_val)
5070 return ret_val;
5071 break;
5072 case e1000_phy_bm:
5073 case e1000_phy_82578:
5074 ret_val = e1000e_copper_link_setup_m88(hw);
5075 if (ret_val)
5076 return ret_val;
5077 break;
5078 case e1000_phy_82577:
5079 case e1000_phy_82579:
5080 ret_val = e1000_copper_link_setup_82577(hw);
5081 if (ret_val)
5082 return ret_val;
5083 break;
5084 case e1000_phy_ife:
5085 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data);
5086 if (ret_val)
5087 return ret_val;
5088
5089 reg_data &= ~IFE_PMC_AUTO_MDIX;
5090
5091 switch (hw->phy.mdix) {
5092 case 1:
5093 reg_data &= ~IFE_PMC_FORCE_MDIX;
5094 break;
5095 case 2:
5096 reg_data |= IFE_PMC_FORCE_MDIX;
5097 break;
5098 case 0:
5099 default:
5100 reg_data |= IFE_PMC_AUTO_MDIX;
5101 break;
5102 }
5103 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5104 if (ret_val)
5105 return ret_val;
5106 break;
5107 default:
5108 break;
5109 }
5110
5111 return e1000e_setup_copper_link(hw);
5112 }
5113
5114 /**
5115 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5116 * @hw: pointer to the HW structure
5117 *
5118 * Calls the PHY specific link setup function and then calls the
5119 * generic setup_copper_link to finish configuring the link for
5120 * Lynxpoint PCH devices
5121 **/
e1000_setup_copper_link_pch_lpt(struct e1000_hw * hw)5122 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5123 {
5124 u32 ctrl;
5125 s32 ret_val;
5126
5127 ctrl = er32(CTRL);
5128 ctrl |= E1000_CTRL_SLU;
5129 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5130 ew32(CTRL, ctrl);
5131
5132 ret_val = e1000_copper_link_setup_82577(hw);
5133 if (ret_val)
5134 return ret_val;
5135
5136 return e1000e_setup_copper_link(hw);
5137 }
5138
5139 /**
5140 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5141 * @hw: pointer to the HW structure
5142 * @speed: pointer to store current link speed
5143 * @duplex: pointer to store the current link duplex
5144 *
5145 * Calls the generic get_speed_and_duplex to retrieve the current link
5146 * information and then calls the Kumeran lock loss workaround for links at
5147 * gigabit speeds.
5148 **/
e1000_get_link_up_info_ich8lan(struct e1000_hw * hw,u16 * speed,u16 * duplex)5149 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5150 u16 *duplex)
5151 {
5152 s32 ret_val;
5153
5154 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5155 if (ret_val)
5156 return ret_val;
5157
5158 if ((hw->mac.type == e1000_ich8lan) &&
5159 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5160 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5161 }
5162
5163 return ret_val;
5164 }
5165
5166 /**
5167 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5168 * @hw: pointer to the HW structure
5169 *
5170 * Work-around for 82566 Kumeran PCS lock loss:
5171 * On link status change (i.e. PCI reset, speed change) and link is up and
5172 * speed is gigabit-
5173 * 0) if workaround is optionally disabled do nothing
5174 * 1) wait 1ms for Kumeran link to come up
5175 * 2) check Kumeran Diagnostic register PCS lock loss bit
5176 * 3) if not set the link is locked (all is good), otherwise...
5177 * 4) reset the PHY
5178 * 5) repeat up to 10 times
5179 * Note: this is only called for IGP3 copper when speed is 1gb.
5180 **/
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw * hw)5181 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5182 {
5183 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5184 u32 phy_ctrl;
5185 s32 ret_val;
5186 u16 i, data;
5187 bool link;
5188
5189 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5190 return 0;
5191
5192 /* Make sure link is up before proceeding. If not just return.
5193 * Attempting this while link is negotiating fouled up link
5194 * stability
5195 */
5196 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5197 if (!link)
5198 return 0;
5199
5200 for (i = 0; i < 10; i++) {
5201 /* read once to clear */
5202 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5203 if (ret_val)
5204 return ret_val;
5205 /* and again to get new status */
5206 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5207 if (ret_val)
5208 return ret_val;
5209
5210 /* check for PCS lock */
5211 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5212 return 0;
5213
5214 /* Issue PHY reset */
5215 e1000_phy_hw_reset(hw);
5216 mdelay(5);
5217 }
5218 /* Disable GigE link negotiation */
5219 phy_ctrl = er32(PHY_CTRL);
5220 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5221 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5222 ew32(PHY_CTRL, phy_ctrl);
5223
5224 /* Call gig speed drop workaround on Gig disable before accessing
5225 * any PHY registers
5226 */
5227 e1000e_gig_downshift_workaround_ich8lan(hw);
5228
5229 /* unable to acquire PCS lock */
5230 return -E1000_ERR_PHY;
5231 }
5232
5233 /**
5234 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5235 * @hw: pointer to the HW structure
5236 * @state: boolean value used to set the current Kumeran workaround state
5237 *
5238 * If ICH8, set the current Kumeran workaround state (enabled - true
5239 * /disabled - false).
5240 **/
e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw * hw,bool state)5241 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5242 bool state)
5243 {
5244 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5245
5246 if (hw->mac.type != e1000_ich8lan) {
5247 e_dbg("Workaround applies to ICH8 only.\n");
5248 return;
5249 }
5250
5251 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5252 }
5253
5254 /**
5255 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5256 * @hw: pointer to the HW structure
5257 *
5258 * Workaround for 82566 power-down on D3 entry:
5259 * 1) disable gigabit link
5260 * 2) write VR power-down enable
5261 * 3) read it back
5262 * Continue if successful, else issue LCD reset and repeat
5263 **/
e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw * hw)5264 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5265 {
5266 u32 reg;
5267 u16 data;
5268 u8 retry = 0;
5269
5270 if (hw->phy.type != e1000_phy_igp_3)
5271 return;
5272
5273 /* Try the workaround twice (if needed) */
5274 do {
5275 /* Disable link */
5276 reg = er32(PHY_CTRL);
5277 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5278 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5279 ew32(PHY_CTRL, reg);
5280
5281 /* Call gig speed drop workaround on Gig disable before
5282 * accessing any PHY registers
5283 */
5284 if (hw->mac.type == e1000_ich8lan)
5285 e1000e_gig_downshift_workaround_ich8lan(hw);
5286
5287 /* Write VR power-down enable */
5288 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5289 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5290 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5291
5292 /* Read it back and test */
5293 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5294 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5295 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5296 break;
5297
5298 /* Issue PHY reset and repeat at most one more time */
5299 reg = er32(CTRL);
5300 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5301 retry++;
5302 } while (retry);
5303 }
5304
5305 /**
5306 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5307 * @hw: pointer to the HW structure
5308 *
5309 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5310 * LPLU, Gig disable, MDIC PHY reset):
5311 * 1) Set Kumeran Near-end loopback
5312 * 2) Clear Kumeran Near-end loopback
5313 * Should only be called for ICH8[m] devices with any 1G Phy.
5314 **/
e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw * hw)5315 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5316 {
5317 s32 ret_val;
5318 u16 reg_data;
5319
5320 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5321 return;
5322
5323 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5324 ®_data);
5325 if (ret_val)
5326 return;
5327 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5328 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5329 reg_data);
5330 if (ret_val)
5331 return;
5332 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5333 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5334 }
5335
5336 /**
5337 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5338 * @hw: pointer to the HW structure
5339 *
5340 * During S0 to Sx transition, it is possible the link remains at gig
5341 * instead of negotiating to a lower speed. Before going to Sx, set
5342 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5343 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5344 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5345 * needs to be written.
5346 * Parts that support (and are linked to a partner which support) EEE in
5347 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5348 * than 10Mbps w/o EEE.
5349 **/
e1000_suspend_workarounds_ich8lan(struct e1000_hw * hw)5350 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5351 {
5352 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5353 u32 phy_ctrl;
5354 s32 ret_val;
5355
5356 phy_ctrl = er32(PHY_CTRL);
5357 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5358
5359 if (hw->phy.type == e1000_phy_i217) {
5360 u16 phy_reg, device_id = hw->adapter->pdev->device;
5361
5362 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5363 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5364 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5365 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5366 (hw->mac.type >= e1000_pch_spt)) {
5367 u32 fextnvm6 = er32(FEXTNVM6);
5368
5369 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5370 }
5371
5372 ret_val = hw->phy.ops.acquire(hw);
5373 if (ret_val)
5374 goto out;
5375
5376 if (!dev_spec->eee_disable) {
5377 u16 eee_advert;
5378
5379 ret_val =
5380 e1000_read_emi_reg_locked(hw,
5381 I217_EEE_ADVERTISEMENT,
5382 &eee_advert);
5383 if (ret_val)
5384 goto release;
5385
5386 /* Disable LPLU if both link partners support 100BaseT
5387 * EEE and 100Full is advertised on both ends of the
5388 * link, and enable Auto Enable LPI since there will
5389 * be no driver to enable LPI while in Sx.
5390 */
5391 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5392 (dev_spec->eee_lp_ability &
5393 I82579_EEE_100_SUPPORTED) &&
5394 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5395 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5396 E1000_PHY_CTRL_NOND0A_LPLU);
5397
5398 /* Set Auto Enable LPI after link up */
5399 e1e_rphy_locked(hw,
5400 I217_LPI_GPIO_CTRL, &phy_reg);
5401 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5402 e1e_wphy_locked(hw,
5403 I217_LPI_GPIO_CTRL, phy_reg);
5404 }
5405 }
5406
5407 /* For i217 Intel Rapid Start Technology support,
5408 * when the system is going into Sx and no manageability engine
5409 * is present, the driver must configure proxy to reset only on
5410 * power good. LPI (Low Power Idle) state must also reset only
5411 * on power good, as well as the MTA (Multicast table array).
5412 * The SMBus release must also be disabled on LCD reset.
5413 */
5414 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5415 /* Enable proxy to reset only on power good. */
5416 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5417 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5418 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5419
5420 /* Set bit enable LPI (EEE) to reset only on
5421 * power good.
5422 */
5423 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5424 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5425 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5426
5427 /* Disable the SMB release on LCD reset. */
5428 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5429 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5430 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5431 }
5432
5433 /* Enable MTA to reset for Intel Rapid Start Technology
5434 * Support
5435 */
5436 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5437 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5438 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5439
5440 release:
5441 hw->phy.ops.release(hw);
5442 }
5443 out:
5444 ew32(PHY_CTRL, phy_ctrl);
5445
5446 if (hw->mac.type == e1000_ich8lan)
5447 e1000e_gig_downshift_workaround_ich8lan(hw);
5448
5449 if (hw->mac.type >= e1000_pchlan) {
5450 e1000_oem_bits_config_ich8lan(hw, false);
5451
5452 /* Reset PHY to activate OEM bits on 82577/8 */
5453 if (hw->mac.type == e1000_pchlan)
5454 e1000e_phy_hw_reset_generic(hw);
5455
5456 ret_val = hw->phy.ops.acquire(hw);
5457 if (ret_val)
5458 return;
5459 e1000_write_smbus_addr(hw);
5460 hw->phy.ops.release(hw);
5461 }
5462 }
5463
5464 /**
5465 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5466 * @hw: pointer to the HW structure
5467 *
5468 * During Sx to S0 transitions on non-managed devices or managed devices
5469 * on which PHY resets are not blocked, if the PHY registers cannot be
5470 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5471 * the PHY.
5472 * On i217, setup Intel Rapid Start Technology.
5473 **/
e1000_resume_workarounds_pchlan(struct e1000_hw * hw)5474 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5475 {
5476 s32 ret_val;
5477
5478 if (hw->mac.type < e1000_pch2lan)
5479 return;
5480
5481 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5482 if (ret_val) {
5483 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5484 return;
5485 }
5486
5487 /* For i217 Intel Rapid Start Technology support when the system
5488 * is transitioning from Sx and no manageability engine is present
5489 * configure SMBus to restore on reset, disable proxy, and enable
5490 * the reset on MTA (Multicast table array).
5491 */
5492 if (hw->phy.type == e1000_phy_i217) {
5493 u16 phy_reg;
5494
5495 ret_val = hw->phy.ops.acquire(hw);
5496 if (ret_val) {
5497 e_dbg("Failed to setup iRST\n");
5498 return;
5499 }
5500
5501 /* Clear Auto Enable LPI after link up */
5502 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5503 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5504 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5505
5506 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5507 /* Restore clear on SMB if no manageability engine
5508 * is present
5509 */
5510 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5511 if (ret_val)
5512 goto release;
5513 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5514 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5515
5516 /* Disable Proxy */
5517 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5518 }
5519 /* Enable reset on MTA */
5520 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5521 if (ret_val)
5522 goto release;
5523 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5524 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5525 release:
5526 if (ret_val)
5527 e_dbg("Error %d in resume workarounds\n", ret_val);
5528 hw->phy.ops.release(hw);
5529 }
5530 }
5531
5532 /**
5533 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5534 * @hw: pointer to the HW structure
5535 *
5536 * Return the LED back to the default configuration.
5537 **/
e1000_cleanup_led_ich8lan(struct e1000_hw * hw)5538 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5539 {
5540 if (hw->phy.type == e1000_phy_ife)
5541 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5542
5543 ew32(LEDCTL, hw->mac.ledctl_default);
5544 return 0;
5545 }
5546
5547 /**
5548 * e1000_led_on_ich8lan - Turn LEDs on
5549 * @hw: pointer to the HW structure
5550 *
5551 * Turn on the LEDs.
5552 **/
e1000_led_on_ich8lan(struct e1000_hw * hw)5553 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5554 {
5555 if (hw->phy.type == e1000_phy_ife)
5556 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5557 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5558
5559 ew32(LEDCTL, hw->mac.ledctl_mode2);
5560 return 0;
5561 }
5562
5563 /**
5564 * e1000_led_off_ich8lan - Turn LEDs off
5565 * @hw: pointer to the HW structure
5566 *
5567 * Turn off the LEDs.
5568 **/
e1000_led_off_ich8lan(struct e1000_hw * hw)5569 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5570 {
5571 if (hw->phy.type == e1000_phy_ife)
5572 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5573 (IFE_PSCL_PROBE_MODE |
5574 IFE_PSCL_PROBE_LEDS_OFF));
5575
5576 ew32(LEDCTL, hw->mac.ledctl_mode1);
5577 return 0;
5578 }
5579
5580 /**
5581 * e1000_setup_led_pchlan - Configures SW controllable LED
5582 * @hw: pointer to the HW structure
5583 *
5584 * This prepares the SW controllable LED for use.
5585 **/
e1000_setup_led_pchlan(struct e1000_hw * hw)5586 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5587 {
5588 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5589 }
5590
5591 /**
5592 * e1000_cleanup_led_pchlan - Restore the default LED operation
5593 * @hw: pointer to the HW structure
5594 *
5595 * Return the LED back to the default configuration.
5596 **/
e1000_cleanup_led_pchlan(struct e1000_hw * hw)5597 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5598 {
5599 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5600 }
5601
5602 /**
5603 * e1000_led_on_pchlan - Turn LEDs on
5604 * @hw: pointer to the HW structure
5605 *
5606 * Turn on the LEDs.
5607 **/
e1000_led_on_pchlan(struct e1000_hw * hw)5608 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5609 {
5610 u16 data = (u16)hw->mac.ledctl_mode2;
5611 u32 i, led;
5612
5613 /* If no link, then turn LED on by setting the invert bit
5614 * for each LED that's mode is "link_up" in ledctl_mode2.
5615 */
5616 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5617 for (i = 0; i < 3; i++) {
5618 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5619 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5620 E1000_LEDCTL_MODE_LINK_UP)
5621 continue;
5622 if (led & E1000_PHY_LED0_IVRT)
5623 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5624 else
5625 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5626 }
5627 }
5628
5629 return e1e_wphy(hw, HV_LED_CONFIG, data);
5630 }
5631
5632 /**
5633 * e1000_led_off_pchlan - Turn LEDs off
5634 * @hw: pointer to the HW structure
5635 *
5636 * Turn off the LEDs.
5637 **/
e1000_led_off_pchlan(struct e1000_hw * hw)5638 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5639 {
5640 u16 data = (u16)hw->mac.ledctl_mode1;
5641 u32 i, led;
5642
5643 /* If no link, then turn LED off by clearing the invert bit
5644 * for each LED that's mode is "link_up" in ledctl_mode1.
5645 */
5646 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5647 for (i = 0; i < 3; i++) {
5648 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5649 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5650 E1000_LEDCTL_MODE_LINK_UP)
5651 continue;
5652 if (led & E1000_PHY_LED0_IVRT)
5653 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5654 else
5655 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5656 }
5657 }
5658
5659 return e1e_wphy(hw, HV_LED_CONFIG, data);
5660 }
5661
5662 /**
5663 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5664 * @hw: pointer to the HW structure
5665 *
5666 * Read appropriate register for the config done bit for completion status
5667 * and configure the PHY through s/w for EEPROM-less parts.
5668 *
5669 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5670 * config done bit, so only an error is logged and continues. If we were
5671 * to return with error, EEPROM-less silicon would not be able to be reset
5672 * or change link.
5673 **/
e1000_get_cfg_done_ich8lan(struct e1000_hw * hw)5674 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5675 {
5676 s32 ret_val = 0;
5677 u32 bank = 0;
5678 u32 status;
5679
5680 e1000e_get_cfg_done_generic(hw);
5681
5682 /* Wait for indication from h/w that it has completed basic config */
5683 if (hw->mac.type >= e1000_ich10lan) {
5684 e1000_lan_init_done_ich8lan(hw);
5685 } else {
5686 ret_val = e1000e_get_auto_rd_done(hw);
5687 if (ret_val) {
5688 /* When auto config read does not complete, do not
5689 * return with an error. This can happen in situations
5690 * where there is no eeprom and prevents getting link.
5691 */
5692 e_dbg("Auto Read Done did not complete\n");
5693 ret_val = 0;
5694 }
5695 }
5696
5697 /* Clear PHY Reset Asserted bit */
5698 status = er32(STATUS);
5699 if (status & E1000_STATUS_PHYRA)
5700 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5701 else
5702 e_dbg("PHY Reset Asserted not set - needs delay\n");
5703
5704 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5705 if (hw->mac.type <= e1000_ich9lan) {
5706 if (!(er32(EECD) & E1000_EECD_PRES) &&
5707 (hw->phy.type == e1000_phy_igp_3)) {
5708 e1000e_phy_init_script_igp3(hw);
5709 }
5710 } else {
5711 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5712 /* Maybe we should do a basic PHY config */
5713 e_dbg("EEPROM not present\n");
5714 ret_val = -E1000_ERR_CONFIG;
5715 }
5716 }
5717
5718 return ret_val;
5719 }
5720
5721 /**
5722 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5723 * @hw: pointer to the HW structure
5724 *
5725 * In the case of a PHY power down to save power, or to turn off link during a
5726 * driver unload, or wake on lan is not enabled, remove the link.
5727 **/
e1000_power_down_phy_copper_ich8lan(struct e1000_hw * hw)5728 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5729 {
5730 /* If the management interface is not enabled, then power down */
5731 if (!(hw->mac.ops.check_mng_mode(hw) ||
5732 hw->phy.ops.check_reset_block(hw)))
5733 e1000_power_down_phy_copper(hw);
5734 }
5735
5736 /**
5737 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5738 * @hw: pointer to the HW structure
5739 *
5740 * Clears hardware counters specific to the silicon family and calls
5741 * clear_hw_cntrs_generic to clear all general purpose counters.
5742 **/
e1000_clear_hw_cntrs_ich8lan(struct e1000_hw * hw)5743 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5744 {
5745 u16 phy_data;
5746 s32 ret_val;
5747
5748 e1000e_clear_hw_cntrs_base(hw);
5749
5750 er32(ALGNERRC);
5751 er32(RXERRC);
5752 er32(TNCRS);
5753 er32(CEXTERR);
5754 er32(TSCTC);
5755 er32(TSCTFC);
5756
5757 er32(MGTPRC);
5758 er32(MGTPDC);
5759 er32(MGTPTC);
5760
5761 er32(IAC);
5762 er32(ICRXOC);
5763
5764 /* Clear PHY statistics registers */
5765 if ((hw->phy.type == e1000_phy_82578) ||
5766 (hw->phy.type == e1000_phy_82579) ||
5767 (hw->phy.type == e1000_phy_i217) ||
5768 (hw->phy.type == e1000_phy_82577)) {
5769 ret_val = hw->phy.ops.acquire(hw);
5770 if (ret_val)
5771 return;
5772 ret_val = hw->phy.ops.set_page(hw,
5773 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5774 if (ret_val)
5775 goto release;
5776 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5777 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5778 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5779 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5780 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5781 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5782 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5783 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5784 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5785 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5786 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5787 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5788 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5789 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5790 release:
5791 hw->phy.ops.release(hw);
5792 }
5793 }
5794
5795 static const struct e1000_mac_operations ich8_mac_ops = {
5796 /* check_mng_mode dependent on mac type */
5797 .check_for_link = e1000_check_for_copper_link_ich8lan,
5798 /* cleanup_led dependent on mac type */
5799 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
5800 .get_bus_info = e1000_get_bus_info_ich8lan,
5801 .set_lan_id = e1000_set_lan_id_single_port,
5802 .get_link_up_info = e1000_get_link_up_info_ich8lan,
5803 /* led_on dependent on mac type */
5804 /* led_off dependent on mac type */
5805 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
5806 .reset_hw = e1000_reset_hw_ich8lan,
5807 .init_hw = e1000_init_hw_ich8lan,
5808 .setup_link = e1000_setup_link_ich8lan,
5809 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5810 /* id_led_init dependent on mac type */
5811 .config_collision_dist = e1000e_config_collision_dist_generic,
5812 .rar_set = e1000e_rar_set_generic,
5813 .rar_get_count = e1000e_rar_get_count_generic,
5814 };
5815
5816 static const struct e1000_phy_operations ich8_phy_ops = {
5817 .acquire = e1000_acquire_swflag_ich8lan,
5818 .check_reset_block = e1000_check_reset_block_ich8lan,
5819 .commit = NULL,
5820 .get_cfg_done = e1000_get_cfg_done_ich8lan,
5821 .get_cable_length = e1000e_get_cable_length_igp_2,
5822 .read_reg = e1000e_read_phy_reg_igp,
5823 .release = e1000_release_swflag_ich8lan,
5824 .reset = e1000_phy_hw_reset_ich8lan,
5825 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
5826 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
5827 .write_reg = e1000e_write_phy_reg_igp,
5828 };
5829
5830 static const struct e1000_nvm_operations ich8_nvm_ops = {
5831 .acquire = e1000_acquire_nvm_ich8lan,
5832 .read = e1000_read_nvm_ich8lan,
5833 .release = e1000_release_nvm_ich8lan,
5834 .reload = e1000e_reload_nvm_generic,
5835 .update = e1000_update_nvm_checksum_ich8lan,
5836 .valid_led_default = e1000_valid_led_default_ich8lan,
5837 .validate = e1000_validate_nvm_checksum_ich8lan,
5838 .write = e1000_write_nvm_ich8lan,
5839 };
5840
5841 static const struct e1000_nvm_operations spt_nvm_ops = {
5842 .acquire = e1000_acquire_nvm_ich8lan,
5843 .release = e1000_release_nvm_ich8lan,
5844 .read = e1000_read_nvm_spt,
5845 .update = e1000_update_nvm_checksum_spt,
5846 .reload = e1000e_reload_nvm_generic,
5847 .valid_led_default = e1000_valid_led_default_ich8lan,
5848 .validate = e1000_validate_nvm_checksum_ich8lan,
5849 .write = e1000_write_nvm_ich8lan,
5850 };
5851
5852 const struct e1000_info e1000_ich8_info = {
5853 .mac = e1000_ich8lan,
5854 .flags = FLAG_HAS_WOL
5855 | FLAG_IS_ICH
5856 | FLAG_HAS_CTRLEXT_ON_LOAD
5857 | FLAG_HAS_AMT
5858 | FLAG_HAS_FLASH
5859 | FLAG_APME_IN_WUC,
5860 .pba = 8,
5861 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5862 .get_variants = e1000_get_variants_ich8lan,
5863 .mac_ops = &ich8_mac_ops,
5864 .phy_ops = &ich8_phy_ops,
5865 .nvm_ops = &ich8_nvm_ops,
5866 };
5867
5868 const struct e1000_info e1000_ich9_info = {
5869 .mac = e1000_ich9lan,
5870 .flags = FLAG_HAS_JUMBO_FRAMES
5871 | FLAG_IS_ICH
5872 | FLAG_HAS_WOL
5873 | FLAG_HAS_CTRLEXT_ON_LOAD
5874 | FLAG_HAS_AMT
5875 | FLAG_HAS_FLASH
5876 | FLAG_APME_IN_WUC,
5877 .pba = 18,
5878 .max_hw_frame_size = DEFAULT_JUMBO,
5879 .get_variants = e1000_get_variants_ich8lan,
5880 .mac_ops = &ich8_mac_ops,
5881 .phy_ops = &ich8_phy_ops,
5882 .nvm_ops = &ich8_nvm_ops,
5883 };
5884
5885 const struct e1000_info e1000_ich10_info = {
5886 .mac = e1000_ich10lan,
5887 .flags = FLAG_HAS_JUMBO_FRAMES
5888 | FLAG_IS_ICH
5889 | FLAG_HAS_WOL
5890 | FLAG_HAS_CTRLEXT_ON_LOAD
5891 | FLAG_HAS_AMT
5892 | FLAG_HAS_FLASH
5893 | FLAG_APME_IN_WUC,
5894 .pba = 18,
5895 .max_hw_frame_size = DEFAULT_JUMBO,
5896 .get_variants = e1000_get_variants_ich8lan,
5897 .mac_ops = &ich8_mac_ops,
5898 .phy_ops = &ich8_phy_ops,
5899 .nvm_ops = &ich8_nvm_ops,
5900 };
5901
5902 const struct e1000_info e1000_pch_info = {
5903 .mac = e1000_pchlan,
5904 .flags = FLAG_IS_ICH
5905 | FLAG_HAS_WOL
5906 | FLAG_HAS_CTRLEXT_ON_LOAD
5907 | FLAG_HAS_AMT
5908 | FLAG_HAS_FLASH
5909 | FLAG_HAS_JUMBO_FRAMES
5910 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5911 | FLAG_APME_IN_WUC,
5912 .flags2 = FLAG2_HAS_PHY_STATS,
5913 .pba = 26,
5914 .max_hw_frame_size = 4096,
5915 .get_variants = e1000_get_variants_ich8lan,
5916 .mac_ops = &ich8_mac_ops,
5917 .phy_ops = &ich8_phy_ops,
5918 .nvm_ops = &ich8_nvm_ops,
5919 };
5920
5921 const struct e1000_info e1000_pch2_info = {
5922 .mac = e1000_pch2lan,
5923 .flags = FLAG_IS_ICH
5924 | FLAG_HAS_WOL
5925 | FLAG_HAS_HW_TIMESTAMP
5926 | FLAG_HAS_CTRLEXT_ON_LOAD
5927 | FLAG_HAS_AMT
5928 | FLAG_HAS_FLASH
5929 | FLAG_HAS_JUMBO_FRAMES
5930 | FLAG_APME_IN_WUC,
5931 .flags2 = FLAG2_HAS_PHY_STATS
5932 | FLAG2_HAS_EEE
5933 | FLAG2_CHECK_SYSTIM_OVERFLOW,
5934 .pba = 26,
5935 .max_hw_frame_size = 9022,
5936 .get_variants = e1000_get_variants_ich8lan,
5937 .mac_ops = &ich8_mac_ops,
5938 .phy_ops = &ich8_phy_ops,
5939 .nvm_ops = &ich8_nvm_ops,
5940 };
5941
5942 const struct e1000_info e1000_pch_lpt_info = {
5943 .mac = e1000_pch_lpt,
5944 .flags = FLAG_IS_ICH
5945 | FLAG_HAS_WOL
5946 | FLAG_HAS_HW_TIMESTAMP
5947 | FLAG_HAS_CTRLEXT_ON_LOAD
5948 | FLAG_HAS_AMT
5949 | FLAG_HAS_FLASH
5950 | FLAG_HAS_JUMBO_FRAMES
5951 | FLAG_APME_IN_WUC,
5952 .flags2 = FLAG2_HAS_PHY_STATS
5953 | FLAG2_HAS_EEE
5954 | FLAG2_CHECK_SYSTIM_OVERFLOW,
5955 .pba = 26,
5956 .max_hw_frame_size = 9022,
5957 .get_variants = e1000_get_variants_ich8lan,
5958 .mac_ops = &ich8_mac_ops,
5959 .phy_ops = &ich8_phy_ops,
5960 .nvm_ops = &ich8_nvm_ops,
5961 };
5962
5963 const struct e1000_info e1000_pch_spt_info = {
5964 .mac = e1000_pch_spt,
5965 .flags = FLAG_IS_ICH
5966 | FLAG_HAS_WOL
5967 | FLAG_HAS_HW_TIMESTAMP
5968 | FLAG_HAS_CTRLEXT_ON_LOAD
5969 | FLAG_HAS_AMT
5970 | FLAG_HAS_FLASH
5971 | FLAG_HAS_JUMBO_FRAMES
5972 | FLAG_APME_IN_WUC,
5973 .flags2 = FLAG2_HAS_PHY_STATS
5974 | FLAG2_HAS_EEE,
5975 .pba = 26,
5976 .max_hw_frame_size = 9022,
5977 .get_variants = e1000_get_variants_ich8lan,
5978 .mac_ops = &ich8_mac_ops,
5979 .phy_ops = &ich8_phy_ops,
5980 .nvm_ops = &spt_nvm_ops,
5981 };
5982
5983 const struct e1000_info e1000_pch_cnp_info = {
5984 .mac = e1000_pch_cnp,
5985 .flags = FLAG_IS_ICH
5986 | FLAG_HAS_WOL
5987 | FLAG_HAS_HW_TIMESTAMP
5988 | FLAG_HAS_CTRLEXT_ON_LOAD
5989 | FLAG_HAS_AMT
5990 | FLAG_HAS_FLASH
5991 | FLAG_HAS_JUMBO_FRAMES
5992 | FLAG_APME_IN_WUC,
5993 .flags2 = FLAG2_HAS_PHY_STATS
5994 | FLAG2_HAS_EEE,
5995 .pba = 26,
5996 .max_hw_frame_size = 9022,
5997 .get_variants = e1000_get_variants_ich8lan,
5998 .mac_ops = &ich8_mac_ops,
5999 .phy_ops = &ich8_phy_ops,
6000 .nvm_ops = &spt_nvm_ops,
6001 };
6002
6003 const struct e1000_info e1000_pch_tgp_info = {
6004 .mac = e1000_pch_tgp,
6005 .flags = FLAG_IS_ICH
6006 | FLAG_HAS_WOL
6007 | FLAG_HAS_HW_TIMESTAMP
6008 | FLAG_HAS_CTRLEXT_ON_LOAD
6009 | FLAG_HAS_AMT
6010 | FLAG_HAS_FLASH
6011 | FLAG_HAS_JUMBO_FRAMES
6012 | FLAG_APME_IN_WUC,
6013 .flags2 = FLAG2_HAS_PHY_STATS
6014 | FLAG2_HAS_EEE,
6015 .pba = 26,
6016 .max_hw_frame_size = 9022,
6017 .get_variants = e1000_get_variants_ich8lan,
6018 .mac_ops = &ich8_mac_ops,
6019 .phy_ops = &ich8_phy_ops,
6020 .nvm_ops = &spt_nvm_ops,
6021 };
6022