1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2019, Mellanox Technologies */ 3 4 #ifndef MLX5_IFC_DR_H 5 #define MLX5_IFC_DR_H 6 7 enum { 8 MLX5DR_ACTION_MDFY_HW_FLD_L2_0 = 0, 9 MLX5DR_ACTION_MDFY_HW_FLD_L2_1 = 1, 10 MLX5DR_ACTION_MDFY_HW_FLD_L2_2 = 2, 11 MLX5DR_ACTION_MDFY_HW_FLD_L3_0 = 3, 12 MLX5DR_ACTION_MDFY_HW_FLD_L3_1 = 4, 13 MLX5DR_ACTION_MDFY_HW_FLD_L3_2 = 5, 14 MLX5DR_ACTION_MDFY_HW_FLD_L3_3 = 6, 15 MLX5DR_ACTION_MDFY_HW_FLD_L3_4 = 7, 16 MLX5DR_ACTION_MDFY_HW_FLD_L4_0 = 8, 17 MLX5DR_ACTION_MDFY_HW_FLD_L4_1 = 9, 18 MLX5DR_ACTION_MDFY_HW_FLD_MPLS = 10, 19 MLX5DR_ACTION_MDFY_HW_FLD_L2_TNL_0 = 11, 20 MLX5DR_ACTION_MDFY_HW_FLD_REG_0 = 12, 21 MLX5DR_ACTION_MDFY_HW_FLD_REG_1 = 13, 22 MLX5DR_ACTION_MDFY_HW_FLD_REG_2 = 14, 23 MLX5DR_ACTION_MDFY_HW_FLD_REG_3 = 15, 24 MLX5DR_ACTION_MDFY_HW_FLD_L4_2 = 16, 25 MLX5DR_ACTION_MDFY_HW_FLD_FLEX_0 = 17, 26 MLX5DR_ACTION_MDFY_HW_FLD_FLEX_1 = 18, 27 MLX5DR_ACTION_MDFY_HW_FLD_FLEX_2 = 19, 28 MLX5DR_ACTION_MDFY_HW_FLD_FLEX_3 = 20, 29 MLX5DR_ACTION_MDFY_HW_FLD_L2_TNL_1 = 21, 30 MLX5DR_ACTION_MDFY_HW_FLD_METADATA = 22, 31 MLX5DR_ACTION_MDFY_HW_FLD_RESERVED = 23, 32 }; 33 34 enum { 35 MLX5DR_ACTION_MDFY_HW_OP_COPY = 0x1, 36 MLX5DR_ACTION_MDFY_HW_OP_SET = 0x2, 37 MLX5DR_ACTION_MDFY_HW_OP_ADD = 0x3, 38 }; 39 40 enum { 41 MLX5DR_ACTION_MDFY_HW_HDR_L3_NONE = 0x0, 42 MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV4 = 0x1, 43 MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6 = 0x2, 44 }; 45 46 enum { 47 MLX5DR_ACTION_MDFY_HW_HDR_L4_NONE = 0x0, 48 MLX5DR_ACTION_MDFY_HW_HDR_L4_TCP = 0x1, 49 MLX5DR_ACTION_MDFY_HW_HDR_L4_UDP = 0x2, 50 }; 51 52 enum { 53 MLX5DR_STE_LU_TYPE_NOP = 0x00, 54 MLX5DR_STE_LU_TYPE_SRC_GVMI_AND_QP = 0x05, 55 MLX5DR_STE_LU_TYPE_ETHL2_TUNNELING_I = 0x0a, 56 MLX5DR_STE_LU_TYPE_ETHL2_DST_O = 0x06, 57 MLX5DR_STE_LU_TYPE_ETHL2_DST_I = 0x07, 58 MLX5DR_STE_LU_TYPE_ETHL2_DST_D = 0x1b, 59 MLX5DR_STE_LU_TYPE_ETHL2_SRC_O = 0x08, 60 MLX5DR_STE_LU_TYPE_ETHL2_SRC_I = 0x09, 61 MLX5DR_STE_LU_TYPE_ETHL2_SRC_D = 0x1c, 62 MLX5DR_STE_LU_TYPE_ETHL2_SRC_DST_O = 0x36, 63 MLX5DR_STE_LU_TYPE_ETHL2_SRC_DST_I = 0x37, 64 MLX5DR_STE_LU_TYPE_ETHL2_SRC_DST_D = 0x38, 65 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_DST_O = 0x0d, 66 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_DST_I = 0x0e, 67 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_DST_D = 0x1e, 68 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_SRC_O = 0x0f, 69 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_SRC_I = 0x10, 70 MLX5DR_STE_LU_TYPE_ETHL3_IPV6_SRC_D = 0x1f, 71 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_5_TUPLE_O = 0x11, 72 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_5_TUPLE_I = 0x12, 73 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_5_TUPLE_D = 0x20, 74 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_MISC_O = 0x29, 75 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_MISC_I = 0x2a, 76 MLX5DR_STE_LU_TYPE_ETHL3_IPV4_MISC_D = 0x2b, 77 MLX5DR_STE_LU_TYPE_ETHL4_O = 0x13, 78 MLX5DR_STE_LU_TYPE_ETHL4_I = 0x14, 79 MLX5DR_STE_LU_TYPE_ETHL4_D = 0x21, 80 MLX5DR_STE_LU_TYPE_ETHL4_MISC_O = 0x2c, 81 MLX5DR_STE_LU_TYPE_ETHL4_MISC_I = 0x2d, 82 MLX5DR_STE_LU_TYPE_ETHL4_MISC_D = 0x2e, 83 MLX5DR_STE_LU_TYPE_MPLS_FIRST_O = 0x15, 84 MLX5DR_STE_LU_TYPE_MPLS_FIRST_I = 0x24, 85 MLX5DR_STE_LU_TYPE_MPLS_FIRST_D = 0x25, 86 MLX5DR_STE_LU_TYPE_GRE = 0x16, 87 MLX5DR_STE_LU_TYPE_FLEX_PARSER_0 = 0x22, 88 MLX5DR_STE_LU_TYPE_FLEX_PARSER_1 = 0x23, 89 MLX5DR_STE_LU_TYPE_FLEX_PARSER_TNL_HEADER = 0x19, 90 MLX5DR_STE_LU_TYPE_GENERAL_PURPOSE = 0x18, 91 MLX5DR_STE_LU_TYPE_STEERING_REGISTERS_0 = 0x2f, 92 MLX5DR_STE_LU_TYPE_STEERING_REGISTERS_1 = 0x30, 93 MLX5DR_STE_LU_TYPE_DONT_CARE = 0x0f, 94 }; 95 96 enum mlx5dr_ste_entry_type { 97 MLX5DR_STE_TYPE_TX = 1, 98 MLX5DR_STE_TYPE_RX = 2, 99 MLX5DR_STE_TYPE_MODIFY_PKT = 6, 100 }; 101 102 struct mlx5_ifc_ste_general_bits { 103 u8 entry_type[0x4]; 104 u8 reserved_at_4[0x4]; 105 u8 entry_sub_type[0x8]; 106 u8 byte_mask[0x10]; 107 108 u8 next_table_base_63_48[0x10]; 109 u8 next_lu_type[0x8]; 110 u8 next_table_base_39_32_size[0x8]; 111 112 u8 next_table_base_31_5_size[0x1b]; 113 u8 linear_hash_enable[0x1]; 114 u8 reserved_at_5c[0x2]; 115 u8 next_table_rank[0x2]; 116 117 u8 reserved_at_60[0xa0]; 118 u8 tag_value[0x60]; 119 u8 bit_mask[0x60]; 120 }; 121 122 struct mlx5_ifc_ste_sx_transmit_bits { 123 u8 entry_type[0x4]; 124 u8 reserved_at_4[0x4]; 125 u8 entry_sub_type[0x8]; 126 u8 byte_mask[0x10]; 127 128 u8 next_table_base_63_48[0x10]; 129 u8 next_lu_type[0x8]; 130 u8 next_table_base_39_32_size[0x8]; 131 132 u8 next_table_base_31_5_size[0x1b]; 133 u8 linear_hash_enable[0x1]; 134 u8 reserved_at_5c[0x2]; 135 u8 next_table_rank[0x2]; 136 137 u8 sx_wire[0x1]; 138 u8 sx_func_lb[0x1]; 139 u8 sx_sniffer[0x1]; 140 u8 sx_wire_enable[0x1]; 141 u8 sx_func_lb_enable[0x1]; 142 u8 sx_sniffer_enable[0x1]; 143 u8 action_type[0x3]; 144 u8 reserved_at_69[0x1]; 145 u8 action_description[0x6]; 146 u8 gvmi[0x10]; 147 148 u8 encap_pointer_vlan_data[0x20]; 149 150 u8 loopback_syndome_en[0x8]; 151 u8 loopback_syndome[0x8]; 152 u8 counter_trigger[0x10]; 153 154 u8 miss_address_63_48[0x10]; 155 u8 counter_trigger_23_16[0x8]; 156 u8 miss_address_39_32[0x8]; 157 158 u8 miss_address_31_6[0x1a]; 159 u8 learning_point[0x1]; 160 u8 go_back[0x1]; 161 u8 match_polarity[0x1]; 162 u8 mask_mode[0x1]; 163 u8 miss_rank[0x2]; 164 }; 165 166 struct mlx5_ifc_ste_rx_steering_mult_bits { 167 u8 entry_type[0x4]; 168 u8 reserved_at_4[0x4]; 169 u8 entry_sub_type[0x8]; 170 u8 byte_mask[0x10]; 171 172 u8 next_table_base_63_48[0x10]; 173 u8 next_lu_type[0x8]; 174 u8 next_table_base_39_32_size[0x8]; 175 176 u8 next_table_base_31_5_size[0x1b]; 177 u8 linear_hash_enable[0x1]; 178 u8 reserved_at_[0x2]; 179 u8 next_table_rank[0x2]; 180 181 u8 member_count[0x10]; 182 u8 gvmi[0x10]; 183 184 u8 qp_list_pointer[0x20]; 185 186 u8 reserved_at_a0[0x1]; 187 u8 tunneling_action[0x3]; 188 u8 action_description[0x4]; 189 u8 reserved_at_a8[0x8]; 190 u8 counter_trigger_15_0[0x10]; 191 192 u8 miss_address_63_48[0x10]; 193 u8 counter_trigger_23_16[0x08]; 194 u8 miss_address_39_32[0x8]; 195 196 u8 miss_address_31_6[0x1a]; 197 u8 learning_point[0x1]; 198 u8 fail_on_error[0x1]; 199 u8 match_polarity[0x1]; 200 u8 mask_mode[0x1]; 201 u8 miss_rank[0x2]; 202 }; 203 204 struct mlx5_ifc_ste_modify_packet_bits { 205 u8 entry_type[0x4]; 206 u8 reserved_at_4[0x4]; 207 u8 entry_sub_type[0x8]; 208 u8 byte_mask[0x10]; 209 210 u8 next_table_base_63_48[0x10]; 211 u8 next_lu_type[0x8]; 212 u8 next_table_base_39_32_size[0x8]; 213 214 u8 next_table_base_31_5_size[0x1b]; 215 u8 linear_hash_enable[0x1]; 216 u8 reserved_at_[0x2]; 217 u8 next_table_rank[0x2]; 218 219 u8 number_of_re_write_actions[0x10]; 220 u8 gvmi[0x10]; 221 222 u8 header_re_write_actions_pointer[0x20]; 223 224 u8 reserved_at_a0[0x1]; 225 u8 tunneling_action[0x3]; 226 u8 action_description[0x4]; 227 u8 reserved_at_a8[0x8]; 228 u8 counter_trigger_15_0[0x10]; 229 230 u8 miss_address_63_48[0x10]; 231 u8 counter_trigger_23_16[0x08]; 232 u8 miss_address_39_32[0x8]; 233 234 u8 miss_address_31_6[0x1a]; 235 u8 learning_point[0x1]; 236 u8 fail_on_error[0x1]; 237 u8 match_polarity[0x1]; 238 u8 mask_mode[0x1]; 239 u8 miss_rank[0x2]; 240 }; 241 242 struct mlx5_ifc_ste_eth_l2_src_bits { 243 u8 smac_47_16[0x20]; 244 245 u8 smac_15_0[0x10]; 246 u8 l3_ethertype[0x10]; 247 248 u8 qp_type[0x2]; 249 u8 ethertype_filter[0x1]; 250 u8 reserved_at_43[0x1]; 251 u8 sx_sniffer[0x1]; 252 u8 force_lb[0x1]; 253 u8 functional_lb[0x1]; 254 u8 port[0x1]; 255 u8 reserved_at_48[0x4]; 256 u8 first_priority[0x3]; 257 u8 first_cfi[0x1]; 258 u8 first_vlan_qualifier[0x2]; 259 u8 reserved_at_52[0x2]; 260 u8 first_vlan_id[0xc]; 261 262 u8 ip_fragmented[0x1]; 263 u8 tcp_syn[0x1]; 264 u8 encp_type[0x2]; 265 u8 l3_type[0x2]; 266 u8 l4_type[0x2]; 267 u8 reserved_at_68[0x4]; 268 u8 second_priority[0x3]; 269 u8 second_cfi[0x1]; 270 u8 second_vlan_qualifier[0x2]; 271 u8 reserved_at_72[0x2]; 272 u8 second_vlan_id[0xc]; 273 }; 274 275 struct mlx5_ifc_ste_eth_l2_dst_bits { 276 u8 dmac_47_16[0x20]; 277 278 u8 dmac_15_0[0x10]; 279 u8 l3_ethertype[0x10]; 280 281 u8 qp_type[0x2]; 282 u8 ethertype_filter[0x1]; 283 u8 reserved_at_43[0x1]; 284 u8 sx_sniffer[0x1]; 285 u8 force_lb[0x1]; 286 u8 functional_lb[0x1]; 287 u8 port[0x1]; 288 u8 reserved_at_48[0x4]; 289 u8 first_priority[0x3]; 290 u8 first_cfi[0x1]; 291 u8 first_vlan_qualifier[0x2]; 292 u8 reserved_at_52[0x2]; 293 u8 first_vlan_id[0xc]; 294 295 u8 ip_fragmented[0x1]; 296 u8 tcp_syn[0x1]; 297 u8 encp_type[0x2]; 298 u8 l3_type[0x2]; 299 u8 l4_type[0x2]; 300 u8 reserved_at_68[0x4]; 301 u8 second_priority[0x3]; 302 u8 second_cfi[0x1]; 303 u8 second_vlan_qualifier[0x2]; 304 u8 reserved_at_72[0x2]; 305 u8 second_vlan_id[0xc]; 306 }; 307 308 struct mlx5_ifc_ste_eth_l2_src_dst_bits { 309 u8 dmac_47_16[0x20]; 310 311 u8 dmac_15_0[0x10]; 312 u8 smac_47_32[0x10]; 313 314 u8 smac_31_0[0x20]; 315 316 u8 sx_sniffer[0x1]; 317 u8 force_lb[0x1]; 318 u8 functional_lb[0x1]; 319 u8 port[0x1]; 320 u8 l3_type[0x2]; 321 u8 reserved_at_66[0x6]; 322 u8 first_priority[0x3]; 323 u8 first_cfi[0x1]; 324 u8 first_vlan_qualifier[0x2]; 325 u8 reserved_at_72[0x2]; 326 u8 first_vlan_id[0xc]; 327 }; 328 329 struct mlx5_ifc_ste_eth_l3_ipv4_5_tuple_bits { 330 u8 destination_address[0x20]; 331 332 u8 source_address[0x20]; 333 334 u8 source_port[0x10]; 335 u8 destination_port[0x10]; 336 337 u8 fragmented[0x1]; 338 u8 first_fragment[0x1]; 339 u8 reserved_at_62[0x2]; 340 u8 reserved_at_64[0x1]; 341 u8 ecn[0x2]; 342 u8 tcp_ns[0x1]; 343 u8 tcp_cwr[0x1]; 344 u8 tcp_ece[0x1]; 345 u8 tcp_urg[0x1]; 346 u8 tcp_ack[0x1]; 347 u8 tcp_psh[0x1]; 348 u8 tcp_rst[0x1]; 349 u8 tcp_syn[0x1]; 350 u8 tcp_fin[0x1]; 351 u8 dscp[0x6]; 352 u8 reserved_at_76[0x2]; 353 u8 protocol[0x8]; 354 }; 355 356 struct mlx5_ifc_ste_eth_l3_ipv6_dst_bits { 357 u8 dst_ip_127_96[0x20]; 358 359 u8 dst_ip_95_64[0x20]; 360 361 u8 dst_ip_63_32[0x20]; 362 363 u8 dst_ip_31_0[0x20]; 364 }; 365 366 struct mlx5_ifc_ste_eth_l2_tnl_bits { 367 u8 dmac_47_16[0x20]; 368 369 u8 dmac_15_0[0x10]; 370 u8 l3_ethertype[0x10]; 371 372 u8 l2_tunneling_network_id[0x20]; 373 374 u8 ip_fragmented[0x1]; 375 u8 tcp_syn[0x1]; 376 u8 encp_type[0x2]; 377 u8 l3_type[0x2]; 378 u8 l4_type[0x2]; 379 u8 first_priority[0x3]; 380 u8 first_cfi[0x1]; 381 u8 reserved_at_6c[0x3]; 382 u8 gre_key_flag[0x1]; 383 u8 first_vlan_qualifier[0x2]; 384 u8 reserved_at_72[0x2]; 385 u8 first_vlan_id[0xc]; 386 }; 387 388 struct mlx5_ifc_ste_eth_l3_ipv6_src_bits { 389 u8 src_ip_127_96[0x20]; 390 391 u8 src_ip_95_64[0x20]; 392 393 u8 src_ip_63_32[0x20]; 394 395 u8 src_ip_31_0[0x20]; 396 }; 397 398 struct mlx5_ifc_ste_eth_l3_ipv4_misc_bits { 399 u8 version[0x4]; 400 u8 ihl[0x4]; 401 u8 reserved_at_8[0x8]; 402 u8 total_length[0x10]; 403 404 u8 identification[0x10]; 405 u8 flags[0x3]; 406 u8 fragment_offset[0xd]; 407 408 u8 time_to_live[0x8]; 409 u8 reserved_at_48[0x8]; 410 u8 checksum[0x10]; 411 412 u8 reserved_at_60[0x20]; 413 }; 414 415 struct mlx5_ifc_ste_eth_l4_bits { 416 u8 fragmented[0x1]; 417 u8 first_fragment[0x1]; 418 u8 reserved_at_2[0x6]; 419 u8 protocol[0x8]; 420 u8 dst_port[0x10]; 421 422 u8 ipv6_version[0x4]; 423 u8 reserved_at_24[0x1]; 424 u8 ecn[0x2]; 425 u8 tcp_ns[0x1]; 426 u8 tcp_cwr[0x1]; 427 u8 tcp_ece[0x1]; 428 u8 tcp_urg[0x1]; 429 u8 tcp_ack[0x1]; 430 u8 tcp_psh[0x1]; 431 u8 tcp_rst[0x1]; 432 u8 tcp_syn[0x1]; 433 u8 tcp_fin[0x1]; 434 u8 src_port[0x10]; 435 436 u8 ipv6_payload_length[0x10]; 437 u8 ipv6_hop_limit[0x8]; 438 u8 dscp[0x6]; 439 u8 reserved_at_5e[0x2]; 440 441 u8 tcp_data_offset[0x4]; 442 u8 reserved_at_64[0x8]; 443 u8 flow_label[0x14]; 444 }; 445 446 struct mlx5_ifc_ste_eth_l4_misc_bits { 447 u8 checksum[0x10]; 448 u8 length[0x10]; 449 450 u8 seq_num[0x20]; 451 452 u8 ack_num[0x20]; 453 454 u8 urgent_pointer[0x10]; 455 u8 window_size[0x10]; 456 }; 457 458 struct mlx5_ifc_ste_mpls_bits { 459 u8 mpls0_label[0x14]; 460 u8 mpls0_exp[0x3]; 461 u8 mpls0_s_bos[0x1]; 462 u8 mpls0_ttl[0x8]; 463 464 u8 mpls1_label[0x20]; 465 466 u8 mpls2_label[0x20]; 467 468 u8 reserved_at_60[0x16]; 469 u8 mpls4_s_bit[0x1]; 470 u8 mpls4_qualifier[0x1]; 471 u8 mpls3_s_bit[0x1]; 472 u8 mpls3_qualifier[0x1]; 473 u8 mpls2_s_bit[0x1]; 474 u8 mpls2_qualifier[0x1]; 475 u8 mpls1_s_bit[0x1]; 476 u8 mpls1_qualifier[0x1]; 477 u8 mpls0_s_bit[0x1]; 478 u8 mpls0_qualifier[0x1]; 479 }; 480 481 struct mlx5_ifc_ste_register_0_bits { 482 u8 register_0_h[0x20]; 483 484 u8 register_0_l[0x20]; 485 486 u8 register_1_h[0x20]; 487 488 u8 register_1_l[0x20]; 489 }; 490 491 struct mlx5_ifc_ste_register_1_bits { 492 u8 register_2_h[0x20]; 493 494 u8 register_2_l[0x20]; 495 496 u8 register_3_h[0x20]; 497 498 u8 register_3_l[0x20]; 499 }; 500 501 struct mlx5_ifc_ste_gre_bits { 502 u8 gre_c_present[0x1]; 503 u8 reserved_at_30[0x1]; 504 u8 gre_k_present[0x1]; 505 u8 gre_s_present[0x1]; 506 u8 strict_src_route[0x1]; 507 u8 recur[0x3]; 508 u8 flags[0x5]; 509 u8 version[0x3]; 510 u8 gre_protocol[0x10]; 511 512 u8 checksum[0x10]; 513 u8 offset[0x10]; 514 515 u8 gre_key_h[0x18]; 516 u8 gre_key_l[0x8]; 517 518 u8 seq_num[0x20]; 519 }; 520 521 struct mlx5_ifc_ste_flex_parser_0_bits { 522 u8 parser_3_label[0x14]; 523 u8 parser_3_exp[0x3]; 524 u8 parser_3_s_bos[0x1]; 525 u8 parser_3_ttl[0x8]; 526 527 u8 flex_parser_2[0x20]; 528 529 u8 flex_parser_1[0x20]; 530 531 u8 flex_parser_0[0x20]; 532 }; 533 534 struct mlx5_ifc_ste_flex_parser_1_bits { 535 u8 flex_parser_7[0x20]; 536 537 u8 flex_parser_6[0x20]; 538 539 u8 flex_parser_5[0x20]; 540 541 u8 flex_parser_4[0x20]; 542 }; 543 544 struct mlx5_ifc_ste_flex_parser_tnl_bits { 545 u8 flex_parser_tunneling_header_63_32[0x20]; 546 547 u8 flex_parser_tunneling_header_31_0[0x20]; 548 549 u8 reserved_at_40[0x40]; 550 }; 551 552 struct mlx5_ifc_ste_flex_parser_tnl_vxlan_gpe_bits { 553 u8 outer_vxlan_gpe_flags[0x8]; 554 u8 reserved_at_8[0x10]; 555 u8 outer_vxlan_gpe_next_protocol[0x8]; 556 557 u8 outer_vxlan_gpe_vni[0x18]; 558 u8 reserved_at_38[0x8]; 559 560 u8 reserved_at_40[0x40]; 561 }; 562 563 struct mlx5_ifc_ste_flex_parser_tnl_geneve_bits { 564 u8 reserved_at_0[0x2]; 565 u8 geneve_opt_len[0x6]; 566 u8 geneve_oam[0x1]; 567 u8 reserved_at_9[0x7]; 568 u8 geneve_protocol_type[0x10]; 569 570 u8 geneve_vni[0x18]; 571 u8 reserved_at_38[0x8]; 572 573 u8 reserved_at_40[0x40]; 574 }; 575 576 struct mlx5_ifc_ste_general_purpose_bits { 577 u8 general_purpose_lookup_field[0x20]; 578 579 u8 reserved_at_20[0x20]; 580 581 u8 reserved_at_40[0x20]; 582 583 u8 reserved_at_60[0x20]; 584 }; 585 586 struct mlx5_ifc_ste_src_gvmi_qp_bits { 587 u8 loopback_syndrome[0x8]; 588 u8 reserved_at_8[0x8]; 589 u8 source_gvmi[0x10]; 590 591 u8 reserved_at_20[0x5]; 592 u8 force_lb[0x1]; 593 u8 functional_lb[0x1]; 594 u8 source_is_requestor[0x1]; 595 u8 source_qp[0x18]; 596 597 u8 reserved_at_40[0x20]; 598 599 u8 reserved_at_60[0x20]; 600 }; 601 602 struct mlx5_ifc_l2_hdr_bits { 603 u8 dmac_47_16[0x20]; 604 605 u8 dmac_15_0[0x10]; 606 u8 smac_47_32[0x10]; 607 608 u8 smac_31_0[0x20]; 609 610 u8 ethertype[0x10]; 611 u8 vlan_type[0x10]; 612 613 u8 vlan[0x10]; 614 u8 reserved_at_90[0x10]; 615 }; 616 617 /* Both HW set and HW add share the same HW format with different opcodes */ 618 struct mlx5_ifc_dr_action_hw_set_bits { 619 u8 opcode[0x8]; 620 u8 destination_field_code[0x8]; 621 u8 reserved_at_10[0x2]; 622 u8 destination_left_shifter[0x6]; 623 u8 reserved_at_18[0x3]; 624 u8 destination_length[0x5]; 625 626 u8 inline_data[0x20]; 627 }; 628 629 struct mlx5_ifc_dr_action_hw_copy_bits { 630 u8 opcode[0x8]; 631 u8 destination_field_code[0x8]; 632 u8 reserved_at_10[0x2]; 633 u8 destination_left_shifter[0x6]; 634 u8 reserved_at_18[0x2]; 635 u8 destination_length[0x6]; 636 637 u8 reserved_at_20[0x8]; 638 u8 source_field_code[0x8]; 639 u8 reserved_at_30[0x2]; 640 u8 source_left_shifter[0x6]; 641 u8 reserved_at_38[0x8]; 642 }; 643 644 #endif /* MLX5_IFC_DR_H */ 645