1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /*
3 * core.h - DesignWare HS OTG Controller common declarations
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #ifndef __DWC2_CORE_H__
39 #define __DWC2_CORE_H__
40
41 #include <linux/phy/phy.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/usb/gadget.h>
44 #include <linux/usb/otg.h>
45 #include <linux/usb/phy.h>
46 #include "hw.h"
47
48 /*
49 * Suggested defines for tracers:
50 * - no_printk: Disable tracing
51 * - pr_info: Print this info to the console
52 * - trace_printk: Print this info to trace buffer (good for verbose logging)
53 */
54
55 #define DWC2_TRACE_SCHEDULER no_printk
56 #define DWC2_TRACE_SCHEDULER_VB no_printk
57
58 /* Detailed scheduler tracing, but won't overwhelm console */
59 #define dwc2_sch_dbg(hsotg, fmt, ...) \
60 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
61 dev_name(hsotg->dev), ##__VA_ARGS__)
62
63 /* Verbose scheduler tracing */
64 #define dwc2_sch_vdbg(hsotg, fmt, ...) \
65 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
66 dev_name(hsotg->dev), ##__VA_ARGS__)
67
68 /* Maximum number of Endpoints/HostChannels */
69 #define MAX_EPS_CHANNELS 16
70
71 /* dwc2-hsotg declarations */
72 static const char * const dwc2_hsotg_supply_names[] = {
73 "vusb_d", /* digital USB supply, 1.2V */
74 "vusb_a", /* analog USB supply, 1.1V */
75 };
76
77 #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names)
78
79 /*
80 * EP0_MPS_LIMIT
81 *
82 * Unfortunately there seems to be a limit of the amount of data that can
83 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
84 * packets (which practically means 1 packet and 63 bytes of data) when the
85 * MPS is set to 64.
86 *
87 * This means if we are wanting to move >127 bytes of data, we need to
88 * split the transactions up, but just doing one packet at a time does
89 * not work (this may be an implicit DATA0 PID on first packet of the
90 * transaction) and doing 2 packets is outside the controller's limits.
91 *
92 * If we try to lower the MPS size for EP0, then no transfers work properly
93 * for EP0, and the system will fail basic enumeration. As no cause for this
94 * has currently been found, we cannot support any large IN transfers for
95 * EP0.
96 */
97 #define EP0_MPS_LIMIT 64
98
99 struct dwc2_hsotg;
100 struct dwc2_hsotg_req;
101
102 /**
103 * struct dwc2_hsotg_ep - driver endpoint definition.
104 * @ep: The gadget layer representation of the endpoint.
105 * @name: The driver generated name for the endpoint.
106 * @queue: Queue of requests for this endpoint.
107 * @parent: Reference back to the parent device structure.
108 * @req: The current request that the endpoint is processing. This is
109 * used to indicate an request has been loaded onto the endpoint
110 * and has yet to be completed (maybe due to data move, or simply
111 * awaiting an ack from the core all the data has been completed).
112 * @debugfs: File entry for debugfs file for this endpoint.
113 * @dir_in: Set to true if this endpoint is of the IN direction, which
114 * means that it is sending data to the Host.
115 * @map_dir: Set to the value of dir_in when the DMA buffer is mapped.
116 * @index: The index for the endpoint registers.
117 * @mc: Multi Count - number of transactions per microframe
118 * @interval: Interval for periodic endpoints, in frames or microframes.
119 * @name: The name array passed to the USB core.
120 * @halted: Set if the endpoint has been halted.
121 * @periodic: Set if this is a periodic ep, such as Interrupt
122 * @isochronous: Set if this is a isochronous ep
123 * @send_zlp: Set if we need to send a zero-length packet.
124 * @desc_list_dma: The DMA address of descriptor chain currently in use.
125 * @desc_list: Pointer to descriptor DMA chain head currently in use.
126 * @desc_count: Count of entries within the DMA descriptor chain of EP.
127 * @next_desc: index of next free descriptor in the ISOC chain under SW control.
128 * @compl_desc: index of next descriptor to be completed by xFerComplete
129 * @total_data: The total number of data bytes done.
130 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
131 * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0.
132 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
133 * @last_load: The offset of data for the last start of request.
134 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
135 * @target_frame: Targeted frame num to setup next ISOC transfer
136 * @frame_overrun: Indicates SOF number overrun in DSTS
137 *
138 * This is the driver's state for each registered endpoint, allowing it
139 * to keep track of transactions that need doing. Each endpoint has a
140 * lock to protect the state, to try and avoid using an overall lock
141 * for the host controller as much as possible.
142 *
143 * For periodic IN endpoints, we have fifo_size and fifo_load to try
144 * and keep track of the amount of data in the periodic FIFO for each
145 * of these as we don't have a status register that tells us how much
146 * is in each of them. (note, this may actually be useless information
147 * as in shared-fifo mode periodic in acts like a single-frame packet
148 * buffer than a fifo)
149 */
150 struct dwc2_hsotg_ep {
151 struct usb_ep ep;
152 struct list_head queue;
153 struct dwc2_hsotg *parent;
154 struct dwc2_hsotg_req *req;
155 struct dentry *debugfs;
156
157 unsigned long total_data;
158 unsigned int size_loaded;
159 unsigned int last_load;
160 unsigned int fifo_load;
161 unsigned short fifo_size;
162 unsigned short fifo_index;
163
164 unsigned char dir_in;
165 unsigned char map_dir;
166 unsigned char index;
167 unsigned char mc;
168 u16 interval;
169
170 unsigned int halted:1;
171 unsigned int periodic:1;
172 unsigned int isochronous:1;
173 unsigned int send_zlp:1;
174 unsigned int target_frame;
175 #define TARGET_FRAME_INITIAL 0xFFFFFFFF
176 bool frame_overrun;
177
178 dma_addr_t desc_list_dma;
179 struct dwc2_dma_desc *desc_list;
180 u8 desc_count;
181
182 unsigned int next_desc;
183 unsigned int compl_desc;
184
185 char name[10];
186 };
187
188 /**
189 * struct dwc2_hsotg_req - data transfer request
190 * @req: The USB gadget request
191 * @queue: The list of requests for the endpoint this is queued for.
192 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
193 */
194 struct dwc2_hsotg_req {
195 struct usb_request req;
196 struct list_head queue;
197 void *saved_req_buf;
198 };
199
200 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
201 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
202 #define call_gadget(_hs, _entry) \
203 do { \
204 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
205 (_hs)->driver && (_hs)->driver->_entry) { \
206 spin_unlock(&_hs->lock); \
207 (_hs)->driver->_entry(&(_hs)->gadget); \
208 spin_lock(&_hs->lock); \
209 } \
210 } while (0)
211 #else
212 #define call_gadget(_hs, _entry) do {} while (0)
213 #endif
214
215 struct dwc2_hsotg;
216 struct dwc2_host_chan;
217
218 /* Device States */
219 enum dwc2_lx_state {
220 DWC2_L0, /* On state */
221 DWC2_L1, /* LPM sleep state */
222 DWC2_L2, /* USB suspend state */
223 DWC2_L3, /* Off state */
224 };
225
226 /* Gadget ep0 states */
227 enum dwc2_ep0_state {
228 DWC2_EP0_SETUP,
229 DWC2_EP0_DATA_IN,
230 DWC2_EP0_DATA_OUT,
231 DWC2_EP0_STATUS_IN,
232 DWC2_EP0_STATUS_OUT,
233 };
234
235 /**
236 * struct dwc2_core_params - Parameters for configuring the core
237 *
238 * @otg_cap: Specifies the OTG capabilities.
239 * 0 - HNP and SRP capable
240 * 1 - SRP Only capable
241 * 2 - No HNP/SRP capable (always available)
242 * Defaults to best available option (0, 1, then 2)
243 * @host_dma: Specifies whether to use slave or DMA mode for accessing
244 * the data FIFOs. The driver will automatically detect the
245 * value for this parameter if none is specified.
246 * 0 - Slave (always available)
247 * 1 - DMA (default, if available)
248 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
249 * address DMA mode or descriptor DMA mode for accessing
250 * the data FIFOs. The driver will automatically detect the
251 * value for this if none is specified.
252 * 0 - Address DMA
253 * 1 - Descriptor DMA (default, if available)
254 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
255 * address DMA mode or descriptor DMA mode for accessing
256 * the data FIFOs in Full Speed mode only. The driver
257 * will automatically detect the value for this if none is
258 * specified.
259 * 0 - Address DMA
260 * 1 - Descriptor DMA in FS (default, if available)
261 * @speed: Specifies the maximum speed of operation in host and
262 * device mode. The actual speed depends on the speed of
263 * the attached device and the value of phy_type.
264 * 0 - High Speed
265 * (default when phy_type is UTMI+ or ULPI)
266 * 1 - Full Speed
267 * (default when phy_type is Full Speed)
268 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
269 * 1 - Allow dynamic FIFO sizing (default, if available)
270 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
271 * are enabled for non-periodic IN endpoints in device
272 * mode.
273 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
274 * dynamic FIFO sizing is enabled
275 * 16 to 32768
276 * Actual maximum value is autodetected and also
277 * the default.
278 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
279 * in host mode when dynamic FIFO sizing is enabled
280 * 16 to 32768
281 * Actual maximum value is autodetected and also
282 * the default.
283 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
284 * host mode when dynamic FIFO sizing is enabled
285 * 16 to 32768
286 * Actual maximum value is autodetected and also
287 * the default.
288 * @max_transfer_size: The maximum transfer size supported, in bytes
289 * 2047 to 65,535
290 * Actual maximum value is autodetected and also
291 * the default.
292 * @max_packet_count: The maximum number of packets in a transfer
293 * 15 to 511
294 * Actual maximum value is autodetected and also
295 * the default.
296 * @host_channels: The number of host channel registers to use
297 * 1 to 16
298 * Actual maximum value is autodetected and also
299 * the default.
300 * @phy_type: Specifies the type of PHY interface to use. By default,
301 * the driver will automatically detect the phy_type.
302 * 0 - Full Speed Phy
303 * 1 - UTMI+ Phy
304 * 2 - ULPI Phy
305 * Defaults to best available option (2, 1, then 0)
306 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
307 * is applicable for a phy_type of UTMI+ or ULPI. (For a
308 * ULPI phy_type, this parameter indicates the data width
309 * between the MAC and the ULPI Wrapper.) Also, this
310 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
311 * parameter was set to "8 and 16 bits", meaning that the
312 * core has been configured to work at either data path
313 * width.
314 * 8 or 16 (default 16 if available)
315 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
316 * data rate. This parameter is only applicable if phy_type
317 * is ULPI.
318 * 0 - single data rate ULPI interface with 8 bit wide
319 * data bus (default)
320 * 1 - double data rate ULPI interface with 4 bit wide
321 * data bus
322 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
323 * external supply to drive the VBus
324 * 0 - Internal supply (default)
325 * 1 - External supply
326 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
327 * speed PHY. This parameter is only applicable if phy_type
328 * is FS.
329 * 0 - No (default)
330 * 1 - Yes
331 * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled.
332 * 0 - Disable (default)
333 * 1 - Enable
334 * @acg_enable: For enabling Active Clock Gating in the controller
335 * 0 - No
336 * 1 - Yes
337 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
338 * 0 - No (default)
339 * 1 - Yes
340 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
341 * when attached to a Full Speed or Low Speed device in
342 * host mode.
343 * 0 - Don't support low power mode (default)
344 * 1 - Support low power mode
345 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
346 * when connected to a Low Speed device in host
347 * mode. This parameter is applicable only if
348 * host_support_fs_ls_low_power is enabled.
349 * 0 - 48 MHz
350 * (default when phy_type is UTMI+ or ULPI)
351 * 1 - 6 MHz
352 * (default when phy_type is Full Speed)
353 * @oc_disable: Flag to disable overcurrent condition.
354 * 0 - Allow overcurrent condition to get detected
355 * 1 - Disable overcurrent condtion to get detected
356 * @ts_dline: Enable Term Select Dline pulsing
357 * 0 - No (default)
358 * 1 - Yes
359 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
360 * 0 - No (default for core < 2.92a)
361 * 1 - Yes (default for core >= 2.92a)
362 * @ahbcfg: This field allows the default value of the GAHBCFG
363 * register to be overridden
364 * -1 - GAHBCFG value will be set to 0x06
365 * (INCR, default)
366 * all others - GAHBCFG value will be overridden with
367 * this value
368 * Not all bits can be controlled like this, the
369 * bits defined by GAHBCFG_CTRL_MASK are controlled
370 * by the driver and are ignored in this
371 * configuration value.
372 * @uframe_sched: True to enable the microframe scheduler
373 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
374 * Disable CONIDSTSCHNG controller interrupt in such
375 * case.
376 * 0 - No (default)
377 * 1 - Yes
378 * @power_down: Specifies whether the controller support power_down.
379 * If power_down is enabled, the controller will enter
380 * power_down in both peripheral and host mode when
381 * needed.
382 * 0 - No (default)
383 * 1 - Partial power down
384 * 2 - Hibernation
385 * @lpm: Enable LPM support.
386 * 0 - No
387 * 1 - Yes
388 * @lpm_clock_gating: Enable core PHY clock gating.
389 * 0 - No
390 * 1 - Yes
391 * @besl: Enable LPM Errata support.
392 * 0 - No
393 * 1 - Yes
394 * @hird_threshold_en: HIRD or HIRD Threshold enable.
395 * 0 - No
396 * 1 - Yes
397 * @hird_threshold: Value of BESL or HIRD Threshold.
398 * @ref_clk_per: Indicates in terms of pico seconds the period
399 * of ref_clk.
400 * 62500 - 16MHz
401 * 58823 - 17MHz
402 * 52083 - 19.2MHz
403 * 50000 - 20MHz
404 * 41666 - 24MHz
405 * 33333 - 30MHz (default)
406 * 25000 - 40MHz
407 * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which
408 * the controller should generate an interrupt if the
409 * device had been in L1 state until that period.
410 * This is used by SW to initiate Remote WakeUp in the
411 * controller so as to sync to the uF number from the host.
412 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
413 * register.
414 * 0 - Deactivate the transceiver (default)
415 * 1 - Activate the transceiver
416 * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level
417 * detection using GGPIO register.
418 * 0 - Deactivate the external level detection (default)
419 * 1 - Activate the external level detection
420 * @g_dma: Enables gadget dma usage (default: autodetect).
421 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
422 * @g_rx_fifo_size: The periodic rx fifo size for the device, in
423 * DWORDS from 16-32768 (default: 2048 if
424 * possible, otherwise autodetect).
425 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
426 * DWORDS from 16-32768 (default: 1024 if
427 * possible, otherwise autodetect).
428 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
429 * mode. Each value corresponds to one EP
430 * starting from EP1 (max 15 values). Sizes are
431 * in DWORDS with possible values from from
432 * 16-32768 (default: 256, 256, 256, 256, 768,
433 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
434 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL
435 * while full&low speed device connect. And change speed
436 * back to DWC2_SPEED_PARAM_HIGH while device is gone.
437 * 0 - No (default)
438 * 1 - Yes
439 * @service_interval: Enable service interval based scheduling.
440 * 0 - No
441 * 1 - Yes
442 *
443 * The following parameters may be specified when starting the module. These
444 * parameters define how the DWC_otg controller should be configured. A
445 * value of -1 (or any other out of range value) for any parameter means
446 * to read the value from hardware (if possible) or use the builtin
447 * default described above.
448 */
449 struct dwc2_core_params {
450 u8 otg_cap;
451 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
452 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
453 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
454
455 u8 phy_type;
456 #define DWC2_PHY_TYPE_PARAM_FS 0
457 #define DWC2_PHY_TYPE_PARAM_UTMI 1
458 #define DWC2_PHY_TYPE_PARAM_ULPI 2
459
460 u8 speed;
461 #define DWC2_SPEED_PARAM_HIGH 0
462 #define DWC2_SPEED_PARAM_FULL 1
463 #define DWC2_SPEED_PARAM_LOW 2
464
465 u8 phy_utmi_width;
466 bool phy_ulpi_ddr;
467 bool phy_ulpi_ext_vbus;
468 bool enable_dynamic_fifo;
469 bool en_multiple_tx_fifo;
470 bool i2c_enable;
471 bool acg_enable;
472 bool ulpi_fs_ls;
473 bool ts_dline;
474 bool reload_ctl;
475 bool uframe_sched;
476 bool external_id_pin_ctl;
477
478 int power_down;
479 #define DWC2_POWER_DOWN_PARAM_NONE 0
480 #define DWC2_POWER_DOWN_PARAM_PARTIAL 1
481 #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2
482
483 bool lpm;
484 bool lpm_clock_gating;
485 bool besl;
486 bool hird_threshold_en;
487 bool service_interval;
488 u8 hird_threshold;
489 bool activate_stm_fs_transceiver;
490 bool activate_stm_id_vb_detection;
491 bool ipg_isoc_en;
492 u16 max_packet_count;
493 u32 max_transfer_size;
494 u32 ahbcfg;
495
496 /* GREFCLK parameters */
497 u32 ref_clk_per;
498 u16 sof_cnt_wkup_alert;
499
500 /* Host parameters */
501 bool host_dma;
502 bool dma_desc_enable;
503 bool dma_desc_fs_enable;
504 bool host_support_fs_ls_low_power;
505 bool host_ls_low_power_phy_clk;
506 bool oc_disable;
507
508 u8 host_channels;
509 u16 host_rx_fifo_size;
510 u16 host_nperio_tx_fifo_size;
511 u16 host_perio_tx_fifo_size;
512
513 /* Gadget parameters */
514 bool g_dma;
515 bool g_dma_desc;
516 u32 g_rx_fifo_size;
517 u32 g_np_tx_fifo_size;
518 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
519
520 bool change_speed_quirk;
521 };
522
523 /**
524 * struct dwc2_hw_params - Autodetected parameters.
525 *
526 * These parameters are the various parameters read from hardware
527 * registers during initialization. They typically contain the best
528 * supported or maximum value that can be configured in the
529 * corresponding dwc2_core_params value.
530 *
531 * The values that are not in dwc2_core_params are documented below.
532 *
533 * @op_mode: Mode of Operation
534 * 0 - HNP- and SRP-Capable OTG (Host & Device)
535 * 1 - SRP-Capable OTG (Host & Device)
536 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
537 * 3 - SRP-Capable Device
538 * 4 - Non-OTG Device
539 * 5 - SRP-Capable Host
540 * 6 - Non-OTG Host
541 * @arch: Architecture
542 * 0 - Slave only
543 * 1 - External DMA
544 * 2 - Internal DMA
545 * @ipg_isoc_en: This feature indicates that the controller supports
546 * the worst-case scenario of Rx followed by Rx
547 * Interpacket Gap (IPG) (32 bitTimes) as per the utmi
548 * specification for any token following ISOC OUT token.
549 * 0 - Don't support
550 * 1 - Support
551 * @power_optimized: Are power optimizations enabled?
552 * @num_dev_ep: Number of device endpoints available
553 * @num_dev_in_eps: Number of device IN endpoints available
554 * @num_dev_perio_in_ep: Number of device periodic IN endpoints
555 * available
556 * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue
557 * Depth
558 * 0 to 30
559 * @host_perio_tx_q_depth:
560 * Host Mode Periodic Request Queue Depth
561 * 2, 4 or 8
562 * @nperio_tx_q_depth:
563 * Non-Periodic Request Queue Depth
564 * 2, 4 or 8
565 * @hs_phy_type: High-speed PHY interface type
566 * 0 - High-speed interface not supported
567 * 1 - UTMI+
568 * 2 - ULPI
569 * 3 - UTMI+ and ULPI
570 * @fs_phy_type: Full-speed PHY interface type
571 * 0 - Full speed interface not supported
572 * 1 - Dedicated full speed interface
573 * 2 - FS pins shared with UTMI+ pins
574 * 3 - FS pins shared with ULPI pins
575 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
576 * @hibernation: Is hibernation enabled?
577 * @utmi_phy_data_width: UTMI+ PHY data width
578 * 0 - 8 bits
579 * 1 - 16 bits
580 * 2 - 8 or 16 bits
581 * @snpsid: Value from SNPSID register
582 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
583 * @g_tx_fifo_size: Power-on values of TxFIFO sizes
584 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
585 * address DMA mode or descriptor DMA mode for accessing
586 * the data FIFOs. The driver will automatically detect the
587 * value for this if none is specified.
588 * 0 - Address DMA
589 * 1 - Descriptor DMA (default, if available)
590 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
591 * 1 - Allow dynamic FIFO sizing (default, if available)
592 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
593 * are enabled for non-periodic IN endpoints in device
594 * mode.
595 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
596 * in host mode when dynamic FIFO sizing is enabled
597 * 16 to 32768
598 * Actual maximum value is autodetected and also
599 * the default.
600 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
601 * host mode when dynamic FIFO sizing is enabled
602 * 16 to 32768
603 * Actual maximum value is autodetected and also
604 * the default.
605 * @max_transfer_size: The maximum transfer size supported, in bytes
606 * 2047 to 65,535
607 * Actual maximum value is autodetected and also
608 * the default.
609 * @max_packet_count: The maximum number of packets in a transfer
610 * 15 to 511
611 * Actual maximum value is autodetected and also
612 * the default.
613 * @host_channels: The number of host channel registers to use
614 * 1 to 16
615 * Actual maximum value is autodetected and also
616 * the default.
617 * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
618 * in device mode when dynamic FIFO sizing is enabled
619 * 16 to 32768
620 * Actual maximum value is autodetected and also
621 * the default.
622 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
623 * speed PHY. This parameter is only applicable if phy_type
624 * is FS.
625 * 0 - No (default)
626 * 1 - Yes
627 * @acg_enable: For enabling Active Clock Gating in the controller
628 * 0 - Disable
629 * 1 - Enable
630 * @lpm_mode: For enabling Link Power Management in the controller
631 * 0 - Disable
632 * 1 - Enable
633 * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic
634 * FIFO sizing is enabled 16 to 32768
635 * Actual maximum value is autodetected and also
636 * the default.
637 * @service_interval_mode: For enabling service interval based scheduling in the
638 * controller.
639 * 0 - Disable
640 * 1 - Enable
641 */
642 struct dwc2_hw_params {
643 unsigned op_mode:3;
644 unsigned arch:2;
645 unsigned dma_desc_enable:1;
646 unsigned enable_dynamic_fifo:1;
647 unsigned en_multiple_tx_fifo:1;
648 unsigned rx_fifo_size:16;
649 unsigned host_nperio_tx_fifo_size:16;
650 unsigned dev_nperio_tx_fifo_size:16;
651 unsigned host_perio_tx_fifo_size:16;
652 unsigned nperio_tx_q_depth:3;
653 unsigned host_perio_tx_q_depth:3;
654 unsigned dev_token_q_depth:5;
655 unsigned max_transfer_size:26;
656 unsigned max_packet_count:11;
657 unsigned host_channels:5;
658 unsigned hs_phy_type:2;
659 unsigned fs_phy_type:2;
660 unsigned i2c_enable:1;
661 unsigned acg_enable:1;
662 unsigned num_dev_ep:4;
663 unsigned num_dev_in_eps : 4;
664 unsigned num_dev_perio_in_ep:4;
665 unsigned total_fifo_size:16;
666 unsigned power_optimized:1;
667 unsigned hibernation:1;
668 unsigned utmi_phy_data_width:2;
669 unsigned lpm_mode:1;
670 unsigned ipg_isoc_en:1;
671 unsigned service_interval_mode:1;
672 u32 snpsid;
673 u32 dev_ep_dirs;
674 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
675 };
676
677 /* Size of control and EP0 buffers */
678 #define DWC2_CTRL_BUFF_SIZE 8
679
680 /**
681 * struct dwc2_gregs_backup - Holds global registers state before
682 * entering partial power down
683 * @gotgctl: Backup of GOTGCTL register
684 * @gintmsk: Backup of GINTMSK register
685 * @gahbcfg: Backup of GAHBCFG register
686 * @gusbcfg: Backup of GUSBCFG register
687 * @grxfsiz: Backup of GRXFSIZ register
688 * @gnptxfsiz: Backup of GNPTXFSIZ register
689 * @gi2cctl: Backup of GI2CCTL register
690 * @glpmcfg: Backup of GLPMCFG register
691 * @gdfifocfg: Backup of GDFIFOCFG register
692 * @pcgcctl: Backup of PCGCCTL register
693 * @pcgcctl1: Backup of PCGCCTL1 register
694 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
695 * @gpwrdn: Backup of GPWRDN register
696 * @valid: True if registers values backuped.
697 */
698 struct dwc2_gregs_backup {
699 u32 gotgctl;
700 u32 gintmsk;
701 u32 gahbcfg;
702 u32 gusbcfg;
703 u32 grxfsiz;
704 u32 gnptxfsiz;
705 u32 gi2cctl;
706 u32 glpmcfg;
707 u32 pcgcctl;
708 u32 pcgcctl1;
709 u32 gdfifocfg;
710 u32 gpwrdn;
711 bool valid;
712 };
713
714 /**
715 * struct dwc2_dregs_backup - Holds device registers state before
716 * entering partial power down
717 * @dcfg: Backup of DCFG register
718 * @dctl: Backup of DCTL register
719 * @daintmsk: Backup of DAINTMSK register
720 * @diepmsk: Backup of DIEPMSK register
721 * @doepmsk: Backup of DOEPMSK register
722 * @diepctl: Backup of DIEPCTL register
723 * @dieptsiz: Backup of DIEPTSIZ register
724 * @diepdma: Backup of DIEPDMA register
725 * @doepctl: Backup of DOEPCTL register
726 * @doeptsiz: Backup of DOEPTSIZ register
727 * @doepdma: Backup of DOEPDMA register
728 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
729 * @valid: True if registers values backuped.
730 */
731 struct dwc2_dregs_backup {
732 u32 dcfg;
733 u32 dctl;
734 u32 daintmsk;
735 u32 diepmsk;
736 u32 doepmsk;
737 u32 diepctl[MAX_EPS_CHANNELS];
738 u32 dieptsiz[MAX_EPS_CHANNELS];
739 u32 diepdma[MAX_EPS_CHANNELS];
740 u32 doepctl[MAX_EPS_CHANNELS];
741 u32 doeptsiz[MAX_EPS_CHANNELS];
742 u32 doepdma[MAX_EPS_CHANNELS];
743 u32 dtxfsiz[MAX_EPS_CHANNELS];
744 bool valid;
745 };
746
747 /**
748 * struct dwc2_hregs_backup - Holds host registers state before
749 * entering partial power down
750 * @hcfg: Backup of HCFG register
751 * @haintmsk: Backup of HAINTMSK register
752 * @hcintmsk: Backup of HCINTMSK register
753 * @hprt0: Backup of HPTR0 register
754 * @hfir: Backup of HFIR register
755 * @hptxfsiz: Backup of HPTXFSIZ register
756 * @valid: True if registers values backuped.
757 */
758 struct dwc2_hregs_backup {
759 u32 hcfg;
760 u32 haintmsk;
761 u32 hcintmsk[MAX_EPS_CHANNELS];
762 u32 hprt0;
763 u32 hfir;
764 u32 hptxfsiz;
765 bool valid;
766 };
767
768 /*
769 * Constants related to high speed periodic scheduling
770 *
771 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
772 * reservation point of view it's assumed that the schedule goes right back to
773 * the beginning after the end of the schedule.
774 *
775 * What does that mean for scheduling things with a long interval? It means
776 * we'll reserve time for them in every possible microframe that they could
777 * ever be scheduled in. ...but we'll still only actually schedule them as
778 * often as they were requested.
779 *
780 * We keep our schedule in a "bitmap" structure. This simplifies having
781 * to keep track of and merge intervals: we just let the bitmap code do most
782 * of the heavy lifting. In a way scheduling is much like memory allocation.
783 *
784 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
785 * supposed to schedule for periodic transfers). That's according to spec.
786 *
787 * Note that though we only schedule 80% of each microframe, the bitmap that we
788 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
789 * space for each uFrame).
790 *
791 * Requirements:
792 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
793 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
794 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
795 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
796 */
797 #define DWC2_US_PER_UFRAME 125
798 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100
799
800 #define DWC2_HS_SCHEDULE_UFRAMES 8
801 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
802 DWC2_HS_PERIODIC_US_PER_UFRAME)
803
804 /*
805 * Constants related to low speed scheduling
806 *
807 * For high speed we schedule every 1us. For low speed that's a bit overkill,
808 * so we make up a unit called a "slice" that's worth 25us. There are 40
809 * slices in a full frame and we can schedule 36 of those (90%) for periodic
810 * transfers.
811 *
812 * Our low speed schedule can be as short as 1 frame or could be longer. When
813 * we only schedule 1 frame it means that we'll need to reserve a time every
814 * frame even for things that only transfer very rarely, so something that runs
815 * every 2048 frames will get time reserved in every frame. Our low speed
816 * schedule can be longer and we'll be able to handle more overlap, but that
817 * will come at increased memory cost and increased time to schedule.
818 *
819 * Note: one other advantage of a short low speed schedule is that if we mess
820 * up and miss scheduling we can jump in and use any of the slots that we
821 * happened to reserve.
822 *
823 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
824 * the schedule. There will be one schedule per TT.
825 *
826 * Requirements:
827 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
828 */
829 #define DWC2_US_PER_SLICE 25
830 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
831
832 #define DWC2_ROUND_US_TO_SLICE(us) \
833 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
834 DWC2_US_PER_SLICE)
835
836 #define DWC2_LS_PERIODIC_US_PER_FRAME \
837 900
838 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
839 (DWC2_LS_PERIODIC_US_PER_FRAME / \
840 DWC2_US_PER_SLICE)
841
842 #define DWC2_LS_SCHEDULE_FRAMES 1
843 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
844 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
845
846 /**
847 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
848 * and periodic schedules
849 *
850 * These are common for both host and peripheral modes:
851 *
852 * @dev: The struct device pointer
853 * @regs: Pointer to controller regs
854 * @hw_params: Parameters that were autodetected from the
855 * hardware registers
856 * @params: Parameters that define how the core should be configured
857 * @op_state: The operational State, during transitions (a_host=>
858 * a_peripheral and b_device=>b_host) this may not match
859 * the core, but allows the software to determine
860 * transitions
861 * @dr_mode: Requested mode of operation, one of following:
862 * - USB_DR_MODE_PERIPHERAL
863 * - USB_DR_MODE_HOST
864 * - USB_DR_MODE_OTG
865 * @role_sw: usb_role_switch handle
866 * @hcd_enabled: Host mode sub-driver initialization indicator.
867 * @gadget_enabled: Peripheral mode sub-driver initialization indicator.
868 * @ll_hw_enabled: Status of low-level hardware resources.
869 * @hibernated: True if core is hibernated
870 * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a
871 * remote wakeup.
872 * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend.
873 * @need_phy_for_wake: Quirk saying that we should keep the PHY on at
874 * suspend if we need USB to wake us up.
875 * @frame_number: Frame number read from the core. For both device
876 * and host modes. The value ranges are from 0
877 * to HFNUM_MAX_FRNUM.
878 * @phy: The otg phy transceiver structure for phy control.
879 * @uphy: The otg phy transceiver structure for old USB phy
880 * control.
881 * @plat: The platform specific configuration data. This can be
882 * removed once all SoCs support usb transceiver.
883 * @supplies: Definition of USB power supplies
884 * @vbus_supply: Regulator supplying vbus.
885 * @usb33d: Optional 3.3v regulator used on some stm32 devices to
886 * supply ID and VBUS detection hardware.
887 * @lock: Spinlock that protects all the driver data structures
888 * @priv: Stores a pointer to the struct usb_hcd
889 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
890 * transfer are in process of being queued
891 * @srp_success: Stores status of SRP request in the case of a FS PHY
892 * with an I2C interface
893 * @wq_otg: Workqueue object used for handling of some interrupts
894 * @wf_otg: Work object for handling Connector ID Status Change
895 * interrupt
896 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
897 * @lx_state: Lx state of connected device
898 * @gr_backup: Backup of global registers during suspend
899 * @dr_backup: Backup of device registers during suspend
900 * @hr_backup: Backup of host registers during suspend
901 * @needs_byte_swap: Specifies whether the opposite endianness.
902 *
903 * These are for host mode:
904 *
905 * @flags: Flags for handling root port state changes
906 * @flags.d32: Contain all root port flags
907 * @flags.b: Separate root port flags from each other
908 * @flags.b.port_connect_status_change: True if root port connect status
909 * changed
910 * @flags.b.port_connect_status: True if device connected to root port
911 * @flags.b.port_reset_change: True if root port reset status changed
912 * @flags.b.port_enable_change: True if root port enable status changed
913 * @flags.b.port_suspend_change: True if root port suspend status changed
914 * @flags.b.port_over_current_change: True if root port over current state
915 * changed.
916 * @flags.b.port_l1_change: True if root port l1 status changed
917 * @flags.b.reserved: Reserved bits of root port register
918 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
919 * Transfers associated with these QHs are not currently
920 * assigned to a host channel.
921 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
922 * Transfers associated with these QHs are currently
923 * assigned to a host channel.
924 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
925 * non-periodic schedule
926 * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule.
927 * Transfers associated with these QHs are not currently
928 * assigned to a host channel.
929 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
930 * list of QHs for periodic transfers that are _not_
931 * scheduled for the next frame. Each QH in the list has an
932 * interval counter that determines when it needs to be
933 * scheduled for execution. This scheduling mechanism
934 * allows only a simple calculation for periodic bandwidth
935 * used (i.e. must assume that all periodic transfers may
936 * need to execute in the same frame). However, it greatly
937 * simplifies scheduling and should be sufficient for the
938 * vast majority of OTG hosts, which need to connect to a
939 * small number of peripherals at one time. Items move from
940 * this list to periodic_sched_ready when the QH interval
941 * counter is 0 at SOF.
942 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
943 * the next frame, but have not yet been assigned to host
944 * channels. Items move from this list to
945 * periodic_sched_assigned as host channels become
946 * available during the current frame.
947 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
948 * frame that are assigned to host channels. Items move
949 * from this list to periodic_sched_queued as the
950 * transactions for the QH are queued to the DWC_otg
951 * controller.
952 * @periodic_sched_queued: List of periodic QHs that have been queued for
953 * execution. Items move from this list to either
954 * periodic_sched_inactive or periodic_sched_ready when the
955 * channel associated with the transfer is released. If the
956 * interval for the QH is 1, the item moves to
957 * periodic_sched_ready because it must be rescheduled for
958 * the next frame. Otherwise, the item moves to
959 * periodic_sched_inactive.
960 * @split_order: List keeping track of channels doing splits, in order.
961 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
962 * This value is in microseconds per (micro)frame. The
963 * assumption is that all periodic transfers may occur in
964 * the same (micro)frame.
965 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
966 * host is in high speed mode; low speed schedules are
967 * stored elsewhere since we need one per TT.
968 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
969 * SOF enable/disable.
970 * @free_hc_list: Free host channels in the controller. This is a list of
971 * struct dwc2_host_chan items.
972 * @periodic_channels: Number of host channels assigned to periodic transfers.
973 * Currently assuming that there is a dedicated host
974 * channel for each periodic transaction and at least one
975 * host channel is available for non-periodic transactions.
976 * @non_periodic_channels: Number of host channels assigned to non-periodic
977 * transfers
978 * @available_host_channels: Number of host channels available for the
979 * microframe scheduler to use
980 * @hc_ptr_array: Array of pointers to the host channel descriptors.
981 * Allows accessing a host channel descriptor given the
982 * host channel number. This is useful in interrupt
983 * handlers.
984 * @status_buf: Buffer used for data received during the status phase of
985 * a control transfer.
986 * @status_buf_dma: DMA address for status_buf
987 * @start_work: Delayed work for handling host A-cable connection
988 * @reset_work: Delayed work for handling a port reset
989 * @phy_reset_work: Work structure for doing a PHY reset
990 * @otg_port: OTG port number
991 * @frame_list: Frame list
992 * @frame_list_dma: Frame list DMA address
993 * @frame_list_sz: Frame list size
994 * @desc_gen_cache: Kmem cache for generic descriptors
995 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
996 * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf
997 *
998 * These are for peripheral mode:
999 *
1000 * @driver: USB gadget driver
1001 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
1002 * @num_of_eps: Number of available EPs (excluding EP0)
1003 * @debug_root: Root directrory for debugfs.
1004 * @ep0_reply: Request used for ep0 reply.
1005 * @ep0_buff: Buffer for EP0 reply data, if needed.
1006 * @ctrl_buff: Buffer for EP0 control requests.
1007 * @ctrl_req: Request for EP0 control packets.
1008 * @ep0_state: EP0 control transfers state
1009 * @delayed_status: true when gadget driver asks for delayed status
1010 * @test_mode: USB test mode requested by the host
1011 * @remote_wakeup_allowed: True if device is allowed to wake-up host by
1012 * remote-wakeup signalling
1013 * @setup_desc_dma: EP0 setup stage desc chain DMA address
1014 * @setup_desc: EP0 setup stage desc chain pointer
1015 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
1016 * @ctrl_in_desc: EP0 IN data phase desc chain pointer
1017 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
1018 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
1019 * @irq: Interrupt request line number
1020 * @clk: Pointer to otg clock
1021 * @reset: Pointer to dwc2 reset controller
1022 * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10.
1023 * @regset: A pointer to a struct debugfs_regset32, which contains
1024 * a pointer to an array of register definitions, the
1025 * array size and the base address where the register bank
1026 * is to be found.
1027 * @bus_suspended: True if bus is suspended
1028 * @last_frame_num: Number of last frame. Range from 0 to 32768
1029 * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1030 * defined, for missed SOFs tracking. Array holds that
1031 * frame numbers, which not equal to last_frame_num +1
1032 * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1033 * defined, for missed SOFs tracking.
1034 * If current_frame_number != last_frame_num+1
1035 * then last_frame_num added to this array
1036 * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array
1037 * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed
1038 * 0 - if missed SOFs frame numbers not dumbed
1039 * @fifo_mem: Total internal RAM for FIFOs (bytes)
1040 * @fifo_map: Each bit intend for concrete fifo. If that bit is set,
1041 * then that fifo is used
1042 * @gadget: Represents a usb gadget device
1043 * @connected: Used in slave mode. True if device connected with host
1044 * @eps_in: The IN endpoints being supplied to the gadget framework
1045 * @eps_out: The OUT endpoints being supplied to the gadget framework
1046 * @new_connection: Used in host mode. True if there are new connected
1047 * device
1048 * @enabled: Indicates the enabling state of controller
1049 *
1050 */
1051 struct dwc2_hsotg {
1052 struct device *dev;
1053 void __iomem *regs;
1054 /** Params detected from hardware */
1055 struct dwc2_hw_params hw_params;
1056 /** Params to actually use */
1057 struct dwc2_core_params params;
1058 enum usb_otg_state op_state;
1059 enum usb_dr_mode dr_mode;
1060 struct usb_role_switch *role_sw;
1061 unsigned int hcd_enabled:1;
1062 unsigned int gadget_enabled:1;
1063 unsigned int ll_hw_enabled:1;
1064 unsigned int hibernated:1;
1065 unsigned int reset_phy_on_wake:1;
1066 unsigned int need_phy_for_wake:1;
1067 unsigned int phy_off_for_suspend:1;
1068 u16 frame_number;
1069
1070 struct phy *phy;
1071 struct usb_phy *uphy;
1072 struct dwc2_hsotg_plat *plat;
1073 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
1074 struct regulator *vbus_supply;
1075 struct regulator *usb33d;
1076
1077 spinlock_t lock;
1078 void *priv;
1079 int irq;
1080 struct clk *clk;
1081 struct reset_control *reset;
1082 struct reset_control *reset_ecc;
1083
1084 unsigned int queuing_high_bandwidth:1;
1085 unsigned int srp_success:1;
1086
1087 struct workqueue_struct *wq_otg;
1088 struct work_struct wf_otg;
1089 struct timer_list wkp_timer;
1090 enum dwc2_lx_state lx_state;
1091 struct dwc2_gregs_backup gr_backup;
1092 struct dwc2_dregs_backup dr_backup;
1093 struct dwc2_hregs_backup hr_backup;
1094
1095 struct dentry *debug_root;
1096 struct debugfs_regset32 *regset;
1097 bool needs_byte_swap;
1098
1099 /* DWC OTG HW Release versions */
1100 #define DWC2_CORE_REV_2_71a 0x4f54271a
1101 #define DWC2_CORE_REV_2_72a 0x4f54272a
1102 #define DWC2_CORE_REV_2_80a 0x4f54280a
1103 #define DWC2_CORE_REV_2_90a 0x4f54290a
1104 #define DWC2_CORE_REV_2_91a 0x4f54291a
1105 #define DWC2_CORE_REV_2_92a 0x4f54292a
1106 #define DWC2_CORE_REV_2_94a 0x4f54294a
1107 #define DWC2_CORE_REV_3_00a 0x4f54300a
1108 #define DWC2_CORE_REV_3_10a 0x4f54310a
1109 #define DWC2_CORE_REV_4_00a 0x4f54400a
1110 #define DWC2_CORE_REV_4_20a 0x4f54420a
1111 #define DWC2_FS_IOT_REV_1_00a 0x5531100a
1112 #define DWC2_HS_IOT_REV_1_00a 0x5532100a
1113 #define DWC2_CORE_REV_MASK 0x0000ffff
1114
1115 /* DWC OTG HW Core ID */
1116 #define DWC2_OTG_ID 0x4f540000
1117 #define DWC2_FS_IOT_ID 0x55310000
1118 #define DWC2_HS_IOT_ID 0x55320000
1119
1120 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1121 union dwc2_hcd_internal_flags {
1122 u32 d32;
1123 struct {
1124 unsigned port_connect_status_change:1;
1125 unsigned port_connect_status:1;
1126 unsigned port_reset_change:1;
1127 unsigned port_enable_change:1;
1128 unsigned port_suspend_change:1;
1129 unsigned port_over_current_change:1;
1130 unsigned port_l1_change:1;
1131 unsigned reserved:25;
1132 } b;
1133 } flags;
1134
1135 struct list_head non_periodic_sched_inactive;
1136 struct list_head non_periodic_sched_waiting;
1137 struct list_head non_periodic_sched_active;
1138 struct list_head *non_periodic_qh_ptr;
1139 struct list_head periodic_sched_inactive;
1140 struct list_head periodic_sched_ready;
1141 struct list_head periodic_sched_assigned;
1142 struct list_head periodic_sched_queued;
1143 struct list_head split_order;
1144 u16 periodic_usecs;
1145 unsigned long hs_periodic_bitmap[
1146 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
1147 u16 periodic_qh_count;
1148 bool bus_suspended;
1149 bool new_connection;
1150
1151 u16 last_frame_num;
1152
1153 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
1154 #define FRAME_NUM_ARRAY_SIZE 1000
1155 u16 *frame_num_array;
1156 u16 *last_frame_num_array;
1157 int frame_num_idx;
1158 int dumped_frame_num_array;
1159 #endif
1160
1161 struct list_head free_hc_list;
1162 int periodic_channels;
1163 int non_periodic_channels;
1164 int available_host_channels;
1165 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
1166 u8 *status_buf;
1167 dma_addr_t status_buf_dma;
1168 #define DWC2_HCD_STATUS_BUF_SIZE 64
1169
1170 struct delayed_work start_work;
1171 struct delayed_work reset_work;
1172 struct work_struct phy_reset_work;
1173 u8 otg_port;
1174 u32 *frame_list;
1175 dma_addr_t frame_list_dma;
1176 u32 frame_list_sz;
1177 struct kmem_cache *desc_gen_cache;
1178 struct kmem_cache *desc_hsisoc_cache;
1179 struct kmem_cache *unaligned_cache;
1180 #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024
1181
1182 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1183
1184 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1185 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1186 /* Gadget structures */
1187 struct usb_gadget_driver *driver;
1188 int fifo_mem;
1189 unsigned int dedicated_fifos:1;
1190 unsigned char num_of_eps;
1191 u32 fifo_map;
1192
1193 struct usb_request *ep0_reply;
1194 struct usb_request *ctrl_req;
1195 void *ep0_buff;
1196 void *ctrl_buff;
1197 enum dwc2_ep0_state ep0_state;
1198 unsigned delayed_status : 1;
1199 u8 test_mode;
1200
1201 dma_addr_t setup_desc_dma[2];
1202 struct dwc2_dma_desc *setup_desc[2];
1203 dma_addr_t ctrl_in_desc_dma;
1204 struct dwc2_dma_desc *ctrl_in_desc;
1205 dma_addr_t ctrl_out_desc_dma;
1206 struct dwc2_dma_desc *ctrl_out_desc;
1207
1208 struct usb_gadget gadget;
1209 unsigned int enabled:1;
1210 unsigned int connected:1;
1211 unsigned int remote_wakeup_allowed:1;
1212 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1213 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
1214 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
1215 };
1216
1217 /* Normal architectures just use readl/write */
dwc2_readl(struct dwc2_hsotg * hsotg,u32 offset)1218 static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)
1219 {
1220 u32 val;
1221
1222 val = readl(hsotg->regs + offset);
1223 if (hsotg->needs_byte_swap)
1224 return swab32(val);
1225 else
1226 return val;
1227 }
1228
dwc2_writel(struct dwc2_hsotg * hsotg,u32 value,u32 offset)1229 static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)
1230 {
1231 if (hsotg->needs_byte_swap)
1232 writel(swab32(value), hsotg->regs + offset);
1233 else
1234 writel(value, hsotg->regs + offset);
1235
1236 #ifdef DWC2_LOG_WRITES
1237 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset);
1238 #endif
1239 }
1240
dwc2_readl_rep(struct dwc2_hsotg * hsotg,u32 offset,void * buffer,unsigned int count)1241 static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset,
1242 void *buffer, unsigned int count)
1243 {
1244 if (count) {
1245 u32 *buf = buffer;
1246
1247 do {
1248 u32 x = dwc2_readl(hsotg, offset);
1249 *buf++ = x;
1250 } while (--count);
1251 }
1252 }
1253
dwc2_writel_rep(struct dwc2_hsotg * hsotg,u32 offset,const void * buffer,unsigned int count)1254 static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset,
1255 const void *buffer, unsigned int count)
1256 {
1257 if (count) {
1258 const u32 *buf = buffer;
1259
1260 do {
1261 dwc2_writel(hsotg, *buf++, offset);
1262 } while (--count);
1263 }
1264 }
1265
1266 /* Reasons for halting a host channel */
1267 enum dwc2_halt_status {
1268 DWC2_HC_XFER_NO_HALT_STATUS,
1269 DWC2_HC_XFER_COMPLETE,
1270 DWC2_HC_XFER_URB_COMPLETE,
1271 DWC2_HC_XFER_ACK,
1272 DWC2_HC_XFER_NAK,
1273 DWC2_HC_XFER_NYET,
1274 DWC2_HC_XFER_STALL,
1275 DWC2_HC_XFER_XACT_ERR,
1276 DWC2_HC_XFER_FRAME_OVERRUN,
1277 DWC2_HC_XFER_BABBLE_ERR,
1278 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1279 DWC2_HC_XFER_AHB_ERR,
1280 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1281 DWC2_HC_XFER_URB_DEQUEUE,
1282 };
1283
1284 /* Core version information */
dwc2_is_iot(struct dwc2_hsotg * hsotg)1285 static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
1286 {
1287 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000;
1288 }
1289
dwc2_is_fs_iot(struct dwc2_hsotg * hsotg)1290 static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
1291 {
1292 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000;
1293 }
1294
dwc2_is_hs_iot(struct dwc2_hsotg * hsotg)1295 static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
1296 {
1297 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000;
1298 }
1299
1300 /*
1301 * The following functions support initialization of the core driver component
1302 * and the DWC_otg controller
1303 */
1304 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
1305 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1306 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore);
1307 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host);
1308 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
1309 int reset, int is_host);
1310 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg);
1311 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy);
1312
1313 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host);
1314 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1315
1316 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
1317
1318 int dwc2_check_core_version(struct dwc2_hsotg *hsotg);
1319
1320 /*
1321 * Common core Functions.
1322 * The following functions support managing the DWC_otg controller in either
1323 * device or host mode.
1324 */
1325 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1326 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1327 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1328
1329 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1330 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1331
1332 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
1333 int is_host);
1334 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg);
1335 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg);
1336
1337 void dwc2_enable_acg(struct dwc2_hsotg *hsotg);
1338
1339 /* This function should be called on every hardware interrupt. */
1340 irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1341
1342 /* The device ID match table */
1343 extern const struct of_device_id dwc2_of_match_table[];
1344
1345 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1346 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
1347
1348 /* Common polling functions */
1349 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1350 u32 timeout);
1351 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1352 u32 timeout);
1353 /* Parameters */
1354 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1355 int dwc2_init_params(struct dwc2_hsotg *hsotg);
1356
1357 /*
1358 * The following functions check the controller's OTG operation mode
1359 * capability (GHWCFG2.OTG_MODE).
1360 *
1361 * These functions can be used before the internal hsotg->hw_params
1362 * are read in and cached so they always read directly from the
1363 * GHWCFG2 register.
1364 */
1365 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg);
1366 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1367 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1368 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1369
1370 /*
1371 * Returns the mode of operation, host or device
1372 */
dwc2_is_host_mode(struct dwc2_hsotg * hsotg)1373 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1374 {
1375 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1376 }
1377
dwc2_is_device_mode(struct dwc2_hsotg * hsotg)1378 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1379 {
1380 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1381 }
1382
1383 int dwc2_drd_init(struct dwc2_hsotg *hsotg);
1384 void dwc2_drd_suspend(struct dwc2_hsotg *hsotg);
1385 void dwc2_drd_resume(struct dwc2_hsotg *hsotg);
1386 void dwc2_drd_exit(struct dwc2_hsotg *hsotg);
1387
1388 /*
1389 * Dump core registers and SPRAM
1390 */
1391 void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1392 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1393 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1394
1395 /* Gadget defines */
1396 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1397 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1398 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1399 int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1400 int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
1401 int dwc2_gadget_init(struct dwc2_hsotg *hsotg);
1402 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1403 bool reset);
1404 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg);
1405 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1406 void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1407 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
1408 #define dwc2_is_device_connected(hsotg) (hsotg->connected)
1409 #define dwc2_is_device_enabled(hsotg) (hsotg->enabled)
1410 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1411 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup);
1412 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg);
1413 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1414 int rem_wakeup, int reset);
1415 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg);
1416 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg);
1417 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg);
1418 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg);
1419 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg);
1420 #else
dwc2_hsotg_remove(struct dwc2_hsotg * dwc2)1421 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
1422 { return 0; }
dwc2_hsotg_suspend(struct dwc2_hsotg * dwc2)1423 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
1424 { return 0; }
dwc2_hsotg_resume(struct dwc2_hsotg * dwc2)1425 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
1426 { return 0; }
dwc2_gadget_init(struct dwc2_hsotg * hsotg)1427 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
1428 { return 0; }
dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg * dwc2,bool reset)1429 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1430 bool reset) {}
dwc2_hsotg_core_disconnect(struct dwc2_hsotg * hsotg)1431 static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {}
dwc2_hsotg_core_connect(struct dwc2_hsotg * hsotg)1432 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
dwc2_hsotg_disconnect(struct dwc2_hsotg * dwc2)1433 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
dwc2_hsotg_set_test_mode(struct dwc2_hsotg * hsotg,int testmode)1434 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
1435 int testmode)
1436 { return 0; }
1437 #define dwc2_is_device_connected(hsotg) (0)
1438 #define dwc2_is_device_enabled(hsotg) (0)
dwc2_backup_device_registers(struct dwc2_hsotg * hsotg)1439 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1440 { return 0; }
dwc2_restore_device_registers(struct dwc2_hsotg * hsotg,int remote_wakeup)1441 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg,
1442 int remote_wakeup)
1443 { return 0; }
dwc2_gadget_enter_hibernation(struct dwc2_hsotg * hsotg)1444 static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
1445 { return 0; }
dwc2_gadget_exit_hibernation(struct dwc2_hsotg * hsotg,int rem_wakeup,int reset)1446 static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1447 int rem_wakeup, int reset)
1448 { return 0; }
dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg * hsotg)1449 static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
1450 { return 0; }
dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg * hsotg)1451 static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
1452 { return 0; }
dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg * hsotg)1453 static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
1454 { return 0; }
dwc2_gadget_init_lpm(struct dwc2_hsotg * hsotg)1455 static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {}
dwc2_gadget_program_ref_clk(struct dwc2_hsotg * hsotg)1456 static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {}
1457 #endif
1458
1459 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1460 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1461 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1462 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1463 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1464 void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1465 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
1466 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1467 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
1468 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg);
1469 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1470 int rem_wakeup, int reset);
1471 bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2);
dwc2_host_schedule_phy_reset(struct dwc2_hsotg * hsotg)1472 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg)
1473 { schedule_work(&hsotg->phy_reset_work); }
1474 #else
dwc2_hcd_get_frame_number(struct dwc2_hsotg * hsotg)1475 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1476 { return 0; }
dwc2_hcd_get_future_frame_number(struct dwc2_hsotg * hsotg,int us)1477 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1478 int us)
1479 { return 0; }
dwc2_hcd_connect(struct dwc2_hsotg * hsotg)1480 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
dwc2_hcd_disconnect(struct dwc2_hsotg * hsotg,bool force)1481 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
dwc2_hcd_start(struct dwc2_hsotg * hsotg)1482 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
dwc2_hcd_remove(struct dwc2_hsotg * hsotg)1483 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
dwc2_core_init(struct dwc2_hsotg * hsotg,bool initial_setup)1484 static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
1485 { return 0; }
dwc2_hcd_init(struct dwc2_hsotg * hsotg)1486 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
1487 { return 0; }
dwc2_backup_host_registers(struct dwc2_hsotg * hsotg)1488 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1489 { return 0; }
dwc2_restore_host_registers(struct dwc2_hsotg * hsotg)1490 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1491 { return 0; }
dwc2_host_enter_hibernation(struct dwc2_hsotg * hsotg)1492 static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
1493 { return 0; }
dwc2_host_exit_hibernation(struct dwc2_hsotg * hsotg,int rem_wakeup,int reset)1494 static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1495 int rem_wakeup, int reset)
1496 { return 0; }
dwc2_host_can_poweroff_phy(struct dwc2_hsotg * dwc2)1497 static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
1498 { return false; }
dwc2_host_schedule_phy_reset(struct dwc2_hsotg * hsotg)1499 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {}
1500
1501 #endif
1502
1503 #endif /* __DWC2_CORE_H__ */
1504