1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/etherdevice.h>
5
6 #include "hclge_cmd.h"
7 #include "hclge_main.h"
8 #include "hclge_tm.h"
9
10 enum hclge_shaper_level {
11 HCLGE_SHAPER_LVL_PRI = 0,
12 HCLGE_SHAPER_LVL_PG = 1,
13 HCLGE_SHAPER_LVL_PORT = 2,
14 HCLGE_SHAPER_LVL_QSET = 3,
15 HCLGE_SHAPER_LVL_CNT = 4,
16 HCLGE_SHAPER_LVL_VF = 0,
17 HCLGE_SHAPER_LVL_PF = 1,
18 };
19
20 #define HCLGE_TM_PFC_PKT_GET_CMD_NUM 3
21 #define HCLGE_TM_PFC_NUM_GET_PER_CMD 3
22
23 #define HCLGE_SHAPER_BS_U_DEF 5
24 #define HCLGE_SHAPER_BS_S_DEF 20
25
26 /* hclge_shaper_para_calc: calculate ir parameter for the shaper
27 * @ir: Rate to be config, its unit is Mbps
28 * @shaper_level: the shaper level. eg: port, pg, priority, queueset
29 * @ir_para: parameters of IR shaper
30 * @max_tm_rate: max tm rate is available to config
31 *
32 * the formula:
33 *
34 * IR_b * (2 ^ IR_u) * 8
35 * IR(Mbps) = ------------------------- * CLOCK(1000Mbps)
36 * Tick * (2 ^ IR_s)
37 *
38 * @return: 0: calculate sucessful, negative: fail
39 */
hclge_shaper_para_calc(u32 ir,u8 shaper_level,struct hclge_shaper_ir_para * ir_para,u32 max_tm_rate)40 static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
41 struct hclge_shaper_ir_para *ir_para,
42 u32 max_tm_rate)
43 {
44 #define DIVISOR_CLK (1000 * 8)
45 #define DIVISOR_IR_B_126 (126 * DIVISOR_CLK)
46
47 static const u16 tick_array[HCLGE_SHAPER_LVL_CNT] = {
48 6 * 256, /* Prioriy level */
49 6 * 32, /* Prioriy group level */
50 6 * 8, /* Port level */
51 6 * 256 /* Qset level */
52 };
53 u8 ir_u_calc = 0;
54 u8 ir_s_calc = 0;
55 u32 ir_calc;
56 u32 tick;
57
58 /* Calc tick */
59 if (shaper_level >= HCLGE_SHAPER_LVL_CNT ||
60 ir > max_tm_rate)
61 return -EINVAL;
62
63 tick = tick_array[shaper_level];
64
65 /**
66 * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0
67 * the formula is changed to:
68 * 126 * 1 * 8
69 * ir_calc = ---------------- * 1000
70 * tick * 1
71 */
72 ir_calc = (DIVISOR_IR_B_126 + (tick >> 1) - 1) / tick;
73
74 if (ir_calc == ir) {
75 ir_para->ir_b = 126;
76 ir_para->ir_u = 0;
77 ir_para->ir_s = 0;
78
79 return 0;
80 } else if (ir_calc > ir) {
81 /* Increasing the denominator to select ir_s value */
82 while (ir_calc >= ir && ir) {
83 ir_s_calc++;
84 ir_calc = DIVISOR_IR_B_126 / (tick * (1 << ir_s_calc));
85 }
86
87 ir_para->ir_b = (ir * tick * (1 << ir_s_calc) +
88 (DIVISOR_CLK >> 1)) / DIVISOR_CLK;
89 } else {
90 /* Increasing the numerator to select ir_u value */
91 u32 numerator;
92
93 while (ir_calc < ir) {
94 ir_u_calc++;
95 numerator = DIVISOR_IR_B_126 * (1 << ir_u_calc);
96 ir_calc = (numerator + (tick >> 1)) / tick;
97 }
98
99 if (ir_calc == ir) {
100 ir_para->ir_b = 126;
101 } else {
102 u32 denominator = DIVISOR_CLK * (1 << --ir_u_calc);
103 ir_para->ir_b = (ir * tick + (denominator >> 1)) /
104 denominator;
105 }
106 }
107
108 ir_para->ir_u = ir_u_calc;
109 ir_para->ir_s = ir_s_calc;
110
111 return 0;
112 }
113
hclge_pfc_stats_get(struct hclge_dev * hdev,enum hclge_opcode_type opcode,u64 * stats)114 static int hclge_pfc_stats_get(struct hclge_dev *hdev,
115 enum hclge_opcode_type opcode, u64 *stats)
116 {
117 struct hclge_desc desc[HCLGE_TM_PFC_PKT_GET_CMD_NUM];
118 int ret, i, j;
119
120 if (!(opcode == HCLGE_OPC_QUERY_PFC_RX_PKT_CNT ||
121 opcode == HCLGE_OPC_QUERY_PFC_TX_PKT_CNT))
122 return -EINVAL;
123
124 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM - 1; i++) {
125 hclge_cmd_setup_basic_desc(&desc[i], opcode, true);
126 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
127 }
128
129 hclge_cmd_setup_basic_desc(&desc[i], opcode, true);
130
131 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_TM_PFC_PKT_GET_CMD_NUM);
132 if (ret)
133 return ret;
134
135 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM; i++) {
136 struct hclge_pfc_stats_cmd *pfc_stats =
137 (struct hclge_pfc_stats_cmd *)desc[i].data;
138
139 for (j = 0; j < HCLGE_TM_PFC_NUM_GET_PER_CMD; j++) {
140 u32 index = i * HCLGE_TM_PFC_PKT_GET_CMD_NUM + j;
141
142 if (index < HCLGE_MAX_TC_NUM)
143 stats[index] =
144 le64_to_cpu(pfc_stats->pkt_num[j]);
145 }
146 }
147 return 0;
148 }
149
hclge_pfc_rx_stats_get(struct hclge_dev * hdev,u64 * stats)150 int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats)
151 {
152 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_RX_PKT_CNT, stats);
153 }
154
hclge_pfc_tx_stats_get(struct hclge_dev * hdev,u64 * stats)155 int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats)
156 {
157 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_TX_PKT_CNT, stats);
158 }
159
hclge_mac_pause_en_cfg(struct hclge_dev * hdev,bool tx,bool rx)160 int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx)
161 {
162 struct hclge_desc desc;
163
164 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PAUSE_EN, false);
165
166 desc.data[0] = cpu_to_le32((tx ? HCLGE_TX_MAC_PAUSE_EN_MSK : 0) |
167 (rx ? HCLGE_RX_MAC_PAUSE_EN_MSK : 0));
168
169 return hclge_cmd_send(&hdev->hw, &desc, 1);
170 }
171
hclge_pfc_pause_en_cfg(struct hclge_dev * hdev,u8 tx_rx_bitmap,u8 pfc_bitmap)172 int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
173 u8 pfc_bitmap)
174 {
175 struct hclge_desc desc;
176 struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)desc.data;
177
178 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PFC_PAUSE_EN, false);
179
180 pfc->tx_rx_en_bitmap = tx_rx_bitmap;
181 pfc->pri_en_bitmap = pfc_bitmap;
182
183 return hclge_cmd_send(&hdev->hw, &desc, 1);
184 }
185
hclge_pause_param_cfg(struct hclge_dev * hdev,const u8 * addr,u8 pause_trans_gap,u16 pause_trans_time)186 static int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr,
187 u8 pause_trans_gap, u16 pause_trans_time)
188 {
189 struct hclge_cfg_pause_param_cmd *pause_param;
190 struct hclge_desc desc;
191
192 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
193
194 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, false);
195
196 ether_addr_copy(pause_param->mac_addr, addr);
197 ether_addr_copy(pause_param->mac_addr_extra, addr);
198 pause_param->pause_trans_gap = pause_trans_gap;
199 pause_param->pause_trans_time = cpu_to_le16(pause_trans_time);
200
201 return hclge_cmd_send(&hdev->hw, &desc, 1);
202 }
203
hclge_pause_addr_cfg(struct hclge_dev * hdev,const u8 * mac_addr)204 int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr)
205 {
206 struct hclge_cfg_pause_param_cmd *pause_param;
207 struct hclge_desc desc;
208 u16 trans_time;
209 u8 trans_gap;
210 int ret;
211
212 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
213
214 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true);
215
216 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
217 if (ret)
218 return ret;
219
220 trans_gap = pause_param->pause_trans_gap;
221 trans_time = le16_to_cpu(pause_param->pause_trans_time);
222
223 return hclge_pause_param_cfg(hdev, mac_addr, trans_gap, trans_time);
224 }
225
hclge_fill_pri_array(struct hclge_dev * hdev,u8 * pri,u8 pri_id)226 static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id)
227 {
228 u8 tc;
229
230 tc = hdev->tm_info.prio_tc[pri_id];
231
232 if (tc >= hdev->tm_info.num_tc)
233 return -EINVAL;
234
235 /**
236 * the register for priority has four bytes, the first bytes includes
237 * priority0 and priority1, the higher 4bit stands for priority1
238 * while the lower 4bit stands for priority0, as below:
239 * first byte: | pri_1 | pri_0 |
240 * second byte: | pri_3 | pri_2 |
241 * third byte: | pri_5 | pri_4 |
242 * fourth byte: | pri_7 | pri_6 |
243 */
244 pri[pri_id >> 1] |= tc << ((pri_id & 1) * 4);
245
246 return 0;
247 }
248
hclge_up_to_tc_map(struct hclge_dev * hdev)249 static int hclge_up_to_tc_map(struct hclge_dev *hdev)
250 {
251 struct hclge_desc desc;
252 u8 *pri = (u8 *)desc.data;
253 u8 pri_id;
254 int ret;
255
256 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, false);
257
258 for (pri_id = 0; pri_id < HNAE3_MAX_USER_PRIO; pri_id++) {
259 ret = hclge_fill_pri_array(hdev, pri, pri_id);
260 if (ret)
261 return ret;
262 }
263
264 return hclge_cmd_send(&hdev->hw, &desc, 1);
265 }
266
hclge_tm_pg_to_pri_map_cfg(struct hclge_dev * hdev,u8 pg_id,u8 pri_bit_map)267 static int hclge_tm_pg_to_pri_map_cfg(struct hclge_dev *hdev,
268 u8 pg_id, u8 pri_bit_map)
269 {
270 struct hclge_pg_to_pri_link_cmd *map;
271 struct hclge_desc desc;
272
273 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_TO_PRI_LINK, false);
274
275 map = (struct hclge_pg_to_pri_link_cmd *)desc.data;
276
277 map->pg_id = pg_id;
278 map->pri_bit_map = pri_bit_map;
279
280 return hclge_cmd_send(&hdev->hw, &desc, 1);
281 }
282
hclge_tm_qs_to_pri_map_cfg(struct hclge_dev * hdev,u16 qs_id,u8 pri)283 static int hclge_tm_qs_to_pri_map_cfg(struct hclge_dev *hdev,
284 u16 qs_id, u8 pri)
285 {
286 struct hclge_qs_to_pri_link_cmd *map;
287 struct hclge_desc desc;
288
289 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_TO_PRI_LINK, false);
290
291 map = (struct hclge_qs_to_pri_link_cmd *)desc.data;
292
293 map->qs_id = cpu_to_le16(qs_id);
294 map->priority = pri;
295 map->link_vld = HCLGE_TM_QS_PRI_LINK_VLD_MSK;
296
297 return hclge_cmd_send(&hdev->hw, &desc, 1);
298 }
299
hclge_tm_q_to_qs_map_cfg(struct hclge_dev * hdev,u16 q_id,u16 qs_id)300 static int hclge_tm_q_to_qs_map_cfg(struct hclge_dev *hdev,
301 u16 q_id, u16 qs_id)
302 {
303 struct hclge_nq_to_qs_link_cmd *map;
304 struct hclge_desc desc;
305
306 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NQ_TO_QS_LINK, false);
307
308 map = (struct hclge_nq_to_qs_link_cmd *)desc.data;
309
310 map->nq_id = cpu_to_le16(q_id);
311 map->qset_id = cpu_to_le16(qs_id | HCLGE_TM_Q_QS_LINK_VLD_MSK);
312
313 return hclge_cmd_send(&hdev->hw, &desc, 1);
314 }
315
hclge_tm_pg_weight_cfg(struct hclge_dev * hdev,u8 pg_id,u8 dwrr)316 static int hclge_tm_pg_weight_cfg(struct hclge_dev *hdev, u8 pg_id,
317 u8 dwrr)
318 {
319 struct hclge_pg_weight_cmd *weight;
320 struct hclge_desc desc;
321
322 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_WEIGHT, false);
323
324 weight = (struct hclge_pg_weight_cmd *)desc.data;
325
326 weight->pg_id = pg_id;
327 weight->dwrr = dwrr;
328
329 return hclge_cmd_send(&hdev->hw, &desc, 1);
330 }
331
hclge_tm_pri_weight_cfg(struct hclge_dev * hdev,u8 pri_id,u8 dwrr)332 static int hclge_tm_pri_weight_cfg(struct hclge_dev *hdev, u8 pri_id,
333 u8 dwrr)
334 {
335 struct hclge_priority_weight_cmd *weight;
336 struct hclge_desc desc;
337
338 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_WEIGHT, false);
339
340 weight = (struct hclge_priority_weight_cmd *)desc.data;
341
342 weight->pri_id = pri_id;
343 weight->dwrr = dwrr;
344
345 return hclge_cmd_send(&hdev->hw, &desc, 1);
346 }
347
hclge_tm_qs_weight_cfg(struct hclge_dev * hdev,u16 qs_id,u8 dwrr)348 static int hclge_tm_qs_weight_cfg(struct hclge_dev *hdev, u16 qs_id,
349 u8 dwrr)
350 {
351 struct hclge_qs_weight_cmd *weight;
352 struct hclge_desc desc;
353
354 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_WEIGHT, false);
355
356 weight = (struct hclge_qs_weight_cmd *)desc.data;
357
358 weight->qs_id = cpu_to_le16(qs_id);
359 weight->dwrr = dwrr;
360
361 return hclge_cmd_send(&hdev->hw, &desc, 1);
362 }
363
hclge_tm_get_shapping_para(u8 ir_b,u8 ir_u,u8 ir_s,u8 bs_b,u8 bs_s)364 static u32 hclge_tm_get_shapping_para(u8 ir_b, u8 ir_u, u8 ir_s,
365 u8 bs_b, u8 bs_s)
366 {
367 u32 shapping_para = 0;
368
369 hclge_tm_set_field(shapping_para, IR_B, ir_b);
370 hclge_tm_set_field(shapping_para, IR_U, ir_u);
371 hclge_tm_set_field(shapping_para, IR_S, ir_s);
372 hclge_tm_set_field(shapping_para, BS_B, bs_b);
373 hclge_tm_set_field(shapping_para, BS_S, bs_s);
374
375 return shapping_para;
376 }
377
hclge_tm_pg_shapping_cfg(struct hclge_dev * hdev,enum hclge_shap_bucket bucket,u8 pg_id,u32 shapping_para)378 static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev,
379 enum hclge_shap_bucket bucket, u8 pg_id,
380 u32 shapping_para)
381 {
382 struct hclge_pg_shapping_cmd *shap_cfg_cmd;
383 enum hclge_opcode_type opcode;
384 struct hclge_desc desc;
385
386 opcode = bucket ? HCLGE_OPC_TM_PG_P_SHAPPING :
387 HCLGE_OPC_TM_PG_C_SHAPPING;
388 hclge_cmd_setup_basic_desc(&desc, opcode, false);
389
390 shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data;
391
392 shap_cfg_cmd->pg_id = pg_id;
393
394 shap_cfg_cmd->pg_shapping_para = cpu_to_le32(shapping_para);
395
396 return hclge_cmd_send(&hdev->hw, &desc, 1);
397 }
398
hclge_tm_port_shaper_cfg(struct hclge_dev * hdev)399 static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev)
400 {
401 struct hclge_port_shapping_cmd *shap_cfg_cmd;
402 struct hclge_shaper_ir_para ir_para;
403 struct hclge_desc desc;
404 u32 shapping_para;
405 int ret;
406
407 ret = hclge_shaper_para_calc(hdev->hw.mac.speed, HCLGE_SHAPER_LVL_PORT,
408 &ir_para,
409 hdev->ae_dev->dev_specs.max_tm_rate);
410 if (ret)
411 return ret;
412
413 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PORT_SHAPPING, false);
414 shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data;
415
416 shapping_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u,
417 ir_para.ir_s,
418 HCLGE_SHAPER_BS_U_DEF,
419 HCLGE_SHAPER_BS_S_DEF);
420
421 shap_cfg_cmd->port_shapping_para = cpu_to_le32(shapping_para);
422
423 return hclge_cmd_send(&hdev->hw, &desc, 1);
424 }
425
hclge_tm_pri_shapping_cfg(struct hclge_dev * hdev,enum hclge_shap_bucket bucket,u8 pri_id,u32 shapping_para)426 static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev,
427 enum hclge_shap_bucket bucket, u8 pri_id,
428 u32 shapping_para)
429 {
430 struct hclge_pri_shapping_cmd *shap_cfg_cmd;
431 enum hclge_opcode_type opcode;
432 struct hclge_desc desc;
433
434 opcode = bucket ? HCLGE_OPC_TM_PRI_P_SHAPPING :
435 HCLGE_OPC_TM_PRI_C_SHAPPING;
436
437 hclge_cmd_setup_basic_desc(&desc, opcode, false);
438
439 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data;
440
441 shap_cfg_cmd->pri_id = pri_id;
442
443 shap_cfg_cmd->pri_shapping_para = cpu_to_le32(shapping_para);
444
445 return hclge_cmd_send(&hdev->hw, &desc, 1);
446 }
447
hclge_tm_pg_schd_mode_cfg(struct hclge_dev * hdev,u8 pg_id)448 static int hclge_tm_pg_schd_mode_cfg(struct hclge_dev *hdev, u8 pg_id)
449 {
450 struct hclge_desc desc;
451
452 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_SCH_MODE_CFG, false);
453
454 if (hdev->tm_info.pg_info[pg_id].pg_sch_mode == HCLGE_SCH_MODE_DWRR)
455 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
456 else
457 desc.data[1] = 0;
458
459 desc.data[0] = cpu_to_le32(pg_id);
460
461 return hclge_cmd_send(&hdev->hw, &desc, 1);
462 }
463
hclge_tm_pri_schd_mode_cfg(struct hclge_dev * hdev,u8 pri_id)464 static int hclge_tm_pri_schd_mode_cfg(struct hclge_dev *hdev, u8 pri_id)
465 {
466 struct hclge_desc desc;
467
468 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_SCH_MODE_CFG, false);
469
470 if (hdev->tm_info.tc_info[pri_id].tc_sch_mode == HCLGE_SCH_MODE_DWRR)
471 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
472 else
473 desc.data[1] = 0;
474
475 desc.data[0] = cpu_to_le32(pri_id);
476
477 return hclge_cmd_send(&hdev->hw, &desc, 1);
478 }
479
hclge_tm_qs_schd_mode_cfg(struct hclge_dev * hdev,u16 qs_id,u8 mode)480 static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id, u8 mode)
481 {
482 struct hclge_desc desc;
483
484 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, false);
485
486 if (mode == HCLGE_SCH_MODE_DWRR)
487 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
488 else
489 desc.data[1] = 0;
490
491 desc.data[0] = cpu_to_le32(qs_id);
492
493 return hclge_cmd_send(&hdev->hw, &desc, 1);
494 }
495
hclge_tm_qs_bp_cfg(struct hclge_dev * hdev,u8 tc,u8 grp_id,u32 bit_map)496 static int hclge_tm_qs_bp_cfg(struct hclge_dev *hdev, u8 tc, u8 grp_id,
497 u32 bit_map)
498 {
499 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd;
500 struct hclge_desc desc;
501
502 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_BP_TO_QSET_MAPPING,
503 false);
504
505 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data;
506
507 bp_to_qs_map_cmd->tc_id = tc;
508 bp_to_qs_map_cmd->qs_group_id = grp_id;
509 bp_to_qs_map_cmd->qs_bit_map = cpu_to_le32(bit_map);
510
511 return hclge_cmd_send(&hdev->hw, &desc, 1);
512 }
513
hclge_tm_qs_shaper_cfg(struct hclge_vport * vport,int max_tx_rate)514 int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate)
515 {
516 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
517 struct hclge_qs_shapping_cmd *shap_cfg_cmd;
518 struct hclge_shaper_ir_para ir_para;
519 struct hclge_dev *hdev = vport->back;
520 struct hclge_desc desc;
521 u32 shaper_para;
522 int ret, i;
523
524 if (!max_tx_rate)
525 max_tx_rate = hdev->ae_dev->dev_specs.max_tm_rate;
526
527 ret = hclge_shaper_para_calc(max_tx_rate, HCLGE_SHAPER_LVL_QSET,
528 &ir_para,
529 hdev->ae_dev->dev_specs.max_tm_rate);
530 if (ret)
531 return ret;
532
533 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u,
534 ir_para.ir_s,
535 HCLGE_SHAPER_BS_U_DEF,
536 HCLGE_SHAPER_BS_S_DEF);
537
538 for (i = 0; i < kinfo->num_tc; i++) {
539 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QCN_SHAPPING_CFG,
540 false);
541
542 shap_cfg_cmd = (struct hclge_qs_shapping_cmd *)desc.data;
543 shap_cfg_cmd->qs_id = cpu_to_le16(vport->qs_offset + i);
544 shap_cfg_cmd->qs_shapping_para = cpu_to_le32(shaper_para);
545
546 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
547 if (ret) {
548 dev_err(&hdev->pdev->dev,
549 "vf%u, qs%u failed to set tx_rate:%d, ret=%d\n",
550 vport->vport_id, shap_cfg_cmd->qs_id,
551 max_tx_rate, ret);
552 return ret;
553 }
554 }
555
556 return 0;
557 }
558
hclge_tm_vport_tc_info_update(struct hclge_vport * vport)559 static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport)
560 {
561 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
562 struct hclge_dev *hdev = vport->back;
563 u16 max_rss_size;
564 u8 i;
565
566 /* TC configuration is shared by PF/VF in one port, only allow
567 * one tc for VF for simplicity. VF's vport_id is non zero.
568 */
569 kinfo->num_tc = vport->vport_id ? 1 :
570 min_t(u16, vport->alloc_tqps, hdev->tm_info.num_tc);
571 vport->qs_offset = (vport->vport_id ? HNAE3_MAX_TC : 0) +
572 (vport->vport_id ? (vport->vport_id - 1) : 0);
573
574 max_rss_size = min_t(u16, hdev->rss_size_max,
575 vport->alloc_tqps / kinfo->num_tc);
576
577 /* Set to user value, no larger than max_rss_size. */
578 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size &&
579 kinfo->req_rss_size <= max_rss_size) {
580 dev_info(&hdev->pdev->dev, "rss changes from %u to %u\n",
581 kinfo->rss_size, kinfo->req_rss_size);
582 kinfo->rss_size = kinfo->req_rss_size;
583 } else if (kinfo->rss_size > max_rss_size ||
584 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) {
585 /* if user not set rss, the rss_size should compare with the
586 * valid msi numbers to ensure one to one map between tqp and
587 * irq as default.
588 */
589 if (!kinfo->req_rss_size)
590 max_rss_size = min_t(u16, max_rss_size,
591 (hdev->num_nic_msi - 1) /
592 kinfo->num_tc);
593
594 /* Set to the maximum specification value (max_rss_size). */
595 kinfo->rss_size = max_rss_size;
596 }
597
598 kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size;
599 vport->dwrr = 100; /* 100 percent as init */
600 vport->alloc_rss_size = kinfo->rss_size;
601 vport->bw_limit = hdev->tm_info.pg_info[0].bw_limit;
602
603 for (i = 0; i < HNAE3_MAX_TC; i++) {
604 if (hdev->hw_tc_map & BIT(i) && i < kinfo->num_tc) {
605 kinfo->tc_info[i].enable = true;
606 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
607 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
608 kinfo->tc_info[i].tc = i;
609 } else {
610 /* Set to default queue if TC is disable */
611 kinfo->tc_info[i].enable = false;
612 kinfo->tc_info[i].tqp_offset = 0;
613 kinfo->tc_info[i].tqp_count = 1;
614 kinfo->tc_info[i].tc = 0;
615 }
616 }
617
618 memcpy(kinfo->prio_tc, hdev->tm_info.prio_tc,
619 sizeof_field(struct hnae3_knic_private_info, prio_tc));
620 }
621
hclge_tm_vport_info_update(struct hclge_dev * hdev)622 static void hclge_tm_vport_info_update(struct hclge_dev *hdev)
623 {
624 struct hclge_vport *vport = hdev->vport;
625 u32 i;
626
627 for (i = 0; i < hdev->num_alloc_vport; i++) {
628 hclge_tm_vport_tc_info_update(vport);
629
630 vport++;
631 }
632 }
633
hclge_tm_tc_info_init(struct hclge_dev * hdev)634 static void hclge_tm_tc_info_init(struct hclge_dev *hdev)
635 {
636 u8 i;
637
638 for (i = 0; i < hdev->tm_info.num_tc; i++) {
639 hdev->tm_info.tc_info[i].tc_id = i;
640 hdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR;
641 hdev->tm_info.tc_info[i].pgid = 0;
642 hdev->tm_info.tc_info[i].bw_limit =
643 hdev->tm_info.pg_info[0].bw_limit;
644 }
645
646 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
647 hdev->tm_info.prio_tc[i] =
648 (i >= hdev->tm_info.num_tc) ? 0 : i;
649 }
650
hclge_tm_pg_info_init(struct hclge_dev * hdev)651 static void hclge_tm_pg_info_init(struct hclge_dev *hdev)
652 {
653 #define BW_PERCENT 100
654 #define DEFAULT_BW_WEIGHT 1
655
656 u8 i;
657
658 for (i = 0; i < hdev->tm_info.num_pg; i++) {
659 int k;
660
661 hdev->tm_info.pg_dwrr[i] = i ? 0 : BW_PERCENT;
662
663 hdev->tm_info.pg_info[i].pg_id = i;
664 hdev->tm_info.pg_info[i].pg_sch_mode = HCLGE_SCH_MODE_DWRR;
665
666 hdev->tm_info.pg_info[i].bw_limit =
667 hdev->ae_dev->dev_specs.max_tm_rate;
668
669 if (i != 0)
670 continue;
671
672 hdev->tm_info.pg_info[i].tc_bit_map = hdev->hw_tc_map;
673 for (k = 0; k < hdev->tm_info.num_tc; k++)
674 hdev->tm_info.pg_info[i].tc_dwrr[k] = BW_PERCENT;
675 for (; k < HNAE3_MAX_TC; k++)
676 hdev->tm_info.pg_info[i].tc_dwrr[k] = DEFAULT_BW_WEIGHT;
677 }
678 }
679
hclge_update_fc_mode_by_dcb_flag(struct hclge_dev * hdev)680 static void hclge_update_fc_mode_by_dcb_flag(struct hclge_dev *hdev)
681 {
682 if (hdev->tm_info.num_tc == 1 && !hdev->tm_info.pfc_en) {
683 if (hdev->fc_mode_last_time == HCLGE_FC_PFC)
684 dev_warn(&hdev->pdev->dev,
685 "Only 1 tc used, but last mode is FC_PFC\n");
686
687 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
688 } else if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) {
689 /* fc_mode_last_time record the last fc_mode when
690 * DCB is enabled, so that fc_mode can be set to
691 * the correct value when DCB is disabled.
692 */
693 hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
694 hdev->tm_info.fc_mode = HCLGE_FC_PFC;
695 }
696 }
697
hclge_update_fc_mode(struct hclge_dev * hdev)698 static void hclge_update_fc_mode(struct hclge_dev *hdev)
699 {
700 if (!hdev->tm_info.pfc_en) {
701 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
702 return;
703 }
704
705 if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) {
706 hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
707 hdev->tm_info.fc_mode = HCLGE_FC_PFC;
708 }
709 }
710
hclge_tm_pfc_info_update(struct hclge_dev * hdev)711 void hclge_tm_pfc_info_update(struct hclge_dev *hdev)
712 {
713 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
714 hclge_update_fc_mode(hdev);
715 else
716 hclge_update_fc_mode_by_dcb_flag(hdev);
717 }
718
hclge_tm_schd_info_init(struct hclge_dev * hdev)719 static void hclge_tm_schd_info_init(struct hclge_dev *hdev)
720 {
721 hclge_tm_pg_info_init(hdev);
722
723 hclge_tm_tc_info_init(hdev);
724
725 hclge_tm_vport_info_update(hdev);
726
727 hclge_tm_pfc_info_update(hdev);
728 }
729
hclge_tm_pg_to_pri_map(struct hclge_dev * hdev)730 static int hclge_tm_pg_to_pri_map(struct hclge_dev *hdev)
731 {
732 int ret;
733 u32 i;
734
735 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
736 return 0;
737
738 for (i = 0; i < hdev->tm_info.num_pg; i++) {
739 /* Cfg mapping */
740 ret = hclge_tm_pg_to_pri_map_cfg(
741 hdev, i, hdev->tm_info.pg_info[i].tc_bit_map);
742 if (ret)
743 return ret;
744 }
745
746 return 0;
747 }
748
hclge_tm_pg_shaper_cfg(struct hclge_dev * hdev)749 static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev)
750 {
751 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
752 struct hclge_shaper_ir_para ir_para;
753 u32 shaper_para;
754 int ret;
755 u32 i;
756
757 /* Cfg pg schd */
758 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
759 return 0;
760
761 /* Pg to pri */
762 for (i = 0; i < hdev->tm_info.num_pg; i++) {
763 /* Calc shaper para */
764 ret = hclge_shaper_para_calc(hdev->tm_info.pg_info[i].bw_limit,
765 HCLGE_SHAPER_LVL_PG,
766 &ir_para, max_tm_rate);
767 if (ret)
768 return ret;
769
770 shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
771 HCLGE_SHAPER_BS_U_DEF,
772 HCLGE_SHAPER_BS_S_DEF);
773 ret = hclge_tm_pg_shapping_cfg(hdev,
774 HCLGE_TM_SHAP_C_BUCKET, i,
775 shaper_para);
776 if (ret)
777 return ret;
778
779 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b,
780 ir_para.ir_u,
781 ir_para.ir_s,
782 HCLGE_SHAPER_BS_U_DEF,
783 HCLGE_SHAPER_BS_S_DEF);
784 ret = hclge_tm_pg_shapping_cfg(hdev,
785 HCLGE_TM_SHAP_P_BUCKET, i,
786 shaper_para);
787 if (ret)
788 return ret;
789 }
790
791 return 0;
792 }
793
hclge_tm_pg_dwrr_cfg(struct hclge_dev * hdev)794 static int hclge_tm_pg_dwrr_cfg(struct hclge_dev *hdev)
795 {
796 int ret;
797 u32 i;
798
799 /* cfg pg schd */
800 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
801 return 0;
802
803 /* pg to prio */
804 for (i = 0; i < hdev->tm_info.num_pg; i++) {
805 /* Cfg dwrr */
806 ret = hclge_tm_pg_weight_cfg(hdev, i, hdev->tm_info.pg_dwrr[i]);
807 if (ret)
808 return ret;
809 }
810
811 return 0;
812 }
813
hclge_vport_q_to_qs_map(struct hclge_dev * hdev,struct hclge_vport * vport)814 static int hclge_vport_q_to_qs_map(struct hclge_dev *hdev,
815 struct hclge_vport *vport)
816 {
817 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
818 struct hnae3_queue **tqp = kinfo->tqp;
819 struct hnae3_tc_info *v_tc_info;
820 u32 i, j;
821 int ret;
822
823 for (i = 0; i < kinfo->num_tc; i++) {
824 v_tc_info = &kinfo->tc_info[i];
825 for (j = 0; j < v_tc_info->tqp_count; j++) {
826 struct hnae3_queue *q = tqp[v_tc_info->tqp_offset + j];
827
828 ret = hclge_tm_q_to_qs_map_cfg(hdev,
829 hclge_get_queue_id(q),
830 vport->qs_offset + i);
831 if (ret)
832 return ret;
833 }
834 }
835
836 return 0;
837 }
838
hclge_tm_pri_q_qs_cfg(struct hclge_dev * hdev)839 static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev)
840 {
841 struct hclge_vport *vport = hdev->vport;
842 int ret;
843 u32 i, k;
844
845 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
846 /* Cfg qs -> pri mapping, one by one mapping */
847 for (k = 0; k < hdev->num_alloc_vport; k++) {
848 struct hnae3_knic_private_info *kinfo =
849 &vport[k].nic.kinfo;
850
851 for (i = 0; i < kinfo->num_tc; i++) {
852 ret = hclge_tm_qs_to_pri_map_cfg(
853 hdev, vport[k].qs_offset + i, i);
854 if (ret)
855 return ret;
856 }
857 }
858 } else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) {
859 /* Cfg qs -> pri mapping, qs = tc, pri = vf, 8 qs -> 1 pri */
860 for (k = 0; k < hdev->num_alloc_vport; k++)
861 for (i = 0; i < HNAE3_MAX_TC; i++) {
862 ret = hclge_tm_qs_to_pri_map_cfg(
863 hdev, vport[k].qs_offset + i, k);
864 if (ret)
865 return ret;
866 }
867 } else {
868 return -EINVAL;
869 }
870
871 /* Cfg q -> qs mapping */
872 for (i = 0; i < hdev->num_alloc_vport; i++) {
873 ret = hclge_vport_q_to_qs_map(hdev, vport);
874 if (ret)
875 return ret;
876
877 vport++;
878 }
879
880 return 0;
881 }
882
hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev * hdev)883 static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev)
884 {
885 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
886 struct hclge_shaper_ir_para ir_para;
887 u32 shaper_para;
888 int ret;
889 u32 i;
890
891 for (i = 0; i < hdev->tm_info.num_tc; i++) {
892 ret = hclge_shaper_para_calc(hdev->tm_info.tc_info[i].bw_limit,
893 HCLGE_SHAPER_LVL_PRI,
894 &ir_para, max_tm_rate);
895 if (ret)
896 return ret;
897
898 shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
899 HCLGE_SHAPER_BS_U_DEF,
900 HCLGE_SHAPER_BS_S_DEF);
901 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, i,
902 shaper_para);
903 if (ret)
904 return ret;
905
906 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b,
907 ir_para.ir_u,
908 ir_para.ir_s,
909 HCLGE_SHAPER_BS_U_DEF,
910 HCLGE_SHAPER_BS_S_DEF);
911 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, i,
912 shaper_para);
913 if (ret)
914 return ret;
915 }
916
917 return 0;
918 }
919
hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport * vport)920 static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport)
921 {
922 struct hclge_dev *hdev = vport->back;
923 struct hclge_shaper_ir_para ir_para;
924 u32 shaper_para;
925 int ret;
926
927 ret = hclge_shaper_para_calc(vport->bw_limit, HCLGE_SHAPER_LVL_VF,
928 &ir_para,
929 hdev->ae_dev->dev_specs.max_tm_rate);
930 if (ret)
931 return ret;
932
933 shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
934 HCLGE_SHAPER_BS_U_DEF,
935 HCLGE_SHAPER_BS_S_DEF);
936 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET,
937 vport->vport_id, shaper_para);
938 if (ret)
939 return ret;
940
941 shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u,
942 ir_para.ir_s,
943 HCLGE_SHAPER_BS_U_DEF,
944 HCLGE_SHAPER_BS_S_DEF);
945 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET,
946 vport->vport_id, shaper_para);
947 if (ret)
948 return ret;
949
950 return 0;
951 }
952
hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport * vport)953 static int hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport *vport)
954 {
955 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
956 struct hclge_dev *hdev = vport->back;
957 u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
958 struct hclge_shaper_ir_para ir_para;
959 u32 i;
960 int ret;
961
962 for (i = 0; i < kinfo->num_tc; i++) {
963 ret = hclge_shaper_para_calc(hdev->tm_info.tc_info[i].bw_limit,
964 HCLGE_SHAPER_LVL_QSET,
965 &ir_para, max_tm_rate);
966 if (ret)
967 return ret;
968 }
969
970 return 0;
971 }
972
hclge_tm_pri_vnet_base_shaper_cfg(struct hclge_dev * hdev)973 static int hclge_tm_pri_vnet_base_shaper_cfg(struct hclge_dev *hdev)
974 {
975 struct hclge_vport *vport = hdev->vport;
976 int ret;
977 u32 i;
978
979 /* Need config vport shaper */
980 for (i = 0; i < hdev->num_alloc_vport; i++) {
981 ret = hclge_tm_pri_vnet_base_shaper_pri_cfg(vport);
982 if (ret)
983 return ret;
984
985 ret = hclge_tm_pri_vnet_base_shaper_qs_cfg(vport);
986 if (ret)
987 return ret;
988
989 vport++;
990 }
991
992 return 0;
993 }
994
hclge_tm_pri_shaper_cfg(struct hclge_dev * hdev)995 static int hclge_tm_pri_shaper_cfg(struct hclge_dev *hdev)
996 {
997 int ret;
998
999 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
1000 ret = hclge_tm_pri_tc_base_shaper_cfg(hdev);
1001 if (ret)
1002 return ret;
1003 } else {
1004 ret = hclge_tm_pri_vnet_base_shaper_cfg(hdev);
1005 if (ret)
1006 return ret;
1007 }
1008
1009 return 0;
1010 }
1011
hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev * hdev)1012 static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)
1013 {
1014 struct hclge_vport *vport = hdev->vport;
1015 struct hclge_pg_info *pg_info;
1016 u8 dwrr;
1017 int ret;
1018 u32 i, k;
1019
1020 for (i = 0; i < hdev->tm_info.num_tc; i++) {
1021 pg_info =
1022 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
1023 dwrr = pg_info->tc_dwrr[i];
1024
1025 ret = hclge_tm_pri_weight_cfg(hdev, i, dwrr);
1026 if (ret)
1027 return ret;
1028
1029 for (k = 0; k < hdev->num_alloc_vport; k++) {
1030 ret = hclge_tm_qs_weight_cfg(
1031 hdev, vport[k].qs_offset + i,
1032 vport[k].dwrr);
1033 if (ret)
1034 return ret;
1035 }
1036 }
1037
1038 return 0;
1039 }
1040
hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev * hdev)1041 static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev)
1042 {
1043 #define DEFAULT_TC_OFFSET 14
1044
1045 struct hclge_ets_tc_weight_cmd *ets_weight;
1046 struct hclge_desc desc;
1047 unsigned int i;
1048
1049 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, false);
1050 ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data;
1051
1052 for (i = 0; i < HNAE3_MAX_TC; i++) {
1053 struct hclge_pg_info *pg_info;
1054
1055 pg_info = &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
1056 ets_weight->tc_weight[i] = pg_info->tc_dwrr[i];
1057 }
1058
1059 ets_weight->weight_offset = DEFAULT_TC_OFFSET;
1060
1061 return hclge_cmd_send(&hdev->hw, &desc, 1);
1062 }
1063
hclge_tm_pri_vnet_base_dwrr_pri_cfg(struct hclge_vport * vport)1064 static int hclge_tm_pri_vnet_base_dwrr_pri_cfg(struct hclge_vport *vport)
1065 {
1066 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1067 struct hclge_dev *hdev = vport->back;
1068 int ret;
1069 u8 i;
1070
1071 /* Vf dwrr */
1072 ret = hclge_tm_pri_weight_cfg(hdev, vport->vport_id, vport->dwrr);
1073 if (ret)
1074 return ret;
1075
1076 /* Qset dwrr */
1077 for (i = 0; i < kinfo->num_tc; i++) {
1078 ret = hclge_tm_qs_weight_cfg(
1079 hdev, vport->qs_offset + i,
1080 hdev->tm_info.pg_info[0].tc_dwrr[i]);
1081 if (ret)
1082 return ret;
1083 }
1084
1085 return 0;
1086 }
1087
hclge_tm_pri_vnet_base_dwrr_cfg(struct hclge_dev * hdev)1088 static int hclge_tm_pri_vnet_base_dwrr_cfg(struct hclge_dev *hdev)
1089 {
1090 struct hclge_vport *vport = hdev->vport;
1091 int ret;
1092 u32 i;
1093
1094 for (i = 0; i < hdev->num_alloc_vport; i++) {
1095 ret = hclge_tm_pri_vnet_base_dwrr_pri_cfg(vport);
1096 if (ret)
1097 return ret;
1098
1099 vport++;
1100 }
1101
1102 return 0;
1103 }
1104
hclge_tm_pri_dwrr_cfg(struct hclge_dev * hdev)1105 static int hclge_tm_pri_dwrr_cfg(struct hclge_dev *hdev)
1106 {
1107 int ret;
1108
1109 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
1110 ret = hclge_tm_pri_tc_base_dwrr_cfg(hdev);
1111 if (ret)
1112 return ret;
1113
1114 if (!hnae3_dev_dcb_supported(hdev))
1115 return 0;
1116
1117 ret = hclge_tm_ets_tc_dwrr_cfg(hdev);
1118 if (ret == -EOPNOTSUPP) {
1119 dev_warn(&hdev->pdev->dev,
1120 "fw %08x does't support ets tc weight cmd\n",
1121 hdev->fw_version);
1122 ret = 0;
1123 }
1124
1125 return ret;
1126 } else {
1127 ret = hclge_tm_pri_vnet_base_dwrr_cfg(hdev);
1128 if (ret)
1129 return ret;
1130 }
1131
1132 return 0;
1133 }
1134
hclge_tm_map_cfg(struct hclge_dev * hdev)1135 static int hclge_tm_map_cfg(struct hclge_dev *hdev)
1136 {
1137 int ret;
1138
1139 ret = hclge_up_to_tc_map(hdev);
1140 if (ret)
1141 return ret;
1142
1143 ret = hclge_tm_pg_to_pri_map(hdev);
1144 if (ret)
1145 return ret;
1146
1147 return hclge_tm_pri_q_qs_cfg(hdev);
1148 }
1149
hclge_tm_shaper_cfg(struct hclge_dev * hdev)1150 static int hclge_tm_shaper_cfg(struct hclge_dev *hdev)
1151 {
1152 int ret;
1153
1154 ret = hclge_tm_port_shaper_cfg(hdev);
1155 if (ret)
1156 return ret;
1157
1158 ret = hclge_tm_pg_shaper_cfg(hdev);
1159 if (ret)
1160 return ret;
1161
1162 return hclge_tm_pri_shaper_cfg(hdev);
1163 }
1164
hclge_tm_dwrr_cfg(struct hclge_dev * hdev)1165 int hclge_tm_dwrr_cfg(struct hclge_dev *hdev)
1166 {
1167 int ret;
1168
1169 ret = hclge_tm_pg_dwrr_cfg(hdev);
1170 if (ret)
1171 return ret;
1172
1173 return hclge_tm_pri_dwrr_cfg(hdev);
1174 }
1175
hclge_tm_lvl2_schd_mode_cfg(struct hclge_dev * hdev)1176 static int hclge_tm_lvl2_schd_mode_cfg(struct hclge_dev *hdev)
1177 {
1178 int ret;
1179 u8 i;
1180
1181 /* Only being config on TC-Based scheduler mode */
1182 if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE)
1183 return 0;
1184
1185 for (i = 0; i < hdev->tm_info.num_pg; i++) {
1186 ret = hclge_tm_pg_schd_mode_cfg(hdev, i);
1187 if (ret)
1188 return ret;
1189 }
1190
1191 return 0;
1192 }
1193
hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport * vport)1194 static int hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport *vport)
1195 {
1196 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1197 struct hclge_dev *hdev = vport->back;
1198 int ret;
1199 u8 i;
1200
1201 if (vport->vport_id >= HNAE3_MAX_TC)
1202 return -EINVAL;
1203
1204 ret = hclge_tm_pri_schd_mode_cfg(hdev, vport->vport_id);
1205 if (ret)
1206 return ret;
1207
1208 for (i = 0; i < kinfo->num_tc; i++) {
1209 u8 sch_mode = hdev->tm_info.tc_info[i].tc_sch_mode;
1210
1211 ret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i,
1212 sch_mode);
1213 if (ret)
1214 return ret;
1215 }
1216
1217 return 0;
1218 }
1219
hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev * hdev)1220 static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev)
1221 {
1222 struct hclge_vport *vport = hdev->vport;
1223 int ret;
1224 u8 i, k;
1225
1226 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
1227 for (i = 0; i < hdev->tm_info.num_tc; i++) {
1228 ret = hclge_tm_pri_schd_mode_cfg(hdev, i);
1229 if (ret)
1230 return ret;
1231
1232 for (k = 0; k < hdev->num_alloc_vport; k++) {
1233 ret = hclge_tm_qs_schd_mode_cfg(
1234 hdev, vport[k].qs_offset + i,
1235 HCLGE_SCH_MODE_DWRR);
1236 if (ret)
1237 return ret;
1238 }
1239 }
1240 } else {
1241 for (i = 0; i < hdev->num_alloc_vport; i++) {
1242 ret = hclge_tm_schd_mode_vnet_base_cfg(vport);
1243 if (ret)
1244 return ret;
1245
1246 vport++;
1247 }
1248 }
1249
1250 return 0;
1251 }
1252
hclge_tm_schd_mode_hw(struct hclge_dev * hdev)1253 static int hclge_tm_schd_mode_hw(struct hclge_dev *hdev)
1254 {
1255 int ret;
1256
1257 ret = hclge_tm_lvl2_schd_mode_cfg(hdev);
1258 if (ret)
1259 return ret;
1260
1261 return hclge_tm_lvl34_schd_mode_cfg(hdev);
1262 }
1263
hclge_tm_schd_setup_hw(struct hclge_dev * hdev)1264 int hclge_tm_schd_setup_hw(struct hclge_dev *hdev)
1265 {
1266 int ret;
1267
1268 /* Cfg tm mapping */
1269 ret = hclge_tm_map_cfg(hdev);
1270 if (ret)
1271 return ret;
1272
1273 /* Cfg tm shaper */
1274 ret = hclge_tm_shaper_cfg(hdev);
1275 if (ret)
1276 return ret;
1277
1278 /* Cfg dwrr */
1279 ret = hclge_tm_dwrr_cfg(hdev);
1280 if (ret)
1281 return ret;
1282
1283 /* Cfg schd mode for each level schd */
1284 return hclge_tm_schd_mode_hw(hdev);
1285 }
1286
hclge_pause_param_setup_hw(struct hclge_dev * hdev)1287 static int hclge_pause_param_setup_hw(struct hclge_dev *hdev)
1288 {
1289 struct hclge_mac *mac = &hdev->hw.mac;
1290
1291 return hclge_pause_param_cfg(hdev, mac->mac_addr,
1292 HCLGE_DEFAULT_PAUSE_TRANS_GAP,
1293 HCLGE_DEFAULT_PAUSE_TRANS_TIME);
1294 }
1295
hclge_pfc_setup_hw(struct hclge_dev * hdev)1296 static int hclge_pfc_setup_hw(struct hclge_dev *hdev)
1297 {
1298 u8 enable_bitmap = 0;
1299
1300 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
1301 enable_bitmap = HCLGE_TX_MAC_PAUSE_EN_MSK |
1302 HCLGE_RX_MAC_PAUSE_EN_MSK;
1303
1304 return hclge_pfc_pause_en_cfg(hdev, enable_bitmap,
1305 hdev->tm_info.pfc_en);
1306 }
1307
1308 /* Each Tc has a 1024 queue sets to backpress, it divides to
1309 * 32 group, each group contains 32 queue sets, which can be
1310 * represented by u32 bitmap.
1311 */
hclge_bp_setup_hw(struct hclge_dev * hdev,u8 tc)1312 static int hclge_bp_setup_hw(struct hclge_dev *hdev, u8 tc)
1313 {
1314 int i;
1315
1316 for (i = 0; i < HCLGE_BP_GRP_NUM; i++) {
1317 u32 qs_bitmap = 0;
1318 int k, ret;
1319
1320 for (k = 0; k < hdev->num_alloc_vport; k++) {
1321 struct hclge_vport *vport = &hdev->vport[k];
1322 u16 qs_id = vport->qs_offset + tc;
1323 u8 grp, sub_grp;
1324
1325 grp = hnae3_get_field(qs_id, HCLGE_BP_GRP_ID_M,
1326 HCLGE_BP_GRP_ID_S);
1327 sub_grp = hnae3_get_field(qs_id, HCLGE_BP_SUB_GRP_ID_M,
1328 HCLGE_BP_SUB_GRP_ID_S);
1329 if (i == grp)
1330 qs_bitmap |= (1 << sub_grp);
1331 }
1332
1333 ret = hclge_tm_qs_bp_cfg(hdev, tc, i, qs_bitmap);
1334 if (ret)
1335 return ret;
1336 }
1337
1338 return 0;
1339 }
1340
hclge_mac_pause_setup_hw(struct hclge_dev * hdev)1341 static int hclge_mac_pause_setup_hw(struct hclge_dev *hdev)
1342 {
1343 bool tx_en, rx_en;
1344
1345 switch (hdev->tm_info.fc_mode) {
1346 case HCLGE_FC_NONE:
1347 tx_en = false;
1348 rx_en = false;
1349 break;
1350 case HCLGE_FC_RX_PAUSE:
1351 tx_en = false;
1352 rx_en = true;
1353 break;
1354 case HCLGE_FC_TX_PAUSE:
1355 tx_en = true;
1356 rx_en = false;
1357 break;
1358 case HCLGE_FC_FULL:
1359 tx_en = true;
1360 rx_en = true;
1361 break;
1362 case HCLGE_FC_PFC:
1363 tx_en = false;
1364 rx_en = false;
1365 break;
1366 default:
1367 tx_en = true;
1368 rx_en = true;
1369 }
1370
1371 return hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
1372 }
1373
hclge_tm_bp_setup(struct hclge_dev * hdev)1374 static int hclge_tm_bp_setup(struct hclge_dev *hdev)
1375 {
1376 int ret;
1377 int i;
1378
1379 for (i = 0; i < hdev->tm_info.num_tc; i++) {
1380 ret = hclge_bp_setup_hw(hdev, i);
1381 if (ret)
1382 return ret;
1383 }
1384
1385 return 0;
1386 }
1387
hclge_pause_setup_hw(struct hclge_dev * hdev,bool init)1388 int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init)
1389 {
1390 int ret;
1391
1392 ret = hclge_pause_param_setup_hw(hdev);
1393 if (ret)
1394 return ret;
1395
1396 ret = hclge_mac_pause_setup_hw(hdev);
1397 if (ret)
1398 return ret;
1399
1400 /* Only DCB-supported dev supports qset back pressure and pfc cmd */
1401 if (!hnae3_dev_dcb_supported(hdev))
1402 return 0;
1403
1404 /* GE MAC does not support PFC, when driver is initializing and MAC
1405 * is in GE Mode, ignore the error here, otherwise initialization
1406 * will fail.
1407 */
1408 ret = hclge_pfc_setup_hw(hdev);
1409 if (init && ret == -EOPNOTSUPP)
1410 dev_warn(&hdev->pdev->dev, "GE MAC does not support pfc\n");
1411 else if (ret) {
1412 dev_err(&hdev->pdev->dev, "config pfc failed! ret = %d\n",
1413 ret);
1414 return ret;
1415 }
1416
1417 return hclge_tm_bp_setup(hdev);
1418 }
1419
hclge_tm_prio_tc_info_update(struct hclge_dev * hdev,u8 * prio_tc)1420 void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc)
1421 {
1422 struct hclge_vport *vport = hdev->vport;
1423 struct hnae3_knic_private_info *kinfo;
1424 u32 i, k;
1425
1426 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
1427 hdev->tm_info.prio_tc[i] = prio_tc[i];
1428
1429 for (k = 0; k < hdev->num_alloc_vport; k++) {
1430 kinfo = &vport[k].nic.kinfo;
1431 kinfo->prio_tc[i] = prio_tc[i];
1432 }
1433 }
1434 }
1435
hclge_tm_schd_info_update(struct hclge_dev * hdev,u8 num_tc)1436 void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc)
1437 {
1438 u8 bit_map = 0;
1439 u8 i;
1440
1441 hdev->tm_info.num_tc = num_tc;
1442
1443 for (i = 0; i < hdev->tm_info.num_tc; i++)
1444 bit_map |= BIT(i);
1445
1446 if (!bit_map) {
1447 bit_map = 1;
1448 hdev->tm_info.num_tc = 1;
1449 }
1450
1451 hdev->hw_tc_map = bit_map;
1452
1453 hclge_tm_schd_info_init(hdev);
1454 }
1455
hclge_tm_init_hw(struct hclge_dev * hdev,bool init)1456 int hclge_tm_init_hw(struct hclge_dev *hdev, bool init)
1457 {
1458 int ret;
1459
1460 if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) &&
1461 (hdev->tx_sch_mode != HCLGE_FLAG_VNET_BASE_SCH_MODE))
1462 return -ENOTSUPP;
1463
1464 ret = hclge_tm_schd_setup_hw(hdev);
1465 if (ret)
1466 return ret;
1467
1468 ret = hclge_pause_setup_hw(hdev, init);
1469 if (ret)
1470 return ret;
1471
1472 return 0;
1473 }
1474
hclge_tm_schd_init(struct hclge_dev * hdev)1475 int hclge_tm_schd_init(struct hclge_dev *hdev)
1476 {
1477 /* fc_mode is HCLGE_FC_FULL on reset */
1478 hdev->tm_info.fc_mode = HCLGE_FC_FULL;
1479 hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
1480
1481 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE &&
1482 hdev->tm_info.num_pg != 1)
1483 return -EINVAL;
1484
1485 hclge_tm_schd_info_init(hdev);
1486
1487 return hclge_tm_init_hw(hdev, true);
1488 }
1489
hclge_tm_vport_map_update(struct hclge_dev * hdev)1490 int hclge_tm_vport_map_update(struct hclge_dev *hdev)
1491 {
1492 struct hclge_vport *vport = hdev->vport;
1493 int ret;
1494
1495 hclge_tm_vport_tc_info_update(vport);
1496
1497 ret = hclge_vport_q_to_qs_map(hdev, vport);
1498 if (ret)
1499 return ret;
1500
1501 if (hdev->tm_info.num_tc == 1 && !hdev->tm_info.pfc_en)
1502 return 0;
1503
1504 return hclge_tm_bp_setup(hdev);
1505 }
1506