1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef _ASM_X86_INSN_H
3 #define _ASM_X86_INSN_H
4 /*
5 * x86 instruction analysis
6 *
7 * Copyright (C) IBM Corporation, 2009
8 */
9
10 /* insn_attr_t is defined in inat.h */
11 #include <asm/inat.h> /* __ignore_sync_check__ */
12
13 struct insn_field {
14 union {
15 insn_value_t value;
16 insn_byte_t bytes[4];
17 };
18 /* !0 if we've run insn_get_xxx() for this field */
19 unsigned char got;
20 unsigned char nbytes;
21 };
22
23 struct insn {
24 struct insn_field prefixes; /*
25 * Prefixes
26 * prefixes.bytes[3]: last prefix
27 */
28 struct insn_field rex_prefix; /* REX prefix */
29 struct insn_field vex_prefix; /* VEX prefix */
30 struct insn_field opcode; /*
31 * opcode.bytes[0]: opcode1
32 * opcode.bytes[1]: opcode2
33 * opcode.bytes[2]: opcode3
34 */
35 struct insn_field modrm;
36 struct insn_field sib;
37 struct insn_field displacement;
38 union {
39 struct insn_field immediate;
40 struct insn_field moffset1; /* for 64bit MOV */
41 struct insn_field immediate1; /* for 64bit imm or off16/32 */
42 };
43 union {
44 struct insn_field moffset2; /* for 64bit MOV */
45 struct insn_field immediate2; /* for 64bit imm or seg16 */
46 };
47
48 int emulate_prefix_size;
49 insn_attr_t attr;
50 unsigned char opnd_bytes;
51 unsigned char addr_bytes;
52 unsigned char length;
53 unsigned char x86_64;
54
55 const insn_byte_t *kaddr; /* kernel address of insn to analyze */
56 const insn_byte_t *end_kaddr; /* kernel address of last insn in buffer */
57 const insn_byte_t *next_byte;
58 };
59
60 #define MAX_INSN_SIZE 15
61
62 #define X86_MODRM_MOD(modrm) (((modrm) & 0xc0) >> 6)
63 #define X86_MODRM_REG(modrm) (((modrm) & 0x38) >> 3)
64 #define X86_MODRM_RM(modrm) ((modrm) & 0x07)
65
66 #define X86_SIB_SCALE(sib) (((sib) & 0xc0) >> 6)
67 #define X86_SIB_INDEX(sib) (((sib) & 0x38) >> 3)
68 #define X86_SIB_BASE(sib) ((sib) & 0x07)
69
70 #define X86_REX_W(rex) ((rex) & 8)
71 #define X86_REX_R(rex) ((rex) & 4)
72 #define X86_REX_X(rex) ((rex) & 2)
73 #define X86_REX_B(rex) ((rex) & 1)
74
75 /* VEX bit flags */
76 #define X86_VEX_W(vex) ((vex) & 0x80) /* VEX3 Byte2 */
77 #define X86_VEX_R(vex) ((vex) & 0x80) /* VEX2/3 Byte1 */
78 #define X86_VEX_X(vex) ((vex) & 0x40) /* VEX3 Byte1 */
79 #define X86_VEX_B(vex) ((vex) & 0x20) /* VEX3 Byte1 */
80 #define X86_VEX_L(vex) ((vex) & 0x04) /* VEX3 Byte2, VEX2 Byte1 */
81 /* VEX bit fields */
82 #define X86_EVEX_M(vex) ((vex) & 0x03) /* EVEX Byte1 */
83 #define X86_VEX3_M(vex) ((vex) & 0x1f) /* VEX3 Byte1 */
84 #define X86_VEX2_M 1 /* VEX2.M always 1 */
85 #define X86_VEX_V(vex) (((vex) & 0x78) >> 3) /* VEX3 Byte2, VEX2 Byte1 */
86 #define X86_VEX_P(vex) ((vex) & 0x03) /* VEX3 Byte2, VEX2 Byte1 */
87 #define X86_VEX_M_MAX 0x1f /* VEX3.M Maximum value */
88
89 extern void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64);
90 extern int insn_get_prefixes(struct insn *insn);
91 extern int insn_get_opcode(struct insn *insn);
92 extern int insn_get_modrm(struct insn *insn);
93 extern int insn_get_sib(struct insn *insn);
94 extern int insn_get_displacement(struct insn *insn);
95 extern int insn_get_immediate(struct insn *insn);
96 extern int insn_get_length(struct insn *insn);
97
98 enum insn_mode {
99 INSN_MODE_32,
100 INSN_MODE_64,
101 /* Mode is determined by the current kernel build. */
102 INSN_MODE_KERN,
103 INSN_NUM_MODES,
104 };
105
106 extern int insn_decode(struct insn *insn, const void *kaddr, int buf_len, enum insn_mode m);
107
108 #define insn_decode_kernel(_insn, _ptr) insn_decode((_insn), (_ptr), MAX_INSN_SIZE, INSN_MODE_KERN)
109
110 /* Attribute will be determined after getting ModRM (for opcode groups) */
insn_get_attribute(struct insn * insn)111 static inline void insn_get_attribute(struct insn *insn)
112 {
113 insn_get_modrm(insn);
114 }
115
116 /* Instruction uses RIP-relative addressing */
117 extern int insn_rip_relative(struct insn *insn);
118
119 /* Init insn for kernel text */
kernel_insn_init(struct insn * insn,const void * kaddr,int buf_len)120 static inline void kernel_insn_init(struct insn *insn,
121 const void *kaddr, int buf_len)
122 {
123 #ifdef CONFIG_X86_64
124 insn_init(insn, kaddr, buf_len, 1);
125 #else /* CONFIG_X86_32 */
126 insn_init(insn, kaddr, buf_len, 0);
127 #endif
128 }
129
insn_is_avx(struct insn * insn)130 static inline int insn_is_avx(struct insn *insn)
131 {
132 if (!insn->prefixes.got)
133 insn_get_prefixes(insn);
134 return (insn->vex_prefix.value != 0);
135 }
136
insn_is_evex(struct insn * insn)137 static inline int insn_is_evex(struct insn *insn)
138 {
139 if (!insn->prefixes.got)
140 insn_get_prefixes(insn);
141 return (insn->vex_prefix.nbytes == 4);
142 }
143
insn_has_emulate_prefix(struct insn * insn)144 static inline int insn_has_emulate_prefix(struct insn *insn)
145 {
146 return !!insn->emulate_prefix_size;
147 }
148
149 /* Ensure this instruction is decoded completely */
insn_complete(struct insn * insn)150 static inline int insn_complete(struct insn *insn)
151 {
152 return insn->opcode.got && insn->modrm.got && insn->sib.got &&
153 insn->displacement.got && insn->immediate.got;
154 }
155
insn_vex_m_bits(struct insn * insn)156 static inline insn_byte_t insn_vex_m_bits(struct insn *insn)
157 {
158 if (insn->vex_prefix.nbytes == 2) /* 2 bytes VEX */
159 return X86_VEX2_M;
160 else if (insn->vex_prefix.nbytes == 3) /* 3 bytes VEX */
161 return X86_VEX3_M(insn->vex_prefix.bytes[1]);
162 else /* EVEX */
163 return X86_EVEX_M(insn->vex_prefix.bytes[1]);
164 }
165
insn_vex_p_bits(struct insn * insn)166 static inline insn_byte_t insn_vex_p_bits(struct insn *insn)
167 {
168 if (insn->vex_prefix.nbytes == 2) /* 2 bytes VEX */
169 return X86_VEX_P(insn->vex_prefix.bytes[1]);
170 else
171 return X86_VEX_P(insn->vex_prefix.bytes[2]);
172 }
173
174 /* Get the last prefix id from last prefix or VEX prefix */
insn_last_prefix_id(struct insn * insn)175 static inline int insn_last_prefix_id(struct insn *insn)
176 {
177 if (insn_is_avx(insn))
178 return insn_vex_p_bits(insn); /* VEX_p is a SIMD prefix id */
179
180 if (insn->prefixes.bytes[3])
181 return inat_get_last_prefix_id(insn->prefixes.bytes[3]);
182
183 return 0;
184 }
185
186 /* Offset of each field from kaddr */
insn_offset_rex_prefix(struct insn * insn)187 static inline int insn_offset_rex_prefix(struct insn *insn)
188 {
189 return insn->prefixes.nbytes;
190 }
insn_offset_vex_prefix(struct insn * insn)191 static inline int insn_offset_vex_prefix(struct insn *insn)
192 {
193 return insn_offset_rex_prefix(insn) + insn->rex_prefix.nbytes;
194 }
insn_offset_opcode(struct insn * insn)195 static inline int insn_offset_opcode(struct insn *insn)
196 {
197 return insn_offset_vex_prefix(insn) + insn->vex_prefix.nbytes;
198 }
insn_offset_modrm(struct insn * insn)199 static inline int insn_offset_modrm(struct insn *insn)
200 {
201 return insn_offset_opcode(insn) + insn->opcode.nbytes;
202 }
insn_offset_sib(struct insn * insn)203 static inline int insn_offset_sib(struct insn *insn)
204 {
205 return insn_offset_modrm(insn) + insn->modrm.nbytes;
206 }
insn_offset_displacement(struct insn * insn)207 static inline int insn_offset_displacement(struct insn *insn)
208 {
209 return insn_offset_sib(insn) + insn->sib.nbytes;
210 }
insn_offset_immediate(struct insn * insn)211 static inline int insn_offset_immediate(struct insn *insn)
212 {
213 return insn_offset_displacement(insn) + insn->displacement.nbytes;
214 }
215
216 /**
217 * for_each_insn_prefix() -- Iterate prefixes in the instruction
218 * @insn: Pointer to struct insn.
219 * @idx: Index storage.
220 * @prefix: Prefix byte.
221 *
222 * Iterate prefix bytes of given @insn. Each prefix byte is stored in @prefix
223 * and the index is stored in @idx (note that this @idx is just for a cursor,
224 * do not change it.)
225 * Since prefixes.nbytes can be bigger than 4 if some prefixes
226 * are repeated, it cannot be used for looping over the prefixes.
227 */
228 #define for_each_insn_prefix(insn, idx, prefix) \
229 for (idx = 0; idx < ARRAY_SIZE(insn->prefixes.bytes) && (prefix = insn->prefixes.bytes[idx]) != 0; idx++)
230
231 #define POP_SS_OPCODE 0x1f
232 #define MOV_SREG_OPCODE 0x8e
233
234 /*
235 * Intel SDM Vol.3A 6.8.3 states;
236 * "Any single-step trap that would be delivered following the MOV to SS
237 * instruction or POP to SS instruction (because EFLAGS.TF is 1) is
238 * suppressed."
239 * This function returns true if @insn is MOV SS or POP SS. On these
240 * instructions, single stepping is suppressed.
241 */
insn_masking_exception(struct insn * insn)242 static inline int insn_masking_exception(struct insn *insn)
243 {
244 return insn->opcode.bytes[0] == POP_SS_OPCODE ||
245 (insn->opcode.bytes[0] == MOV_SREG_OPCODE &&
246 X86_MODRM_REG(insn->modrm.bytes[0]) == 2);
247 }
248
249 #endif /* _ASM_X86_INSN_H */
250