1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8 #ifndef __MSM_DRV_H__
9 #define __MSM_DRV_H__
10
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/cpufreq.h>
14 #include <linux/module.h>
15 #include <linux/component.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/slab.h>
20 #include <linux/list.h>
21 #include <linux/iommu.h>
22 #include <linux/types.h>
23 #include <linux/of_graph.h>
24 #include <linux/of_device.h>
25 #include <linux/sizes.h>
26 #include <linux/kthread.h>
27
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_plane_helper.h>
31 #include <drm/drm_probe_helper.h>
32 #include <drm/drm_fb_helper.h>
33 #include <drm/msm_drm.h>
34 #include <drm/drm_gem.h>
35
36 struct msm_kms;
37 struct msm_gpu;
38 struct msm_mmu;
39 struct msm_mdss;
40 struct msm_rd_state;
41 struct msm_perf_state;
42 struct msm_gem_submit;
43 struct msm_fence_context;
44 struct msm_gem_address_space;
45 struct msm_gem_vma;
46
47 #define MAX_CRTCS 8
48 #define MAX_PLANES 20
49 #define MAX_ENCODERS 8
50 #define MAX_BRIDGES 8
51 #define MAX_CONNECTORS 8
52
53 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
54
55 struct msm_file_private {
56 rwlock_t queuelock;
57 struct list_head submitqueues;
58 int queueid;
59 struct msm_gem_address_space *aspace;
60 struct kref ref;
61 int seqno;
62 };
63
64 enum msm_mdp_plane_property {
65 PLANE_PROP_ZPOS,
66 PLANE_PROP_ALPHA,
67 PLANE_PROP_PREMULTIPLIED,
68 PLANE_PROP_MAX_NUM
69 };
70
71 #define MSM_GPU_MAX_RINGS 4
72 #define MAX_H_TILES_PER_DISPLAY 2
73
74 /**
75 * enum msm_display_caps - features/capabilities supported by displays
76 * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported
77 * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported
78 * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported
79 * @MSM_DISPLAY_CAP_EDID: EDID supported
80 */
81 enum msm_display_caps {
82 MSM_DISPLAY_CAP_VID_MODE = BIT(0),
83 MSM_DISPLAY_CAP_CMD_MODE = BIT(1),
84 MSM_DISPLAY_CAP_HOT_PLUG = BIT(2),
85 MSM_DISPLAY_CAP_EDID = BIT(3),
86 };
87
88 /**
89 * enum msm_event_wait - type of HW events to wait for
90 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
91 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
92 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
93 */
94 enum msm_event_wait {
95 MSM_ENC_COMMIT_DONE = 0,
96 MSM_ENC_TX_COMPLETE,
97 MSM_ENC_VBLANK,
98 };
99
100 /**
101 * struct msm_display_topology - defines a display topology pipeline
102 * @num_lm: number of layer mixers used
103 * @num_enc: number of compression encoder blocks used
104 * @num_intf: number of interfaces the panel is mounted on
105 */
106 struct msm_display_topology {
107 u32 num_lm;
108 u32 num_enc;
109 u32 num_intf;
110 u32 num_dspp;
111 };
112
113 /**
114 * struct msm_display_info - defines display properties
115 * @intf_type: DRM_MODE_ENCODER_ type
116 * @capabilities: Bitmask of display flags
117 * @num_of_h_tiles: Number of horizontal tiles in case of split interface
118 * @h_tile_instance: Controller instance used per tile. Number of elements is
119 * based on num_of_h_tiles
120 * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
121 * used instead of panel TE in cmd mode panels
122 */
123 struct msm_display_info {
124 int intf_type;
125 uint32_t capabilities;
126 uint32_t num_of_h_tiles;
127 uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
128 bool is_te_using_watchdog_timer;
129 };
130
131 /* Commit/Event thread specific structure */
132 struct msm_drm_thread {
133 struct drm_device *dev;
134 unsigned int crtc_id;
135 struct kthread_worker *worker;
136 };
137
138 struct msm_drm_private {
139
140 struct drm_device *dev;
141
142 struct msm_kms *kms;
143
144 /* subordinate devices, if present: */
145 struct platform_device *gpu_pdev;
146
147 /* top level MDSS wrapper device (for MDP5/DPU only) */
148 struct msm_mdss *mdss;
149
150 /* possibly this should be in the kms component, but it is
151 * shared by both mdp4 and mdp5..
152 */
153 struct hdmi *hdmi;
154
155 /* eDP is for mdp5 only, but kms has not been created
156 * when edp_bind() and edp_init() are called. Here is the only
157 * place to keep the edp instance.
158 */
159 struct msm_edp *edp;
160
161 /* DSI is shared by mdp4 and mdp5 */
162 struct msm_dsi *dsi[2];
163
164 struct msm_dp *dp;
165
166 /* when we have more than one 'msm_gpu' these need to be an array: */
167 struct msm_gpu *gpu;
168 struct msm_file_private *lastctx;
169 /* gpu is only set on open(), but we need this info earlier */
170 bool is_a2xx;
171
172 struct drm_fb_helper *fbdev;
173
174 struct msm_rd_state *rd; /* debugfs to dump all submits */
175 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
176 struct msm_perf_state *perf;
177
178 /* list of GEM objects: */
179 struct list_head inactive_list;
180
181 /* worker for delayed free of objects: */
182 struct work_struct free_work;
183 struct llist_head free_list;
184
185 struct workqueue_struct *wq;
186
187 unsigned int num_planes;
188 struct drm_plane *planes[MAX_PLANES];
189
190 unsigned int num_crtcs;
191 struct drm_crtc *crtcs[MAX_CRTCS];
192
193 struct msm_drm_thread event_thread[MAX_CRTCS];
194
195 unsigned int num_encoders;
196 struct drm_encoder *encoders[MAX_ENCODERS];
197
198 unsigned int num_bridges;
199 struct drm_bridge *bridges[MAX_BRIDGES];
200
201 unsigned int num_connectors;
202 struct drm_connector *connectors[MAX_CONNECTORS];
203
204 /* Properties */
205 struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
206
207 /* VRAM carveout, used when no IOMMU: */
208 struct {
209 unsigned long size;
210 dma_addr_t paddr;
211 /* NOTE: mm managed at the page level, size is in # of pages
212 * and position mm_node->start is in # of pages:
213 */
214 struct drm_mm mm;
215 spinlock_t lock; /* Protects drm_mm node allocation/removal */
216 } vram;
217
218 struct notifier_block vmap_notifier;
219 struct shrinker shrinker;
220
221 struct drm_atomic_state *pm_state;
222 };
223
224 struct msm_format {
225 uint32_t pixel_format;
226 };
227
228 struct msm_pending_timer;
229
230 int msm_atomic_prepare_fb(struct drm_plane *plane,
231 struct drm_plane_state *new_state);
232 void msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
233 struct msm_kms *kms, int crtc_idx);
234 void msm_atomic_commit_tail(struct drm_atomic_state *state);
235 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
236 void msm_atomic_state_clear(struct drm_atomic_state *state);
237 void msm_atomic_state_free(struct drm_atomic_state *state);
238
239 int msm_crtc_enable_vblank(struct drm_crtc *crtc);
240 void msm_crtc_disable_vblank(struct drm_crtc *crtc);
241
242 int msm_gem_init_vma(struct msm_gem_address_space *aspace,
243 struct msm_gem_vma *vma, int npages,
244 u64 range_start, u64 range_end);
245 void msm_gem_purge_vma(struct msm_gem_address_space *aspace,
246 struct msm_gem_vma *vma);
247 void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
248 struct msm_gem_vma *vma);
249 int msm_gem_map_vma(struct msm_gem_address_space *aspace,
250 struct msm_gem_vma *vma, int prot,
251 struct sg_table *sgt, int npages);
252 void msm_gem_close_vma(struct msm_gem_address_space *aspace,
253 struct msm_gem_vma *vma);
254
255
256 struct msm_gem_address_space *
257 msm_gem_address_space_get(struct msm_gem_address_space *aspace);
258
259 void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
260
261 struct msm_gem_address_space *
262 msm_gem_address_space_create(struct msm_mmu *mmu, const char *name,
263 u64 va_start, u64 size);
264
265 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
266 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
267
268 bool msm_use_mmu(struct drm_device *dev);
269
270 void msm_gem_submit_free(struct msm_gem_submit *submit);
271 int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
272 struct drm_file *file);
273
274 void msm_gem_shrinker_init(struct drm_device *dev);
275 void msm_gem_shrinker_cleanup(struct drm_device *dev);
276
277 int msm_gem_mmap_obj(struct drm_gem_object *obj,
278 struct vm_area_struct *vma);
279 int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
280 vm_fault_t msm_gem_fault(struct vm_fault *vmf);
281 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
282 int msm_gem_get_iova(struct drm_gem_object *obj,
283 struct msm_gem_address_space *aspace, uint64_t *iova);
284 int msm_gem_get_and_pin_iova_range(struct drm_gem_object *obj,
285 struct msm_gem_address_space *aspace, uint64_t *iova,
286 u64 range_start, u64 range_end);
287 int msm_gem_get_and_pin_iova(struct drm_gem_object *obj,
288 struct msm_gem_address_space *aspace, uint64_t *iova);
289 uint64_t msm_gem_iova(struct drm_gem_object *obj,
290 struct msm_gem_address_space *aspace);
291 void msm_gem_unpin_iova(struct drm_gem_object *obj,
292 struct msm_gem_address_space *aspace);
293 struct page **msm_gem_get_pages(struct drm_gem_object *obj);
294 void msm_gem_put_pages(struct drm_gem_object *obj);
295 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
296 struct drm_mode_create_dumb *args);
297 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
298 uint32_t handle, uint64_t *offset);
299 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
300 void *msm_gem_prime_vmap(struct drm_gem_object *obj);
301 void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
302 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
303 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
304 struct dma_buf_attachment *attach, struct sg_table *sg);
305 int msm_gem_prime_pin(struct drm_gem_object *obj);
306 void msm_gem_prime_unpin(struct drm_gem_object *obj);
307 void *msm_gem_get_vaddr(struct drm_gem_object *obj);
308 void *msm_gem_get_vaddr_active(struct drm_gem_object *obj);
309 void msm_gem_put_vaddr(struct drm_gem_object *obj);
310 int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
311 int msm_gem_sync_object(struct drm_gem_object *obj,
312 struct msm_fence_context *fctx, bool exclusive);
313 void msm_gem_active_get(struct drm_gem_object *obj, struct msm_gpu *gpu);
314 void msm_gem_active_put(struct drm_gem_object *obj);
315 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
316 int msm_gem_cpu_fini(struct drm_gem_object *obj);
317 void msm_gem_free_object(struct drm_gem_object *obj);
318 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
319 uint32_t size, uint32_t flags, uint32_t *handle, char *name);
320 struct drm_gem_object *msm_gem_new(struct drm_device *dev,
321 uint32_t size, uint32_t flags);
322 struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev,
323 uint32_t size, uint32_t flags);
324 void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
325 uint32_t flags, struct msm_gem_address_space *aspace,
326 struct drm_gem_object **bo, uint64_t *iova);
327 void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size,
328 uint32_t flags, struct msm_gem_address_space *aspace,
329 struct drm_gem_object **bo, uint64_t *iova);
330 void msm_gem_kernel_put(struct drm_gem_object *bo,
331 struct msm_gem_address_space *aspace, bool locked);
332 struct drm_gem_object *msm_gem_import(struct drm_device *dev,
333 struct dma_buf *dmabuf, struct sg_table *sgt);
334 void msm_gem_free_work(struct work_struct *work);
335
336 __printf(2, 3)
337 void msm_gem_object_set_name(struct drm_gem_object *bo, const char *fmt, ...);
338
339 int msm_framebuffer_prepare(struct drm_framebuffer *fb,
340 struct msm_gem_address_space *aspace);
341 void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
342 struct msm_gem_address_space *aspace);
343 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
344 struct msm_gem_address_space *aspace, int plane);
345 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
346 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
347 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
348 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
349 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
350 int w, int h, int p, uint32_t format);
351
352 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
353 void msm_fbdev_free(struct drm_device *dev);
354
355 struct hdmi;
356 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
357 struct drm_encoder *encoder);
358 void __init msm_hdmi_register(void);
359 void __exit msm_hdmi_unregister(void);
360
361 struct msm_edp;
362 void __init msm_edp_register(void);
363 void __exit msm_edp_unregister(void);
364 int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
365 struct drm_encoder *encoder);
366
367 struct msm_dsi;
368 #ifdef CONFIG_DRM_MSM_DSI
369 void __init msm_dsi_register(void);
370 void __exit msm_dsi_unregister(void);
371 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
372 struct drm_encoder *encoder);
373 #else
msm_dsi_register(void)374 static inline void __init msm_dsi_register(void)
375 {
376 }
msm_dsi_unregister(void)377 static inline void __exit msm_dsi_unregister(void)
378 {
379 }
msm_dsi_modeset_init(struct msm_dsi * msm_dsi,struct drm_device * dev,struct drm_encoder * encoder)380 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
381 struct drm_device *dev,
382 struct drm_encoder *encoder)
383 {
384 return -EINVAL;
385 }
386 #endif
387
388 #ifdef CONFIG_DRM_MSM_DP
389 int __init msm_dp_register(void);
390 void __exit msm_dp_unregister(void);
391 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
392 struct drm_encoder *encoder);
393 int msm_dp_display_enable(struct msm_dp *dp, struct drm_encoder *encoder);
394 int msm_dp_display_disable(struct msm_dp *dp, struct drm_encoder *encoder);
395 int msm_dp_display_pre_disable(struct msm_dp *dp, struct drm_encoder *encoder);
396 void msm_dp_display_mode_set(struct msm_dp *dp, struct drm_encoder *encoder,
397 struct drm_display_mode *mode,
398 struct drm_display_mode *adjusted_mode);
399 void msm_dp_irq_postinstall(struct msm_dp *dp_display);
400
401 void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);
402
403 #else
msm_dp_register(void)404 static inline int __init msm_dp_register(void)
405 {
406 return -EINVAL;
407 }
msm_dp_unregister(void)408 static inline void __exit msm_dp_unregister(void)
409 {
410 }
msm_dp_modeset_init(struct msm_dp * dp_display,struct drm_device * dev,struct drm_encoder * encoder)411 static inline int msm_dp_modeset_init(struct msm_dp *dp_display,
412 struct drm_device *dev,
413 struct drm_encoder *encoder)
414 {
415 return -EINVAL;
416 }
msm_dp_display_enable(struct msm_dp * dp,struct drm_encoder * encoder)417 static inline int msm_dp_display_enable(struct msm_dp *dp,
418 struct drm_encoder *encoder)
419 {
420 return -EINVAL;
421 }
msm_dp_display_disable(struct msm_dp * dp,struct drm_encoder * encoder)422 static inline int msm_dp_display_disable(struct msm_dp *dp,
423 struct drm_encoder *encoder)
424 {
425 return -EINVAL;
426 }
msm_dp_display_pre_disable(struct msm_dp * dp,struct drm_encoder * encoder)427 static inline int msm_dp_display_pre_disable(struct msm_dp *dp,
428 struct drm_encoder *encoder)
429 {
430 return -EINVAL;
431 }
msm_dp_display_mode_set(struct msm_dp * dp,struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)432 static inline void msm_dp_display_mode_set(struct msm_dp *dp,
433 struct drm_encoder *encoder,
434 struct drm_display_mode *mode,
435 struct drm_display_mode *adjusted_mode)
436 {
437 }
438
msm_dp_irq_postinstall(struct msm_dp * dp_display)439 static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display)
440 {
441 }
442
msm_dp_debugfs_init(struct msm_dp * dp_display,struct drm_minor * minor)443 static inline void msm_dp_debugfs_init(struct msm_dp *dp_display,
444 struct drm_minor *minor)
445 {
446 }
447
448 #endif
449
450 void __init msm_mdp_register(void);
451 void __exit msm_mdp_unregister(void);
452 void __init msm_dpu_register(void);
453 void __exit msm_dpu_unregister(void);
454
455 #ifdef CONFIG_DEBUG_FS
456 void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
457 void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
458 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
459 int msm_debugfs_late_init(struct drm_device *dev);
460 int msm_rd_debugfs_init(struct drm_minor *minor);
461 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
462 __printf(3, 4)
463 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
464 const char *fmt, ...);
465 int msm_perf_debugfs_init(struct drm_minor *minor);
466 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
467 #else
msm_debugfs_late_init(struct drm_device * dev)468 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
469 __printf(3, 4)
msm_rd_dump_submit(struct msm_rd_state * rd,struct msm_gem_submit * submit,const char * fmt,...)470 static inline void msm_rd_dump_submit(struct msm_rd_state *rd,
471 struct msm_gem_submit *submit,
472 const char *fmt, ...) {}
msm_rd_debugfs_cleanup(struct msm_drm_private * priv)473 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
msm_perf_debugfs_cleanup(struct msm_drm_private * priv)474 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
475 #endif
476
477 struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
478
479 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
480 const char *name);
481 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
482 const char *dbgname);
483 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
484 const char *dbgname);
485 void msm_writel(u32 data, void __iomem *addr);
486 u32 msm_readl(const void __iomem *addr);
487
488 struct msm_gpu_submitqueue;
489 int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
490 struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
491 u32 id);
492 int msm_submitqueue_create(struct drm_device *drm,
493 struct msm_file_private *ctx,
494 u32 prio, u32 flags, u32 *id);
495 int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx,
496 struct drm_msm_submitqueue_query *args);
497 int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
498 void msm_submitqueue_close(struct msm_file_private *ctx);
499
500 void msm_submitqueue_destroy(struct kref *kref);
501
__msm_file_private_destroy(struct kref * kref)502 static inline void __msm_file_private_destroy(struct kref *kref)
503 {
504 struct msm_file_private *ctx = container_of(kref,
505 struct msm_file_private, ref);
506
507 msm_gem_address_space_put(ctx->aspace);
508 kfree(ctx);
509 }
510
msm_file_private_put(struct msm_file_private * ctx)511 static inline void msm_file_private_put(struct msm_file_private *ctx)
512 {
513 kref_put(&ctx->ref, __msm_file_private_destroy);
514 }
515
msm_file_private_get(struct msm_file_private * ctx)516 static inline struct msm_file_private *msm_file_private_get(
517 struct msm_file_private *ctx)
518 {
519 kref_get(&ctx->ref);
520 return ctx;
521 }
522
523 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
524 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
525
align_pitch(int width,int bpp)526 static inline int align_pitch(int width, int bpp)
527 {
528 int bytespp = (bpp + 7) / 8;
529 /* adreno needs pitch aligned to 32 pixels: */
530 return bytespp * ALIGN(width, 32);
531 }
532
533 /* for the generated headers: */
534 #define INVALID_IDX(idx) ({BUG(); 0;})
535 #define fui(x) ({BUG(); 0;})
536 #define util_float_to_half(x) ({BUG(); 0;})
537
538
539 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
540
541 /* for conditionally setting boolean flag(s): */
542 #define COND(bool, val) ((bool) ? (val) : 0)
543
timeout_to_jiffies(const ktime_t * timeout)544 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
545 {
546 ktime_t now = ktime_get();
547 s64 remaining_jiffies;
548
549 if (ktime_compare(*timeout, now) < 0) {
550 remaining_jiffies = 0;
551 } else {
552 ktime_t rem = ktime_sub(*timeout, now);
553 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
554 }
555
556 return clamp(remaining_jiffies, 0LL, (s64)INT_MAX);
557 }
558
559 #endif /* __MSM_DRV_H__ */
560