1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 #include "ixgbe_x540.h"
5 #include "ixgbe_type.h"
6 #include "ixgbe_common.h"
7 #include "ixgbe_phy.h"
8
9 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed);
10 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *);
11 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *);
12 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *);
13 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *);
14
ixgbe_get_invariants_X550_x(struct ixgbe_hw * hw)15 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
16 {
17 struct ixgbe_mac_info *mac = &hw->mac;
18 struct ixgbe_phy_info *phy = &hw->phy;
19 struct ixgbe_link_info *link = &hw->link;
20
21 /* Start with X540 invariants, since so simular */
22 ixgbe_get_invariants_X540(hw);
23
24 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
25 phy->ops.set_phy_power = NULL;
26
27 link->addr = IXGBE_CS4227;
28
29 return 0;
30 }
31
ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw * hw)32 static s32 ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw)
33 {
34 struct ixgbe_phy_info *phy = &hw->phy;
35
36 /* Start with X540 invariants, since so similar */
37 ixgbe_get_invariants_X540(hw);
38
39 phy->ops.set_phy_power = NULL;
40
41 return 0;
42 }
43
ixgbe_get_invariants_X550_a(struct ixgbe_hw * hw)44 static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw)
45 {
46 struct ixgbe_mac_info *mac = &hw->mac;
47 struct ixgbe_phy_info *phy = &hw->phy;
48
49 /* Start with X540 invariants, since so simular */
50 ixgbe_get_invariants_X540(hw);
51
52 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
53 phy->ops.set_phy_power = NULL;
54
55 return 0;
56 }
57
ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw * hw)58 static s32 ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw)
59 {
60 struct ixgbe_phy_info *phy = &hw->phy;
61
62 /* Start with X540 invariants, since so similar */
63 ixgbe_get_invariants_X540(hw);
64
65 phy->ops.set_phy_power = NULL;
66
67 return 0;
68 }
69
70 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
71 * @hw: pointer to hardware structure
72 **/
ixgbe_setup_mux_ctl(struct ixgbe_hw * hw)73 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
74 {
75 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
76
77 if (hw->bus.lan_id) {
78 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
79 esdp |= IXGBE_ESDP_SDP1_DIR;
80 }
81 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
82 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
83 IXGBE_WRITE_FLUSH(hw);
84 }
85
86 /**
87 * ixgbe_read_cs4227 - Read CS4227 register
88 * @hw: pointer to hardware structure
89 * @reg: register number to write
90 * @value: pointer to receive value read
91 *
92 * Returns status code
93 */
ixgbe_read_cs4227(struct ixgbe_hw * hw,u16 reg,u16 * value)94 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
95 {
96 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
97 }
98
99 /**
100 * ixgbe_write_cs4227 - Write CS4227 register
101 * @hw: pointer to hardware structure
102 * @reg: register number to write
103 * @value: value to write to register
104 *
105 * Returns status code
106 */
ixgbe_write_cs4227(struct ixgbe_hw * hw,u16 reg,u16 value)107 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
108 {
109 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
110 }
111
112 /**
113 * ixgbe_read_pe - Read register from port expander
114 * @hw: pointer to hardware structure
115 * @reg: register number to read
116 * @value: pointer to receive read value
117 *
118 * Returns status code
119 */
ixgbe_read_pe(struct ixgbe_hw * hw,u8 reg,u8 * value)120 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
121 {
122 s32 status;
123
124 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
125 if (status)
126 hw_err(hw, "port expander access failed with %d\n", status);
127 return status;
128 }
129
130 /**
131 * ixgbe_write_pe - Write register to port expander
132 * @hw: pointer to hardware structure
133 * @reg: register number to write
134 * @value: value to write
135 *
136 * Returns status code
137 */
ixgbe_write_pe(struct ixgbe_hw * hw,u8 reg,u8 value)138 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
139 {
140 s32 status;
141
142 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
143 value);
144 if (status)
145 hw_err(hw, "port expander access failed with %d\n", status);
146 return status;
147 }
148
149 /**
150 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
151 * @hw: pointer to hardware structure
152 *
153 * This function assumes that the caller has acquired the proper semaphore.
154 * Returns error code
155 */
ixgbe_reset_cs4227(struct ixgbe_hw * hw)156 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
157 {
158 s32 status;
159 u32 retry;
160 u16 value;
161 u8 reg;
162
163 /* Trigger hard reset. */
164 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
165 if (status)
166 return status;
167 reg |= IXGBE_PE_BIT1;
168 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
169 if (status)
170 return status;
171
172 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
173 if (status)
174 return status;
175 reg &= ~IXGBE_PE_BIT1;
176 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
177 if (status)
178 return status;
179
180 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
181 if (status)
182 return status;
183 reg &= ~IXGBE_PE_BIT1;
184 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
185 if (status)
186 return status;
187
188 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
189
190 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
191 if (status)
192 return status;
193 reg |= IXGBE_PE_BIT1;
194 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
195 if (status)
196 return status;
197
198 /* Wait for the reset to complete. */
199 msleep(IXGBE_CS4227_RESET_DELAY);
200 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
201 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
202 &value);
203 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
204 break;
205 msleep(IXGBE_CS4227_CHECK_DELAY);
206 }
207 if (retry == IXGBE_CS4227_RETRIES) {
208 hw_err(hw, "CS4227 reset did not complete\n");
209 return -EIO;
210 }
211
212 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
213 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
214 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
215 return -EIO;
216 }
217
218 return 0;
219 }
220
221 /**
222 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
223 * @hw: pointer to hardware structure
224 */
ixgbe_check_cs4227(struct ixgbe_hw * hw)225 static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
226 {
227 u32 swfw_mask = hw->phy.phy_semaphore_mask;
228 s32 status;
229 u16 value;
230 u8 retry;
231
232 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
233 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
234 if (status) {
235 hw_err(hw, "semaphore failed with %d\n", status);
236 msleep(IXGBE_CS4227_CHECK_DELAY);
237 continue;
238 }
239
240 /* Get status of reset flow. */
241 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
242 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
243 goto out;
244
245 if (status || value != IXGBE_CS4227_RESET_PENDING)
246 break;
247
248 /* Reset is pending. Wait and check again. */
249 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
250 msleep(IXGBE_CS4227_CHECK_DELAY);
251 }
252 /* If still pending, assume other instance failed. */
253 if (retry == IXGBE_CS4227_RETRIES) {
254 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
255 if (status) {
256 hw_err(hw, "semaphore failed with %d\n", status);
257 return;
258 }
259 }
260
261 /* Reset the CS4227. */
262 status = ixgbe_reset_cs4227(hw);
263 if (status) {
264 hw_err(hw, "CS4227 reset failed: %d", status);
265 goto out;
266 }
267
268 /* Reset takes so long, temporarily release semaphore in case the
269 * other driver instance is waiting for the reset indication.
270 */
271 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
272 IXGBE_CS4227_RESET_PENDING);
273 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
274 usleep_range(10000, 12000);
275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
276 if (status) {
277 hw_err(hw, "semaphore failed with %d", status);
278 return;
279 }
280
281 /* Record completion for next time. */
282 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
283 IXGBE_CS4227_RESET_COMPLETE);
284
285 out:
286 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
287 msleep(hw->eeprom.semaphore_delay);
288 }
289
290 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
291 * @hw: pointer to hardware structure
292 *
293 * Returns error code
294 */
ixgbe_identify_phy_x550em(struct ixgbe_hw * hw)295 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
296 {
297 switch (hw->device_id) {
298 case IXGBE_DEV_ID_X550EM_A_SFP:
299 if (hw->bus.lan_id)
300 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
301 else
302 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
303 return ixgbe_identify_module_generic(hw);
304 case IXGBE_DEV_ID_X550EM_X_SFP:
305 /* set up for CS4227 usage */
306 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
307 ixgbe_setup_mux_ctl(hw);
308 ixgbe_check_cs4227(hw);
309 fallthrough;
310 case IXGBE_DEV_ID_X550EM_A_SFP_N:
311 return ixgbe_identify_module_generic(hw);
312 case IXGBE_DEV_ID_X550EM_X_KX4:
313 hw->phy.type = ixgbe_phy_x550em_kx4;
314 break;
315 case IXGBE_DEV_ID_X550EM_X_XFI:
316 hw->phy.type = ixgbe_phy_x550em_xfi;
317 break;
318 case IXGBE_DEV_ID_X550EM_X_KR:
319 case IXGBE_DEV_ID_X550EM_A_KR:
320 case IXGBE_DEV_ID_X550EM_A_KR_L:
321 hw->phy.type = ixgbe_phy_x550em_kr;
322 break;
323 case IXGBE_DEV_ID_X550EM_A_10G_T:
324 if (hw->bus.lan_id)
325 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
326 else
327 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
328 fallthrough;
329 case IXGBE_DEV_ID_X550EM_X_10G_T:
330 return ixgbe_identify_phy_generic(hw);
331 case IXGBE_DEV_ID_X550EM_X_1G_T:
332 hw->phy.type = ixgbe_phy_ext_1g_t;
333 break;
334 case IXGBE_DEV_ID_X550EM_A_1G_T:
335 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
336 hw->phy.type = ixgbe_phy_fw;
337 hw->phy.ops.read_reg = NULL;
338 hw->phy.ops.write_reg = NULL;
339 if (hw->bus.lan_id)
340 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
341 else
342 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
343 break;
344 default:
345 break;
346 }
347 return 0;
348 }
349
ixgbe_read_phy_reg_x550em(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)350 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
351 u32 device_type, u16 *phy_data)
352 {
353 return -EOPNOTSUPP;
354 }
355
ixgbe_write_phy_reg_x550em(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)356 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
357 u32 device_type, u16 phy_data)
358 {
359 return -EOPNOTSUPP;
360 }
361
362 /**
363 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
364 * @hw: pointer to the hardware structure
365 * @addr: I2C bus address to read from
366 * @reg: I2C device register to read from
367 * @val: pointer to location to receive read value
368 *
369 * Returns an error code on error.
370 **/
ixgbe_read_i2c_combined_generic(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 * val)371 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
372 u16 reg, u16 *val)
373 {
374 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
375 }
376
377 /**
378 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
379 * @hw: pointer to the hardware structure
380 * @addr: I2C bus address to read from
381 * @reg: I2C device register to read from
382 * @val: pointer to location to receive read value
383 *
384 * Returns an error code on error.
385 **/
386 static s32
ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 * val)387 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
388 u16 reg, u16 *val)
389 {
390 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
391 }
392
393 /**
394 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
395 * @hw: pointer to the hardware structure
396 * @addr: I2C bus address to write to
397 * @reg: I2C device register to write to
398 * @val: value to write
399 *
400 * Returns an error code on error.
401 **/
ixgbe_write_i2c_combined_generic(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 val)402 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
403 u8 addr, u16 reg, u16 val)
404 {
405 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
406 }
407
408 /**
409 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
410 * @hw: pointer to the hardware structure
411 * @addr: I2C bus address to write to
412 * @reg: I2C device register to write to
413 * @val: value to write
414 *
415 * Returns an error code on error.
416 **/
417 static s32
ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 val)418 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
419 u8 addr, u16 reg, u16 val)
420 {
421 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
422 }
423
424 /**
425 * ixgbe_fw_phy_activity - Perform an activity on a PHY
426 * @hw: pointer to hardware structure
427 * @activity: activity to perform
428 * @data: Pointer to 4 32-bit words of data
429 */
ixgbe_fw_phy_activity(struct ixgbe_hw * hw,u16 activity,u32 (* data)[FW_PHY_ACT_DATA_COUNT])430 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
431 u32 (*data)[FW_PHY_ACT_DATA_COUNT])
432 {
433 union {
434 struct ixgbe_hic_phy_activity_req cmd;
435 struct ixgbe_hic_phy_activity_resp rsp;
436 } hic;
437 u16 retries = FW_PHY_ACT_RETRIES;
438 s32 rc;
439 u32 i;
440
441 do {
442 memset(&hic, 0, sizeof(hic));
443 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
444 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
445 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
446 hic.cmd.port_number = hw->bus.lan_id;
447 hic.cmd.activity_id = cpu_to_le16(activity);
448 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i)
449 hic.cmd.data[i] = cpu_to_be32((*data)[i]);
450
451 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
452 IXGBE_HI_COMMAND_TIMEOUT,
453 true);
454 if (rc)
455 return rc;
456 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
457 FW_CEM_RESP_STATUS_SUCCESS) {
458 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
459 (*data)[i] = be32_to_cpu(hic.rsp.data[i]);
460 return 0;
461 }
462 usleep_range(20, 30);
463 --retries;
464 } while (retries > 0);
465
466 return -EIO;
467 }
468
469 static const struct {
470 u16 fw_speed;
471 ixgbe_link_speed phy_speed;
472 } ixgbe_fw_map[] = {
473 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
474 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
475 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
476 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
477 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
478 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
479 };
480
481 /**
482 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
483 * @hw: pointer to hardware structure
484 *
485 * Returns error code
486 */
ixgbe_get_phy_id_fw(struct ixgbe_hw * hw)487 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
488 {
489 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
490 u16 phy_speeds;
491 u16 phy_id_lo;
492 s32 rc;
493 u16 i;
494
495 if (hw->phy.id)
496 return 0;
497
498 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
499 if (rc)
500 return rc;
501
502 hw->phy.speeds_supported = 0;
503 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
504 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
505 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
506 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
507 }
508
509 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
510 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
511 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
512 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
513 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
514 return -EFAULT;
515
516 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
517 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
518 IXGBE_LINK_SPEED_1GB_FULL;
519 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
520 return 0;
521 }
522
523 /**
524 * ixgbe_identify_phy_fw - Get PHY type based on firmware command
525 * @hw: pointer to hardware structure
526 *
527 * Returns error code
528 */
ixgbe_identify_phy_fw(struct ixgbe_hw * hw)529 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
530 {
531 if (hw->bus.lan_id)
532 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
533 else
534 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
535
536 hw->phy.type = ixgbe_phy_fw;
537 hw->phy.ops.read_reg = NULL;
538 hw->phy.ops.write_reg = NULL;
539 return ixgbe_get_phy_id_fw(hw);
540 }
541
542 /**
543 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
544 * @hw: pointer to hardware structure
545 *
546 * Returns error code
547 */
ixgbe_shutdown_fw_phy(struct ixgbe_hw * hw)548 static s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
549 {
550 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
551
552 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
553 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
554 }
555
556 /**
557 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
558 * @hw: pointer to hardware structure
559 */
ixgbe_setup_fw_link(struct ixgbe_hw * hw)560 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw)
561 {
562 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
563 s32 rc;
564 u16 i;
565
566 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
567 return 0;
568
569 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
570 hw_err(hw, "rx_pause not valid in strict IEEE mode\n");
571 return -EINVAL;
572 }
573
574 switch (hw->fc.requested_mode) {
575 case ixgbe_fc_full:
576 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
577 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
578 break;
579 case ixgbe_fc_rx_pause:
580 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
581 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
582 break;
583 case ixgbe_fc_tx_pause:
584 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
585 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
586 break;
587 default:
588 break;
589 }
590
591 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
592 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
593 setup[0] |= ixgbe_fw_map[i].fw_speed;
594 }
595 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
596
597 if (hw->phy.eee_speeds_advertised)
598 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
599
600 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
601 if (rc)
602 return rc;
603
604 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
605 return -EIO;
606
607 return 0;
608 }
609
610 /**
611 * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs
612 * @hw: pointer to hardware structure
613 *
614 * Called at init time to set up flow control.
615 */
ixgbe_fc_autoneg_fw(struct ixgbe_hw * hw)616 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
617 {
618 if (hw->fc.requested_mode == ixgbe_fc_default)
619 hw->fc.requested_mode = ixgbe_fc_full;
620
621 return ixgbe_setup_fw_link(hw);
622 }
623
624 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
625 * @hw: pointer to hardware structure
626 *
627 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
628 * ixgbe_hw struct in order to set up EEPROM access.
629 **/
ixgbe_init_eeprom_params_X550(struct ixgbe_hw * hw)630 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
631 {
632 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
633 u32 eec;
634 u16 eeprom_size;
635
636 if (eeprom->type == ixgbe_eeprom_uninitialized) {
637 eeprom->semaphore_delay = 10;
638 eeprom->type = ixgbe_flash;
639
640 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
641 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
642 IXGBE_EEC_SIZE_SHIFT);
643 eeprom->word_size = BIT(eeprom_size +
644 IXGBE_EEPROM_WORD_SIZE_SHIFT);
645
646 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
647 eeprom->type, eeprom->word_size);
648 }
649
650 return 0;
651 }
652
653 /**
654 * ixgbe_iosf_wait - Wait for IOSF command completion
655 * @hw: pointer to hardware structure
656 * @ctrl: pointer to location to receive final IOSF control value
657 *
658 * Return: failing status on timeout
659 *
660 * Note: ctrl can be NULL if the IOSF control register value is not needed
661 */
ixgbe_iosf_wait(struct ixgbe_hw * hw,u32 * ctrl)662 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
663 {
664 u32 i, command;
665
666 /* Check every 10 usec to see if the address cycle completed.
667 * The SB IOSF BUSY bit will clear when the operation is
668 * complete.
669 */
670 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
671 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
672 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
673 break;
674 udelay(10);
675 }
676 if (ctrl)
677 *ctrl = command;
678 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
679 hw_dbg(hw, "IOSF wait timed out\n");
680 return -EIO;
681 }
682
683 return 0;
684 }
685
686 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
687 * IOSF device
688 * @hw: pointer to hardware structure
689 * @reg_addr: 32 bit PHY register to write
690 * @device_type: 3 bit device type
691 * @phy_data: Pointer to read data from the register
692 **/
ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u32 * data)693 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
694 u32 device_type, u32 *data)
695 {
696 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
697 u32 command, error;
698 s32 ret;
699
700 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
701 if (ret)
702 return ret;
703
704 ret = ixgbe_iosf_wait(hw, NULL);
705 if (ret)
706 goto out;
707
708 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
709 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
710
711 /* Write IOSF control register */
712 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
713
714 ret = ixgbe_iosf_wait(hw, &command);
715
716 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
717 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
718 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
719 hw_dbg(hw, "Failed to read, error %x\n", error);
720 ret = -EIO;
721 goto out;
722 }
723
724 if (!ret)
725 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
726
727 out:
728 hw->mac.ops.release_swfw_sync(hw, gssr);
729 return ret;
730 }
731
732 /**
733 * ixgbe_get_phy_token - Get the token for shared PHY access
734 * @hw: Pointer to hardware structure
735 */
ixgbe_get_phy_token(struct ixgbe_hw * hw)736 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
737 {
738 struct ixgbe_hic_phy_token_req token_cmd;
739 s32 status;
740
741 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
742 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
743 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
744 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
745 token_cmd.port_number = hw->bus.lan_id;
746 token_cmd.command_type = FW_PHY_TOKEN_REQ;
747 token_cmd.pad = 0;
748 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
749 IXGBE_HI_COMMAND_TIMEOUT,
750 true);
751 if (status)
752 return status;
753 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
754 return 0;
755 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
756 return -EIO;
757
758 return -EAGAIN;
759 }
760
761 /**
762 * ixgbe_put_phy_token - Put the token for shared PHY access
763 * @hw: Pointer to hardware structure
764 */
ixgbe_put_phy_token(struct ixgbe_hw * hw)765 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
766 {
767 struct ixgbe_hic_phy_token_req token_cmd;
768 s32 status;
769
770 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
771 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
772 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
773 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
774 token_cmd.port_number = hw->bus.lan_id;
775 token_cmd.command_type = FW_PHY_TOKEN_REL;
776 token_cmd.pad = 0;
777 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
778 IXGBE_HI_COMMAND_TIMEOUT,
779 true);
780 if (status)
781 return status;
782 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
783 return 0;
784 return -EIO;
785 }
786
787 /**
788 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
789 * @hw: pointer to hardware structure
790 * @reg_addr: 32 bit PHY register to write
791 * @device_type: 3 bit device type
792 * @data: Data to write to the register
793 **/
ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw * hw,u32 reg_addr,__always_unused u32 device_type,u32 data)794 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
795 __always_unused u32 device_type,
796 u32 data)
797 {
798 struct ixgbe_hic_internal_phy_req write_cmd;
799
800 memset(&write_cmd, 0, sizeof(write_cmd));
801 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
802 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
803 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
804 write_cmd.port_number = hw->bus.lan_id;
805 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
806 write_cmd.address = cpu_to_be16(reg_addr);
807 write_cmd.write_data = cpu_to_be32(data);
808
809 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd),
810 IXGBE_HI_COMMAND_TIMEOUT, false);
811 }
812
813 /**
814 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
815 * @hw: pointer to hardware structure
816 * @reg_addr: 32 bit PHY register to write
817 * @device_type: 3 bit device type
818 * @data: Pointer to read data from the register
819 **/
ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw * hw,u32 reg_addr,__always_unused u32 device_type,u32 * data)820 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
821 __always_unused u32 device_type,
822 u32 *data)
823 {
824 union {
825 struct ixgbe_hic_internal_phy_req cmd;
826 struct ixgbe_hic_internal_phy_resp rsp;
827 } hic;
828 s32 status;
829
830 memset(&hic, 0, sizeof(hic));
831 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
832 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
833 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
834 hic.cmd.port_number = hw->bus.lan_id;
835 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
836 hic.cmd.address = cpu_to_be16(reg_addr);
837
838 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
839 IXGBE_HI_COMMAND_TIMEOUT, true);
840
841 /* Extract the register value from the response. */
842 *data = be32_to_cpu(hic.rsp.read_data);
843
844 return status;
845 }
846
847 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
848 * @hw: pointer to hardware structure
849 * @offset: offset of word in the EEPROM to read
850 * @words: number of words
851 * @data: word(s) read from the EEPROM
852 *
853 * Reads a 16 bit word(s) from the EEPROM using the hostif.
854 **/
ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)855 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
856 u16 offset, u16 words, u16 *data)
857 {
858 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
859 struct ixgbe_hic_read_shadow_ram buffer;
860 u32 current_word = 0;
861 u16 words_to_read;
862 s32 status;
863 u32 i;
864
865 /* Take semaphore for the entire operation. */
866 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
867 if (status) {
868 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
869 return status;
870 }
871
872 while (words) {
873 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
874 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
875 else
876 words_to_read = words;
877
878 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
879 buffer.hdr.req.buf_lenh = 0;
880 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
881 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
882
883 /* convert offset from words to bytes */
884 buffer.address = (__force u32)cpu_to_be32((offset +
885 current_word) * 2);
886 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2);
887 buffer.pad2 = 0;
888 buffer.pad3 = 0;
889
890 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
891 IXGBE_HI_COMMAND_TIMEOUT);
892 if (status) {
893 hw_dbg(hw, "Host interface command failed\n");
894 goto out;
895 }
896
897 for (i = 0; i < words_to_read; i++) {
898 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
899 2 * i;
900 u32 value = IXGBE_READ_REG(hw, reg);
901
902 data[current_word] = (u16)(value & 0xffff);
903 current_word++;
904 i++;
905 if (i < words_to_read) {
906 value >>= 16;
907 data[current_word] = (u16)(value & 0xffff);
908 current_word++;
909 }
910 }
911 words -= words_to_read;
912 }
913
914 out:
915 hw->mac.ops.release_swfw_sync(hw, mask);
916 return status;
917 }
918
919 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
920 * @hw: pointer to hardware structure
921 * @ptr: pointer offset in eeprom
922 * @size: size of section pointed by ptr, if 0 first word will be used as size
923 * @csum: address of checksum to update
924 *
925 * Returns error status for any failure
926 **/
ixgbe_checksum_ptr_x550(struct ixgbe_hw * hw,u16 ptr,u16 size,u16 * csum,u16 * buffer,u32 buffer_size)927 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
928 u16 size, u16 *csum, u16 *buffer,
929 u32 buffer_size)
930 {
931 u16 buf[256];
932 s32 status;
933 u16 length, bufsz, i, start;
934 u16 *local_buffer;
935
936 bufsz = ARRAY_SIZE(buf);
937
938 /* Read a chunk at the pointer location */
939 if (!buffer) {
940 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
941 if (status) {
942 hw_dbg(hw, "Failed to read EEPROM image\n");
943 return status;
944 }
945 local_buffer = buf;
946 } else {
947 if (buffer_size < ptr)
948 return -EINVAL;
949 local_buffer = &buffer[ptr];
950 }
951
952 if (size) {
953 start = 0;
954 length = size;
955 } else {
956 start = 1;
957 length = local_buffer[0];
958
959 /* Skip pointer section if length is invalid. */
960 if (length == 0xFFFF || length == 0 ||
961 (ptr + length) >= hw->eeprom.word_size)
962 return 0;
963 }
964
965 if (buffer && ((u32)start + (u32)length > buffer_size))
966 return -EINVAL;
967
968 for (i = start; length; i++, length--) {
969 if (i == bufsz && !buffer) {
970 ptr += bufsz;
971 i = 0;
972 if (length < bufsz)
973 bufsz = length;
974
975 /* Read a chunk at the pointer location */
976 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
977 bufsz, buf);
978 if (status) {
979 hw_dbg(hw, "Failed to read EEPROM image\n");
980 return status;
981 }
982 }
983 *csum += local_buffer[i];
984 }
985 return 0;
986 }
987
988 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
989 * @hw: pointer to hardware structure
990 * @buffer: pointer to buffer containing calculated checksum
991 * @buffer_size: size of buffer
992 *
993 * Returns a negative error code on error, or the 16-bit checksum
994 **/
ixgbe_calc_checksum_X550(struct ixgbe_hw * hw,u16 * buffer,u32 buffer_size)995 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
996 u32 buffer_size)
997 {
998 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
999 u16 *local_buffer;
1000 s32 status;
1001 u16 checksum = 0;
1002 u16 pointer, i, size;
1003
1004 hw->eeprom.ops.init_params(hw);
1005
1006 if (!buffer) {
1007 /* Read pointer area */
1008 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1009 IXGBE_EEPROM_LAST_WORD + 1,
1010 eeprom_ptrs);
1011 if (status) {
1012 hw_dbg(hw, "Failed to read EEPROM image\n");
1013 return status;
1014 }
1015 local_buffer = eeprom_ptrs;
1016 } else {
1017 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
1018 return -EINVAL;
1019 local_buffer = buffer;
1020 }
1021
1022 /* For X550 hardware include 0x0-0x41 in the checksum, skip the
1023 * checksum word itself
1024 */
1025 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1026 if (i != IXGBE_EEPROM_CHECKSUM)
1027 checksum += local_buffer[i];
1028
1029 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
1030 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1031 */
1032 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1033 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1034 continue;
1035
1036 pointer = local_buffer[i];
1037
1038 /* Skip pointer section if the pointer is invalid. */
1039 if (pointer == 0xFFFF || pointer == 0 ||
1040 pointer >= hw->eeprom.word_size)
1041 continue;
1042
1043 switch (i) {
1044 case IXGBE_PCIE_GENERAL_PTR:
1045 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1046 break;
1047 case IXGBE_PCIE_CONFIG0_PTR:
1048 case IXGBE_PCIE_CONFIG1_PTR:
1049 size = IXGBE_PCIE_CONFIG_SIZE;
1050 break;
1051 default:
1052 size = 0;
1053 break;
1054 }
1055
1056 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
1057 buffer, buffer_size);
1058 if (status)
1059 return status;
1060 }
1061
1062 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1063
1064 return (s32)checksum;
1065 }
1066
1067 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1068 * @hw: pointer to hardware structure
1069 *
1070 * Returns a negative error code on error, or the 16-bit checksum
1071 **/
ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw * hw)1072 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1073 {
1074 return ixgbe_calc_checksum_X550(hw, NULL, 0);
1075 }
1076
1077 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1078 * @hw: pointer to hardware structure
1079 * @offset: offset of word in the EEPROM to read
1080 * @data: word read from the EEPROM
1081 *
1082 * Reads a 16 bit word from the EEPROM using the hostif.
1083 **/
ixgbe_read_ee_hostif_X550(struct ixgbe_hw * hw,u16 offset,u16 * data)1084 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
1085 {
1086 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
1087 struct ixgbe_hic_read_shadow_ram buffer;
1088 s32 status;
1089
1090 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1091 buffer.hdr.req.buf_lenh = 0;
1092 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1093 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1094
1095 /* convert offset from words to bytes */
1096 buffer.address = (__force u32)cpu_to_be32(offset * 2);
1097 /* one word */
1098 buffer.length = (__force u16)cpu_to_be16(sizeof(u16));
1099
1100 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
1101 if (status)
1102 return status;
1103
1104 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
1105 IXGBE_HI_COMMAND_TIMEOUT);
1106 if (!status) {
1107 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1108 FW_NVM_DATA_OFFSET);
1109 }
1110
1111 hw->mac.ops.release_swfw_sync(hw, mask);
1112 return status;
1113 }
1114
1115 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1116 * @hw: pointer to hardware structure
1117 * @checksum_val: calculated checksum
1118 *
1119 * Performs checksum calculation and validates the EEPROM checksum. If the
1120 * caller does not need checksum_val, the value can be NULL.
1121 **/
ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw * hw,u16 * checksum_val)1122 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
1123 u16 *checksum_val)
1124 {
1125 s32 status;
1126 u16 checksum;
1127 u16 read_checksum = 0;
1128
1129 /* Read the first word from the EEPROM. If this times out or fails, do
1130 * not continue or we could be in for a very long wait while every
1131 * EEPROM read fails
1132 */
1133 status = hw->eeprom.ops.read(hw, 0, &checksum);
1134 if (status) {
1135 hw_dbg(hw, "EEPROM read failed\n");
1136 return status;
1137 }
1138
1139 status = hw->eeprom.ops.calc_checksum(hw);
1140 if (status < 0)
1141 return status;
1142
1143 checksum = (u16)(status & 0xffff);
1144
1145 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1146 &read_checksum);
1147 if (status)
1148 return status;
1149
1150 /* Verify read checksum from EEPROM is the same as
1151 * calculated checksum
1152 */
1153 if (read_checksum != checksum) {
1154 status = -EIO;
1155 hw_dbg(hw, "Invalid EEPROM checksum");
1156 }
1157
1158 /* If the user cares, return the calculated checksum */
1159 if (checksum_val)
1160 *checksum_val = checksum;
1161
1162 return status;
1163 }
1164
1165 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1166 * @hw: pointer to hardware structure
1167 * @offset: offset of word in the EEPROM to write
1168 * @data: word write to the EEPROM
1169 *
1170 * Write a 16 bit word to the EEPROM using the hostif.
1171 **/
ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw * hw,u16 offset,u16 data)1172 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1173 u16 data)
1174 {
1175 s32 status;
1176 struct ixgbe_hic_write_shadow_ram buffer;
1177
1178 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1179 buffer.hdr.req.buf_lenh = 0;
1180 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1181 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1182
1183 /* one word */
1184 buffer.length = cpu_to_be16(sizeof(u16));
1185 buffer.data = data;
1186 buffer.address = cpu_to_be32(offset * 2);
1187
1188 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1189 IXGBE_HI_COMMAND_TIMEOUT, false);
1190 return status;
1191 }
1192
1193 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1194 * @hw: pointer to hardware structure
1195 * @offset: offset of word in the EEPROM to write
1196 * @data: word write to the EEPROM
1197 *
1198 * Write a 16 bit word to the EEPROM using the hostif.
1199 **/
ixgbe_write_ee_hostif_X550(struct ixgbe_hw * hw,u16 offset,u16 data)1200 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
1201 {
1202 s32 status = 0;
1203
1204 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
1205 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1206 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1207 } else {
1208 hw_dbg(hw, "write ee hostif failed to get semaphore");
1209 status = -EBUSY;
1210 }
1211
1212 return status;
1213 }
1214
1215 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1216 * @hw: pointer to hardware structure
1217 *
1218 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1219 **/
ixgbe_update_flash_X550(struct ixgbe_hw * hw)1220 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1221 {
1222 s32 status = 0;
1223 union ixgbe_hic_hdr2 buffer;
1224
1225 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
1226 buffer.req.buf_lenh = 0;
1227 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
1228 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
1229
1230 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1231 IXGBE_HI_COMMAND_TIMEOUT, false);
1232 return status;
1233 }
1234
1235 /**
1236 * ixgbe_get_bus_info_X550em - Set PCI bus info
1237 * @hw: pointer to hardware structure
1238 *
1239 * Sets bus link width and speed to unknown because X550em is
1240 * not a PCI device.
1241 **/
ixgbe_get_bus_info_X550em(struct ixgbe_hw * hw)1242 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1243 {
1244 hw->bus.type = ixgbe_bus_type_internal;
1245 hw->bus.width = ixgbe_bus_width_unknown;
1246 hw->bus.speed = ixgbe_bus_speed_unknown;
1247
1248 hw->mac.ops.set_lan_id(hw);
1249
1250 return 0;
1251 }
1252
1253 /**
1254 * ixgbe_fw_recovery_mode - Check FW NVM recovery mode
1255 * @hw: pointer t hardware structure
1256 *
1257 * Returns true if in FW NVM recovery mode.
1258 */
ixgbe_fw_recovery_mode_X550(struct ixgbe_hw * hw)1259 static bool ixgbe_fw_recovery_mode_X550(struct ixgbe_hw *hw)
1260 {
1261 u32 fwsm;
1262
1263 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
1264 return !!(fwsm & IXGBE_FWSM_FW_NVM_RECOVERY_MODE);
1265 }
1266
1267 /** ixgbe_disable_rx_x550 - Disable RX unit
1268 *
1269 * Enables the Rx DMA unit for x550
1270 **/
ixgbe_disable_rx_x550(struct ixgbe_hw * hw)1271 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1272 {
1273 u32 rxctrl, pfdtxgswc;
1274 s32 status;
1275 struct ixgbe_hic_disable_rxen fw_cmd;
1276
1277 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1278 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1279 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1280 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1281 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1282 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1283 hw->mac.set_lben = true;
1284 } else {
1285 hw->mac.set_lben = false;
1286 }
1287
1288 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1289 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1290 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1291 fw_cmd.port_number = hw->bus.lan_id;
1292
1293 status = ixgbe_host_interface_command(hw, &fw_cmd,
1294 sizeof(struct ixgbe_hic_disable_rxen),
1295 IXGBE_HI_COMMAND_TIMEOUT, true);
1296
1297 /* If we fail - disable RX using register write */
1298 if (status) {
1299 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1300 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1301 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1302 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1303 }
1304 }
1305 }
1306 }
1307
1308 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1309 * @hw: pointer to hardware structure
1310 *
1311 * After writing EEPROM to shadow RAM using EEWR register, software calculates
1312 * checksum and updates the EEPROM and instructs the hardware to update
1313 * the flash.
1314 **/
ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw * hw)1315 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1316 {
1317 s32 status;
1318 u16 checksum = 0;
1319
1320 /* Read the first word from the EEPROM. If this times out or fails, do
1321 * not continue or we could be in for a very long wait while every
1322 * EEPROM read fails
1323 */
1324 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1325 if (status) {
1326 hw_dbg(hw, "EEPROM read failed\n");
1327 return status;
1328 }
1329
1330 status = ixgbe_calc_eeprom_checksum_X550(hw);
1331 if (status < 0)
1332 return status;
1333
1334 checksum = (u16)(status & 0xffff);
1335
1336 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1337 checksum);
1338 if (status)
1339 return status;
1340
1341 status = ixgbe_update_flash_X550(hw);
1342
1343 return status;
1344 }
1345
1346 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1347 * @hw: pointer to hardware structure
1348 * @offset: offset of word in the EEPROM to write
1349 * @words: number of words
1350 * @data: word(s) write to the EEPROM
1351 *
1352 *
1353 * Write a 16 bit word(s) to the EEPROM using the hostif.
1354 **/
ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw * hw,u16 offset,u16 words,u16 * data)1355 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1356 u16 offset, u16 words,
1357 u16 *data)
1358 {
1359 s32 status = 0;
1360 u32 i = 0;
1361
1362 /* Take semaphore for the entire operation. */
1363 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1364 if (status) {
1365 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1366 return status;
1367 }
1368
1369 for (i = 0; i < words; i++) {
1370 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1371 data[i]);
1372 if (status) {
1373 hw_dbg(hw, "Eeprom buffered write failed\n");
1374 break;
1375 }
1376 }
1377
1378 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1379
1380 return status;
1381 }
1382
1383 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1384 * IOSF device
1385 *
1386 * @hw: pointer to hardware structure
1387 * @reg_addr: 32 bit PHY register to write
1388 * @device_type: 3 bit device type
1389 * @data: Data to write to the register
1390 **/
ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u32 data)1391 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1392 u32 device_type, u32 data)
1393 {
1394 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1395 u32 command, error;
1396 s32 ret;
1397
1398 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1399 if (ret)
1400 return ret;
1401
1402 ret = ixgbe_iosf_wait(hw, NULL);
1403 if (ret)
1404 goto out;
1405
1406 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1407 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1408
1409 /* Write IOSF control register */
1410 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1411
1412 /* Write IOSF data register */
1413 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1414
1415 ret = ixgbe_iosf_wait(hw, &command);
1416
1417 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1418 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1419 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1420 hw_dbg(hw, "Failed to write, error %x\n", error);
1421 return -EIO;
1422 }
1423
1424 out:
1425 hw->mac.ops.release_swfw_sync(hw, gssr);
1426 return ret;
1427 }
1428
1429 /**
1430 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
1431 * @hw: pointer to hardware structure
1432 *
1433 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
1434 **/
ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw * hw)1435 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
1436 {
1437 s32 status;
1438 u32 reg_val;
1439
1440 /* Disable training protocol FSM. */
1441 status = ixgbe_read_iosf_sb_reg_x550(hw,
1442 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1443 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1444 if (status)
1445 return status;
1446
1447 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1448 status = ixgbe_write_iosf_sb_reg_x550(hw,
1449 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1450 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1451 if (status)
1452 return status;
1453
1454 /* Disable Flex from training TXFFE. */
1455 status = ixgbe_read_iosf_sb_reg_x550(hw,
1456 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1457 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1458 if (status)
1459 return status;
1460
1461 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1462 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1463 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1464 status = ixgbe_write_iosf_sb_reg_x550(hw,
1465 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1466 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1467 if (status)
1468 return status;
1469
1470 status = ixgbe_read_iosf_sb_reg_x550(hw,
1471 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1472 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1473 if (status)
1474 return status;
1475
1476 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1477 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1478 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1479 status = ixgbe_write_iosf_sb_reg_x550(hw,
1480 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1481 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1482 if (status)
1483 return status;
1484
1485 /* Enable override for coefficients. */
1486 status = ixgbe_read_iosf_sb_reg_x550(hw,
1487 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1488 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1489 if (status)
1490 return status;
1491
1492 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1493 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1494 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1495 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1496 status = ixgbe_write_iosf_sb_reg_x550(hw,
1497 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1498 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1499 return status;
1500 }
1501
1502 /**
1503 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1504 * internal PHY
1505 * @hw: pointer to hardware structure
1506 **/
ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw * hw)1507 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1508 {
1509 s32 status;
1510 u32 link_ctrl;
1511
1512 /* Restart auto-negotiation. */
1513 status = hw->mac.ops.read_iosf_sb_reg(hw,
1514 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1515 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1516
1517 if (status) {
1518 hw_dbg(hw, "Auto-negotiation did not complete\n");
1519 return status;
1520 }
1521
1522 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1523 status = hw->mac.ops.write_iosf_sb_reg(hw,
1524 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1525 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1526
1527 if (hw->mac.type == ixgbe_mac_x550em_a) {
1528 u32 flx_mask_st20;
1529
1530 /* Indicate to FW that AN restart has been asserted */
1531 status = hw->mac.ops.read_iosf_sb_reg(hw,
1532 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1533 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1534
1535 if (status) {
1536 hw_dbg(hw, "Auto-negotiation did not complete\n");
1537 return status;
1538 }
1539
1540 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1541 status = hw->mac.ops.write_iosf_sb_reg(hw,
1542 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1543 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1544 }
1545
1546 return status;
1547 }
1548
1549 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1550 * @hw: pointer to hardware structure
1551 * @speed: the link speed to force
1552 *
1553 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1554 * internal and external PHY at a specific speed, without autonegotiation.
1555 **/
ixgbe_setup_ixfi_x550em(struct ixgbe_hw * hw,ixgbe_link_speed * speed)1556 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1557 {
1558 struct ixgbe_mac_info *mac = &hw->mac;
1559 s32 status;
1560 u32 reg_val;
1561
1562 /* iXFI is only supported with X552 */
1563 if (mac->type != ixgbe_mac_X550EM_x)
1564 return -EIO;
1565
1566 /* Disable AN and force speed to 10G Serial. */
1567 status = ixgbe_read_iosf_sb_reg_x550(hw,
1568 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1569 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1570 if (status)
1571 return status;
1572
1573 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1574 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1575
1576 /* Select forced link speed for internal PHY. */
1577 switch (*speed) {
1578 case IXGBE_LINK_SPEED_10GB_FULL:
1579 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1580 break;
1581 case IXGBE_LINK_SPEED_1GB_FULL:
1582 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1583 break;
1584 default:
1585 /* Other link speeds are not supported by internal KR PHY. */
1586 return -EINVAL;
1587 }
1588
1589 status = ixgbe_write_iosf_sb_reg_x550(hw,
1590 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1591 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1592 if (status)
1593 return status;
1594
1595 /* Additional configuration needed for x550em_x */
1596 if (hw->mac.type == ixgbe_mac_X550EM_x) {
1597 status = ixgbe_setup_ixfi_x550em_x(hw);
1598 if (status)
1599 return status;
1600 }
1601
1602 /* Toggle port SW reset by AN reset. */
1603 status = ixgbe_restart_an_internal_phy_x550em(hw);
1604
1605 return status;
1606 }
1607
1608 /**
1609 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1610 * @hw: pointer to hardware structure
1611 * @linear: true if SFP module is linear
1612 */
ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw * hw,bool * linear)1613 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1614 {
1615 switch (hw->phy.sfp_type) {
1616 case ixgbe_sfp_type_not_present:
1617 return -ENOENT;
1618 case ixgbe_sfp_type_da_cu_core0:
1619 case ixgbe_sfp_type_da_cu_core1:
1620 *linear = true;
1621 break;
1622 case ixgbe_sfp_type_srlr_core0:
1623 case ixgbe_sfp_type_srlr_core1:
1624 case ixgbe_sfp_type_da_act_lmt_core0:
1625 case ixgbe_sfp_type_da_act_lmt_core1:
1626 case ixgbe_sfp_type_1g_sx_core0:
1627 case ixgbe_sfp_type_1g_sx_core1:
1628 case ixgbe_sfp_type_1g_lx_core0:
1629 case ixgbe_sfp_type_1g_lx_core1:
1630 *linear = false;
1631 break;
1632 case ixgbe_sfp_type_unknown:
1633 case ixgbe_sfp_type_1g_cu_core0:
1634 case ixgbe_sfp_type_1g_cu_core1:
1635 default:
1636 return -EOPNOTSUPP;
1637 }
1638
1639 return 0;
1640 }
1641
1642 /**
1643 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1644 * @hw: pointer to hardware structure
1645 * @speed: the link speed to force
1646 * @autoneg_wait_to_complete: unused
1647 *
1648 * Configures the extern PHY and the integrated KR PHY for SFP support.
1649 */
1650 static s32
ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw * hw,ixgbe_link_speed speed,__always_unused bool autoneg_wait_to_complete)1651 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1652 ixgbe_link_speed speed,
1653 __always_unused bool autoneg_wait_to_complete)
1654 {
1655 s32 status;
1656 u16 reg_slice, reg_val;
1657 bool setup_linear = false;
1658
1659 /* Check if SFP module is supported and linear */
1660 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1661
1662 /* If no SFP module present, then return success. Return success since
1663 * there is no reason to configure CS4227 and SFP not present error is
1664 * not accepted in the setup MAC link flow.
1665 */
1666 if (status == -ENOENT)
1667 return 0;
1668
1669 if (status)
1670 return status;
1671
1672 /* Configure internal PHY for KR/KX. */
1673 ixgbe_setup_kr_speed_x550em(hw, speed);
1674
1675 /* Configure CS4227 LINE side to proper mode. */
1676 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1677 if (setup_linear)
1678 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1679 else
1680 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1681
1682 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1683 reg_val);
1684
1685 return status;
1686 }
1687
1688 /**
1689 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
1690 * @hw: pointer to hardware structure
1691 * @speed: the link speed to force
1692 *
1693 * Configures the integrated PHY for native SFI mode. Used to connect the
1694 * internal PHY directly to an SFP cage, without autonegotiation.
1695 **/
ixgbe_setup_sfi_x550a(struct ixgbe_hw * hw,ixgbe_link_speed * speed)1696 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1697 {
1698 struct ixgbe_mac_info *mac = &hw->mac;
1699 s32 status;
1700 u32 reg_val;
1701
1702 /* Disable all AN and force speed to 10G Serial. */
1703 status = mac->ops.read_iosf_sb_reg(hw,
1704 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1705 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1706 if (status)
1707 return status;
1708
1709 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1710 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1711 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1712 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1713
1714 /* Select forced link speed for internal PHY. */
1715 switch (*speed) {
1716 case IXGBE_LINK_SPEED_10GB_FULL:
1717 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
1718 break;
1719 case IXGBE_LINK_SPEED_1GB_FULL:
1720 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1721 break;
1722 default:
1723 /* Other link speeds are not supported by internal PHY. */
1724 return -EINVAL;
1725 }
1726
1727 status = mac->ops.write_iosf_sb_reg(hw,
1728 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1729 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1730
1731 /* Toggle port SW reset by AN reset. */
1732 status = ixgbe_restart_an_internal_phy_x550em(hw);
1733
1734 return status;
1735 }
1736
1737 /**
1738 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
1739 * @hw: pointer to hardware structure
1740 * @speed: link speed
1741 * @autoneg_wait_to_complete: unused
1742 *
1743 * Configure the the integrated PHY for native SFP support.
1744 */
1745 static s32
ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw * hw,ixgbe_link_speed speed,__always_unused bool autoneg_wait_to_complete)1746 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1747 __always_unused bool autoneg_wait_to_complete)
1748 {
1749 bool setup_linear = false;
1750 u32 reg_phy_int;
1751 s32 ret_val;
1752
1753 /* Check if SFP module is supported and linear */
1754 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1755
1756 /* If no SFP module present, then return success. Return success since
1757 * SFP not present error is not excepted in the setup MAC link flow.
1758 */
1759 if (ret_val == -ENOENT)
1760 return 0;
1761
1762 if (ret_val)
1763 return ret_val;
1764
1765 /* Configure internal PHY for native SFI based on module type */
1766 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
1767 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1768 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
1769 if (ret_val)
1770 return ret_val;
1771
1772 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
1773 if (!setup_linear)
1774 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
1775
1776 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
1777 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1778 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
1779 if (ret_val)
1780 return ret_val;
1781
1782 /* Setup SFI internal link. */
1783 return ixgbe_setup_sfi_x550a(hw, &speed);
1784 }
1785
1786 /**
1787 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
1788 * @hw: pointer to hardware structure
1789 * @speed: link speed
1790 * @autoneg_wait_to_complete: unused
1791 *
1792 * Configure the the integrated PHY for SFP support.
1793 */
1794 static s32
ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw * hw,ixgbe_link_speed speed,__always_unused bool autoneg_wait_to_complete)1795 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1796 __always_unused bool autoneg_wait_to_complete)
1797 {
1798 u32 reg_slice, slice_offset;
1799 bool setup_linear = false;
1800 u16 reg_phy_ext;
1801 s32 ret_val;
1802
1803 /* Check if SFP module is supported and linear */
1804 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1805
1806 /* If no SFP module present, then return success. Return success since
1807 * SFP not present error is not excepted in the setup MAC link flow.
1808 */
1809 if (ret_val == -ENOENT)
1810 return 0;
1811
1812 if (ret_val)
1813 return ret_val;
1814
1815 /* Configure internal PHY for KR/KX. */
1816 ixgbe_setup_kr_speed_x550em(hw, speed);
1817
1818 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE)
1819 return -EFAULT;
1820
1821 /* Get external PHY SKU id */
1822 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
1823 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1824 if (ret_val)
1825 return ret_val;
1826
1827 /* When configuring quad port CS4223, the MAC instance is part
1828 * of the slice offset.
1829 */
1830 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
1831 slice_offset = (hw->bus.lan_id +
1832 (hw->bus.instance_id << 1)) << 12;
1833 else
1834 slice_offset = hw->bus.lan_id << 12;
1835
1836 /* Configure CS4227/CS4223 LINE side to proper mode. */
1837 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
1838
1839 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
1840 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1841 if (ret_val)
1842 return ret_val;
1843
1844 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
1845 (IXGBE_CS4227_EDC_MODE_SR << 1));
1846
1847 if (setup_linear)
1848 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1849 else
1850 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1851
1852 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
1853 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
1854 if (ret_val)
1855 return ret_val;
1856
1857 /* Flush previous write with a read */
1858 return hw->phy.ops.read_reg(hw, reg_slice,
1859 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1860 }
1861
1862 /**
1863 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1864 * @hw: pointer to hardware structure
1865 * @speed: new link speed
1866 * @autoneg_wait: true when waiting for completion is needed
1867 *
1868 * Setup internal/external PHY link speed based on link speed, then set
1869 * external PHY auto advertised link speed.
1870 *
1871 * Returns error status for any failure
1872 **/
ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait)1873 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1874 ixgbe_link_speed speed,
1875 bool autoneg_wait)
1876 {
1877 s32 status;
1878 ixgbe_link_speed force_speed;
1879
1880 /* Setup internal/external PHY link speed to iXFI (10G), unless
1881 * only 1G is auto advertised then setup KX link.
1882 */
1883 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1884 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1885 else
1886 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1887
1888 /* If X552 and internal link mode is XFI, then setup XFI internal link.
1889 */
1890 if (hw->mac.type == ixgbe_mac_X550EM_x &&
1891 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1892 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1893
1894 if (status)
1895 return status;
1896 }
1897
1898 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1899 }
1900
1901 /** ixgbe_check_link_t_X550em - Determine link and speed status
1902 * @hw: pointer to hardware structure
1903 * @speed: pointer to link speed
1904 * @link_up: true when link is up
1905 * @link_up_wait_to_complete: bool used to wait for link up or not
1906 *
1907 * Check that both the MAC and X557 external PHY have link.
1908 **/
ixgbe_check_link_t_X550em(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up,bool link_up_wait_to_complete)1909 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1910 ixgbe_link_speed *speed,
1911 bool *link_up,
1912 bool link_up_wait_to_complete)
1913 {
1914 u32 status;
1915 u16 i, autoneg_status;
1916
1917 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1918 return -EIO;
1919
1920 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1921 link_up_wait_to_complete);
1922
1923 /* If check link fails or MAC link is not up, then return */
1924 if (status || !(*link_up))
1925 return status;
1926
1927 /* MAC link is up, so check external PHY link.
1928 * Link status is latching low, and can only be used to detect link
1929 * drop, and not the current status of the link without performing
1930 * back-to-back reads.
1931 */
1932 for (i = 0; i < 2; i++) {
1933 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
1934 &autoneg_status);
1935
1936 if (status)
1937 return status;
1938 }
1939
1940 /* If external PHY link is not up, then indicate link not up */
1941 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1942 *link_up = false;
1943
1944 return 0;
1945 }
1946
1947 /**
1948 * ixgbe_setup_sgmii - Set up link for sgmii
1949 * @hw: pointer to hardware structure
1950 * @speed: unused
1951 * @autoneg_wait_to_complete: unused
1952 */
1953 static s32
ixgbe_setup_sgmii(struct ixgbe_hw * hw,__always_unused ixgbe_link_speed speed,__always_unused bool autoneg_wait_to_complete)1954 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed,
1955 __always_unused bool autoneg_wait_to_complete)
1956 {
1957 struct ixgbe_mac_info *mac = &hw->mac;
1958 u32 lval, sval, flx_val;
1959 s32 rc;
1960
1961 rc = mac->ops.read_iosf_sb_reg(hw,
1962 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1963 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1964 if (rc)
1965 return rc;
1966
1967 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1968 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1969 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1970 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1971 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1972 rc = mac->ops.write_iosf_sb_reg(hw,
1973 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1974 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1975 if (rc)
1976 return rc;
1977
1978 rc = mac->ops.read_iosf_sb_reg(hw,
1979 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1980 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1981 if (rc)
1982 return rc;
1983
1984 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1985 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1986 rc = mac->ops.write_iosf_sb_reg(hw,
1987 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1988 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1989 if (rc)
1990 return rc;
1991
1992 rc = mac->ops.read_iosf_sb_reg(hw,
1993 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1994 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1995 if (rc)
1996 return rc;
1997
1998 rc = mac->ops.read_iosf_sb_reg(hw,
1999 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2000 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2001 if (rc)
2002 return rc;
2003
2004 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2005 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2006 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2007 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2008 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2009
2010 rc = mac->ops.write_iosf_sb_reg(hw,
2011 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2012 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2013 if (rc)
2014 return rc;
2015
2016 rc = ixgbe_restart_an_internal_phy_x550em(hw);
2017 return rc;
2018 }
2019
2020 /**
2021 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
2022 * @hw: pointer to hardware structure
2023 * @speed: the link speed to force
2024 * @autoneg_wait: true when waiting for completion is needed
2025 */
ixgbe_setup_sgmii_fw(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait)2026 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
2027 bool autoneg_wait)
2028 {
2029 struct ixgbe_mac_info *mac = &hw->mac;
2030 u32 lval, sval, flx_val;
2031 s32 rc;
2032
2033 rc = mac->ops.read_iosf_sb_reg(hw,
2034 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2035 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
2036 if (rc)
2037 return rc;
2038
2039 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2040 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2041 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
2042 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
2043 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2044 rc = mac->ops.write_iosf_sb_reg(hw,
2045 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2046 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2047 if (rc)
2048 return rc;
2049
2050 rc = mac->ops.read_iosf_sb_reg(hw,
2051 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2052 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
2053 if (rc)
2054 return rc;
2055
2056 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
2057 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
2058 rc = mac->ops.write_iosf_sb_reg(hw,
2059 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2060 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
2061 if (rc)
2062 return rc;
2063
2064 rc = mac->ops.write_iosf_sb_reg(hw,
2065 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2066 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2067 if (rc)
2068 return rc;
2069
2070 rc = mac->ops.read_iosf_sb_reg(hw,
2071 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2072 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2073 if (rc)
2074 return rc;
2075
2076 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2077 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2078 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2079 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2080 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2081
2082 rc = mac->ops.write_iosf_sb_reg(hw,
2083 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2084 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2085 if (rc)
2086 return rc;
2087
2088 ixgbe_restart_an_internal_phy_x550em(hw);
2089
2090 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
2091 }
2092
2093 /**
2094 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
2095 * @hw: pointer to hardware structure
2096 *
2097 * Enable flow control according to IEEE clause 37.
2098 */
ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw * hw)2099 static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
2100 {
2101 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
2102 ixgbe_link_speed speed;
2103 s32 status = -EIO;
2104 bool link_up;
2105
2106 /* AN should have completed when the cable was plugged in.
2107 * Look for reasons to bail out. Bail out if:
2108 * - FC autoneg is disabled, or if
2109 * - link is not up.
2110 */
2111 if (hw->fc.disable_fc_autoneg)
2112 goto out;
2113
2114 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2115 if (!link_up)
2116 goto out;
2117
2118 /* Check if auto-negotiation has completed */
2119 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
2120 if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
2121 status = -EIO;
2122 goto out;
2123 }
2124
2125 /* Negotiate the flow control */
2126 status = ixgbe_negotiate_fc(hw, info[0], info[0],
2127 FW_PHY_ACT_GET_LINK_INFO_FC_RX,
2128 FW_PHY_ACT_GET_LINK_INFO_FC_TX,
2129 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
2130 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
2131
2132 out:
2133 if (!status) {
2134 hw->fc.fc_was_autonegged = true;
2135 } else {
2136 hw->fc.fc_was_autonegged = false;
2137 hw->fc.current_mode = hw->fc.requested_mode;
2138 }
2139 }
2140
2141 /** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers
2142 * @hw: pointer to hardware structure
2143 **/
ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw * hw)2144 static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw)
2145 {
2146 struct ixgbe_mac_info *mac = &hw->mac;
2147
2148 switch (mac->ops.get_media_type(hw)) {
2149 case ixgbe_media_type_fiber:
2150 mac->ops.setup_fc = NULL;
2151 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
2152 break;
2153 case ixgbe_media_type_copper:
2154 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T &&
2155 hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) {
2156 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2157 break;
2158 }
2159 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
2160 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
2161 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
2162 mac->ops.check_link = ixgbe_check_mac_link_generic;
2163 break;
2164 case ixgbe_media_type_backplane:
2165 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
2166 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
2167 break;
2168 default:
2169 break;
2170 }
2171 }
2172
2173 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
2174 * @hw: pointer to hardware structure
2175 **/
ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw * hw)2176 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
2177 {
2178 struct ixgbe_mac_info *mac = &hw->mac;
2179
2180 mac->ops.setup_fc = ixgbe_setup_fc_x550em;
2181
2182 switch (mac->ops.get_media_type(hw)) {
2183 case ixgbe_media_type_fiber:
2184 /* CS4227 does not support autoneg, so disable the laser control
2185 * functions for SFP+ fiber
2186 */
2187 mac->ops.disable_tx_laser = NULL;
2188 mac->ops.enable_tx_laser = NULL;
2189 mac->ops.flap_tx_laser = NULL;
2190 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
2191 switch (hw->device_id) {
2192 case IXGBE_DEV_ID_X550EM_A_SFP_N:
2193 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n;
2194 break;
2195 case IXGBE_DEV_ID_X550EM_A_SFP:
2196 mac->ops.setup_mac_link =
2197 ixgbe_setup_mac_link_sfp_x550a;
2198 break;
2199 default:
2200 mac->ops.setup_mac_link =
2201 ixgbe_setup_mac_link_sfp_x550em;
2202 break;
2203 }
2204 mac->ops.set_rate_select_speed =
2205 ixgbe_set_soft_rate_select_speed;
2206 break;
2207 case ixgbe_media_type_copper:
2208 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
2209 break;
2210 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2211 mac->ops.setup_fc = ixgbe_setup_fc_generic;
2212 mac->ops.check_link = ixgbe_check_link_t_X550em;
2213 break;
2214 case ixgbe_media_type_backplane:
2215 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
2216 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
2217 mac->ops.setup_link = ixgbe_setup_sgmii;
2218 break;
2219 default:
2220 break;
2221 }
2222
2223 /* Additional modification for X550em_a devices */
2224 if (hw->mac.type == ixgbe_mac_x550em_a)
2225 ixgbe_init_mac_link_ops_X550em_a(hw);
2226 }
2227
2228 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
2229 * @hw: pointer to hardware structure
2230 */
ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw * hw)2231 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
2232 {
2233 s32 status;
2234 bool linear;
2235
2236 /* Check if SFP module is supported */
2237 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
2238 if (status)
2239 return status;
2240
2241 ixgbe_init_mac_link_ops_X550em(hw);
2242 hw->phy.ops.reset = NULL;
2243
2244 return 0;
2245 }
2246
2247 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
2248 * @hw: pointer to hardware structure
2249 * @speed: pointer to link speed
2250 * @autoneg: true when autoneg or autotry is enabled
2251 **/
ixgbe_get_link_capabilities_X550em(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * autoneg)2252 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
2253 ixgbe_link_speed *speed,
2254 bool *autoneg)
2255 {
2256 if (hw->phy.type == ixgbe_phy_fw) {
2257 *autoneg = true;
2258 *speed = hw->phy.speeds_supported;
2259 return 0;
2260 }
2261
2262 /* SFP */
2263 if (hw->phy.media_type == ixgbe_media_type_fiber) {
2264 /* CS4227 SFP must not enable auto-negotiation */
2265 *autoneg = false;
2266
2267 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
2268 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
2269 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
2270 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
2271 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2272 return 0;
2273 }
2274
2275 /* Link capabilities are based on SFP */
2276 if (hw->phy.multispeed_fiber)
2277 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2278 IXGBE_LINK_SPEED_1GB_FULL;
2279 else
2280 *speed = IXGBE_LINK_SPEED_10GB_FULL;
2281 } else {
2282 switch (hw->phy.type) {
2283 case ixgbe_phy_x550em_kx4:
2284 *speed = IXGBE_LINK_SPEED_1GB_FULL |
2285 IXGBE_LINK_SPEED_2_5GB_FULL |
2286 IXGBE_LINK_SPEED_10GB_FULL;
2287 break;
2288 case ixgbe_phy_x550em_xfi:
2289 *speed = IXGBE_LINK_SPEED_1GB_FULL |
2290 IXGBE_LINK_SPEED_10GB_FULL;
2291 break;
2292 case ixgbe_phy_ext_1g_t:
2293 case ixgbe_phy_sgmii:
2294 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2295 break;
2296 case ixgbe_phy_x550em_kr:
2297 if (hw->mac.type == ixgbe_mac_x550em_a) {
2298 /* check different backplane modes */
2299 if (hw->phy.nw_mng_if_sel &
2300 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
2301 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
2302 break;
2303 } else if (hw->device_id ==
2304 IXGBE_DEV_ID_X550EM_A_KR_L) {
2305 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2306 break;
2307 }
2308 }
2309 fallthrough;
2310 default:
2311 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2312 IXGBE_LINK_SPEED_1GB_FULL;
2313 break;
2314 }
2315 *autoneg = true;
2316 }
2317 return 0;
2318 }
2319
2320 /**
2321 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2322 * @hw: pointer to hardware structure
2323 * @lsc: pointer to boolean flag which indicates whether external Base T
2324 * PHY interrupt is lsc
2325 * @is_overtemp: indicate whether an overtemp event encountered
2326 *
2327 * Determime if external Base T PHY interrupt cause is high temperature
2328 * failure alarm or link status change.
2329 **/
ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw * hw,bool * lsc,bool * is_overtemp)2330 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc,
2331 bool *is_overtemp)
2332 {
2333 u32 status;
2334 u16 reg;
2335
2336 *is_overtemp = false;
2337 *lsc = false;
2338
2339 /* Vendor alarm triggered */
2340 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2341 MDIO_MMD_VEND1,
2342 ®);
2343
2344 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2345 return status;
2346
2347 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2348 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2349 MDIO_MMD_VEND1,
2350 ®);
2351
2352 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2353 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2354 return status;
2355
2356 /* Global alarm triggered */
2357 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2358 MDIO_MMD_VEND1,
2359 ®);
2360
2361 if (status)
2362 return status;
2363
2364 /* If high temperature failure, then return over temp error and exit */
2365 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2366 /* power down the PHY in case the PHY FW didn't already */
2367 ixgbe_set_copper_phy_power(hw, false);
2368 *is_overtemp = true;
2369 return -EIO;
2370 }
2371 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2372 /* device fault alarm triggered */
2373 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2374 MDIO_MMD_VEND1,
2375 ®);
2376 if (status)
2377 return status;
2378
2379 /* if device fault was due to high temp alarm handle and exit */
2380 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2381 /* power down the PHY in case the PHY FW didn't */
2382 ixgbe_set_copper_phy_power(hw, false);
2383 *is_overtemp = true;
2384 return -EIO;
2385 }
2386 }
2387
2388 /* Vendor alarm 2 triggered */
2389 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2390 MDIO_MMD_AN, ®);
2391
2392 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2393 return status;
2394
2395 /* link connect/disconnect event occurred */
2396 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2397 MDIO_MMD_AN, ®);
2398
2399 if (status)
2400 return status;
2401
2402 /* Indicate LSC */
2403 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2404 *lsc = true;
2405
2406 return 0;
2407 }
2408
2409 /**
2410 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2411 * @hw: pointer to hardware structure
2412 *
2413 * Enable link status change and temperature failure alarm for the external
2414 * Base T PHY
2415 *
2416 * Returns PHY access status
2417 **/
ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw * hw)2418 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2419 {
2420 bool lsc, overtemp;
2421 u32 status;
2422 u16 reg;
2423
2424 /* Clear interrupt flags */
2425 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc, &overtemp);
2426
2427 /* Enable link status change alarm */
2428
2429 /* Enable the LASI interrupts on X552 devices to receive notifications
2430 * of the link configurations of the external PHY and correspondingly
2431 * support the configuration of the internal iXFI link, since iXFI does
2432 * not support auto-negotiation. This is not required for X553 devices
2433 * having KR support, which performs auto-negotiations and which is used
2434 * as the internal link to the external PHY. Hence adding a check here
2435 * to avoid enabling LASI interrupts for X553 devices.
2436 */
2437 if (hw->mac.type != ixgbe_mac_x550em_a) {
2438 status = hw->phy.ops.read_reg(hw,
2439 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2440 MDIO_MMD_AN, ®);
2441 if (status)
2442 return status;
2443
2444 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2445
2446 status = hw->phy.ops.write_reg(hw,
2447 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2448 MDIO_MMD_AN, reg);
2449 if (status)
2450 return status;
2451 }
2452
2453 /* Enable high temperature failure and global fault alarms */
2454 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2455 MDIO_MMD_VEND1,
2456 ®);
2457 if (status)
2458 return status;
2459
2460 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2461 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2462
2463 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2464 MDIO_MMD_VEND1,
2465 reg);
2466 if (status)
2467 return status;
2468
2469 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2470 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2471 MDIO_MMD_VEND1,
2472 ®);
2473 if (status)
2474 return status;
2475
2476 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2477 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2478
2479 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2480 MDIO_MMD_VEND1,
2481 reg);
2482 if (status)
2483 return status;
2484
2485 /* Enable chip-wide vendor alarm */
2486 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2487 MDIO_MMD_VEND1,
2488 ®);
2489 if (status)
2490 return status;
2491
2492 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2493
2494 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2495 MDIO_MMD_VEND1,
2496 reg);
2497
2498 return status;
2499 }
2500
2501 /**
2502 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2503 * @hw: pointer to hardware structure
2504 * @is_overtemp: indicate whether an overtemp event encountered
2505 *
2506 * Handle external Base T PHY interrupt. If high temperature
2507 * failure alarm then return error, else if link status change
2508 * then setup internal/external PHY link
2509 **/
ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw * hw,bool * is_overtemp)2510 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw,
2511 bool *is_overtemp)
2512 {
2513 struct ixgbe_phy_info *phy = &hw->phy;
2514 bool lsc;
2515 u32 status;
2516
2517 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc, is_overtemp);
2518 if (status)
2519 return status;
2520
2521 if (lsc && phy->ops.setup_internal_link)
2522 return phy->ops.setup_internal_link(hw);
2523
2524 return 0;
2525 }
2526
2527 /**
2528 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2529 * @hw: pointer to hardware structure
2530 * @speed: link speed
2531 *
2532 * Configures the integrated KR PHY.
2533 **/
ixgbe_setup_kr_speed_x550em(struct ixgbe_hw * hw,ixgbe_link_speed speed)2534 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2535 ixgbe_link_speed speed)
2536 {
2537 s32 status;
2538 u32 reg_val;
2539
2540 status = hw->mac.ops.read_iosf_sb_reg(hw,
2541 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2542 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2543 if (status)
2544 return status;
2545
2546 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2547 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2548 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2549
2550 /* Advertise 10G support. */
2551 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2552 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2553
2554 /* Advertise 1G support. */
2555 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2556 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2557
2558 status = hw->mac.ops.write_iosf_sb_reg(hw,
2559 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2560 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2561
2562 if (hw->mac.type == ixgbe_mac_x550em_a) {
2563 /* Set lane mode to KR auto negotiation */
2564 status = hw->mac.ops.read_iosf_sb_reg(hw,
2565 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2566 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2567
2568 if (status)
2569 return status;
2570
2571 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2572 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2573 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2574 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2575 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2576
2577 status = hw->mac.ops.write_iosf_sb_reg(hw,
2578 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2579 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2580 }
2581
2582 return ixgbe_restart_an_internal_phy_x550em(hw);
2583 }
2584
2585 /**
2586 * ixgbe_setup_kr_x550em - Configure the KR PHY
2587 * @hw: pointer to hardware structure
2588 **/
ixgbe_setup_kr_x550em(struct ixgbe_hw * hw)2589 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2590 {
2591 /* leave link alone for 2.5G */
2592 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2593 return 0;
2594
2595 if (ixgbe_check_reset_blocked(hw))
2596 return 0;
2597
2598 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2599 }
2600
2601 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2602 * @hw: address of hardware structure
2603 * @link_up: address of boolean to indicate link status
2604 *
2605 * Returns error code if unable to get link status.
2606 **/
ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw * hw,bool * link_up)2607 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2608 {
2609 u32 ret;
2610 u16 autoneg_status;
2611
2612 *link_up = false;
2613
2614 /* read this twice back to back to indicate current status */
2615 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2616 &autoneg_status);
2617 if (ret)
2618 return ret;
2619
2620 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2621 &autoneg_status);
2622 if (ret)
2623 return ret;
2624
2625 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2626
2627 return 0;
2628 }
2629
2630 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2631 * @hw: point to hardware structure
2632 *
2633 * Configures the link between the integrated KR PHY and the external X557 PHY
2634 * The driver will call this function when it gets a link status change
2635 * interrupt from the X557 PHY. This function configures the link speed
2636 * between the PHYs to match the link speed of the BASE-T link.
2637 *
2638 * A return of a non-zero value indicates an error, and the base driver should
2639 * not report link up.
2640 **/
ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw * hw)2641 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2642 {
2643 ixgbe_link_speed force_speed;
2644 bool link_up;
2645 u32 status;
2646 u16 speed;
2647
2648 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2649 return -EIO;
2650
2651 if (!(hw->mac.type == ixgbe_mac_X550EM_x &&
2652 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) {
2653 speed = IXGBE_LINK_SPEED_10GB_FULL |
2654 IXGBE_LINK_SPEED_1GB_FULL;
2655 return ixgbe_setup_kr_speed_x550em(hw, speed);
2656 }
2657
2658 /* If link is not up, then there is no setup necessary so return */
2659 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2660 if (status)
2661 return status;
2662
2663 if (!link_up)
2664 return 0;
2665
2666 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2667 MDIO_MMD_AN,
2668 &speed);
2669 if (status)
2670 return status;
2671
2672 /* If link is not still up, then no setup is necessary so return */
2673 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2674 if (status)
2675 return status;
2676
2677 if (!link_up)
2678 return 0;
2679
2680 /* clear everything but the speed and duplex bits */
2681 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2682
2683 switch (speed) {
2684 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2685 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2686 break;
2687 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2688 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2689 break;
2690 default:
2691 /* Internal PHY does not support anything else */
2692 return -EINVAL;
2693 }
2694
2695 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2696 }
2697
2698 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2699 * @hw: pointer to hardware structure
2700 **/
ixgbe_reset_phy_t_X550em(struct ixgbe_hw * hw)2701 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2702 {
2703 s32 status;
2704
2705 status = ixgbe_reset_phy_generic(hw);
2706
2707 if (status)
2708 return status;
2709
2710 /* Configure Link Status Alarm and Temperature Threshold interrupts */
2711 return ixgbe_enable_lasi_ext_t_x550em(hw);
2712 }
2713
2714 /**
2715 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs.
2716 * @hw: pointer to hardware structure
2717 * @led_idx: led number to turn on
2718 **/
ixgbe_led_on_t_x550em(struct ixgbe_hw * hw,u32 led_idx)2719 static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2720 {
2721 u16 phy_data;
2722
2723 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2724 return -EINVAL;
2725
2726 /* To turn on the LED, set mode to ON. */
2727 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2728 MDIO_MMD_VEND1, &phy_data);
2729 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
2730 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2731 MDIO_MMD_VEND1, phy_data);
2732
2733 return 0;
2734 }
2735
2736 /**
2737 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs.
2738 * @hw: pointer to hardware structure
2739 * @led_idx: led number to turn off
2740 **/
ixgbe_led_off_t_x550em(struct ixgbe_hw * hw,u32 led_idx)2741 static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2742 {
2743 u16 phy_data;
2744
2745 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2746 return -EINVAL;
2747
2748 /* To turn on the LED, set mode to ON. */
2749 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2750 MDIO_MMD_VEND1, &phy_data);
2751 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
2752 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2753 MDIO_MMD_VEND1, phy_data);
2754
2755 return 0;
2756 }
2757
2758 /**
2759 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
2760 * @hw: pointer to the HW structure
2761 * @maj: driver version major number
2762 * @min: driver version minor number
2763 * @build: driver version build number
2764 * @sub: driver version sub build number
2765 * @len: length of driver_ver string
2766 * @driver_ver: driver string
2767 *
2768 * Sends driver version number to firmware through the manageability
2769 * block. On success return 0
2770 * else returns -EBUSY when encountering an error acquiring
2771 * semaphore, -EIO when command fails or -ENIVAL when incorrect
2772 * params passed.
2773 **/
ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw * hw,u8 maj,u8 min,u8 build,u8 sub,u16 len,const char * driver_ver)2774 static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
2775 u8 build, u8 sub, u16 len,
2776 const char *driver_ver)
2777 {
2778 struct ixgbe_hic_drv_info2 fw_cmd;
2779 s32 ret_val;
2780 int i;
2781
2782 if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string)))
2783 return -EINVAL;
2784
2785 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
2786 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
2787 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
2788 fw_cmd.port_num = (u8)hw->bus.func;
2789 fw_cmd.ver_maj = maj;
2790 fw_cmd.ver_min = min;
2791 fw_cmd.ver_build = build;
2792 fw_cmd.ver_sub = sub;
2793 fw_cmd.hdr.checksum = 0;
2794 memcpy(fw_cmd.driver_string, driver_ver, len);
2795 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
2796 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
2797
2798 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
2799 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2800 sizeof(fw_cmd),
2801 IXGBE_HI_COMMAND_TIMEOUT,
2802 true);
2803 if (ret_val)
2804 continue;
2805
2806 if (fw_cmd.hdr.cmd_or_resp.ret_status !=
2807 FW_CEM_RESP_STATUS_SUCCESS)
2808 return -EIO;
2809 return 0;
2810 }
2811
2812 return ret_val;
2813 }
2814
2815 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
2816 * @hw: pointer to hardware structure
2817 * @lcd_speed: pointer to lowest common link speed
2818 *
2819 * Determine lowest common link speed with link partner.
2820 **/
ixgbe_get_lcd_t_x550em(struct ixgbe_hw * hw,ixgbe_link_speed * lcd_speed)2821 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
2822 ixgbe_link_speed *lcd_speed)
2823 {
2824 u16 an_lp_status;
2825 s32 status;
2826 u16 word = hw->eeprom.ctrl_word_3;
2827
2828 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2829
2830 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2831 MDIO_MMD_AN,
2832 &an_lp_status);
2833 if (status)
2834 return status;
2835
2836 /* If link partner advertised 1G, return 1G */
2837 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2838 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2839 return status;
2840 }
2841
2842 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2843 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2844 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2845 return status;
2846
2847 /* Link partner not capable of lower speeds, return 10G */
2848 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2849 return status;
2850 }
2851
2852 /**
2853 * ixgbe_setup_fc_x550em - Set up flow control
2854 * @hw: pointer to hardware structure
2855 */
ixgbe_setup_fc_x550em(struct ixgbe_hw * hw)2856 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
2857 {
2858 bool pause, asm_dir;
2859 u32 reg_val;
2860 s32 rc = 0;
2861
2862 /* Validate the requested mode */
2863 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2864 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2865 return -EINVAL;
2866 }
2867
2868 /* 10gig parts do not have a word in the EEPROM to determine the
2869 * default flow control setting, so we explicitly set it to full.
2870 */
2871 if (hw->fc.requested_mode == ixgbe_fc_default)
2872 hw->fc.requested_mode = ixgbe_fc_full;
2873
2874 /* Determine PAUSE and ASM_DIR bits. */
2875 switch (hw->fc.requested_mode) {
2876 case ixgbe_fc_none:
2877 pause = false;
2878 asm_dir = false;
2879 break;
2880 case ixgbe_fc_tx_pause:
2881 pause = false;
2882 asm_dir = true;
2883 break;
2884 case ixgbe_fc_rx_pause:
2885 /* Rx Flow control is enabled and Tx Flow control is
2886 * disabled by software override. Since there really
2887 * isn't a way to advertise that we are capable of RX
2888 * Pause ONLY, we will advertise that we support both
2889 * symmetric and asymmetric Rx PAUSE, as such we fall
2890 * through to the fc_full statement. Later, we will
2891 * disable the adapter's ability to send PAUSE frames.
2892 */
2893 fallthrough;
2894 case ixgbe_fc_full:
2895 pause = true;
2896 asm_dir = true;
2897 break;
2898 default:
2899 hw_err(hw, "Flow control param set incorrectly\n");
2900 return -EIO;
2901 }
2902
2903 switch (hw->device_id) {
2904 case IXGBE_DEV_ID_X550EM_X_KR:
2905 case IXGBE_DEV_ID_X550EM_A_KR:
2906 case IXGBE_DEV_ID_X550EM_A_KR_L:
2907 rc = hw->mac.ops.read_iosf_sb_reg(hw,
2908 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2909 IXGBE_SB_IOSF_TARGET_KR_PHY,
2910 ®_val);
2911 if (rc)
2912 return rc;
2913
2914 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2915 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2916 if (pause)
2917 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2918 if (asm_dir)
2919 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2920 rc = hw->mac.ops.write_iosf_sb_reg(hw,
2921 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2922 IXGBE_SB_IOSF_TARGET_KR_PHY,
2923 reg_val);
2924
2925 /* This device does not fully support AN. */
2926 hw->fc.disable_fc_autoneg = true;
2927 break;
2928 case IXGBE_DEV_ID_X550EM_X_XFI:
2929 hw->fc.disable_fc_autoneg = true;
2930 break;
2931 default:
2932 break;
2933 }
2934 return rc;
2935 }
2936
2937 /**
2938 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
2939 * @hw: pointer to hardware structure
2940 **/
ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw * hw)2941 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
2942 {
2943 u32 link_s1, lp_an_page_low, an_cntl_1;
2944 ixgbe_link_speed speed;
2945 s32 status = -EIO;
2946 bool link_up;
2947
2948 /* AN should have completed when the cable was plugged in.
2949 * Look for reasons to bail out. Bail out if:
2950 * - FC autoneg is disabled, or if
2951 * - link is not up.
2952 */
2953 if (hw->fc.disable_fc_autoneg) {
2954 hw_err(hw, "Flow control autoneg is disabled");
2955 goto out;
2956 }
2957
2958 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2959 if (!link_up) {
2960 hw_err(hw, "The link is down");
2961 goto out;
2962 }
2963
2964 /* Check at auto-negotiation has completed */
2965 status = hw->mac.ops.read_iosf_sb_reg(hw,
2966 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
2967 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
2968
2969 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
2970 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2971 status = -EIO;
2972 goto out;
2973 }
2974
2975 /* Read the 10g AN autoc and LP ability registers and resolve
2976 * local flow control settings accordingly
2977 */
2978 status = hw->mac.ops.read_iosf_sb_reg(hw,
2979 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2980 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
2981
2982 if (status) {
2983 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2984 goto out;
2985 }
2986
2987 status = hw->mac.ops.read_iosf_sb_reg(hw,
2988 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
2989 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
2990
2991 if (status) {
2992 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2993 goto out;
2994 }
2995
2996 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
2997 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
2998 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
2999 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
3000 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
3001
3002 out:
3003 if (!status) {
3004 hw->fc.fc_was_autonegged = true;
3005 } else {
3006 hw->fc.fc_was_autonegged = false;
3007 hw->fc.current_mode = hw->fc.requested_mode;
3008 }
3009 }
3010
3011 /**
3012 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
3013 * @hw: pointer to hardware structure
3014 **/
ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw * hw)3015 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
3016 {
3017 hw->fc.fc_was_autonegged = false;
3018 hw->fc.current_mode = hw->fc.requested_mode;
3019 }
3020
3021 /** ixgbe_enter_lplu_x550em - Transition to low power states
3022 * @hw: pointer to hardware structure
3023 *
3024 * Configures Low Power Link Up on transition to low power states
3025 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
3026 * the X557 PHY immediately prior to entering LPLU.
3027 **/
ixgbe_enter_lplu_t_x550em(struct ixgbe_hw * hw)3028 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3029 {
3030 u16 an_10g_cntl_reg, autoneg_reg, speed;
3031 s32 status;
3032 ixgbe_link_speed lcd_speed;
3033 u32 save_autoneg;
3034 bool link_up;
3035
3036 /* If blocked by MNG FW, then don't restart AN */
3037 if (ixgbe_check_reset_blocked(hw))
3038 return 0;
3039
3040 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3041 if (status)
3042 return status;
3043
3044 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
3045 &hw->eeprom.ctrl_word_3);
3046 if (status)
3047 return status;
3048
3049 /* If link is down, LPLU disabled in NVM, WoL disabled, or
3050 * manageability disabled, then force link down by entering
3051 * low power mode.
3052 */
3053 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3054 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3055 return ixgbe_set_copper_phy_power(hw, false);
3056
3057 /* Determine LCD */
3058 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3059 if (status)
3060 return status;
3061
3062 /* If no valid LCD link speed, then force link down and exit. */
3063 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3064 return ixgbe_set_copper_phy_power(hw, false);
3065
3066 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3067 MDIO_MMD_AN,
3068 &speed);
3069 if (status)
3070 return status;
3071
3072 /* If no link now, speed is invalid so take link down */
3073 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3074 if (status)
3075 return ixgbe_set_copper_phy_power(hw, false);
3076
3077 /* clear everything but the speed bits */
3078 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3079
3080 /* If current speed is already LCD, then exit. */
3081 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3082 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3083 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3084 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3085 return status;
3086
3087 /* Clear AN completed indication */
3088 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3089 MDIO_MMD_AN,
3090 &autoneg_reg);
3091 if (status)
3092 return status;
3093
3094 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
3095 MDIO_MMD_AN,
3096 &an_10g_cntl_reg);
3097 if (status)
3098 return status;
3099
3100 status = hw->phy.ops.read_reg(hw,
3101 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3102 MDIO_MMD_AN,
3103 &autoneg_reg);
3104 if (status)
3105 return status;
3106
3107 save_autoneg = hw->phy.autoneg_advertised;
3108
3109 /* Setup link at least common link speed */
3110 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3111
3112 /* restore autoneg from before setting lplu speed */
3113 hw->phy.autoneg_advertised = save_autoneg;
3114
3115 return status;
3116 }
3117
3118 /**
3119 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
3120 * @hw: pointer to hardware structure
3121 */
ixgbe_reset_phy_fw(struct ixgbe_hw * hw)3122 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
3123 {
3124 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3125 s32 rc;
3126
3127 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
3128 return 0;
3129
3130 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
3131 if (rc)
3132 return rc;
3133 memset(store, 0, sizeof(store));
3134
3135 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
3136 if (rc)
3137 return rc;
3138
3139 return ixgbe_setup_fw_link(hw);
3140 }
3141
3142 /**
3143 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
3144 * @hw: pointer to hardware structure
3145 *
3146 * Return true when an overtemp event detected, otherwise false.
3147 */
ixgbe_check_overtemp_fw(struct ixgbe_hw * hw)3148 static bool ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
3149 {
3150 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3151 s32 rc;
3152
3153 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
3154 if (rc)
3155 return false;
3156
3157 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
3158 ixgbe_shutdown_fw_phy(hw);
3159 return true;
3160 }
3161 return false;
3162 }
3163
3164 /**
3165 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
3166 * @hw: pointer to hardware structure
3167 *
3168 * Read NW_MNG_IF_SEL register and save field values.
3169 */
ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw * hw)3170 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
3171 {
3172 /* Save NW management interface connected on board. This is used
3173 * to determine internal PHY mode.
3174 */
3175 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3176
3177 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
3178 * PHY address. This register field was has only been used for X552.
3179 */
3180 if (hw->mac.type == ixgbe_mac_x550em_a &&
3181 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
3182 hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel &
3183 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
3184 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
3185 }
3186 }
3187
3188 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
3189 * @hw: pointer to hardware structure
3190 *
3191 * Initialize any function pointers that were not able to be
3192 * set during init_shared_code because the PHY/SFP type was
3193 * not known. Perform the SFP init if necessary.
3194 **/
ixgbe_init_phy_ops_X550em(struct ixgbe_hw * hw)3195 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
3196 {
3197 struct ixgbe_phy_info *phy = &hw->phy;
3198 s32 ret_val;
3199
3200 hw->mac.ops.set_lan_id(hw);
3201
3202 ixgbe_read_mng_if_sel_x550em(hw);
3203
3204 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
3205 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
3206 ixgbe_setup_mux_ctl(hw);
3207 }
3208
3209 /* Identify the PHY or SFP module */
3210 ret_val = phy->ops.identify(hw);
3211 if (ret_val == -EOPNOTSUPP || ret_val == -EFAULT)
3212 return ret_val;
3213
3214 /* Setup function pointers based on detected hardware */
3215 ixgbe_init_mac_link_ops_X550em(hw);
3216 if (phy->sfp_type != ixgbe_sfp_type_unknown)
3217 phy->ops.reset = NULL;
3218
3219 /* Set functions pointers based on phy type */
3220 switch (hw->phy.type) {
3221 case ixgbe_phy_x550em_kx4:
3222 phy->ops.setup_link = NULL;
3223 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3224 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3225 break;
3226 case ixgbe_phy_x550em_kr:
3227 phy->ops.setup_link = ixgbe_setup_kr_x550em;
3228 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3229 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3230 break;
3231 case ixgbe_phy_x550em_xfi:
3232 /* link is managed by HW */
3233 phy->ops.setup_link = NULL;
3234 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3235 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3236 break;
3237 case ixgbe_phy_x550em_ext_t:
3238 /* Save NW management interface connected on board. This is used
3239 * to determine internal PHY mode
3240 */
3241 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3242
3243 /* If internal link mode is XFI, then setup iXFI internal link,
3244 * else setup KR now.
3245 */
3246 phy->ops.setup_internal_link =
3247 ixgbe_setup_internal_phy_t_x550em;
3248
3249 /* setup SW LPLU only for first revision */
3250 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3251 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
3252 IXGBE_FUSES0_REV_MASK))
3253 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
3254
3255 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
3256 phy->ops.reset = ixgbe_reset_phy_t_X550em;
3257 break;
3258 case ixgbe_phy_sgmii:
3259 phy->ops.setup_link = NULL;
3260 break;
3261 case ixgbe_phy_fw:
3262 phy->ops.setup_link = ixgbe_setup_fw_link;
3263 phy->ops.reset = ixgbe_reset_phy_fw;
3264 break;
3265 case ixgbe_phy_ext_1g_t:
3266 phy->ops.setup_link = NULL;
3267 phy->ops.read_reg = NULL;
3268 phy->ops.write_reg = NULL;
3269 phy->ops.reset = NULL;
3270 break;
3271 default:
3272 break;
3273 }
3274
3275 return ret_val;
3276 }
3277
3278 /** ixgbe_get_media_type_X550em - Get media type
3279 * @hw: pointer to hardware structure
3280 *
3281 * Returns the media type (fiber, copper, backplane)
3282 *
3283 */
ixgbe_get_media_type_X550em(struct ixgbe_hw * hw)3284 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
3285 {
3286 enum ixgbe_media_type media_type;
3287
3288 /* Detect if there is a copper PHY attached. */
3289 switch (hw->device_id) {
3290 case IXGBE_DEV_ID_X550EM_A_SGMII:
3291 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3292 hw->phy.type = ixgbe_phy_sgmii;
3293 fallthrough;
3294 case IXGBE_DEV_ID_X550EM_X_KR:
3295 case IXGBE_DEV_ID_X550EM_X_KX4:
3296 case IXGBE_DEV_ID_X550EM_X_XFI:
3297 case IXGBE_DEV_ID_X550EM_A_KR:
3298 case IXGBE_DEV_ID_X550EM_A_KR_L:
3299 media_type = ixgbe_media_type_backplane;
3300 break;
3301 case IXGBE_DEV_ID_X550EM_X_SFP:
3302 case IXGBE_DEV_ID_X550EM_A_SFP:
3303 case IXGBE_DEV_ID_X550EM_A_SFP_N:
3304 media_type = ixgbe_media_type_fiber;
3305 break;
3306 case IXGBE_DEV_ID_X550EM_X_1G_T:
3307 case IXGBE_DEV_ID_X550EM_X_10G_T:
3308 case IXGBE_DEV_ID_X550EM_A_10G_T:
3309 case IXGBE_DEV_ID_X550EM_A_1G_T:
3310 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3311 media_type = ixgbe_media_type_copper;
3312 break;
3313 default:
3314 media_type = ixgbe_media_type_unknown;
3315 break;
3316 }
3317 return media_type;
3318 }
3319
3320 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
3321 ** @hw: pointer to hardware structure
3322 **/
ixgbe_init_ext_t_x550em(struct ixgbe_hw * hw)3323 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
3324 {
3325 s32 status;
3326 u16 reg;
3327
3328 status = hw->phy.ops.read_reg(hw,
3329 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
3330 MDIO_MMD_PMAPMD,
3331 ®);
3332 if (status)
3333 return status;
3334
3335 /* If PHY FW reset completed bit is set then this is the first
3336 * SW instance after a power on so the PHY FW must be un-stalled.
3337 */
3338 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
3339 status = hw->phy.ops.read_reg(hw,
3340 IXGBE_MDIO_GLOBAL_RES_PR_10,
3341 MDIO_MMD_VEND1,
3342 ®);
3343 if (status)
3344 return status;
3345
3346 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
3347
3348 status = hw->phy.ops.write_reg(hw,
3349 IXGBE_MDIO_GLOBAL_RES_PR_10,
3350 MDIO_MMD_VEND1,
3351 reg);
3352 if (status)
3353 return status;
3354 }
3355
3356 return status;
3357 }
3358
3359 /**
3360 * ixgbe_set_mdio_speed - Set MDIO clock speed
3361 * @hw: pointer to hardware structure
3362 */
ixgbe_set_mdio_speed(struct ixgbe_hw * hw)3363 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
3364 {
3365 u32 hlreg0;
3366
3367 switch (hw->device_id) {
3368 case IXGBE_DEV_ID_X550EM_X_10G_T:
3369 case IXGBE_DEV_ID_X550EM_A_SGMII:
3370 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3371 case IXGBE_DEV_ID_X550EM_A_10G_T:
3372 case IXGBE_DEV_ID_X550EM_A_SFP:
3373 /* Config MDIO clock speed before the first MDIO PHY access */
3374 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3375 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
3376 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3377 break;
3378 case IXGBE_DEV_ID_X550EM_A_1G_T:
3379 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3380 /* Select fast MDIO clock speed for these devices */
3381 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3382 hlreg0 |= IXGBE_HLREG0_MDCSPD;
3383 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3384 break;
3385 default:
3386 break;
3387 }
3388 }
3389
3390 /** ixgbe_reset_hw_X550em - Perform hardware reset
3391 ** @hw: pointer to hardware structure
3392 **
3393 ** Resets the hardware by resetting the transmit and receive units, masks
3394 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3395 ** reset.
3396 **/
ixgbe_reset_hw_X550em(struct ixgbe_hw * hw)3397 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
3398 {
3399 ixgbe_link_speed link_speed;
3400 s32 status;
3401 u32 ctrl = 0;
3402 u32 i;
3403 bool link_up = false;
3404 u32 swfw_mask = hw->phy.phy_semaphore_mask;
3405
3406 /* Call adapter stop to disable Tx/Rx and clear interrupts */
3407 status = hw->mac.ops.stop_adapter(hw);
3408 if (status)
3409 return status;
3410
3411 /* flush pending Tx transactions */
3412 ixgbe_clear_tx_pending(hw);
3413
3414 /* set MDIO speed before talking to the PHY in case it's the 1st time */
3415 ixgbe_set_mdio_speed(hw);
3416
3417 /* PHY ops must be identified and initialized prior to reset */
3418 status = hw->phy.ops.init(hw);
3419 if (status == -EOPNOTSUPP || status == -EFAULT)
3420 return status;
3421
3422 /* start the external PHY */
3423 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
3424 status = ixgbe_init_ext_t_x550em(hw);
3425 if (status)
3426 return status;
3427 }
3428
3429 /* Setup SFP module if there is one present. */
3430 if (hw->phy.sfp_setup_needed) {
3431 status = hw->mac.ops.setup_sfp(hw);
3432 hw->phy.sfp_setup_needed = false;
3433 }
3434
3435 if (status == -EOPNOTSUPP)
3436 return status;
3437
3438 /* Reset PHY */
3439 if (!hw->phy.reset_disable && hw->phy.ops.reset)
3440 hw->phy.ops.reset(hw);
3441
3442 mac_reset_top:
3443 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
3444 * If link reset is used when link is up, it might reset the PHY when
3445 * mng is using it. If link is down or the flag to force full link
3446 * reset is set, then perform link reset.
3447 */
3448 ctrl = IXGBE_CTRL_LNK_RST;
3449
3450 if (!hw->force_full_reset) {
3451 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3452 if (link_up)
3453 ctrl = IXGBE_CTRL_RST;
3454 }
3455
3456 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
3457 if (status) {
3458 hw_dbg(hw, "semaphore failed with %d", status);
3459 return -EBUSY;
3460 }
3461
3462 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
3463 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3464 IXGBE_WRITE_FLUSH(hw);
3465 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3466 usleep_range(1000, 1200);
3467
3468 /* Poll for reset bit to self-clear meaning reset is complete */
3469 for (i = 0; i < 10; i++) {
3470 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3471 if (!(ctrl & IXGBE_CTRL_RST_MASK))
3472 break;
3473 udelay(1);
3474 }
3475
3476 if (ctrl & IXGBE_CTRL_RST_MASK) {
3477 status = -EIO;
3478 hw_dbg(hw, "Reset polling failed to complete.\n");
3479 }
3480
3481 msleep(50);
3482
3483 /* Double resets are required for recovery from certain error
3484 * clear the multicast table. Also reset num_rar_entries to 128,
3485 * since we modify this value when programming the SAN MAC address.
3486 */
3487 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3488 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3489 goto mac_reset_top;
3490 }
3491
3492 /* Store the permanent mac address */
3493 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
3494
3495 /* Store MAC address from RAR0, clear receive address registers, and
3496 * clear the multicast table. Also reset num_rar_entries to 128,
3497 * since we modify this value when programming the SAN MAC address.
3498 */
3499 hw->mac.num_rar_entries = 128;
3500 hw->mac.ops.init_rx_addrs(hw);
3501
3502 ixgbe_set_mdio_speed(hw);
3503
3504 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
3505 ixgbe_setup_mux_ctl(hw);
3506
3507 return status;
3508 }
3509
3510 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
3511 * anti-spoofing
3512 * @hw: pointer to hardware structure
3513 * @enable: enable or disable switch for Ethertype anti-spoofing
3514 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
3515 **/
ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw * hw,bool enable,int vf)3516 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
3517 bool enable, int vf)
3518 {
3519 int vf_target_reg = vf >> 3;
3520 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
3521 u32 pfvfspoof;
3522
3523 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3524 if (enable)
3525 pfvfspoof |= BIT(vf_target_shift);
3526 else
3527 pfvfspoof &= ~BIT(vf_target_shift);
3528
3529 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3530 }
3531
3532 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
3533 * @hw: pointer to hardware structure
3534 * @enable: enable or disable source address pruning
3535 * @pool: Rx pool to set source address pruning for
3536 **/
ixgbe_set_source_address_pruning_X550(struct ixgbe_hw * hw,bool enable,unsigned int pool)3537 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
3538 bool enable,
3539 unsigned int pool)
3540 {
3541 u64 pfflp;
3542
3543 /* max rx pool is 63 */
3544 if (pool > 63)
3545 return;
3546
3547 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
3548 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
3549
3550 if (enable)
3551 pfflp |= (1ULL << pool);
3552 else
3553 pfflp &= ~(1ULL << pool);
3554
3555 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
3556 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
3557 }
3558
3559 /**
3560 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
3561 * @hw: pointer to hardware structure
3562 *
3563 * Called at init time to set up flow control.
3564 **/
ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw * hw)3565 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
3566 {
3567 s32 status = 0;
3568 u32 an_cntl = 0;
3569
3570 /* Validate the requested mode */
3571 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3572 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3573 return -EINVAL;
3574 }
3575
3576 if (hw->fc.requested_mode == ixgbe_fc_default)
3577 hw->fc.requested_mode = ixgbe_fc_full;
3578
3579 /* Set up the 1G and 10G flow control advertisement registers so the
3580 * HW will be able to do FC autoneg once the cable is plugged in. If
3581 * we link at 10G, the 1G advertisement is harmless and vice versa.
3582 */
3583 status = hw->mac.ops.read_iosf_sb_reg(hw,
3584 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3585 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
3586
3587 if (status) {
3588 hw_dbg(hw, "Auto-Negotiation did not complete\n");
3589 return status;
3590 }
3591
3592 /* The possible values of fc.requested_mode are:
3593 * 0: Flow control is completely disabled
3594 * 1: Rx flow control is enabled (we can receive pause frames,
3595 * but not send pause frames).
3596 * 2: Tx flow control is enabled (we can send pause frames but
3597 * we do not support receiving pause frames).
3598 * 3: Both Rx and Tx flow control (symmetric) are enabled.
3599 * other: Invalid.
3600 */
3601 switch (hw->fc.requested_mode) {
3602 case ixgbe_fc_none:
3603 /* Flow control completely disabled by software override. */
3604 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3605 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3606 break;
3607 case ixgbe_fc_tx_pause:
3608 /* Tx Flow control is enabled, and Rx Flow control is
3609 * disabled by software override.
3610 */
3611 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3612 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3613 break;
3614 case ixgbe_fc_rx_pause:
3615 /* Rx Flow control is enabled and Tx Flow control is
3616 * disabled by software override. Since there really
3617 * isn't a way to advertise that we are capable of RX
3618 * Pause ONLY, we will advertise that we support both
3619 * symmetric and asymmetric Rx PAUSE, as such we fall
3620 * through to the fc_full statement. Later, we will
3621 * disable the adapter's ability to send PAUSE frames.
3622 */
3623 case ixgbe_fc_full:
3624 /* Flow control (both Rx and Tx) is enabled by SW override. */
3625 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3626 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3627 break;
3628 default:
3629 hw_err(hw, "Flow control param set incorrectly\n");
3630 return -EIO;
3631 }
3632
3633 status = hw->mac.ops.write_iosf_sb_reg(hw,
3634 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3635 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
3636
3637 /* Restart auto-negotiation. */
3638 status = ixgbe_restart_an_internal_phy_x550em(hw);
3639
3640 return status;
3641 }
3642
3643 /**
3644 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3645 * @hw: pointer to hardware structure
3646 * @state: set mux if 1, clear if 0
3647 */
ixgbe_set_mux(struct ixgbe_hw * hw,u8 state)3648 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3649 {
3650 u32 esdp;
3651
3652 if (!hw->bus.lan_id)
3653 return;
3654 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3655 if (state)
3656 esdp |= IXGBE_ESDP_SDP1;
3657 else
3658 esdp &= ~IXGBE_ESDP_SDP1;
3659 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3660 IXGBE_WRITE_FLUSH(hw);
3661 }
3662
3663 /**
3664 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3665 * @hw: pointer to hardware structure
3666 * @mask: Mask to specify which semaphore to acquire
3667 *
3668 * Acquires the SWFW semaphore and sets the I2C MUX
3669 */
ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw * hw,u32 mask)3670 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3671 {
3672 s32 status;
3673
3674 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3675 if (status)
3676 return status;
3677
3678 if (mask & IXGBE_GSSR_I2C_MASK)
3679 ixgbe_set_mux(hw, 1);
3680
3681 return 0;
3682 }
3683
3684 /**
3685 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3686 * @hw: pointer to hardware structure
3687 * @mask: Mask to specify which semaphore to release
3688 *
3689 * Releases the SWFW semaphore and sets the I2C MUX
3690 */
ixgbe_release_swfw_sync_X550em(struct ixgbe_hw * hw,u32 mask)3691 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3692 {
3693 if (mask & IXGBE_GSSR_I2C_MASK)
3694 ixgbe_set_mux(hw, 0);
3695
3696 ixgbe_release_swfw_sync_X540(hw, mask);
3697 }
3698
3699 /**
3700 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
3701 * @hw: pointer to hardware structure
3702 * @mask: Mask to specify which semaphore to acquire
3703 *
3704 * Acquires the SWFW semaphore and get the shared PHY token as needed
3705 */
ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw * hw,u32 mask)3706 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3707 {
3708 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3709 int retries = FW_PHY_TOKEN_RETRIES;
3710 s32 status;
3711
3712 while (--retries) {
3713 status = 0;
3714 if (hmask)
3715 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3716 if (status)
3717 return status;
3718 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3719 return 0;
3720
3721 status = ixgbe_get_phy_token(hw);
3722 if (!status)
3723 return 0;
3724 if (hmask)
3725 ixgbe_release_swfw_sync_X540(hw, hmask);
3726 if (status != -EAGAIN)
3727 return status;
3728 msleep(FW_PHY_TOKEN_DELAY);
3729 }
3730
3731 return status;
3732 }
3733
3734 /**
3735 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
3736 * @hw: pointer to hardware structure
3737 * @mask: Mask to specify which semaphore to release
3738 *
3739 * Release the SWFW semaphore and puts the shared PHY token as needed
3740 */
ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw * hw,u32 mask)3741 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3742 {
3743 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3744
3745 if (mask & IXGBE_GSSR_TOKEN_SM)
3746 ixgbe_put_phy_token(hw);
3747
3748 if (hmask)
3749 ixgbe_release_swfw_sync_X540(hw, hmask);
3750 }
3751
3752 /**
3753 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
3754 * @hw: pointer to hardware structure
3755 * @reg_addr: 32 bit address of PHY register to read
3756 * @device_type: 5 bit device type
3757 * @phy_data: Pointer to read data from PHY register
3758 *
3759 * Reads a value from a specified PHY register using the SWFW lock and PHY
3760 * Token. The PHY Token is needed since the MDIO is shared between to MAC
3761 * instances.
3762 */
ixgbe_read_phy_reg_x550a(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)3763 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3764 u32 device_type, u16 *phy_data)
3765 {
3766 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3767 s32 status;
3768
3769 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3770 return -EBUSY;
3771
3772 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
3773
3774 hw->mac.ops.release_swfw_sync(hw, mask);
3775
3776 return status;
3777 }
3778
3779 /**
3780 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
3781 * @hw: pointer to hardware structure
3782 * @reg_addr: 32 bit PHY register to write
3783 * @device_type: 5 bit device type
3784 * @phy_data: Data to write to the PHY register
3785 *
3786 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
3787 * The PHY Token is needed since the MDIO is shared between to MAC instances.
3788 */
ixgbe_write_phy_reg_x550a(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)3789 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3790 u32 device_type, u16 phy_data)
3791 {
3792 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3793 s32 status;
3794
3795 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3796 return -EBUSY;
3797
3798 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
3799 hw->mac.ops.release_swfw_sync(hw, mask);
3800
3801 return status;
3802 }
3803
3804 #define X550_COMMON_MAC \
3805 .init_hw = &ixgbe_init_hw_generic, \
3806 .start_hw = &ixgbe_start_hw_X540, \
3807 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \
3808 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \
3809 .get_mac_addr = &ixgbe_get_mac_addr_generic, \
3810 .get_device_caps = &ixgbe_get_device_caps_generic, \
3811 .stop_adapter = &ixgbe_stop_adapter_generic, \
3812 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \
3813 .read_analog_reg8 = NULL, \
3814 .write_analog_reg8 = NULL, \
3815 .set_rxpba = &ixgbe_set_rxpba_generic, \
3816 .check_link = &ixgbe_check_mac_link_generic, \
3817 .blink_led_start = &ixgbe_blink_led_start_X540, \
3818 .blink_led_stop = &ixgbe_blink_led_stop_X540, \
3819 .set_rar = &ixgbe_set_rar_generic, \
3820 .clear_rar = &ixgbe_clear_rar_generic, \
3821 .set_vmdq = &ixgbe_set_vmdq_generic, \
3822 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \
3823 .clear_vmdq = &ixgbe_clear_vmdq_generic, \
3824 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \
3825 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \
3826 .enable_mc = &ixgbe_enable_mc_generic, \
3827 .disable_mc = &ixgbe_disable_mc_generic, \
3828 .clear_vfta = &ixgbe_clear_vfta_generic, \
3829 .set_vfta = &ixgbe_set_vfta_generic, \
3830 .fc_enable = &ixgbe_fc_enable_generic, \
3831 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_x550, \
3832 .init_uta_tables = &ixgbe_init_uta_tables_generic, \
3833 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \
3834 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \
3835 .set_source_address_pruning = \
3836 &ixgbe_set_source_address_pruning_X550, \
3837 .set_ethertype_anti_spoofing = \
3838 &ixgbe_set_ethertype_anti_spoofing_X550, \
3839 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \
3840 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \
3841 .get_thermal_sensor_data = NULL, \
3842 .init_thermal_sensor_thresh = NULL, \
3843 .fw_recovery_mode = &ixgbe_fw_recovery_mode_X550, \
3844 .enable_rx = &ixgbe_enable_rx_generic, \
3845 .disable_rx = &ixgbe_disable_rx_x550, \
3846
3847 static const struct ixgbe_mac_operations mac_ops_X550 = {
3848 X550_COMMON_MAC
3849 .led_on = ixgbe_led_on_generic,
3850 .led_off = ixgbe_led_off_generic,
3851 .init_led_link_act = ixgbe_init_led_link_act_generic,
3852 .reset_hw = &ixgbe_reset_hw_X540,
3853 .get_media_type = &ixgbe_get_media_type_X540,
3854 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
3855 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
3856 .setup_link = &ixgbe_setup_mac_link_X540,
3857 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
3858 .get_bus_info = &ixgbe_get_bus_info_generic,
3859 .setup_sfp = NULL,
3860 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
3861 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
3862 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3863 .prot_autoc_read = prot_autoc_read_generic,
3864 .prot_autoc_write = prot_autoc_write_generic,
3865 .setup_fc = ixgbe_setup_fc_generic,
3866 .fc_autoneg = ixgbe_fc_autoneg,
3867 };
3868
3869 static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
3870 X550_COMMON_MAC
3871 .led_on = ixgbe_led_on_t_x550em,
3872 .led_off = ixgbe_led_off_t_x550em,
3873 .init_led_link_act = ixgbe_init_led_link_act_generic,
3874 .reset_hw = &ixgbe_reset_hw_X550em,
3875 .get_media_type = &ixgbe_get_media_type_X550em,
3876 .get_san_mac_addr = NULL,
3877 .get_wwn_prefix = NULL,
3878 .setup_link = &ixgbe_setup_mac_link_X540,
3879 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
3880 .get_bus_info = &ixgbe_get_bus_info_X550em,
3881 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3882 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
3883 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
3884 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3885 .setup_fc = NULL, /* defined later */
3886 .fc_autoneg = ixgbe_fc_autoneg,
3887 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550,
3888 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550,
3889 };
3890
3891 static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = {
3892 X550_COMMON_MAC
3893 .led_on = NULL,
3894 .led_off = NULL,
3895 .init_led_link_act = NULL,
3896 .reset_hw = &ixgbe_reset_hw_X550em,
3897 .get_media_type = &ixgbe_get_media_type_X550em,
3898 .get_san_mac_addr = NULL,
3899 .get_wwn_prefix = NULL,
3900 .setup_link = &ixgbe_setup_mac_link_X540,
3901 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
3902 .get_bus_info = &ixgbe_get_bus_info_X550em,
3903 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3904 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
3905 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
3906 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3907 .setup_fc = NULL,
3908 .fc_autoneg = ixgbe_fc_autoneg,
3909 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550,
3910 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550,
3911 };
3912
3913 static const struct ixgbe_mac_operations mac_ops_x550em_a = {
3914 X550_COMMON_MAC
3915 .led_on = ixgbe_led_on_t_x550em,
3916 .led_off = ixgbe_led_off_t_x550em,
3917 .init_led_link_act = ixgbe_init_led_link_act_generic,
3918 .reset_hw = ixgbe_reset_hw_X550em,
3919 .get_media_type = ixgbe_get_media_type_X550em,
3920 .get_san_mac_addr = NULL,
3921 .get_wwn_prefix = NULL,
3922 .setup_link = &ixgbe_setup_mac_link_X540,
3923 .get_link_capabilities = ixgbe_get_link_capabilities_X550em,
3924 .get_bus_info = ixgbe_get_bus_info_X550em,
3925 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3926 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
3927 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
3928 .setup_fc = ixgbe_setup_fc_x550em,
3929 .fc_autoneg = ixgbe_fc_autoneg,
3930 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
3931 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
3932 };
3933
3934 static const struct ixgbe_mac_operations mac_ops_x550em_a_fw = {
3935 X550_COMMON_MAC
3936 .led_on = ixgbe_led_on_generic,
3937 .led_off = ixgbe_led_off_generic,
3938 .init_led_link_act = ixgbe_init_led_link_act_generic,
3939 .reset_hw = ixgbe_reset_hw_X550em,
3940 .get_media_type = ixgbe_get_media_type_X550em,
3941 .get_san_mac_addr = NULL,
3942 .get_wwn_prefix = NULL,
3943 .setup_link = NULL, /* defined later */
3944 .get_link_capabilities = ixgbe_get_link_capabilities_X550em,
3945 .get_bus_info = ixgbe_get_bus_info_X550em,
3946 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3947 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
3948 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
3949 .setup_fc = ixgbe_setup_fc_x550em,
3950 .fc_autoneg = ixgbe_fc_autoneg,
3951 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
3952 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
3953 };
3954
3955 #define X550_COMMON_EEP \
3956 .read = &ixgbe_read_ee_hostif_X550, \
3957 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \
3958 .write = &ixgbe_write_ee_hostif_X550, \
3959 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \
3960 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \
3961 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \
3962 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \
3963
3964 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
3965 X550_COMMON_EEP
3966 .init_params = &ixgbe_init_eeprom_params_X550,
3967 };
3968
3969 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
3970 X550_COMMON_EEP
3971 .init_params = &ixgbe_init_eeprom_params_X540,
3972 };
3973
3974 #define X550_COMMON_PHY \
3975 .identify_sfp = &ixgbe_identify_module_generic, \
3976 .reset = NULL, \
3977 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \
3978 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \
3979 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \
3980 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \
3981 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \
3982 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \
3983 .setup_link = &ixgbe_setup_phy_link_generic, \
3984 .set_phy_power = NULL,
3985
3986 static const struct ixgbe_phy_operations phy_ops_X550 = {
3987 X550_COMMON_PHY
3988 .check_overtemp = &ixgbe_tn_check_overtemp,
3989 .init = NULL,
3990 .identify = &ixgbe_identify_phy_generic,
3991 .read_reg = &ixgbe_read_phy_reg_generic,
3992 .write_reg = &ixgbe_write_phy_reg_generic,
3993 };
3994
3995 static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
3996 X550_COMMON_PHY
3997 .check_overtemp = &ixgbe_tn_check_overtemp,
3998 .init = &ixgbe_init_phy_ops_X550em,
3999 .identify = &ixgbe_identify_phy_x550em,
4000 .read_reg = &ixgbe_read_phy_reg_generic,
4001 .write_reg = &ixgbe_write_phy_reg_generic,
4002 };
4003
4004 static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = {
4005 X550_COMMON_PHY
4006 .check_overtemp = NULL,
4007 .init = ixgbe_init_phy_ops_X550em,
4008 .identify = ixgbe_identify_phy_x550em,
4009 .read_reg = NULL,
4010 .write_reg = NULL,
4011 .read_reg_mdi = NULL,
4012 .write_reg_mdi = NULL,
4013 };
4014
4015 static const struct ixgbe_phy_operations phy_ops_x550em_a = {
4016 X550_COMMON_PHY
4017 .check_overtemp = &ixgbe_tn_check_overtemp,
4018 .init = &ixgbe_init_phy_ops_X550em,
4019 .identify = &ixgbe_identify_phy_x550em,
4020 .read_reg = &ixgbe_read_phy_reg_x550a,
4021 .write_reg = &ixgbe_write_phy_reg_x550a,
4022 .read_reg_mdi = &ixgbe_read_phy_reg_mdi,
4023 .write_reg_mdi = &ixgbe_write_phy_reg_mdi,
4024 };
4025
4026 static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = {
4027 X550_COMMON_PHY
4028 .check_overtemp = ixgbe_check_overtemp_fw,
4029 .init = ixgbe_init_phy_ops_X550em,
4030 .identify = ixgbe_identify_phy_fw,
4031 .read_reg = NULL,
4032 .write_reg = NULL,
4033 .read_reg_mdi = NULL,
4034 .write_reg_mdi = NULL,
4035 };
4036
4037 static const struct ixgbe_link_operations link_ops_x550em_x = {
4038 .read_link = &ixgbe_read_i2c_combined_generic,
4039 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
4040 .write_link = &ixgbe_write_i2c_combined_generic,
4041 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked,
4042 };
4043
4044 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
4045 IXGBE_MVALS_INIT(X550)
4046 };
4047
4048 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
4049 IXGBE_MVALS_INIT(X550EM_x)
4050 };
4051
4052 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = {
4053 IXGBE_MVALS_INIT(X550EM_a)
4054 };
4055
4056 const struct ixgbe_info ixgbe_X550_info = {
4057 .mac = ixgbe_mac_X550,
4058 .get_invariants = &ixgbe_get_invariants_X540,
4059 .mac_ops = &mac_ops_X550,
4060 .eeprom_ops = &eeprom_ops_X550,
4061 .phy_ops = &phy_ops_X550,
4062 .mbx_ops = &mbx_ops_generic,
4063 .mvals = ixgbe_mvals_X550,
4064 };
4065
4066 const struct ixgbe_info ixgbe_X550EM_x_info = {
4067 .mac = ixgbe_mac_X550EM_x,
4068 .get_invariants = &ixgbe_get_invariants_X550_x,
4069 .mac_ops = &mac_ops_X550EM_x,
4070 .eeprom_ops = &eeprom_ops_X550EM_x,
4071 .phy_ops = &phy_ops_X550EM_x,
4072 .mbx_ops = &mbx_ops_generic,
4073 .mvals = ixgbe_mvals_X550EM_x,
4074 .link_ops = &link_ops_x550em_x,
4075 };
4076
4077 const struct ixgbe_info ixgbe_x550em_x_fw_info = {
4078 .mac = ixgbe_mac_X550EM_x,
4079 .get_invariants = ixgbe_get_invariants_X550_x_fw,
4080 .mac_ops = &mac_ops_X550EM_x_fw,
4081 .eeprom_ops = &eeprom_ops_X550EM_x,
4082 .phy_ops = &phy_ops_x550em_x_fw,
4083 .mbx_ops = &mbx_ops_generic,
4084 .mvals = ixgbe_mvals_X550EM_x,
4085 };
4086
4087 const struct ixgbe_info ixgbe_x550em_a_info = {
4088 .mac = ixgbe_mac_x550em_a,
4089 .get_invariants = &ixgbe_get_invariants_X550_a,
4090 .mac_ops = &mac_ops_x550em_a,
4091 .eeprom_ops = &eeprom_ops_X550EM_x,
4092 .phy_ops = &phy_ops_x550em_a,
4093 .mbx_ops = &mbx_ops_generic,
4094 .mvals = ixgbe_mvals_x550em_a,
4095 };
4096
4097 const struct ixgbe_info ixgbe_x550em_a_fw_info = {
4098 .mac = ixgbe_mac_x550em_a,
4099 .get_invariants = ixgbe_get_invariants_X550_a_fw,
4100 .mac_ops = &mac_ops_x550em_a_fw,
4101 .eeprom_ops = &eeprom_ops_X550EM_x,
4102 .phy_ops = &phy_ops_x550em_a_fw,
4103 .mbx_ops = &mbx_ops_generic,
4104 .mvals = ixgbe_mvals_x550em_a,
4105 };
4106