1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, Intel Corporation
5 */
6
7 #ifndef SPI_PXA2XX_H
8 #define SPI_PXA2XX_H
9
10 #include <linux/atomic.h>
11 #include <linux/dmaengine.h>
12 #include <linux/errno.h>
13 #include <linux/io.h>
14 #include <linux/interrupt.h>
15 #include <linux/platform_device.h>
16 #include <linux/pxa2xx_ssp.h>
17 #include <linux/scatterlist.h>
18 #include <linux/sizes.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/pxa2xx_spi.h>
21
22 struct driver_data {
23 /* Driver model hookup */
24 struct platform_device *pdev;
25
26 /* SSP Info */
27 struct ssp_device *ssp;
28
29 /* SPI framework hookup */
30 enum pxa_ssp_type ssp_type;
31 struct spi_controller *controller;
32
33 /* PXA hookup */
34 struct pxa2xx_spi_controller *controller_info;
35
36 /* SSP register addresses */
37 void __iomem *ioaddr;
38 phys_addr_t ssdr_physical;
39
40 /* SSP masks*/
41 u32 dma_cr1;
42 u32 int_cr1;
43 u32 clear_sr;
44 u32 mask_sr;
45
46 /* DMA engine support */
47 atomic_t dma_running;
48
49 /* Current transfer state info */
50 void *tx;
51 void *tx_end;
52 void *rx;
53 void *rx_end;
54 u8 n_bytes;
55 int (*write)(struct driver_data *drv_data);
56 int (*read)(struct driver_data *drv_data);
57 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
58 void (*cs_control)(u32 command);
59
60 void __iomem *lpss_base;
61
62 /* GPIOs for chip selects */
63 struct gpio_desc **cs_gpiods;
64
65 /* Optional slave FIFO ready signal */
66 struct gpio_desc *gpiod_ready;
67 };
68
69 struct chip_data {
70 u32 cr1;
71 u32 dds_rate;
72 u32 timeout;
73 u8 n_bytes;
74 u32 dma_burst_size;
75 u32 threshold;
76 u32 dma_threshold;
77 u16 lpss_rx_threshold;
78 u16 lpss_tx_threshold;
79 u8 enable_dma;
80 union {
81 struct gpio_desc *gpiod_cs;
82 unsigned int frm;
83 };
84 int gpio_cs_inverted;
85 int (*write)(struct driver_data *drv_data);
86 int (*read)(struct driver_data *drv_data);
87 void (*cs_control)(u32 command);
88 };
89
pxa2xx_spi_read(const struct driver_data * drv_data,unsigned reg)90 static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data,
91 unsigned reg)
92 {
93 return __raw_readl(drv_data->ioaddr + reg);
94 }
95
pxa2xx_spi_write(const struct driver_data * drv_data,unsigned reg,u32 val)96 static inline void pxa2xx_spi_write(const struct driver_data *drv_data,
97 unsigned reg, u32 val)
98 {
99 __raw_writel(val, drv_data->ioaddr + reg);
100 }
101
102 #define DMA_ALIGNMENT 8
103
pxa25x_ssp_comp(struct driver_data * drv_data)104 static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
105 {
106 switch (drv_data->ssp_type) {
107 case PXA25x_SSP:
108 case CE4100_SSP:
109 case QUARK_X1000_SSP:
110 return 1;
111 default:
112 return 0;
113 }
114 }
115
write_SSSR_CS(struct driver_data * drv_data,u32 val)116 static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
117 {
118 if (drv_data->ssp_type == CE4100_SSP ||
119 drv_data->ssp_type == QUARK_X1000_SSP)
120 val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK;
121
122 pxa2xx_spi_write(drv_data, SSSR, val);
123 }
124
125 extern int pxa2xx_spi_flush(struct driver_data *drv_data);
126
127 #define MAX_DMA_LEN SZ_64K
128 #define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
129
130 extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
131 extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
132 struct spi_transfer *xfer);
133 extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
134 extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
135 extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
136 extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
137 extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
138 struct spi_device *spi,
139 u8 bits_per_word,
140 u32 *burst_code,
141 u32 *threshold);
142
143 #endif /* SPI_PXA2XX_H */
144