1 // SPDX-License-Identifier: GPL-2.0-only
2 /**
3 * SDHCI Controller driver for TI's OMAP SoCs
4 *
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9 #include <linux/delay.h>
10 #include <linux/mmc/mmc.h>
11 #include <linux/mmc/slot-gpio.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/sys_soc.h>
20 #include <linux/thermal.h>
21
22 #include "sdhci-pltfm.h"
23
24 #define SDHCI_OMAP_CON 0x12c
25 #define CON_DW8 BIT(5)
26 #define CON_DMA_MASTER BIT(20)
27 #define CON_DDR BIT(19)
28 #define CON_CLKEXTFREE BIT(16)
29 #define CON_PADEN BIT(15)
30 #define CON_CTPL BIT(11)
31 #define CON_INIT BIT(1)
32 #define CON_OD BIT(0)
33
34 #define SDHCI_OMAP_DLL 0x0134
35 #define DLL_SWT BIT(20)
36 #define DLL_FORCE_SR_C_SHIFT 13
37 #define DLL_FORCE_SR_C_MASK (0x7f << DLL_FORCE_SR_C_SHIFT)
38 #define DLL_FORCE_VALUE BIT(12)
39 #define DLL_CALIB BIT(1)
40
41 #define SDHCI_OMAP_CMD 0x20c
42
43 #define SDHCI_OMAP_PSTATE 0x0224
44 #define PSTATE_DLEV_DAT0 BIT(20)
45 #define PSTATE_DATI BIT(1)
46
47 #define SDHCI_OMAP_HCTL 0x228
48 #define HCTL_SDBP BIT(8)
49 #define HCTL_SDVS_SHIFT 9
50 #define HCTL_SDVS_MASK (0x7 << HCTL_SDVS_SHIFT)
51 #define HCTL_SDVS_33 (0x7 << HCTL_SDVS_SHIFT)
52 #define HCTL_SDVS_30 (0x6 << HCTL_SDVS_SHIFT)
53 #define HCTL_SDVS_18 (0x5 << HCTL_SDVS_SHIFT)
54
55 #define SDHCI_OMAP_SYSCTL 0x22c
56 #define SYSCTL_CEN BIT(2)
57 #define SYSCTL_CLKD_SHIFT 6
58 #define SYSCTL_CLKD_MASK 0x3ff
59
60 #define SDHCI_OMAP_STAT 0x230
61
62 #define SDHCI_OMAP_IE 0x234
63 #define INT_CC_EN BIT(0)
64
65 #define SDHCI_OMAP_ISE 0x238
66
67 #define SDHCI_OMAP_AC12 0x23c
68 #define AC12_V1V8_SIGEN BIT(19)
69 #define AC12_SCLK_SEL BIT(23)
70
71 #define SDHCI_OMAP_CAPA 0x240
72 #define CAPA_VS33 BIT(24)
73 #define CAPA_VS30 BIT(25)
74 #define CAPA_VS18 BIT(26)
75
76 #define SDHCI_OMAP_CAPA2 0x0244
77 #define CAPA2_TSDR50 BIT(13)
78
79 #define SDHCI_OMAP_TIMEOUT 1 /* 1 msec */
80
81 #define SYSCTL_CLKD_MAX 0x3FF
82
83 #define IOV_1V8 1800000 /* 180000 uV */
84 #define IOV_3V0 3000000 /* 300000 uV */
85 #define IOV_3V3 3300000 /* 330000 uV */
86
87 #define MAX_PHASE_DELAY 0x7C
88
89 /* sdhci-omap controller flags */
90 #define SDHCI_OMAP_REQUIRE_IODELAY BIT(0)
91 #define SDHCI_OMAP_SPECIAL_RESET BIT(1)
92
93 struct sdhci_omap_data {
94 u32 offset;
95 u8 flags;
96 };
97
98 struct sdhci_omap_host {
99 char *version;
100 void __iomem *base;
101 struct device *dev;
102 struct regulator *pbias;
103 bool pbias_enabled;
104 struct sdhci_host *host;
105 u8 bus_mode;
106 u8 power_mode;
107 u8 timing;
108 u8 flags;
109
110 struct pinctrl *pinctrl;
111 struct pinctrl_state **pinctrl_state;
112 bool is_tuning;
113 /* Omap specific context save */
114 u32 con;
115 u32 hctl;
116 u32 sysctl;
117 u32 capa;
118 u32 ie;
119 u32 ise;
120 };
121
122 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
123 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host);
124
sdhci_omap_readl(struct sdhci_omap_host * host,unsigned int offset)125 static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
126 unsigned int offset)
127 {
128 return readl(host->base + offset);
129 }
130
sdhci_omap_writel(struct sdhci_omap_host * host,unsigned int offset,u32 data)131 static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
132 unsigned int offset, u32 data)
133 {
134 writel(data, host->base + offset);
135 }
136
sdhci_omap_set_pbias(struct sdhci_omap_host * omap_host,bool power_on,unsigned int iov)137 static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
138 bool power_on, unsigned int iov)
139 {
140 int ret;
141 struct device *dev = omap_host->dev;
142
143 if (IS_ERR(omap_host->pbias))
144 return 0;
145
146 if (power_on) {
147 ret = regulator_set_voltage(omap_host->pbias, iov, iov);
148 if (ret) {
149 dev_err(dev, "pbias set voltage failed\n");
150 return ret;
151 }
152
153 if (omap_host->pbias_enabled)
154 return 0;
155
156 ret = regulator_enable(omap_host->pbias);
157 if (ret) {
158 dev_err(dev, "pbias reg enable fail\n");
159 return ret;
160 }
161
162 omap_host->pbias_enabled = true;
163 } else {
164 if (!omap_host->pbias_enabled)
165 return 0;
166
167 ret = regulator_disable(omap_host->pbias);
168 if (ret) {
169 dev_err(dev, "pbias reg disable fail\n");
170 return ret;
171 }
172 omap_host->pbias_enabled = false;
173 }
174
175 return 0;
176 }
177
sdhci_omap_enable_iov(struct sdhci_omap_host * omap_host,unsigned int iov)178 static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
179 unsigned int iov)
180 {
181 int ret;
182 struct sdhci_host *host = omap_host->host;
183 struct mmc_host *mmc = host->mmc;
184
185 ret = sdhci_omap_set_pbias(omap_host, false, 0);
186 if (ret)
187 return ret;
188
189 if (!IS_ERR(mmc->supply.vqmmc)) {
190 ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov);
191 if (ret) {
192 dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
193 return ret;
194 }
195 }
196
197 ret = sdhci_omap_set_pbias(omap_host, true, iov);
198 if (ret)
199 return ret;
200
201 return 0;
202 }
203
sdhci_omap_conf_bus_power(struct sdhci_omap_host * omap_host,unsigned char signal_voltage)204 static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
205 unsigned char signal_voltage)
206 {
207 u32 reg;
208 ktime_t timeout;
209
210 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
211 reg &= ~HCTL_SDVS_MASK;
212
213 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
214 reg |= HCTL_SDVS_33;
215 else
216 reg |= HCTL_SDVS_18;
217
218 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
219
220 reg |= HCTL_SDBP;
221 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
222
223 /* wait 1ms */
224 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
225 while (1) {
226 bool timedout = ktime_after(ktime_get(), timeout);
227
228 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)
229 break;
230 if (WARN_ON(timedout))
231 return;
232 usleep_range(5, 10);
233 }
234 }
235
sdhci_omap_enable_sdio_irq(struct mmc_host * mmc,int enable)236 static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable)
237 {
238 struct sdhci_host *host = mmc_priv(mmc);
239 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
240 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
241 u32 reg;
242
243 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
244 if (enable)
245 reg |= (CON_CTPL | CON_CLKEXTFREE);
246 else
247 reg &= ~(CON_CTPL | CON_CLKEXTFREE);
248 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
249
250 sdhci_enable_sdio_irq(mmc, enable);
251 }
252
sdhci_omap_set_dll(struct sdhci_omap_host * omap_host,int count)253 static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
254 int count)
255 {
256 int i;
257 u32 reg;
258
259 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
260 reg |= DLL_FORCE_VALUE;
261 reg &= ~DLL_FORCE_SR_C_MASK;
262 reg |= (count << DLL_FORCE_SR_C_SHIFT);
263 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
264
265 reg |= DLL_CALIB;
266 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
267 for (i = 0; i < 1000; i++) {
268 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
269 if (reg & DLL_CALIB)
270 break;
271 }
272 reg &= ~DLL_CALIB;
273 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
274 }
275
sdhci_omap_disable_tuning(struct sdhci_omap_host * omap_host)276 static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
277 {
278 u32 reg;
279
280 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
281 reg &= ~AC12_SCLK_SEL;
282 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
283
284 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
285 reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
286 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
287 }
288
sdhci_omap_execute_tuning(struct mmc_host * mmc,u32 opcode)289 static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
290 {
291 struct sdhci_host *host = mmc_priv(mmc);
292 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
293 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
294 struct thermal_zone_device *thermal_dev;
295 struct device *dev = omap_host->dev;
296 struct mmc_ios *ios = &mmc->ios;
297 u32 start_window = 0, max_window = 0;
298 bool single_point_failure = false;
299 bool dcrc_was_enabled = false;
300 u8 cur_match, prev_match = 0;
301 u32 length = 0, max_len = 0;
302 u32 phase_delay = 0;
303 int temperature;
304 int ret = 0;
305 u32 reg;
306 int i;
307
308 /* clock tuning is not needed for upto 52MHz */
309 if (ios->clock <= 52000000)
310 return 0;
311
312 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
313 if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
314 return 0;
315
316 thermal_dev = thermal_zone_get_zone_by_name("cpu_thermal");
317 if (IS_ERR(thermal_dev)) {
318 dev_err(dev, "Unable to get thermal zone for tuning\n");
319 return PTR_ERR(thermal_dev);
320 }
321
322 ret = thermal_zone_get_temp(thermal_dev, &temperature);
323 if (ret)
324 return ret;
325
326 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
327 reg |= DLL_SWT;
328 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
329
330 /*
331 * OMAP5/DRA74X/DRA72x Errata i802:
332 * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
333 * during the tuning procedure. So disable it during the
334 * tuning procedure.
335 */
336 if (host->ier & SDHCI_INT_DATA_CRC) {
337 host->ier &= ~SDHCI_INT_DATA_CRC;
338 dcrc_was_enabled = true;
339 }
340
341 omap_host->is_tuning = true;
342
343 /*
344 * Stage 1: Search for a maximum pass window ignoring any
345 * any single point failures. If the tuning value ends up
346 * near it, move away from it in stage 2 below
347 */
348 while (phase_delay <= MAX_PHASE_DELAY) {
349 sdhci_omap_set_dll(omap_host, phase_delay);
350
351 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
352 if (cur_match) {
353 if (prev_match) {
354 length++;
355 } else if (single_point_failure) {
356 /* ignore single point failure */
357 length++;
358 } else {
359 start_window = phase_delay;
360 length = 1;
361 }
362 } else {
363 single_point_failure = prev_match;
364 }
365
366 if (length > max_len) {
367 max_window = start_window;
368 max_len = length;
369 }
370
371 prev_match = cur_match;
372 phase_delay += 4;
373 }
374
375 if (!max_len) {
376 dev_err(dev, "Unable to find match\n");
377 ret = -EIO;
378 goto tuning_error;
379 }
380
381 /*
382 * Assign tuning value as a ratio of maximum pass window based
383 * on temperature
384 */
385 if (temperature < -20000)
386 phase_delay = min(max_window + 4 * (max_len - 1) - 24,
387 max_window +
388 DIV_ROUND_UP(13 * max_len, 16) * 4);
389 else if (temperature < 20000)
390 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
391 else if (temperature < 40000)
392 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
393 else if (temperature < 70000)
394 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
395 else if (temperature < 90000)
396 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
397 else if (temperature < 120000)
398 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
399 else
400 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
401
402 /*
403 * Stage 2: Search for a single point failure near the chosen tuning
404 * value in two steps. First in the +3 to +10 range and then in the
405 * +2 to -10 range. If found, move away from it in the appropriate
406 * direction by the appropriate amount depending on the temperature.
407 */
408 for (i = 3; i <= 10; i++) {
409 sdhci_omap_set_dll(omap_host, phase_delay + i);
410
411 if (mmc_send_tuning(mmc, opcode, NULL)) {
412 if (temperature < 10000)
413 phase_delay += i + 6;
414 else if (temperature < 20000)
415 phase_delay += i - 12;
416 else if (temperature < 70000)
417 phase_delay += i - 8;
418 else
419 phase_delay += i - 6;
420
421 goto single_failure_found;
422 }
423 }
424
425 for (i = 2; i >= -10; i--) {
426 sdhci_omap_set_dll(omap_host, phase_delay + i);
427
428 if (mmc_send_tuning(mmc, opcode, NULL)) {
429 if (temperature < 10000)
430 phase_delay += i + 12;
431 else if (temperature < 20000)
432 phase_delay += i + 8;
433 else if (temperature < 70000)
434 phase_delay += i + 8;
435 else if (temperature < 90000)
436 phase_delay += i + 10;
437 else
438 phase_delay += i + 12;
439
440 goto single_failure_found;
441 }
442 }
443
444 single_failure_found:
445 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
446 if (!(reg & AC12_SCLK_SEL)) {
447 ret = -EIO;
448 goto tuning_error;
449 }
450
451 sdhci_omap_set_dll(omap_host, phase_delay);
452
453 omap_host->is_tuning = false;
454
455 goto ret;
456
457 tuning_error:
458 omap_host->is_tuning = false;
459 dev_err(dev, "Tuning failed\n");
460 sdhci_omap_disable_tuning(omap_host);
461
462 ret:
463 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
464 /* Reenable forbidden interrupt */
465 if (dcrc_was_enabled)
466 host->ier |= SDHCI_INT_DATA_CRC;
467 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
468 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
469 return ret;
470 }
471
sdhci_omap_card_busy(struct mmc_host * mmc)472 static int sdhci_omap_card_busy(struct mmc_host *mmc)
473 {
474 u32 reg, ac12;
475 int ret = false;
476 struct sdhci_host *host = mmc_priv(mmc);
477 struct sdhci_pltfm_host *pltfm_host;
478 struct sdhci_omap_host *omap_host;
479 u32 ier = host->ier;
480
481 pltfm_host = sdhci_priv(host);
482 omap_host = sdhci_pltfm_priv(pltfm_host);
483
484 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
485 ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
486 reg &= ~CON_CLKEXTFREE;
487 if (ac12 & AC12_V1V8_SIGEN)
488 reg |= CON_CLKEXTFREE;
489 reg |= CON_PADEN;
490 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
491
492 disable_irq(host->irq);
493 ier |= SDHCI_INT_CARD_INT;
494 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
495 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
496
497 /*
498 * Delay is required for PSTATE to correctly reflect
499 * DLEV/CLEV values after PADEN is set.
500 */
501 usleep_range(50, 100);
502 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
503 if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0))
504 ret = true;
505
506 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
507 reg &= ~(CON_CLKEXTFREE | CON_PADEN);
508 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
509
510 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
511 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
512 enable_irq(host->irq);
513
514 return ret;
515 }
516
sdhci_omap_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)517 static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
518 struct mmc_ios *ios)
519 {
520 u32 reg;
521 int ret;
522 unsigned int iov;
523 struct sdhci_host *host = mmc_priv(mmc);
524 struct sdhci_pltfm_host *pltfm_host;
525 struct sdhci_omap_host *omap_host;
526 struct device *dev;
527
528 pltfm_host = sdhci_priv(host);
529 omap_host = sdhci_pltfm_priv(pltfm_host);
530 dev = omap_host->dev;
531
532 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
533 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
534 if (!(reg & CAPA_VS33))
535 return -EOPNOTSUPP;
536
537 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
538
539 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
540 reg &= ~AC12_V1V8_SIGEN;
541 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
542
543 iov = IOV_3V3;
544 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
545 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
546 if (!(reg & CAPA_VS18))
547 return -EOPNOTSUPP;
548
549 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
550
551 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
552 reg |= AC12_V1V8_SIGEN;
553 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
554
555 iov = IOV_1V8;
556 } else {
557 return -EOPNOTSUPP;
558 }
559
560 ret = sdhci_omap_enable_iov(omap_host, iov);
561 if (ret) {
562 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
563 return ret;
564 }
565
566 dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
567 return 0;
568 }
569
sdhci_omap_set_timing(struct sdhci_omap_host * omap_host,u8 timing)570 static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
571 {
572 int ret;
573 struct pinctrl_state *pinctrl_state;
574 struct device *dev = omap_host->dev;
575
576 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
577 return;
578
579 if (omap_host->timing == timing)
580 return;
581
582 sdhci_omap_stop_clock(omap_host);
583
584 pinctrl_state = omap_host->pinctrl_state[timing];
585 ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
586 if (ret) {
587 dev_err(dev, "failed to select pinctrl state\n");
588 return;
589 }
590
591 sdhci_omap_start_clock(omap_host);
592 omap_host->timing = timing;
593 }
594
sdhci_omap_set_power_mode(struct sdhci_omap_host * omap_host,u8 power_mode)595 static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
596 u8 power_mode)
597 {
598 if (omap_host->bus_mode == MMC_POWER_OFF)
599 sdhci_omap_disable_tuning(omap_host);
600 omap_host->power_mode = power_mode;
601 }
602
sdhci_omap_set_bus_mode(struct sdhci_omap_host * omap_host,unsigned int mode)603 static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
604 unsigned int mode)
605 {
606 u32 reg;
607
608 if (omap_host->bus_mode == mode)
609 return;
610
611 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
612 if (mode == MMC_BUSMODE_OPENDRAIN)
613 reg |= CON_OD;
614 else
615 reg &= ~CON_OD;
616 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
617
618 omap_host->bus_mode = mode;
619 }
620
sdhci_omap_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)621 static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
622 {
623 struct sdhci_host *host = mmc_priv(mmc);
624 struct sdhci_pltfm_host *pltfm_host;
625 struct sdhci_omap_host *omap_host;
626
627 pltfm_host = sdhci_priv(host);
628 omap_host = sdhci_pltfm_priv(pltfm_host);
629
630 sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
631 sdhci_omap_set_timing(omap_host, ios->timing);
632 sdhci_set_ios(mmc, ios);
633 sdhci_omap_set_power_mode(omap_host, ios->power_mode);
634 }
635
sdhci_omap_calc_divisor(struct sdhci_pltfm_host * host,unsigned int clock)636 static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
637 unsigned int clock)
638 {
639 u16 dsor;
640
641 dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
642 if (dsor > SYSCTL_CLKD_MAX)
643 dsor = SYSCTL_CLKD_MAX;
644
645 return dsor;
646 }
647
sdhci_omap_start_clock(struct sdhci_omap_host * omap_host)648 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
649 {
650 u32 reg;
651
652 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
653 reg |= SYSCTL_CEN;
654 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
655 }
656
sdhci_omap_stop_clock(struct sdhci_omap_host * omap_host)657 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
658 {
659 u32 reg;
660
661 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
662 reg &= ~SYSCTL_CEN;
663 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
664 }
665
sdhci_omap_set_clock(struct sdhci_host * host,unsigned int clock)666 static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
667 {
668 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
669 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
670 unsigned long clkdiv;
671
672 sdhci_omap_stop_clock(omap_host);
673
674 if (!clock)
675 return;
676
677 clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
678 clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
679 sdhci_enable_clk(host, clkdiv);
680
681 sdhci_omap_start_clock(omap_host);
682 }
683
sdhci_omap_set_power(struct sdhci_host * host,unsigned char mode,unsigned short vdd)684 static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
685 unsigned short vdd)
686 {
687 struct mmc_host *mmc = host->mmc;
688
689 if (!IS_ERR(mmc->supply.vmmc))
690 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
691 }
692
sdhci_omap_enable_dma(struct sdhci_host * host)693 static int sdhci_omap_enable_dma(struct sdhci_host *host)
694 {
695 u32 reg;
696 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
697 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
698
699 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
700 reg &= ~CON_DMA_MASTER;
701 /* Switch to DMA slave mode when using external DMA */
702 if (!host->use_external_dma)
703 reg |= CON_DMA_MASTER;
704
705 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
706
707 return 0;
708 }
709
sdhci_omap_get_min_clock(struct sdhci_host * host)710 static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
711 {
712 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
713
714 return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
715 }
716
sdhci_omap_set_bus_width(struct sdhci_host * host,int width)717 static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
718 {
719 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
720 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
721 u32 reg;
722
723 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
724 if (width == MMC_BUS_WIDTH_8)
725 reg |= CON_DW8;
726 else
727 reg &= ~CON_DW8;
728 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
729
730 sdhci_set_bus_width(host, width);
731 }
732
sdhci_omap_init_74_clocks(struct sdhci_host * host,u8 power_mode)733 static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
734 {
735 u32 reg;
736 ktime_t timeout;
737 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
738 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
739
740 if (omap_host->power_mode == power_mode)
741 return;
742
743 if (power_mode != MMC_POWER_ON)
744 return;
745
746 disable_irq(host->irq);
747
748 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
749 reg |= CON_INIT;
750 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
751 sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
752
753 /* wait 1ms */
754 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
755 while (1) {
756 bool timedout = ktime_after(ktime_get(), timeout);
757
758 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)
759 break;
760 if (WARN_ON(timedout))
761 return;
762 usleep_range(5, 10);
763 }
764
765 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
766 reg &= ~CON_INIT;
767 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
768 sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
769
770 enable_irq(host->irq);
771 }
772
sdhci_omap_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)773 static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
774 unsigned int timing)
775 {
776 u32 reg;
777 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
778 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
779
780 sdhci_omap_stop_clock(omap_host);
781
782 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
783 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
784 reg |= CON_DDR;
785 else
786 reg &= ~CON_DDR;
787 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
788
789 sdhci_set_uhs_signaling(host, timing);
790 sdhci_omap_start_clock(omap_host);
791 }
792
793 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
sdhci_omap_reset(struct sdhci_host * host,u8 mask)794 static void sdhci_omap_reset(struct sdhci_host *host, u8 mask)
795 {
796 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
797 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
798 unsigned long limit = MMC_TIMEOUT_US;
799 unsigned long i = 0;
800
801 /* Don't reset data lines during tuning operation */
802 if (omap_host->is_tuning)
803 mask &= ~SDHCI_RESET_DATA;
804
805 if (omap_host->flags & SDHCI_OMAP_SPECIAL_RESET) {
806 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
807 while ((!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) &&
808 (i++ < limit))
809 udelay(1);
810 i = 0;
811 while ((sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) &&
812 (i++ < limit))
813 udelay(1);
814
815 if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)
816 dev_err(mmc_dev(host->mmc),
817 "Timeout waiting on controller reset in %s\n",
818 __func__);
819 return;
820 }
821
822 sdhci_reset(host, mask);
823 }
824
825 #define CMD_ERR_MASK (SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX |\
826 SDHCI_INT_TIMEOUT)
827 #define CMD_MASK (CMD_ERR_MASK | SDHCI_INT_RESPONSE)
828
sdhci_omap_irq(struct sdhci_host * host,u32 intmask)829 static u32 sdhci_omap_irq(struct sdhci_host *host, u32 intmask)
830 {
831 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
832 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
833
834 if (omap_host->is_tuning && host->cmd && !host->data_early &&
835 (intmask & CMD_ERR_MASK)) {
836
837 /*
838 * Since we are not resetting data lines during tuning
839 * operation, data error or data complete interrupts
840 * might still arrive. Mark this request as a failure
841 * but still wait for the data interrupt
842 */
843 if (intmask & SDHCI_INT_TIMEOUT)
844 host->cmd->error = -ETIMEDOUT;
845 else
846 host->cmd->error = -EILSEQ;
847
848 host->cmd = NULL;
849
850 /*
851 * Sometimes command error interrupts and command complete
852 * interrupt will arrive together. Clear all command related
853 * interrupts here.
854 */
855 sdhci_writel(host, intmask & CMD_MASK, SDHCI_INT_STATUS);
856 intmask &= ~CMD_MASK;
857 }
858
859 return intmask;
860 }
861
sdhci_omap_set_timeout(struct sdhci_host * host,struct mmc_command * cmd)862 static void sdhci_omap_set_timeout(struct sdhci_host *host,
863 struct mmc_command *cmd)
864 {
865 if (cmd->opcode == MMC_ERASE)
866 sdhci_set_data_timeout_irq(host, false);
867
868 __sdhci_set_timeout(host, cmd);
869 }
870
871 static struct sdhci_ops sdhci_omap_ops = {
872 .set_clock = sdhci_omap_set_clock,
873 .set_power = sdhci_omap_set_power,
874 .enable_dma = sdhci_omap_enable_dma,
875 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
876 .get_min_clock = sdhci_omap_get_min_clock,
877 .set_bus_width = sdhci_omap_set_bus_width,
878 .platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
879 .reset = sdhci_omap_reset,
880 .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
881 .irq = sdhci_omap_irq,
882 .set_timeout = sdhci_omap_set_timeout,
883 };
884
sdhci_omap_set_capabilities(struct sdhci_omap_host * omap_host)885 static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
886 {
887 u32 reg;
888 int ret = 0;
889 struct device *dev = omap_host->dev;
890 struct regulator *vqmmc;
891
892 vqmmc = regulator_get(dev, "vqmmc");
893 if (IS_ERR(vqmmc)) {
894 ret = PTR_ERR(vqmmc);
895 goto reg_put;
896 }
897
898 /* voltage capabilities might be set by boot loader, clear it */
899 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
900 reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
901
902 if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3))
903 reg |= CAPA_VS33;
904 if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8))
905 reg |= CAPA_VS18;
906
907 sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
908
909 reg_put:
910 regulator_put(vqmmc);
911
912 return ret;
913 }
914
915 static const struct sdhci_pltfm_data sdhci_omap_pdata = {
916 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
917 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
918 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
919 SDHCI_QUIRK_NO_HISPD_BIT |
920 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
921 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
922 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
923 SDHCI_QUIRK2_RSP_136_HAS_CRC |
924 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
925 .ops = &sdhci_omap_ops,
926 };
927
928 static const struct sdhci_omap_data k2g_data = {
929 .offset = 0x200,
930 };
931
932 static const struct sdhci_omap_data am335_data = {
933 .offset = 0x200,
934 .flags = SDHCI_OMAP_SPECIAL_RESET,
935 };
936
937 static const struct sdhci_omap_data am437_data = {
938 .offset = 0x200,
939 .flags = SDHCI_OMAP_SPECIAL_RESET,
940 };
941
942 static const struct sdhci_omap_data dra7_data = {
943 .offset = 0x200,
944 .flags = SDHCI_OMAP_REQUIRE_IODELAY,
945 };
946
947 static const struct of_device_id omap_sdhci_match[] = {
948 { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
949 { .compatible = "ti,k2g-sdhci", .data = &k2g_data },
950 { .compatible = "ti,am335-sdhci", .data = &am335_data },
951 { .compatible = "ti,am437-sdhci", .data = &am437_data },
952 {},
953 };
954 MODULE_DEVICE_TABLE(of, omap_sdhci_match);
955
956 static struct pinctrl_state
sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host * omap_host,char * mode,u32 * caps,u32 capmask)957 *sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
958 u32 *caps, u32 capmask)
959 {
960 struct device *dev = omap_host->dev;
961 char *version = omap_host->version;
962 struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
963 char str[20];
964
965 if (!(*caps & capmask))
966 goto ret;
967
968 if (version) {
969 snprintf(str, 20, "%s-%s", mode, version);
970 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
971 }
972
973 if (IS_ERR(pinctrl_state))
974 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
975
976 if (IS_ERR(pinctrl_state)) {
977 dev_err(dev, "no pinctrl state for %s mode", mode);
978 *caps &= ~capmask;
979 }
980
981 ret:
982 return pinctrl_state;
983 }
984
sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host * omap_host)985 static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
986 *omap_host)
987 {
988 struct device *dev = omap_host->dev;
989 struct sdhci_host *host = omap_host->host;
990 struct mmc_host *mmc = host->mmc;
991 u32 *caps = &mmc->caps;
992 u32 *caps2 = &mmc->caps2;
993 struct pinctrl_state *state;
994 struct pinctrl_state **pinctrl_state;
995
996 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
997 return 0;
998
999 pinctrl_state = devm_kcalloc(dev,
1000 MMC_TIMING_MMC_HS200 + 1,
1001 sizeof(*pinctrl_state),
1002 GFP_KERNEL);
1003 if (!pinctrl_state)
1004 return -ENOMEM;
1005
1006 omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
1007 if (IS_ERR(omap_host->pinctrl)) {
1008 dev_err(dev, "Cannot get pinctrl\n");
1009 return PTR_ERR(omap_host->pinctrl);
1010 }
1011
1012 state = pinctrl_lookup_state(omap_host->pinctrl, "default");
1013 if (IS_ERR(state)) {
1014 dev_err(dev, "no pinctrl state for default mode\n");
1015 return PTR_ERR(state);
1016 }
1017 pinctrl_state[MMC_TIMING_LEGACY] = state;
1018
1019 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
1020 MMC_CAP_UHS_SDR104);
1021 if (!IS_ERR(state))
1022 pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
1023
1024 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
1025 MMC_CAP_UHS_DDR50);
1026 if (!IS_ERR(state))
1027 pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
1028
1029 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
1030 MMC_CAP_UHS_SDR50);
1031 if (!IS_ERR(state))
1032 pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
1033
1034 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
1035 MMC_CAP_UHS_SDR25);
1036 if (!IS_ERR(state))
1037 pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
1038
1039 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
1040 MMC_CAP_UHS_SDR12);
1041 if (!IS_ERR(state))
1042 pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
1043
1044 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
1045 MMC_CAP_1_8V_DDR);
1046 if (!IS_ERR(state)) {
1047 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1048 } else {
1049 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
1050 caps,
1051 MMC_CAP_3_3V_DDR);
1052 if (!IS_ERR(state))
1053 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1054 }
1055
1056 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1057 MMC_CAP_SD_HIGHSPEED);
1058 if (!IS_ERR(state))
1059 pinctrl_state[MMC_TIMING_SD_HS] = state;
1060
1061 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1062 MMC_CAP_MMC_HIGHSPEED);
1063 if (!IS_ERR(state))
1064 pinctrl_state[MMC_TIMING_MMC_HS] = state;
1065
1066 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
1067 MMC_CAP2_HS200_1_8V_SDR);
1068 if (!IS_ERR(state))
1069 pinctrl_state[MMC_TIMING_MMC_HS200] = state;
1070
1071 omap_host->pinctrl_state = pinctrl_state;
1072
1073 return 0;
1074 }
1075
1076 static const struct soc_device_attribute sdhci_omap_soc_devices[] = {
1077 {
1078 .machine = "DRA7[45]*",
1079 .revision = "ES1.[01]",
1080 },
1081 {
1082 /* sentinel */
1083 }
1084 };
1085
sdhci_omap_probe(struct platform_device * pdev)1086 static int sdhci_omap_probe(struct platform_device *pdev)
1087 {
1088 int ret;
1089 u32 offset;
1090 struct device *dev = &pdev->dev;
1091 struct sdhci_host *host;
1092 struct sdhci_pltfm_host *pltfm_host;
1093 struct sdhci_omap_host *omap_host;
1094 struct mmc_host *mmc;
1095 const struct of_device_id *match;
1096 struct sdhci_omap_data *data;
1097 const struct soc_device_attribute *soc;
1098 struct resource *regs;
1099
1100 match = of_match_device(omap_sdhci_match, dev);
1101 if (!match)
1102 return -EINVAL;
1103
1104 data = (struct sdhci_omap_data *)match->data;
1105 if (!data) {
1106 dev_err(dev, "no sdhci omap data\n");
1107 return -EINVAL;
1108 }
1109 offset = data->offset;
1110
1111 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1112 if (!regs)
1113 return -ENXIO;
1114
1115 host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
1116 sizeof(*omap_host));
1117 if (IS_ERR(host)) {
1118 dev_err(dev, "Failed sdhci_pltfm_init\n");
1119 return PTR_ERR(host);
1120 }
1121
1122 pltfm_host = sdhci_priv(host);
1123 omap_host = sdhci_pltfm_priv(pltfm_host);
1124 omap_host->host = host;
1125 omap_host->base = host->ioaddr;
1126 omap_host->dev = dev;
1127 omap_host->power_mode = MMC_POWER_UNDEFINED;
1128 omap_host->timing = MMC_TIMING_LEGACY;
1129 omap_host->flags = data->flags;
1130 host->ioaddr += offset;
1131 host->mapbase = regs->start + offset;
1132
1133 mmc = host->mmc;
1134 sdhci_get_of_property(pdev);
1135 ret = mmc_of_parse(mmc);
1136 if (ret)
1137 goto err_pltfm_free;
1138
1139 soc = soc_device_match(sdhci_omap_soc_devices);
1140 if (soc) {
1141 omap_host->version = "rev11";
1142 if (!strcmp(dev_name(dev), "4809c000.mmc"))
1143 mmc->f_max = 96000000;
1144 if (!strcmp(dev_name(dev), "480b4000.mmc"))
1145 mmc->f_max = 48000000;
1146 if (!strcmp(dev_name(dev), "480ad000.mmc"))
1147 mmc->f_max = 48000000;
1148 }
1149
1150 if (!mmc_can_gpio_ro(mmc))
1151 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
1152
1153 pltfm_host->clk = devm_clk_get(dev, "fck");
1154 if (IS_ERR(pltfm_host->clk)) {
1155 ret = PTR_ERR(pltfm_host->clk);
1156 goto err_pltfm_free;
1157 }
1158
1159 ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
1160 if (ret) {
1161 dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
1162 goto err_pltfm_free;
1163 }
1164
1165 omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
1166 if (IS_ERR(omap_host->pbias)) {
1167 ret = PTR_ERR(omap_host->pbias);
1168 if (ret != -ENODEV)
1169 goto err_pltfm_free;
1170 dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
1171 }
1172 omap_host->pbias_enabled = false;
1173
1174 /*
1175 * omap_device_pm_domain has callbacks to enable the main
1176 * functional clock, interface clock and also configure the
1177 * SYSCONFIG register of omap devices. The callback will be invoked
1178 * as part of pm_runtime_get_sync.
1179 */
1180 pm_runtime_enable(dev);
1181 ret = pm_runtime_get_sync(dev);
1182 if (ret < 0) {
1183 dev_err(dev, "pm_runtime_get_sync failed\n");
1184 pm_runtime_put_noidle(dev);
1185 goto err_rpm_disable;
1186 }
1187
1188 ret = sdhci_omap_set_capabilities(omap_host);
1189 if (ret) {
1190 dev_err(dev, "failed to set system capabilities\n");
1191 goto err_put_sync;
1192 }
1193
1194 host->mmc_host_ops.start_signal_voltage_switch =
1195 sdhci_omap_start_signal_voltage_switch;
1196 host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
1197 host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
1198 host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
1199 host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq;
1200
1201 /* Switch to external DMA only if there is the "dmas" property */
1202 if (of_find_property(dev->of_node, "dmas", NULL))
1203 sdhci_switch_external_dma(host, true);
1204
1205 /* R1B responses is required to properly manage HW busy detection. */
1206 mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
1207
1208 ret = sdhci_setup_host(host);
1209 if (ret)
1210 goto err_put_sync;
1211
1212 ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
1213 if (ret)
1214 goto err_cleanup_host;
1215
1216 ret = __sdhci_add_host(host);
1217 if (ret)
1218 goto err_cleanup_host;
1219
1220 return 0;
1221
1222 err_cleanup_host:
1223 sdhci_cleanup_host(host);
1224
1225 err_put_sync:
1226 pm_runtime_put_sync(dev);
1227
1228 err_rpm_disable:
1229 pm_runtime_disable(dev);
1230
1231 err_pltfm_free:
1232 sdhci_pltfm_free(pdev);
1233 return ret;
1234 }
1235
sdhci_omap_remove(struct platform_device * pdev)1236 static int sdhci_omap_remove(struct platform_device *pdev)
1237 {
1238 struct device *dev = &pdev->dev;
1239 struct sdhci_host *host = platform_get_drvdata(pdev);
1240
1241 sdhci_remove_host(host, true);
1242 pm_runtime_put_sync(dev);
1243 pm_runtime_disable(dev);
1244 sdhci_pltfm_free(pdev);
1245
1246 return 0;
1247 }
1248 #ifdef CONFIG_PM_SLEEP
sdhci_omap_context_save(struct sdhci_omap_host * omap_host)1249 static void sdhci_omap_context_save(struct sdhci_omap_host *omap_host)
1250 {
1251 omap_host->con = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
1252 omap_host->hctl = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
1253 omap_host->sysctl = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
1254 omap_host->capa = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
1255 omap_host->ie = sdhci_omap_readl(omap_host, SDHCI_OMAP_IE);
1256 omap_host->ise = sdhci_omap_readl(omap_host, SDHCI_OMAP_ISE);
1257 }
1258
1259 /* Order matters here, HCTL must be restored in two phases */
sdhci_omap_context_restore(struct sdhci_omap_host * omap_host)1260 static void sdhci_omap_context_restore(struct sdhci_omap_host *omap_host)
1261 {
1262 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, omap_host->hctl);
1263 sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, omap_host->capa);
1264 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, omap_host->hctl);
1265
1266 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, omap_host->sysctl);
1267 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, omap_host->con);
1268 sdhci_omap_writel(omap_host, SDHCI_OMAP_IE, omap_host->ie);
1269 sdhci_omap_writel(omap_host, SDHCI_OMAP_ISE, omap_host->ise);
1270 }
1271
sdhci_omap_suspend(struct device * dev)1272 static int __maybe_unused sdhci_omap_suspend(struct device *dev)
1273 {
1274 struct sdhci_host *host = dev_get_drvdata(dev);
1275 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1276 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
1277
1278 sdhci_suspend_host(host);
1279
1280 sdhci_omap_context_save(omap_host);
1281
1282 pinctrl_pm_select_idle_state(dev);
1283
1284 pm_runtime_force_suspend(dev);
1285
1286 return 0;
1287 }
1288
sdhci_omap_resume(struct device * dev)1289 static int __maybe_unused sdhci_omap_resume(struct device *dev)
1290 {
1291 struct sdhci_host *host = dev_get_drvdata(dev);
1292 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1293 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
1294
1295 pm_runtime_force_resume(dev);
1296
1297 pinctrl_pm_select_default_state(dev);
1298
1299 sdhci_omap_context_restore(omap_host);
1300
1301 sdhci_resume_host(host);
1302
1303 return 0;
1304 }
1305 #endif
1306 static SIMPLE_DEV_PM_OPS(sdhci_omap_dev_pm_ops, sdhci_omap_suspend,
1307 sdhci_omap_resume);
1308
1309 static struct platform_driver sdhci_omap_driver = {
1310 .probe = sdhci_omap_probe,
1311 .remove = sdhci_omap_remove,
1312 .driver = {
1313 .name = "sdhci-omap",
1314 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1315 .pm = &sdhci_omap_dev_pm_ops,
1316 .of_match_table = omap_sdhci_match,
1317 },
1318 };
1319
1320 module_platform_driver(sdhci_omap_driver);
1321
1322 MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
1323 MODULE_AUTHOR("Texas Instruments Inc.");
1324 MODULE_LICENSE("GPL v2");
1325 MODULE_ALIAS("platform:sdhci_omap");
1326