1 /*
2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/eq.h>
44 #include <linux/debugfs.h>
45
46 #include "mlx5_core.h"
47 #include "lib/eq.h"
48
49 enum {
50 CMD_IF_REV = 5,
51 };
52
53 enum {
54 CMD_MODE_POLLING,
55 CMD_MODE_EVENTS
56 };
57
58 enum {
59 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
60 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
61 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
62 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
63 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
64 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
65 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
66 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
67 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
68 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
69 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
70 };
71
72 static struct mlx5_cmd_work_ent *
cmd_alloc_ent(struct mlx5_cmd * cmd,struct mlx5_cmd_msg * in,struct mlx5_cmd_msg * out,void * uout,int uout_size,mlx5_cmd_cbk_t cbk,void * context,int page_queue)73 cmd_alloc_ent(struct mlx5_cmd *cmd, struct mlx5_cmd_msg *in,
74 struct mlx5_cmd_msg *out, void *uout, int uout_size,
75 mlx5_cmd_cbk_t cbk, void *context, int page_queue)
76 {
77 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
78 struct mlx5_cmd_work_ent *ent;
79
80 ent = kzalloc(sizeof(*ent), alloc_flags);
81 if (!ent)
82 return ERR_PTR(-ENOMEM);
83
84 ent->idx = -EINVAL;
85 ent->in = in;
86 ent->out = out;
87 ent->uout = uout;
88 ent->uout_size = uout_size;
89 ent->callback = cbk;
90 ent->context = context;
91 ent->cmd = cmd;
92 ent->page_queue = page_queue;
93 refcount_set(&ent->refcnt, 1);
94
95 return ent;
96 }
97
cmd_free_ent(struct mlx5_cmd_work_ent * ent)98 static void cmd_free_ent(struct mlx5_cmd_work_ent *ent)
99 {
100 kfree(ent);
101 }
102
alloc_token(struct mlx5_cmd * cmd)103 static u8 alloc_token(struct mlx5_cmd *cmd)
104 {
105 u8 token;
106
107 spin_lock(&cmd->token_lock);
108 cmd->token++;
109 if (cmd->token == 0)
110 cmd->token++;
111 token = cmd->token;
112 spin_unlock(&cmd->token_lock);
113
114 return token;
115 }
116
cmd_alloc_index(struct mlx5_cmd * cmd)117 static int cmd_alloc_index(struct mlx5_cmd *cmd)
118 {
119 unsigned long flags;
120 int ret;
121
122 spin_lock_irqsave(&cmd->alloc_lock, flags);
123 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
124 if (ret < cmd->max_reg_cmds)
125 clear_bit(ret, &cmd->bitmask);
126 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
127
128 return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
129 }
130
cmd_free_index(struct mlx5_cmd * cmd,int idx)131 static void cmd_free_index(struct mlx5_cmd *cmd, int idx)
132 {
133 lockdep_assert_held(&cmd->alloc_lock);
134 set_bit(idx, &cmd->bitmask);
135 }
136
cmd_ent_get(struct mlx5_cmd_work_ent * ent)137 static void cmd_ent_get(struct mlx5_cmd_work_ent *ent)
138 {
139 refcount_inc(&ent->refcnt);
140 }
141
cmd_ent_put(struct mlx5_cmd_work_ent * ent)142 static void cmd_ent_put(struct mlx5_cmd_work_ent *ent)
143 {
144 struct mlx5_cmd *cmd = ent->cmd;
145 unsigned long flags;
146
147 spin_lock_irqsave(&cmd->alloc_lock, flags);
148 if (!refcount_dec_and_test(&ent->refcnt))
149 goto out;
150
151 if (ent->idx >= 0) {
152 cmd_free_index(cmd, ent->idx);
153 up(ent->page_queue ? &cmd->pages_sem : &cmd->sem);
154 }
155
156 cmd_free_ent(ent);
157 out:
158 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
159 }
160
get_inst(struct mlx5_cmd * cmd,int idx)161 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
162 {
163 return cmd->cmd_buf + (idx << cmd->log_stride);
164 }
165
mlx5_calc_cmd_blocks(struct mlx5_cmd_msg * msg)166 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
167 {
168 int size = msg->len;
169 int blen = size - min_t(int, sizeof(msg->first.data), size);
170
171 return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
172 }
173
xor8_buf(void * buf,size_t offset,int len)174 static u8 xor8_buf(void *buf, size_t offset, int len)
175 {
176 u8 *ptr = buf;
177 u8 sum = 0;
178 int i;
179 int end = len + offset;
180
181 for (i = offset; i < end; i++)
182 sum ^= ptr[i];
183
184 return sum;
185 }
186
verify_block_sig(struct mlx5_cmd_prot_block * block)187 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
188 {
189 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
190 int xor_len = sizeof(*block) - sizeof(block->data) - 1;
191
192 if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
193 return -EINVAL;
194
195 if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
196 return -EINVAL;
197
198 return 0;
199 }
200
calc_block_sig(struct mlx5_cmd_prot_block * block)201 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
202 {
203 int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
204 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
205
206 block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
207 block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
208 }
209
calc_chain_sig(struct mlx5_cmd_msg * msg)210 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
211 {
212 struct mlx5_cmd_mailbox *next = msg->next;
213 int n = mlx5_calc_cmd_blocks(msg);
214 int i = 0;
215
216 for (i = 0; i < n && next; i++) {
217 calc_block_sig(next->buf);
218 next = next->next;
219 }
220 }
221
set_signature(struct mlx5_cmd_work_ent * ent,int csum)222 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
223 {
224 ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay));
225 if (csum) {
226 calc_chain_sig(ent->in);
227 calc_chain_sig(ent->out);
228 }
229 }
230
poll_timeout(struct mlx5_cmd_work_ent * ent)231 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
232 {
233 unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
234 u8 own;
235
236 do {
237 own = READ_ONCE(ent->lay->status_own);
238 if (!(own & CMD_OWNER_HW)) {
239 ent->ret = 0;
240 return;
241 }
242 cond_resched();
243 } while (time_before(jiffies, poll_end));
244
245 ent->ret = -ETIMEDOUT;
246 }
247
verify_signature(struct mlx5_cmd_work_ent * ent)248 static int verify_signature(struct mlx5_cmd_work_ent *ent)
249 {
250 struct mlx5_cmd_mailbox *next = ent->out->next;
251 int n = mlx5_calc_cmd_blocks(ent->out);
252 int err;
253 u8 sig;
254 int i = 0;
255
256 sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
257 if (sig != 0xff)
258 return -EINVAL;
259
260 for (i = 0; i < n && next; i++) {
261 err = verify_block_sig(next->buf);
262 if (err)
263 return err;
264
265 next = next->next;
266 }
267
268 return 0;
269 }
270
dump_buf(void * buf,int size,int data_only,int offset)271 static void dump_buf(void *buf, int size, int data_only, int offset)
272 {
273 __be32 *p = buf;
274 int i;
275
276 for (i = 0; i < size; i += 16) {
277 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
278 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
279 be32_to_cpu(p[3]));
280 p += 4;
281 offset += 16;
282 }
283 if (!data_only)
284 pr_debug("\n");
285 }
286
mlx5_internal_err_ret_value(struct mlx5_core_dev * dev,u16 op,u32 * synd,u8 * status)287 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
288 u32 *synd, u8 *status)
289 {
290 *synd = 0;
291 *status = 0;
292
293 switch (op) {
294 case MLX5_CMD_OP_TEARDOWN_HCA:
295 case MLX5_CMD_OP_DISABLE_HCA:
296 case MLX5_CMD_OP_MANAGE_PAGES:
297 case MLX5_CMD_OP_DESTROY_MKEY:
298 case MLX5_CMD_OP_DESTROY_EQ:
299 case MLX5_CMD_OP_DESTROY_CQ:
300 case MLX5_CMD_OP_DESTROY_QP:
301 case MLX5_CMD_OP_DESTROY_PSV:
302 case MLX5_CMD_OP_DESTROY_SRQ:
303 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
304 case MLX5_CMD_OP_DESTROY_XRQ:
305 case MLX5_CMD_OP_DESTROY_DCT:
306 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
307 case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
308 case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
309 case MLX5_CMD_OP_DEALLOC_PD:
310 case MLX5_CMD_OP_DEALLOC_UAR:
311 case MLX5_CMD_OP_DETACH_FROM_MCG:
312 case MLX5_CMD_OP_DEALLOC_XRCD:
313 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
314 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
315 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
316 case MLX5_CMD_OP_DESTROY_LAG:
317 case MLX5_CMD_OP_DESTROY_VPORT_LAG:
318 case MLX5_CMD_OP_DESTROY_TIR:
319 case MLX5_CMD_OP_DESTROY_SQ:
320 case MLX5_CMD_OP_DESTROY_RQ:
321 case MLX5_CMD_OP_DESTROY_RMP:
322 case MLX5_CMD_OP_DESTROY_TIS:
323 case MLX5_CMD_OP_DESTROY_RQT:
324 case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
325 case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
326 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
327 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
328 case MLX5_CMD_OP_2ERR_QP:
329 case MLX5_CMD_OP_2RST_QP:
330 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
331 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
332 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
333 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
334 case MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT:
335 case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
336 case MLX5_CMD_OP_FPGA_DESTROY_QP:
337 case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
338 case MLX5_CMD_OP_DEALLOC_MEMIC:
339 case MLX5_CMD_OP_PAGE_FAULT_RESUME:
340 case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS:
341 return MLX5_CMD_STAT_OK;
342
343 case MLX5_CMD_OP_QUERY_HCA_CAP:
344 case MLX5_CMD_OP_QUERY_ADAPTER:
345 case MLX5_CMD_OP_INIT_HCA:
346 case MLX5_CMD_OP_ENABLE_HCA:
347 case MLX5_CMD_OP_QUERY_PAGES:
348 case MLX5_CMD_OP_SET_HCA_CAP:
349 case MLX5_CMD_OP_QUERY_ISSI:
350 case MLX5_CMD_OP_SET_ISSI:
351 case MLX5_CMD_OP_CREATE_MKEY:
352 case MLX5_CMD_OP_QUERY_MKEY:
353 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
354 case MLX5_CMD_OP_CREATE_EQ:
355 case MLX5_CMD_OP_QUERY_EQ:
356 case MLX5_CMD_OP_GEN_EQE:
357 case MLX5_CMD_OP_CREATE_CQ:
358 case MLX5_CMD_OP_QUERY_CQ:
359 case MLX5_CMD_OP_MODIFY_CQ:
360 case MLX5_CMD_OP_CREATE_QP:
361 case MLX5_CMD_OP_RST2INIT_QP:
362 case MLX5_CMD_OP_INIT2RTR_QP:
363 case MLX5_CMD_OP_RTR2RTS_QP:
364 case MLX5_CMD_OP_RTS2RTS_QP:
365 case MLX5_CMD_OP_SQERR2RTS_QP:
366 case MLX5_CMD_OP_QUERY_QP:
367 case MLX5_CMD_OP_SQD_RTS_QP:
368 case MLX5_CMD_OP_INIT2INIT_QP:
369 case MLX5_CMD_OP_CREATE_PSV:
370 case MLX5_CMD_OP_CREATE_SRQ:
371 case MLX5_CMD_OP_QUERY_SRQ:
372 case MLX5_CMD_OP_ARM_RQ:
373 case MLX5_CMD_OP_CREATE_XRC_SRQ:
374 case MLX5_CMD_OP_QUERY_XRC_SRQ:
375 case MLX5_CMD_OP_ARM_XRC_SRQ:
376 case MLX5_CMD_OP_CREATE_XRQ:
377 case MLX5_CMD_OP_QUERY_XRQ:
378 case MLX5_CMD_OP_ARM_XRQ:
379 case MLX5_CMD_OP_CREATE_DCT:
380 case MLX5_CMD_OP_DRAIN_DCT:
381 case MLX5_CMD_OP_QUERY_DCT:
382 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
383 case MLX5_CMD_OP_QUERY_VPORT_STATE:
384 case MLX5_CMD_OP_MODIFY_VPORT_STATE:
385 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
386 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
387 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
388 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
389 case MLX5_CMD_OP_SET_ROCE_ADDRESS:
390 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
391 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
392 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
393 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
394 case MLX5_CMD_OP_QUERY_VNIC_ENV:
395 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
396 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
397 case MLX5_CMD_OP_QUERY_Q_COUNTER:
398 case MLX5_CMD_OP_SET_MONITOR_COUNTER:
399 case MLX5_CMD_OP_ARM_MONITOR_COUNTER:
400 case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
401 case MLX5_CMD_OP_QUERY_RATE_LIMIT:
402 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
403 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
404 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
405 case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
406 case MLX5_CMD_OP_ALLOC_PD:
407 case MLX5_CMD_OP_ALLOC_UAR:
408 case MLX5_CMD_OP_CONFIG_INT_MODERATION:
409 case MLX5_CMD_OP_ACCESS_REG:
410 case MLX5_CMD_OP_ATTACH_TO_MCG:
411 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
412 case MLX5_CMD_OP_MAD_IFC:
413 case MLX5_CMD_OP_QUERY_MAD_DEMUX:
414 case MLX5_CMD_OP_SET_MAD_DEMUX:
415 case MLX5_CMD_OP_NOP:
416 case MLX5_CMD_OP_ALLOC_XRCD:
417 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
418 case MLX5_CMD_OP_QUERY_CONG_STATUS:
419 case MLX5_CMD_OP_MODIFY_CONG_STATUS:
420 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
421 case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
422 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
423 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
424 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
425 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
426 case MLX5_CMD_OP_CREATE_LAG:
427 case MLX5_CMD_OP_MODIFY_LAG:
428 case MLX5_CMD_OP_QUERY_LAG:
429 case MLX5_CMD_OP_CREATE_VPORT_LAG:
430 case MLX5_CMD_OP_CREATE_TIR:
431 case MLX5_CMD_OP_MODIFY_TIR:
432 case MLX5_CMD_OP_QUERY_TIR:
433 case MLX5_CMD_OP_CREATE_SQ:
434 case MLX5_CMD_OP_MODIFY_SQ:
435 case MLX5_CMD_OP_QUERY_SQ:
436 case MLX5_CMD_OP_CREATE_RQ:
437 case MLX5_CMD_OP_MODIFY_RQ:
438 case MLX5_CMD_OP_QUERY_RQ:
439 case MLX5_CMD_OP_CREATE_RMP:
440 case MLX5_CMD_OP_MODIFY_RMP:
441 case MLX5_CMD_OP_QUERY_RMP:
442 case MLX5_CMD_OP_CREATE_TIS:
443 case MLX5_CMD_OP_MODIFY_TIS:
444 case MLX5_CMD_OP_QUERY_TIS:
445 case MLX5_CMD_OP_CREATE_RQT:
446 case MLX5_CMD_OP_MODIFY_RQT:
447 case MLX5_CMD_OP_QUERY_RQT:
448
449 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
450 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
451 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
452 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
453 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
454 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
455 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
456 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
457 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
458 case MLX5_CMD_OP_FPGA_CREATE_QP:
459 case MLX5_CMD_OP_FPGA_MODIFY_QP:
460 case MLX5_CMD_OP_FPGA_QUERY_QP:
461 case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
462 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
463 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
464 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
465 case MLX5_CMD_OP_CREATE_UCTX:
466 case MLX5_CMD_OP_DESTROY_UCTX:
467 case MLX5_CMD_OP_CREATE_UMEM:
468 case MLX5_CMD_OP_DESTROY_UMEM:
469 case MLX5_CMD_OP_ALLOC_MEMIC:
470 case MLX5_CMD_OP_MODIFY_XRQ:
471 case MLX5_CMD_OP_RELEASE_XRQ_ERROR:
472 *status = MLX5_DRIVER_STATUS_ABORTED;
473 *synd = MLX5_DRIVER_SYND;
474 return -EIO;
475 default:
476 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
477 return -EINVAL;
478 }
479 }
480
mlx5_command_str(int command)481 const char *mlx5_command_str(int command)
482 {
483 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
484
485 switch (command) {
486 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
487 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
488 MLX5_COMMAND_STR_CASE(INIT_HCA);
489 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
490 MLX5_COMMAND_STR_CASE(ENABLE_HCA);
491 MLX5_COMMAND_STR_CASE(DISABLE_HCA);
492 MLX5_COMMAND_STR_CASE(QUERY_PAGES);
493 MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
494 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
495 MLX5_COMMAND_STR_CASE(QUERY_ISSI);
496 MLX5_COMMAND_STR_CASE(SET_ISSI);
497 MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
498 MLX5_COMMAND_STR_CASE(CREATE_MKEY);
499 MLX5_COMMAND_STR_CASE(QUERY_MKEY);
500 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
501 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
502 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
503 MLX5_COMMAND_STR_CASE(CREATE_EQ);
504 MLX5_COMMAND_STR_CASE(DESTROY_EQ);
505 MLX5_COMMAND_STR_CASE(QUERY_EQ);
506 MLX5_COMMAND_STR_CASE(GEN_EQE);
507 MLX5_COMMAND_STR_CASE(CREATE_CQ);
508 MLX5_COMMAND_STR_CASE(DESTROY_CQ);
509 MLX5_COMMAND_STR_CASE(QUERY_CQ);
510 MLX5_COMMAND_STR_CASE(MODIFY_CQ);
511 MLX5_COMMAND_STR_CASE(CREATE_QP);
512 MLX5_COMMAND_STR_CASE(DESTROY_QP);
513 MLX5_COMMAND_STR_CASE(RST2INIT_QP);
514 MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
515 MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
516 MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
517 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
518 MLX5_COMMAND_STR_CASE(2ERR_QP);
519 MLX5_COMMAND_STR_CASE(2RST_QP);
520 MLX5_COMMAND_STR_CASE(QUERY_QP);
521 MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
522 MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
523 MLX5_COMMAND_STR_CASE(CREATE_PSV);
524 MLX5_COMMAND_STR_CASE(DESTROY_PSV);
525 MLX5_COMMAND_STR_CASE(CREATE_SRQ);
526 MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
527 MLX5_COMMAND_STR_CASE(QUERY_SRQ);
528 MLX5_COMMAND_STR_CASE(ARM_RQ);
529 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
530 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
531 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
532 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
533 MLX5_COMMAND_STR_CASE(CREATE_DCT);
534 MLX5_COMMAND_STR_CASE(DESTROY_DCT);
535 MLX5_COMMAND_STR_CASE(DRAIN_DCT);
536 MLX5_COMMAND_STR_CASE(QUERY_DCT);
537 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
538 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
539 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
540 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
541 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
542 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
543 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
544 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
545 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
546 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
547 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
548 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
549 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
550 MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
551 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
552 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
553 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
554 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
555 MLX5_COMMAND_STR_CASE(SET_MONITOR_COUNTER);
556 MLX5_COMMAND_STR_CASE(ARM_MONITOR_COUNTER);
557 MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
558 MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
559 MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
560 MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
561 MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
562 MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
563 MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
564 MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
565 MLX5_COMMAND_STR_CASE(ALLOC_PD);
566 MLX5_COMMAND_STR_CASE(DEALLOC_PD);
567 MLX5_COMMAND_STR_CASE(ALLOC_UAR);
568 MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
569 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
570 MLX5_COMMAND_STR_CASE(ACCESS_REG);
571 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
572 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
573 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
574 MLX5_COMMAND_STR_CASE(MAD_IFC);
575 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
576 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
577 MLX5_COMMAND_STR_CASE(NOP);
578 MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
579 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
580 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
581 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
582 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
583 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
584 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
585 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
586 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
587 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
588 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
589 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
590 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
591 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
592 MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
593 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
594 MLX5_COMMAND_STR_CASE(CREATE_LAG);
595 MLX5_COMMAND_STR_CASE(MODIFY_LAG);
596 MLX5_COMMAND_STR_CASE(QUERY_LAG);
597 MLX5_COMMAND_STR_CASE(DESTROY_LAG);
598 MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
599 MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
600 MLX5_COMMAND_STR_CASE(CREATE_TIR);
601 MLX5_COMMAND_STR_CASE(MODIFY_TIR);
602 MLX5_COMMAND_STR_CASE(DESTROY_TIR);
603 MLX5_COMMAND_STR_CASE(QUERY_TIR);
604 MLX5_COMMAND_STR_CASE(CREATE_SQ);
605 MLX5_COMMAND_STR_CASE(MODIFY_SQ);
606 MLX5_COMMAND_STR_CASE(DESTROY_SQ);
607 MLX5_COMMAND_STR_CASE(QUERY_SQ);
608 MLX5_COMMAND_STR_CASE(CREATE_RQ);
609 MLX5_COMMAND_STR_CASE(MODIFY_RQ);
610 MLX5_COMMAND_STR_CASE(DESTROY_RQ);
611 MLX5_COMMAND_STR_CASE(QUERY_RQ);
612 MLX5_COMMAND_STR_CASE(CREATE_RMP);
613 MLX5_COMMAND_STR_CASE(MODIFY_RMP);
614 MLX5_COMMAND_STR_CASE(DESTROY_RMP);
615 MLX5_COMMAND_STR_CASE(QUERY_RMP);
616 MLX5_COMMAND_STR_CASE(CREATE_TIS);
617 MLX5_COMMAND_STR_CASE(MODIFY_TIS);
618 MLX5_COMMAND_STR_CASE(DESTROY_TIS);
619 MLX5_COMMAND_STR_CASE(QUERY_TIS);
620 MLX5_COMMAND_STR_CASE(CREATE_RQT);
621 MLX5_COMMAND_STR_CASE(MODIFY_RQT);
622 MLX5_COMMAND_STR_CASE(DESTROY_RQT);
623 MLX5_COMMAND_STR_CASE(QUERY_RQT);
624 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
625 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
626 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
627 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
628 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
629 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
630 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
631 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
632 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
633 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
634 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
635 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
636 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
637 MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
638 MLX5_COMMAND_STR_CASE(ALLOC_PACKET_REFORMAT_CONTEXT);
639 MLX5_COMMAND_STR_CASE(DEALLOC_PACKET_REFORMAT_CONTEXT);
640 MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
641 MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
642 MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
643 MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
644 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
645 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
646 MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
647 MLX5_COMMAND_STR_CASE(CREATE_XRQ);
648 MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
649 MLX5_COMMAND_STR_CASE(QUERY_XRQ);
650 MLX5_COMMAND_STR_CASE(ARM_XRQ);
651 MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
652 MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
653 MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
654 MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT);
655 MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
656 MLX5_COMMAND_STR_CASE(ALLOC_MEMIC);
657 MLX5_COMMAND_STR_CASE(DEALLOC_MEMIC);
658 MLX5_COMMAND_STR_CASE(QUERY_ESW_FUNCTIONS);
659 MLX5_COMMAND_STR_CASE(CREATE_UCTX);
660 MLX5_COMMAND_STR_CASE(DESTROY_UCTX);
661 MLX5_COMMAND_STR_CASE(CREATE_UMEM);
662 MLX5_COMMAND_STR_CASE(DESTROY_UMEM);
663 MLX5_COMMAND_STR_CASE(RELEASE_XRQ_ERROR);
664 MLX5_COMMAND_STR_CASE(MODIFY_XRQ);
665 default: return "unknown command opcode";
666 }
667 }
668
cmd_status_str(u8 status)669 static const char *cmd_status_str(u8 status)
670 {
671 switch (status) {
672 case MLX5_CMD_STAT_OK:
673 return "OK";
674 case MLX5_CMD_STAT_INT_ERR:
675 return "internal error";
676 case MLX5_CMD_STAT_BAD_OP_ERR:
677 return "bad operation";
678 case MLX5_CMD_STAT_BAD_PARAM_ERR:
679 return "bad parameter";
680 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
681 return "bad system state";
682 case MLX5_CMD_STAT_BAD_RES_ERR:
683 return "bad resource";
684 case MLX5_CMD_STAT_RES_BUSY:
685 return "resource busy";
686 case MLX5_CMD_STAT_LIM_ERR:
687 return "limits exceeded";
688 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
689 return "bad resource state";
690 case MLX5_CMD_STAT_IX_ERR:
691 return "bad index";
692 case MLX5_CMD_STAT_NO_RES_ERR:
693 return "no resources";
694 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
695 return "bad input length";
696 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
697 return "bad output length";
698 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
699 return "bad QP state";
700 case MLX5_CMD_STAT_BAD_PKT_ERR:
701 return "bad packet (discarded)";
702 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
703 return "bad size too many outstanding CQEs";
704 default:
705 return "unknown status";
706 }
707 }
708
cmd_status_to_err(u8 status)709 static int cmd_status_to_err(u8 status)
710 {
711 switch (status) {
712 case MLX5_CMD_STAT_OK: return 0;
713 case MLX5_CMD_STAT_INT_ERR: return -EIO;
714 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
715 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
716 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
717 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
718 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
719 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
720 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
721 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
722 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
723 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
724 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
725 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
726 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
727 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
728 default: return -EIO;
729 }
730 }
731
732 struct mlx5_ifc_mbox_out_bits {
733 u8 status[0x8];
734 u8 reserved_at_8[0x18];
735
736 u8 syndrome[0x20];
737
738 u8 reserved_at_40[0x40];
739 };
740
741 struct mlx5_ifc_mbox_in_bits {
742 u8 opcode[0x10];
743 u8 uid[0x10];
744
745 u8 reserved_at_20[0x10];
746 u8 op_mod[0x10];
747
748 u8 reserved_at_40[0x40];
749 };
750
mlx5_cmd_mbox_status(void * out,u8 * status,u32 * syndrome)751 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
752 {
753 *status = MLX5_GET(mbox_out, out, status);
754 *syndrome = MLX5_GET(mbox_out, out, syndrome);
755 }
756
mlx5_cmd_check(struct mlx5_core_dev * dev,void * in,void * out)757 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
758 {
759 u32 syndrome;
760 u8 status;
761 u16 opcode;
762 u16 op_mod;
763 u16 uid;
764
765 mlx5_cmd_mbox_status(out, &status, &syndrome);
766 if (!status)
767 return 0;
768
769 opcode = MLX5_GET(mbox_in, in, opcode);
770 op_mod = MLX5_GET(mbox_in, in, op_mod);
771 uid = MLX5_GET(mbox_in, in, uid);
772
773 if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
774 mlx5_core_err_rl(dev,
775 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
776 mlx5_command_str(opcode), opcode, op_mod,
777 cmd_status_str(status), status, syndrome);
778 else
779 mlx5_core_dbg(dev,
780 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
781 mlx5_command_str(opcode),
782 opcode, op_mod,
783 cmd_status_str(status),
784 status,
785 syndrome);
786
787 return cmd_status_to_err(status);
788 }
789
dump_command(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent,int input)790 static void dump_command(struct mlx5_core_dev *dev,
791 struct mlx5_cmd_work_ent *ent, int input)
792 {
793 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
794 u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
795 struct mlx5_cmd_mailbox *next = msg->next;
796 int n = mlx5_calc_cmd_blocks(msg);
797 int data_only;
798 u32 offset = 0;
799 int dump_len;
800 int i;
801
802 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
803
804 if (data_only)
805 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
806 "dump command data %s(0x%x) %s\n",
807 mlx5_command_str(op), op,
808 input ? "INPUT" : "OUTPUT");
809 else
810 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
811 mlx5_command_str(op), op,
812 input ? "INPUT" : "OUTPUT");
813
814 if (data_only) {
815 if (input) {
816 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
817 offset += sizeof(ent->lay->in);
818 } else {
819 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
820 offset += sizeof(ent->lay->out);
821 }
822 } else {
823 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
824 offset += sizeof(*ent->lay);
825 }
826
827 for (i = 0; i < n && next; i++) {
828 if (data_only) {
829 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
830 dump_buf(next->buf, dump_len, 1, offset);
831 offset += MLX5_CMD_DATA_BLOCK_SIZE;
832 } else {
833 mlx5_core_dbg(dev, "command block:\n");
834 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
835 offset += sizeof(struct mlx5_cmd_prot_block);
836 }
837 next = next->next;
838 }
839
840 if (data_only)
841 pr_debug("\n");
842 }
843
msg_to_opcode(struct mlx5_cmd_msg * in)844 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
845 {
846 return MLX5_GET(mbox_in, in->first.data, opcode);
847 }
848
849 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
850
cb_timeout_handler(struct work_struct * work)851 static void cb_timeout_handler(struct work_struct *work)
852 {
853 struct delayed_work *dwork = container_of(work, struct delayed_work,
854 work);
855 struct mlx5_cmd_work_ent *ent = container_of(dwork,
856 struct mlx5_cmd_work_ent,
857 cb_timeout_work);
858 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
859 cmd);
860
861 mlx5_cmd_eq_recover(dev);
862
863 /* Maybe got handled by eq recover ? */
864 if (!test_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state)) {
865 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) Async, recovered after timeout\n", ent->idx,
866 mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in));
867 goto out; /* phew, already handled */
868 }
869
870 ent->ret = -ETIMEDOUT;
871 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) Async, timeout. Will cause a leak of a command resource\n",
872 ent->idx, mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in));
873 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
874
875 out:
876 cmd_ent_put(ent); /* for the cmd_ent_get() took on schedule delayed work */
877 }
878
879 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
880 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
881 struct mlx5_cmd_msg *msg);
882
opcode_allowed(struct mlx5_cmd * cmd,u16 opcode)883 static bool opcode_allowed(struct mlx5_cmd *cmd, u16 opcode)
884 {
885 if (cmd->allowed_opcode == CMD_ALLOWED_OPCODE_ALL)
886 return true;
887
888 return cmd->allowed_opcode == opcode;
889 }
890
mlx5_cmd_is_down(struct mlx5_core_dev * dev)891 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev)
892 {
893 return pci_channel_offline(dev->pdev) ||
894 dev->cmd.state != MLX5_CMDIF_STATE_UP ||
895 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR;
896 }
897
cmd_work_handler(struct work_struct * work)898 static void cmd_work_handler(struct work_struct *work)
899 {
900 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
901 struct mlx5_cmd *cmd = ent->cmd;
902 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
903 unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
904 struct mlx5_cmd_layout *lay;
905 struct semaphore *sem;
906 unsigned long flags;
907 bool poll_cmd = ent->polling;
908 int alloc_ret;
909 int cmd_mode;
910
911 complete(&ent->handling);
912 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
913 down(sem);
914 if (!ent->page_queue) {
915 alloc_ret = cmd_alloc_index(cmd);
916 if (alloc_ret < 0) {
917 mlx5_core_err_rl(dev, "failed to allocate command entry\n");
918 if (ent->callback) {
919 ent->callback(-EAGAIN, ent->context);
920 mlx5_free_cmd_msg(dev, ent->out);
921 free_msg(dev, ent->in);
922 cmd_ent_put(ent);
923 } else {
924 ent->ret = -EAGAIN;
925 complete(&ent->done);
926 }
927 up(sem);
928 return;
929 }
930 ent->idx = alloc_ret;
931 } else {
932 ent->idx = cmd->max_reg_cmds;
933 spin_lock_irqsave(&cmd->alloc_lock, flags);
934 clear_bit(ent->idx, &cmd->bitmask);
935 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
936 }
937
938 cmd->ent_arr[ent->idx] = ent;
939 lay = get_inst(cmd, ent->idx);
940 ent->lay = lay;
941 memset(lay, 0, sizeof(*lay));
942 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
943 ent->op = be32_to_cpu(lay->in[0]) >> 16;
944 if (ent->in->next)
945 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
946 lay->inlen = cpu_to_be32(ent->in->len);
947 if (ent->out->next)
948 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
949 lay->outlen = cpu_to_be32(ent->out->len);
950 lay->type = MLX5_PCI_CMD_XPORT;
951 lay->token = ent->token;
952 lay->status_own = CMD_OWNER_HW;
953 set_signature(ent, !cmd->checksum_disabled);
954 dump_command(dev, ent, 1);
955 ent->ts1 = ktime_get_ns();
956 cmd_mode = cmd->mode;
957
958 if (ent->callback && schedule_delayed_work(&ent->cb_timeout_work, cb_timeout))
959 cmd_ent_get(ent);
960 set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
961
962 cmd_ent_get(ent); /* for the _real_ FW event on completion */
963 /* Skip sending command to fw if internal error */
964 if (mlx5_cmd_is_down(dev) || !opcode_allowed(&dev->cmd, ent->op)) {
965 u8 status = 0;
966 u32 drv_synd;
967
968 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
969 MLX5_SET(mbox_out, ent->out, status, status);
970 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
971
972 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
973 return;
974 }
975
976 /* ring doorbell after the descriptor is valid */
977 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
978 wmb();
979 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
980 /* if not in polling don't use ent after this point */
981 if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
982 poll_timeout(ent);
983 /* make sure we read the descriptor after ownership is SW */
984 rmb();
985 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, (ent->ret == -ETIMEDOUT));
986 }
987 }
988
deliv_status_to_str(u8 status)989 static const char *deliv_status_to_str(u8 status)
990 {
991 switch (status) {
992 case MLX5_CMD_DELIVERY_STAT_OK:
993 return "no errors";
994 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
995 return "signature error";
996 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
997 return "token error";
998 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
999 return "bad block number";
1000 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
1001 return "output pointer not aligned to block size";
1002 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
1003 return "input pointer not aligned to block size";
1004 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
1005 return "firmware internal error";
1006 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
1007 return "command input length error";
1008 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
1009 return "command output length error";
1010 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
1011 return "reserved fields not cleared";
1012 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
1013 return "bad command descriptor type";
1014 default:
1015 return "unknown status code";
1016 }
1017 }
1018
1019 enum {
1020 MLX5_CMD_TIMEOUT_RECOVER_MSEC = 5 * 1000,
1021 };
1022
wait_func_handle_exec_timeout(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent)1023 static void wait_func_handle_exec_timeout(struct mlx5_core_dev *dev,
1024 struct mlx5_cmd_work_ent *ent)
1025 {
1026 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_RECOVER_MSEC);
1027
1028 mlx5_cmd_eq_recover(dev);
1029
1030 /* Re-wait on the ent->done after executing the recovery flow. If the
1031 * recovery flow (or any other recovery flow running simultaneously)
1032 * has recovered an EQE, it should cause the entry to be completed by
1033 * the command interface.
1034 */
1035 if (wait_for_completion_timeout(&ent->done, timeout)) {
1036 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) recovered after timeout\n", ent->idx,
1037 mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in));
1038 return;
1039 }
1040
1041 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) No done completion\n", ent->idx,
1042 mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in));
1043
1044 ent->ret = -ETIMEDOUT;
1045 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
1046 }
1047
wait_func(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent)1048 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
1049 {
1050 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
1051 struct mlx5_cmd *cmd = &dev->cmd;
1052 int err;
1053
1054 if (!wait_for_completion_timeout(&ent->handling, timeout) &&
1055 cancel_work_sync(&ent->work)) {
1056 ent->ret = -ECANCELED;
1057 goto out_err;
1058 }
1059 if (cmd->mode == CMD_MODE_POLLING || ent->polling)
1060 wait_for_completion(&ent->done);
1061 else if (!wait_for_completion_timeout(&ent->done, timeout))
1062 wait_func_handle_exec_timeout(dev, ent);
1063
1064 out_err:
1065 err = ent->ret;
1066
1067 if (err == -ETIMEDOUT) {
1068 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
1069 mlx5_command_str(msg_to_opcode(ent->in)),
1070 msg_to_opcode(ent->in));
1071 } else if (err == -ECANCELED) {
1072 mlx5_core_warn(dev, "%s(0x%x) canceled on out of queue timeout.\n",
1073 mlx5_command_str(msg_to_opcode(ent->in)),
1074 msg_to_opcode(ent->in));
1075 }
1076 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
1077 err, deliv_status_to_str(ent->status), ent->status);
1078
1079 return err;
1080 }
1081
1082 /* Notes:
1083 * 1. Callback functions may not sleep
1084 * 2. page queue commands do not support asynchrous completion
1085 */
mlx5_cmd_invoke(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * in,struct mlx5_cmd_msg * out,void * uout,int uout_size,mlx5_cmd_cbk_t callback,void * context,int page_queue,u8 * status,u8 token,bool force_polling)1086 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
1087 struct mlx5_cmd_msg *out, void *uout, int uout_size,
1088 mlx5_cmd_cbk_t callback,
1089 void *context, int page_queue, u8 *status,
1090 u8 token, bool force_polling)
1091 {
1092 struct mlx5_cmd *cmd = &dev->cmd;
1093 struct mlx5_cmd_work_ent *ent;
1094 struct mlx5_cmd_stats *stats;
1095 int err = 0;
1096 s64 ds;
1097 u16 op;
1098
1099 if (callback && page_queue)
1100 return -EINVAL;
1101
1102 ent = cmd_alloc_ent(cmd, in, out, uout, uout_size,
1103 callback, context, page_queue);
1104 if (IS_ERR(ent))
1105 return PTR_ERR(ent);
1106
1107 /* put for this ent is when consumed, depending on the use case
1108 * 1) (!callback) blocking flow: by caller after wait_func completes
1109 * 2) (callback) flow: by mlx5_cmd_comp_handler() when ent is handled
1110 */
1111
1112 ent->token = token;
1113 ent->polling = force_polling;
1114
1115 init_completion(&ent->handling);
1116 if (!callback)
1117 init_completion(&ent->done);
1118
1119 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
1120 INIT_WORK(&ent->work, cmd_work_handler);
1121 if (page_queue) {
1122 cmd_work_handler(&ent->work);
1123 } else if (!queue_work(cmd->wq, &ent->work)) {
1124 mlx5_core_warn(dev, "failed to queue work\n");
1125 err = -ENOMEM;
1126 goto out_free;
1127 }
1128
1129 if (callback)
1130 goto out; /* mlx5_cmd_comp_handler() will put(ent) */
1131
1132 err = wait_func(dev, ent);
1133 if (err == -ETIMEDOUT || err == -ECANCELED)
1134 goto out_free;
1135
1136 ds = ent->ts2 - ent->ts1;
1137 op = MLX5_GET(mbox_in, in->first.data, opcode);
1138 if (op < MLX5_CMD_OP_MAX) {
1139 stats = &cmd->stats[op];
1140 spin_lock_irq(&stats->lock);
1141 stats->sum += ds;
1142 ++stats->n;
1143 spin_unlock_irq(&stats->lock);
1144 }
1145 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1146 "fw exec time for %s is %lld nsec\n",
1147 mlx5_command_str(op), ds);
1148 *status = ent->status;
1149
1150 out_free:
1151 cmd_ent_put(ent);
1152 out:
1153 return err;
1154 }
1155
dbg_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1156 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1157 size_t count, loff_t *pos)
1158 {
1159 struct mlx5_core_dev *dev = filp->private_data;
1160 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1161 char lbuf[3];
1162 int err;
1163
1164 if (!dbg->in_msg || !dbg->out_msg)
1165 return -ENOMEM;
1166
1167 if (count < sizeof(lbuf) - 1)
1168 return -EINVAL;
1169
1170 if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1171 return -EFAULT;
1172
1173 lbuf[sizeof(lbuf) - 1] = 0;
1174
1175 if (strcmp(lbuf, "go"))
1176 return -EINVAL;
1177
1178 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1179
1180 return err ? err : count;
1181 }
1182
1183 static const struct file_operations fops = {
1184 .owner = THIS_MODULE,
1185 .open = simple_open,
1186 .write = dbg_write,
1187 };
1188
mlx5_copy_to_msg(struct mlx5_cmd_msg * to,void * from,int size,u8 token)1189 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1190 u8 token)
1191 {
1192 struct mlx5_cmd_prot_block *block;
1193 struct mlx5_cmd_mailbox *next;
1194 int copy;
1195
1196 if (!to || !from)
1197 return -ENOMEM;
1198
1199 copy = min_t(int, size, sizeof(to->first.data));
1200 memcpy(to->first.data, from, copy);
1201 size -= copy;
1202 from += copy;
1203
1204 next = to->next;
1205 while (size) {
1206 if (!next) {
1207 /* this is a BUG */
1208 return -ENOMEM;
1209 }
1210
1211 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1212 block = next->buf;
1213 memcpy(block->data, from, copy);
1214 from += copy;
1215 size -= copy;
1216 block->token = token;
1217 next = next->next;
1218 }
1219
1220 return 0;
1221 }
1222
mlx5_copy_from_msg(void * to,struct mlx5_cmd_msg * from,int size)1223 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1224 {
1225 struct mlx5_cmd_prot_block *block;
1226 struct mlx5_cmd_mailbox *next;
1227 int copy;
1228
1229 if (!to || !from)
1230 return -ENOMEM;
1231
1232 copy = min_t(int, size, sizeof(from->first.data));
1233 memcpy(to, from->first.data, copy);
1234 size -= copy;
1235 to += copy;
1236
1237 next = from->next;
1238 while (size) {
1239 if (!next) {
1240 /* this is a BUG */
1241 return -ENOMEM;
1242 }
1243
1244 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1245 block = next->buf;
1246
1247 memcpy(to, block->data, copy);
1248 to += copy;
1249 size -= copy;
1250 next = next->next;
1251 }
1252
1253 return 0;
1254 }
1255
alloc_cmd_box(struct mlx5_core_dev * dev,gfp_t flags)1256 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1257 gfp_t flags)
1258 {
1259 struct mlx5_cmd_mailbox *mailbox;
1260
1261 mailbox = kmalloc(sizeof(*mailbox), flags);
1262 if (!mailbox)
1263 return ERR_PTR(-ENOMEM);
1264
1265 mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1266 &mailbox->dma);
1267 if (!mailbox->buf) {
1268 mlx5_core_dbg(dev, "failed allocation\n");
1269 kfree(mailbox);
1270 return ERR_PTR(-ENOMEM);
1271 }
1272 mailbox->next = NULL;
1273
1274 return mailbox;
1275 }
1276
free_cmd_box(struct mlx5_core_dev * dev,struct mlx5_cmd_mailbox * mailbox)1277 static void free_cmd_box(struct mlx5_core_dev *dev,
1278 struct mlx5_cmd_mailbox *mailbox)
1279 {
1280 dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1281 kfree(mailbox);
1282 }
1283
mlx5_alloc_cmd_msg(struct mlx5_core_dev * dev,gfp_t flags,int size,u8 token)1284 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1285 gfp_t flags, int size,
1286 u8 token)
1287 {
1288 struct mlx5_cmd_mailbox *tmp, *head = NULL;
1289 struct mlx5_cmd_prot_block *block;
1290 struct mlx5_cmd_msg *msg;
1291 int err;
1292 int n;
1293 int i;
1294
1295 msg = kzalloc(sizeof(*msg), flags);
1296 if (!msg)
1297 return ERR_PTR(-ENOMEM);
1298
1299 msg->len = size;
1300 n = mlx5_calc_cmd_blocks(msg);
1301
1302 for (i = 0; i < n; i++) {
1303 tmp = alloc_cmd_box(dev, flags);
1304 if (IS_ERR(tmp)) {
1305 mlx5_core_warn(dev, "failed allocating block\n");
1306 err = PTR_ERR(tmp);
1307 goto err_alloc;
1308 }
1309
1310 block = tmp->buf;
1311 tmp->next = head;
1312 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1313 block->block_num = cpu_to_be32(n - i - 1);
1314 block->token = token;
1315 head = tmp;
1316 }
1317 msg->next = head;
1318 return msg;
1319
1320 err_alloc:
1321 while (head) {
1322 tmp = head->next;
1323 free_cmd_box(dev, head);
1324 head = tmp;
1325 }
1326 kfree(msg);
1327
1328 return ERR_PTR(err);
1329 }
1330
mlx5_free_cmd_msg(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * msg)1331 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1332 struct mlx5_cmd_msg *msg)
1333 {
1334 struct mlx5_cmd_mailbox *head = msg->next;
1335 struct mlx5_cmd_mailbox *next;
1336
1337 while (head) {
1338 next = head->next;
1339 free_cmd_box(dev, head);
1340 head = next;
1341 }
1342 kfree(msg);
1343 }
1344
data_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1345 static ssize_t data_write(struct file *filp, const char __user *buf,
1346 size_t count, loff_t *pos)
1347 {
1348 struct mlx5_core_dev *dev = filp->private_data;
1349 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1350 void *ptr;
1351
1352 if (*pos != 0)
1353 return -EINVAL;
1354
1355 kfree(dbg->in_msg);
1356 dbg->in_msg = NULL;
1357 dbg->inlen = 0;
1358 ptr = memdup_user(buf, count);
1359 if (IS_ERR(ptr))
1360 return PTR_ERR(ptr);
1361 dbg->in_msg = ptr;
1362 dbg->inlen = count;
1363
1364 *pos = count;
1365
1366 return count;
1367 }
1368
data_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)1369 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1370 loff_t *pos)
1371 {
1372 struct mlx5_core_dev *dev = filp->private_data;
1373 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1374
1375 if (!dbg->out_msg)
1376 return -ENOMEM;
1377
1378 return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1379 dbg->outlen);
1380 }
1381
1382 static const struct file_operations dfops = {
1383 .owner = THIS_MODULE,
1384 .open = simple_open,
1385 .write = data_write,
1386 .read = data_read,
1387 };
1388
outlen_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)1389 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1390 loff_t *pos)
1391 {
1392 struct mlx5_core_dev *dev = filp->private_data;
1393 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1394 char outlen[8];
1395 int err;
1396
1397 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1398 if (err < 0)
1399 return err;
1400
1401 return simple_read_from_buffer(buf, count, pos, outlen, err);
1402 }
1403
outlen_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1404 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1405 size_t count, loff_t *pos)
1406 {
1407 struct mlx5_core_dev *dev = filp->private_data;
1408 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1409 char outlen_str[8] = {0};
1410 int outlen;
1411 void *ptr;
1412 int err;
1413
1414 if (*pos != 0 || count > 6)
1415 return -EINVAL;
1416
1417 kfree(dbg->out_msg);
1418 dbg->out_msg = NULL;
1419 dbg->outlen = 0;
1420
1421 if (copy_from_user(outlen_str, buf, count))
1422 return -EFAULT;
1423
1424 err = sscanf(outlen_str, "%d", &outlen);
1425 if (err != 1)
1426 return -EINVAL;
1427
1428 ptr = kzalloc(outlen, GFP_KERNEL);
1429 if (!ptr)
1430 return -ENOMEM;
1431
1432 dbg->out_msg = ptr;
1433 dbg->outlen = outlen;
1434
1435 *pos = count;
1436
1437 return count;
1438 }
1439
1440 static const struct file_operations olfops = {
1441 .owner = THIS_MODULE,
1442 .open = simple_open,
1443 .write = outlen_write,
1444 .read = outlen_read,
1445 };
1446
set_wqname(struct mlx5_core_dev * dev)1447 static void set_wqname(struct mlx5_core_dev *dev)
1448 {
1449 struct mlx5_cmd *cmd = &dev->cmd;
1450
1451 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1452 dev_name(dev->device));
1453 }
1454
clean_debug_files(struct mlx5_core_dev * dev)1455 static void clean_debug_files(struct mlx5_core_dev *dev)
1456 {
1457 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1458
1459 if (!mlx5_debugfs_root)
1460 return;
1461
1462 mlx5_cmdif_debugfs_cleanup(dev);
1463 debugfs_remove_recursive(dbg->dbg_root);
1464 }
1465
create_debugfs_files(struct mlx5_core_dev * dev)1466 static void create_debugfs_files(struct mlx5_core_dev *dev)
1467 {
1468 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1469
1470 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1471
1472 debugfs_create_file("in", 0400, dbg->dbg_root, dev, &dfops);
1473 debugfs_create_file("out", 0200, dbg->dbg_root, dev, &dfops);
1474 debugfs_create_file("out_len", 0600, dbg->dbg_root, dev, &olfops);
1475 debugfs_create_u8("status", 0600, dbg->dbg_root, &dbg->status);
1476 debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1477
1478 mlx5_cmdif_debugfs_init(dev);
1479 }
1480
mlx5_cmd_allowed_opcode(struct mlx5_core_dev * dev,u16 opcode)1481 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode)
1482 {
1483 struct mlx5_cmd *cmd = &dev->cmd;
1484 int i;
1485
1486 for (i = 0; i < cmd->max_reg_cmds; i++)
1487 down(&cmd->sem);
1488 down(&cmd->pages_sem);
1489
1490 cmd->allowed_opcode = opcode;
1491
1492 up(&cmd->pages_sem);
1493 for (i = 0; i < cmd->max_reg_cmds; i++)
1494 up(&cmd->sem);
1495 }
1496
mlx5_cmd_change_mod(struct mlx5_core_dev * dev,int mode)1497 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1498 {
1499 struct mlx5_cmd *cmd = &dev->cmd;
1500 int i;
1501
1502 for (i = 0; i < cmd->max_reg_cmds; i++)
1503 down(&cmd->sem);
1504 down(&cmd->pages_sem);
1505
1506 cmd->mode = mode;
1507
1508 up(&cmd->pages_sem);
1509 for (i = 0; i < cmd->max_reg_cmds; i++)
1510 up(&cmd->sem);
1511 }
1512
cmd_comp_notifier(struct notifier_block * nb,unsigned long type,void * data)1513 static int cmd_comp_notifier(struct notifier_block *nb,
1514 unsigned long type, void *data)
1515 {
1516 struct mlx5_core_dev *dev;
1517 struct mlx5_cmd *cmd;
1518 struct mlx5_eqe *eqe;
1519
1520 cmd = mlx5_nb_cof(nb, struct mlx5_cmd, nb);
1521 dev = container_of(cmd, struct mlx5_core_dev, cmd);
1522 eqe = data;
1523
1524 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
1525
1526 return NOTIFY_OK;
1527 }
mlx5_cmd_use_events(struct mlx5_core_dev * dev)1528 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1529 {
1530 MLX5_NB_INIT(&dev->cmd.nb, cmd_comp_notifier, CMD);
1531 mlx5_eq_notifier_register(dev, &dev->cmd.nb);
1532 mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1533 }
1534
mlx5_cmd_use_polling(struct mlx5_core_dev * dev)1535 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1536 {
1537 mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1538 mlx5_eq_notifier_unregister(dev, &dev->cmd.nb);
1539 }
1540
free_msg(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * msg)1541 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1542 {
1543 unsigned long flags;
1544
1545 if (msg->parent) {
1546 spin_lock_irqsave(&msg->parent->lock, flags);
1547 list_add_tail(&msg->list, &msg->parent->head);
1548 spin_unlock_irqrestore(&msg->parent->lock, flags);
1549 } else {
1550 mlx5_free_cmd_msg(dev, msg);
1551 }
1552 }
1553
mlx5_cmd_comp_handler(struct mlx5_core_dev * dev,u64 vec,bool forced)1554 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1555 {
1556 struct mlx5_cmd *cmd = &dev->cmd;
1557 struct mlx5_cmd_work_ent *ent;
1558 mlx5_cmd_cbk_t callback;
1559 void *context;
1560 int err;
1561 int i;
1562 s64 ds;
1563 struct mlx5_cmd_stats *stats;
1564 unsigned long flags;
1565 unsigned long vector;
1566
1567 /* there can be at most 32 command queues */
1568 vector = vec & 0xffffffff;
1569 for (i = 0; i < (1 << cmd->log_sz); i++) {
1570 if (test_bit(i, &vector)) {
1571 ent = cmd->ent_arr[i];
1572
1573 /* if we already completed the command, ignore it */
1574 if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1575 &ent->state)) {
1576 /* only real completion can free the cmd slot */
1577 if (!forced) {
1578 mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1579 ent->idx);
1580 cmd_ent_put(ent);
1581 }
1582 continue;
1583 }
1584
1585 if (ent->callback && cancel_delayed_work(&ent->cb_timeout_work))
1586 cmd_ent_put(ent); /* timeout work was canceled */
1587
1588 if (!forced || /* Real FW completion */
1589 mlx5_cmd_is_down(dev) || /* No real FW completion is expected */
1590 !opcode_allowed(cmd, ent->op))
1591 cmd_ent_put(ent);
1592
1593 ent->ts2 = ktime_get_ns();
1594 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1595 dump_command(dev, ent, 0);
1596 if (!ent->ret) {
1597 if (!cmd->checksum_disabled)
1598 ent->ret = verify_signature(ent);
1599 else
1600 ent->ret = 0;
1601 if (vec & MLX5_TRIGGERED_CMD_COMP)
1602 ent->status = MLX5_DRIVER_STATUS_ABORTED;
1603 else
1604 ent->status = ent->lay->status_own >> 1;
1605
1606 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1607 ent->ret, deliv_status_to_str(ent->status), ent->status);
1608 }
1609
1610 if (ent->callback) {
1611 ds = ent->ts2 - ent->ts1;
1612 if (ent->op < MLX5_CMD_OP_MAX) {
1613 stats = &cmd->stats[ent->op];
1614 spin_lock_irqsave(&stats->lock, flags);
1615 stats->sum += ds;
1616 ++stats->n;
1617 spin_unlock_irqrestore(&stats->lock, flags);
1618 }
1619
1620 callback = ent->callback;
1621 context = ent->context;
1622 err = ent->ret;
1623 if (!err) {
1624 err = mlx5_copy_from_msg(ent->uout,
1625 ent->out,
1626 ent->uout_size);
1627
1628 err = err ? err : mlx5_cmd_check(dev,
1629 ent->in->first.data,
1630 ent->uout);
1631 }
1632
1633 mlx5_free_cmd_msg(dev, ent->out);
1634 free_msg(dev, ent->in);
1635
1636 err = err ? err : ent->status;
1637 /* final consumer is done, release ent */
1638 cmd_ent_put(ent);
1639 callback(err, context);
1640 } else {
1641 /* release wait_func() so mlx5_cmd_invoke()
1642 * can make the final ent_put()
1643 */
1644 complete(&ent->done);
1645 }
1646 }
1647 }
1648 }
1649
mlx5_cmd_trigger_completions(struct mlx5_core_dev * dev)1650 void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev)
1651 {
1652 struct mlx5_cmd *cmd = &dev->cmd;
1653 unsigned long bitmask;
1654 unsigned long flags;
1655 u64 vector;
1656 int i;
1657
1658 /* wait for pending handlers to complete */
1659 mlx5_eq_synchronize_cmd_irq(dev);
1660 spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
1661 vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
1662 if (!vector)
1663 goto no_trig;
1664
1665 bitmask = vector;
1666 /* we must increment the allocated entries refcount before triggering the completions
1667 * to guarantee pending commands will not get freed in the meanwhile.
1668 * For that reason, it also has to be done inside the alloc_lock.
1669 */
1670 for_each_set_bit(i, &bitmask, (1 << cmd->log_sz))
1671 cmd_ent_get(cmd->ent_arr[i]);
1672 vector |= MLX5_TRIGGERED_CMD_COMP;
1673 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1674
1675 mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
1676 mlx5_cmd_comp_handler(dev, vector, true);
1677 for_each_set_bit(i, &bitmask, (1 << cmd->log_sz))
1678 cmd_ent_put(cmd->ent_arr[i]);
1679 return;
1680
1681 no_trig:
1682 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1683 }
1684
mlx5_cmd_flush(struct mlx5_core_dev * dev)1685 void mlx5_cmd_flush(struct mlx5_core_dev *dev)
1686 {
1687 struct mlx5_cmd *cmd = &dev->cmd;
1688 int i;
1689
1690 for (i = 0; i < cmd->max_reg_cmds; i++) {
1691 while (down_trylock(&cmd->sem)) {
1692 mlx5_cmd_trigger_completions(dev);
1693 cond_resched();
1694 }
1695 }
1696
1697 while (down_trylock(&cmd->pages_sem)) {
1698 mlx5_cmd_trigger_completions(dev);
1699 cond_resched();
1700 }
1701
1702 /* Unlock cmdif */
1703 up(&cmd->pages_sem);
1704 for (i = 0; i < cmd->max_reg_cmds; i++)
1705 up(&cmd->sem);
1706 }
1707
status_to_err(u8 status)1708 static int status_to_err(u8 status)
1709 {
1710 switch (status) {
1711 case MLX5_CMD_DELIVERY_STAT_OK:
1712 case MLX5_DRIVER_STATUS_ABORTED:
1713 return 0;
1714 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
1715 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
1716 return -EBADR;
1717 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
1718 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
1719 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
1720 return -EFAULT; /* Bad address */
1721 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
1722 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
1723 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
1724 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
1725 return -ENOMSG;
1726 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
1727 return -EIO;
1728 default:
1729 return -EINVAL;
1730 }
1731 }
1732
alloc_msg(struct mlx5_core_dev * dev,int in_size,gfp_t gfp)1733 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1734 gfp_t gfp)
1735 {
1736 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1737 struct cmd_msg_cache *ch = NULL;
1738 struct mlx5_cmd *cmd = &dev->cmd;
1739 int i;
1740
1741 if (in_size <= 16)
1742 goto cache_miss;
1743
1744 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1745 ch = &cmd->cache[i];
1746 if (in_size > ch->max_inbox_size)
1747 continue;
1748 spin_lock_irq(&ch->lock);
1749 if (list_empty(&ch->head)) {
1750 spin_unlock_irq(&ch->lock);
1751 continue;
1752 }
1753 msg = list_entry(ch->head.next, typeof(*msg), list);
1754 /* For cached lists, we must explicitly state what is
1755 * the real size
1756 */
1757 msg->len = in_size;
1758 list_del(&msg->list);
1759 spin_unlock_irq(&ch->lock);
1760 break;
1761 }
1762
1763 if (!IS_ERR(msg))
1764 return msg;
1765
1766 cache_miss:
1767 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1768 return msg;
1769 }
1770
is_manage_pages(void * in)1771 static int is_manage_pages(void *in)
1772 {
1773 return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1774 }
1775
cmd_exec(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size,mlx5_cmd_cbk_t callback,void * context,bool force_polling)1776 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1777 int out_size, mlx5_cmd_cbk_t callback, void *context,
1778 bool force_polling)
1779 {
1780 struct mlx5_cmd_msg *inb;
1781 struct mlx5_cmd_msg *outb;
1782 int pages_queue;
1783 gfp_t gfp;
1784 int err;
1785 u8 status = 0;
1786 u32 drv_synd;
1787 u16 opcode;
1788 u8 token;
1789
1790 opcode = MLX5_GET(mbox_in, in, opcode);
1791 if (mlx5_cmd_is_down(dev) || !opcode_allowed(&dev->cmd, opcode)) {
1792 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1793 MLX5_SET(mbox_out, out, status, status);
1794 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1795 return err;
1796 }
1797
1798 pages_queue = is_manage_pages(in);
1799 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1800
1801 inb = alloc_msg(dev, in_size, gfp);
1802 if (IS_ERR(inb)) {
1803 err = PTR_ERR(inb);
1804 return err;
1805 }
1806
1807 token = alloc_token(&dev->cmd);
1808
1809 err = mlx5_copy_to_msg(inb, in, in_size, token);
1810 if (err) {
1811 mlx5_core_warn(dev, "err %d\n", err);
1812 goto out_in;
1813 }
1814
1815 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1816 if (IS_ERR(outb)) {
1817 err = PTR_ERR(outb);
1818 goto out_in;
1819 }
1820
1821 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1822 pages_queue, &status, token, force_polling);
1823 if (err)
1824 goto out_out;
1825
1826 mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1827 if (status) {
1828 err = status_to_err(status);
1829 goto out_out;
1830 }
1831
1832 if (!callback)
1833 err = mlx5_copy_from_msg(out, outb, out_size);
1834
1835 out_out:
1836 if (!callback)
1837 mlx5_free_cmd_msg(dev, outb);
1838
1839 out_in:
1840 if (!callback)
1841 free_msg(dev, inb);
1842 return err;
1843 }
1844
mlx5_cmd_exec(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)1845 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1846 int out_size)
1847 {
1848 int err;
1849
1850 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1851 return err ? : mlx5_cmd_check(dev, in, out);
1852 }
1853 EXPORT_SYMBOL(mlx5_cmd_exec);
1854
mlx5_cmd_init_async_ctx(struct mlx5_core_dev * dev,struct mlx5_async_ctx * ctx)1855 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
1856 struct mlx5_async_ctx *ctx)
1857 {
1858 ctx->dev = dev;
1859 /* Starts at 1 to avoid doing wake_up if we are not cleaning up */
1860 atomic_set(&ctx->num_inflight, 1);
1861 init_completion(&ctx->inflight_done);
1862 }
1863 EXPORT_SYMBOL(mlx5_cmd_init_async_ctx);
1864
1865 /**
1866 * mlx5_cmd_cleanup_async_ctx - Clean up an async_ctx
1867 * @ctx: The ctx to clean
1868 *
1869 * Upon return all callbacks given to mlx5_cmd_exec_cb() have been called. The
1870 * caller must ensure that mlx5_cmd_exec_cb() is not called during or after
1871 * the call mlx5_cleanup_async_ctx().
1872 */
mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx * ctx)1873 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx)
1874 {
1875 if (!atomic_dec_and_test(&ctx->num_inflight))
1876 wait_for_completion(&ctx->inflight_done);
1877 }
1878 EXPORT_SYMBOL(mlx5_cmd_cleanup_async_ctx);
1879
mlx5_cmd_exec_cb_handler(int status,void * _work)1880 static void mlx5_cmd_exec_cb_handler(int status, void *_work)
1881 {
1882 struct mlx5_async_work *work = _work;
1883 struct mlx5_async_ctx *ctx = work->ctx;
1884
1885 work->user_callback(status, work);
1886 if (atomic_dec_and_test(&ctx->num_inflight))
1887 complete(&ctx->inflight_done);
1888 }
1889
mlx5_cmd_exec_cb(struct mlx5_async_ctx * ctx,void * in,int in_size,void * out,int out_size,mlx5_async_cbk_t callback,struct mlx5_async_work * work)1890 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
1891 void *out, int out_size, mlx5_async_cbk_t callback,
1892 struct mlx5_async_work *work)
1893 {
1894 int ret;
1895
1896 work->ctx = ctx;
1897 work->user_callback = callback;
1898 if (WARN_ON(!atomic_inc_not_zero(&ctx->num_inflight)))
1899 return -EIO;
1900 ret = cmd_exec(ctx->dev, in, in_size, out, out_size,
1901 mlx5_cmd_exec_cb_handler, work, false);
1902 if (ret && atomic_dec_and_test(&ctx->num_inflight))
1903 complete(&ctx->inflight_done);
1904
1905 return ret;
1906 }
1907 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1908
mlx5_cmd_exec_polling(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)1909 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1910 void *out, int out_size)
1911 {
1912 int err;
1913
1914 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1915
1916 return err ? : mlx5_cmd_check(dev, in, out);
1917 }
1918 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1919
destroy_msg_cache(struct mlx5_core_dev * dev)1920 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1921 {
1922 struct cmd_msg_cache *ch;
1923 struct mlx5_cmd_msg *msg;
1924 struct mlx5_cmd_msg *n;
1925 int i;
1926
1927 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1928 ch = &dev->cmd.cache[i];
1929 list_for_each_entry_safe(msg, n, &ch->head, list) {
1930 list_del(&msg->list);
1931 mlx5_free_cmd_msg(dev, msg);
1932 }
1933 }
1934 }
1935
1936 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1937 512, 32, 16, 8, 2
1938 };
1939
1940 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1941 16 + MLX5_CMD_DATA_BLOCK_SIZE,
1942 16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1943 16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1944 16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1945 16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1946 };
1947
create_msg_cache(struct mlx5_core_dev * dev)1948 static void create_msg_cache(struct mlx5_core_dev *dev)
1949 {
1950 struct mlx5_cmd *cmd = &dev->cmd;
1951 struct cmd_msg_cache *ch;
1952 struct mlx5_cmd_msg *msg;
1953 int i;
1954 int k;
1955
1956 /* Initialize and fill the caches with initial entries */
1957 for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1958 ch = &cmd->cache[k];
1959 spin_lock_init(&ch->lock);
1960 INIT_LIST_HEAD(&ch->head);
1961 ch->num_ent = cmd_cache_num_ent[k];
1962 ch->max_inbox_size = cmd_cache_ent_size[k];
1963 for (i = 0; i < ch->num_ent; i++) {
1964 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1965 ch->max_inbox_size, 0);
1966 if (IS_ERR(msg))
1967 break;
1968 msg->parent = ch;
1969 list_add_tail(&msg->list, &ch->head);
1970 }
1971 }
1972 }
1973
alloc_cmd_page(struct mlx5_core_dev * dev,struct mlx5_cmd * cmd)1974 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1975 {
1976 cmd->cmd_alloc_buf = dma_alloc_coherent(mlx5_core_dma_dev(dev), MLX5_ADAPTER_PAGE_SIZE,
1977 &cmd->alloc_dma, GFP_KERNEL);
1978 if (!cmd->cmd_alloc_buf)
1979 return -ENOMEM;
1980
1981 /* make sure it is aligned to 4K */
1982 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1983 cmd->cmd_buf = cmd->cmd_alloc_buf;
1984 cmd->dma = cmd->alloc_dma;
1985 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1986 return 0;
1987 }
1988
1989 dma_free_coherent(mlx5_core_dma_dev(dev), MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1990 cmd->alloc_dma);
1991 cmd->cmd_alloc_buf = dma_alloc_coherent(mlx5_core_dma_dev(dev),
1992 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1993 &cmd->alloc_dma, GFP_KERNEL);
1994 if (!cmd->cmd_alloc_buf)
1995 return -ENOMEM;
1996
1997 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1998 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1999 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
2000 return 0;
2001 }
2002
free_cmd_page(struct mlx5_core_dev * dev,struct mlx5_cmd * cmd)2003 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
2004 {
2005 dma_free_coherent(mlx5_core_dma_dev(dev), cmd->alloc_size, cmd->cmd_alloc_buf,
2006 cmd->alloc_dma);
2007 }
2008
cmdif_rev(struct mlx5_core_dev * dev)2009 static u16 cmdif_rev(struct mlx5_core_dev *dev)
2010 {
2011 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
2012 }
2013
mlx5_cmd_init(struct mlx5_core_dev * dev)2014 int mlx5_cmd_init(struct mlx5_core_dev *dev)
2015 {
2016 int size = sizeof(struct mlx5_cmd_prot_block);
2017 int align = roundup_pow_of_two(size);
2018 struct mlx5_cmd *cmd = &dev->cmd;
2019 u32 cmd_h, cmd_l;
2020 u16 cmd_if_rev;
2021 int err;
2022 int i;
2023
2024 memset(cmd, 0, sizeof(*cmd));
2025 cmd_if_rev = cmdif_rev(dev);
2026 if (cmd_if_rev != CMD_IF_REV) {
2027 mlx5_core_err(dev,
2028 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
2029 CMD_IF_REV, cmd_if_rev);
2030 return -EINVAL;
2031 }
2032
2033 cmd->stats = kvzalloc(MLX5_CMD_OP_MAX * sizeof(*cmd->stats), GFP_KERNEL);
2034 if (!cmd->stats)
2035 return -ENOMEM;
2036
2037 cmd->pool = dma_pool_create("mlx5_cmd", mlx5_core_dma_dev(dev), size, align, 0);
2038 if (!cmd->pool) {
2039 err = -ENOMEM;
2040 goto dma_pool_err;
2041 }
2042
2043 err = alloc_cmd_page(dev, cmd);
2044 if (err)
2045 goto err_free_pool;
2046
2047 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
2048 cmd->log_sz = cmd_l >> 4 & 0xf;
2049 cmd->log_stride = cmd_l & 0xf;
2050 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
2051 mlx5_core_err(dev, "firmware reports too many outstanding commands %d\n",
2052 1 << cmd->log_sz);
2053 err = -EINVAL;
2054 goto err_free_page;
2055 }
2056
2057 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
2058 mlx5_core_err(dev, "command queue size overflow\n");
2059 err = -EINVAL;
2060 goto err_free_page;
2061 }
2062
2063 cmd->state = MLX5_CMDIF_STATE_DOWN;
2064 cmd->checksum_disabled = 1;
2065 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
2066 cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
2067
2068 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
2069 if (cmd->cmdif_rev > CMD_IF_REV) {
2070 mlx5_core_err(dev, "driver does not support command interface version. driver %d, firmware %d\n",
2071 CMD_IF_REV, cmd->cmdif_rev);
2072 err = -EOPNOTSUPP;
2073 goto err_free_page;
2074 }
2075
2076 spin_lock_init(&cmd->alloc_lock);
2077 spin_lock_init(&cmd->token_lock);
2078 for (i = 0; i < MLX5_CMD_OP_MAX; i++)
2079 spin_lock_init(&cmd->stats[i].lock);
2080
2081 sema_init(&cmd->sem, cmd->max_reg_cmds);
2082 sema_init(&cmd->pages_sem, 1);
2083
2084 cmd_h = (u32)((u64)(cmd->dma) >> 32);
2085 cmd_l = (u32)(cmd->dma);
2086 if (cmd_l & 0xfff) {
2087 mlx5_core_err(dev, "invalid command queue address\n");
2088 err = -ENOMEM;
2089 goto err_free_page;
2090 }
2091
2092 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
2093 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
2094
2095 /* Make sure firmware sees the complete address before we proceed */
2096 wmb();
2097
2098 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
2099
2100 cmd->mode = CMD_MODE_POLLING;
2101 cmd->allowed_opcode = CMD_ALLOWED_OPCODE_ALL;
2102
2103 create_msg_cache(dev);
2104
2105 set_wqname(dev);
2106 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
2107 if (!cmd->wq) {
2108 mlx5_core_err(dev, "failed to create command workqueue\n");
2109 err = -ENOMEM;
2110 goto err_cache;
2111 }
2112
2113 create_debugfs_files(dev);
2114
2115 return 0;
2116
2117 err_cache:
2118 destroy_msg_cache(dev);
2119
2120 err_free_page:
2121 free_cmd_page(dev, cmd);
2122
2123 err_free_pool:
2124 dma_pool_destroy(cmd->pool);
2125 dma_pool_err:
2126 kvfree(cmd->stats);
2127 return err;
2128 }
2129 EXPORT_SYMBOL(mlx5_cmd_init);
2130
mlx5_cmd_cleanup(struct mlx5_core_dev * dev)2131 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
2132 {
2133 struct mlx5_cmd *cmd = &dev->cmd;
2134
2135 clean_debug_files(dev);
2136 destroy_workqueue(cmd->wq);
2137 destroy_msg_cache(dev);
2138 free_cmd_page(dev, cmd);
2139 dma_pool_destroy(cmd->pool);
2140 kvfree(cmd->stats);
2141 }
2142 EXPORT_SYMBOL(mlx5_cmd_cleanup);
2143
mlx5_cmd_set_state(struct mlx5_core_dev * dev,enum mlx5_cmdif_state cmdif_state)2144 void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
2145 enum mlx5_cmdif_state cmdif_state)
2146 {
2147 dev->cmd.state = cmdif_state;
2148 }
2149 EXPORT_SYMBOL(mlx5_cmd_set_state);
2150