1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef __MLX5_CORE_H__
34 #define __MLX5_CORE_H__
35
36 #include <linux/types.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/if_link.h>
40 #include <linux/firmware.h>
41 #include <linux/mlx5/cq.h>
42 #include <linux/mlx5/fs.h>
43 #include <linux/mlx5/driver.h>
44
45 extern uint mlx5_core_debug_mask;
46
47 #define mlx5_core_dbg(__dev, format, ...) \
48 dev_dbg((__dev)->device, "%s:%d:(pid %d): " format, \
49 __func__, __LINE__, current->pid, \
50 ##__VA_ARGS__)
51
52 #define mlx5_core_dbg_once(__dev, format, ...) \
53 dev_dbg_once((__dev)->device, \
54 "%s:%d:(pid %d): " format, \
55 __func__, __LINE__, current->pid, \
56 ##__VA_ARGS__)
57
58 #define mlx5_core_dbg_mask(__dev, mask, format, ...) \
59 do { \
60 if ((mask) & mlx5_core_debug_mask) \
61 mlx5_core_dbg(__dev, format, ##__VA_ARGS__); \
62 } while (0)
63
64 #define mlx5_core_err(__dev, format, ...) \
65 dev_err((__dev)->device, "%s:%d:(pid %d): " format, \
66 __func__, __LINE__, current->pid, \
67 ##__VA_ARGS__)
68
69 #define mlx5_core_err_rl(__dev, format, ...) \
70 dev_err_ratelimited((__dev)->device, \
71 "%s:%d:(pid %d): " format, \
72 __func__, __LINE__, current->pid, \
73 ##__VA_ARGS__)
74
75 #define mlx5_core_warn(__dev, format, ...) \
76 dev_warn((__dev)->device, "%s:%d:(pid %d): " format, \
77 __func__, __LINE__, current->pid, \
78 ##__VA_ARGS__)
79
80 #define mlx5_core_warn_once(__dev, format, ...) \
81 dev_warn_once((__dev)->device, "%s:%d:(pid %d): " format, \
82 __func__, __LINE__, current->pid, \
83 ##__VA_ARGS__)
84
85 #define mlx5_core_warn_rl(__dev, format, ...) \
86 dev_warn_ratelimited((__dev)->device, \
87 "%s:%d:(pid %d): " format, \
88 __func__, __LINE__, current->pid, \
89 ##__VA_ARGS__)
90
91 #define mlx5_core_info(__dev, format, ...) \
92 dev_info((__dev)->device, format, ##__VA_ARGS__)
93
94 #define mlx5_core_info_rl(__dev, format, ...) \
95 dev_info_ratelimited((__dev)->device, \
96 "%s:%d:(pid %d): " format, \
97 __func__, __LINE__, current->pid, \
98 ##__VA_ARGS__)
99
mlx5_core_dma_dev(struct mlx5_core_dev * dev)100 static inline struct device *mlx5_core_dma_dev(struct mlx5_core_dev *dev)
101 {
102 return &dev->pdev->dev;
103 }
104
105 enum {
106 MLX5_CMD_DATA, /* print command payload only */
107 MLX5_CMD_TIME, /* print command execution time */
108 };
109
110 enum {
111 MLX5_DRIVER_STATUS_ABORTED = 0xfe,
112 MLX5_DRIVER_SYND = 0xbadd00de,
113 };
114
115 enum mlx5_semaphore_space_address {
116 MLX5_SEMAPHORE_SPACE_DOMAIN = 0xA,
117 MLX5_SEMAPHORE_SW_RESET = 0x20,
118 };
119
120 int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
121 int mlx5_query_board_id(struct mlx5_core_dev *dev);
122 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id);
123 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
124 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
125 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev);
126 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force);
127 void mlx5_error_sw_reset(struct mlx5_core_dev *dev);
128 u32 mlx5_health_check_fatal_sensors(struct mlx5_core_dev *dev);
129 int mlx5_health_wait_pci_up(struct mlx5_core_dev *dev);
130 void mlx5_disable_device(struct mlx5_core_dev *dev);
131 void mlx5_recover_device(struct mlx5_core_dev *dev);
132 int mlx5_sriov_init(struct mlx5_core_dev *dev);
133 void mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
134 int mlx5_sriov_attach(struct mlx5_core_dev *dev);
135 void mlx5_sriov_detach(struct mlx5_core_dev *dev);
136 int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs);
137 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id);
138 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id);
139 int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
140 void *context, u32 *element_id);
141 int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
142 void *context, u32 element_id,
143 u32 modify_bitmask);
144 int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
145 u32 element_id);
146 int mlx5_wait_for_pages(struct mlx5_core_dev *dev, int *pages);
147
148 void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev);
149 void mlx5_cmd_flush(struct mlx5_core_dev *dev);
150 void mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
151 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
152
153 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
154 u8 access_reg_group);
155 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,
156 u8 access_reg_group);
157 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
158 u8 feature_group, u8 access_reg_group);
159
160 void mlx5_lag_add(struct mlx5_core_dev *dev, struct net_device *netdev);
161 void mlx5_lag_remove(struct mlx5_core_dev *dev);
162
163 int mlx5_irq_table_init(struct mlx5_core_dev *dev);
164 void mlx5_irq_table_cleanup(struct mlx5_core_dev *dev);
165 int mlx5_irq_table_create(struct mlx5_core_dev *dev);
166 void mlx5_irq_table_destroy(struct mlx5_core_dev *dev);
167 int mlx5_irq_attach_nb(struct mlx5_irq_table *irq_table, int vecidx,
168 struct notifier_block *nb);
169 int mlx5_irq_detach_nb(struct mlx5_irq_table *irq_table, int vecidx,
170 struct notifier_block *nb);
171 struct cpumask *
172 mlx5_irq_get_affinity_mask(struct mlx5_irq_table *irq_table, int vecidx);
173 struct cpu_rmap *mlx5_irq_get_rmap(struct mlx5_irq_table *table);
174 int mlx5_irq_get_num_comp(struct mlx5_irq_table *table);
175
176 int mlx5_events_init(struct mlx5_core_dev *dev);
177 void mlx5_events_cleanup(struct mlx5_core_dev *dev);
178 void mlx5_events_start(struct mlx5_core_dev *dev);
179 void mlx5_events_stop(struct mlx5_core_dev *dev);
180
181 void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv);
182 void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv);
183 void mlx5_attach_device(struct mlx5_core_dev *dev);
184 void mlx5_detach_device(struct mlx5_core_dev *dev);
185 bool mlx5_device_registered(struct mlx5_core_dev *dev);
186 void mlx5_register_device(struct mlx5_core_dev *dev);
187 void mlx5_unregister_device(struct mlx5_core_dev *dev);
188 void mlx5_add_dev_by_protocol(struct mlx5_core_dev *dev, int protocol);
189 void mlx5_remove_dev_by_protocol(struct mlx5_core_dev *dev, int protocol);
190 struct mlx5_core_dev *mlx5_get_next_phys_dev(struct mlx5_core_dev *dev);
191 void mlx5_dev_list_lock(void);
192 void mlx5_dev_list_unlock(void);
193 int mlx5_dev_list_trylock(void);
194
195 bool mlx5_lag_intf_add(struct mlx5_interface *intf, struct mlx5_priv *priv);
196
197 int mlx5_query_mtpps(struct mlx5_core_dev *dev, u32 *mtpps, u32 mtpps_size);
198 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size);
199 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode);
200 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode);
201
202 struct mlx5_dm *mlx5_dm_create(struct mlx5_core_dev *dev);
203 void mlx5_dm_cleanup(struct mlx5_core_dev *dev);
204
205 #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \
206 MLX5_CAP_GEN((mdev), pps_modify) && \
207 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) && \
208 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj))
209
210 int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw,
211 struct netlink_ext_ack *extack);
212 int mlx5_fw_version_query(struct mlx5_core_dev *dev,
213 u32 *running_ver, u32 *stored_ver);
214
215 void mlx5e_init(void);
216 void mlx5e_cleanup(void);
217
mlx5_sriov_is_enabled(struct mlx5_core_dev * dev)218 static inline bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev)
219 {
220 return pci_num_vf(dev->pdev) ? true : false;
221 }
222
mlx5_lag_is_lacp_owner(struct mlx5_core_dev * dev)223 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
224 {
225 /* LACP owner conditions:
226 * 1) Function is physical.
227 * 2) LAG is supported by FW.
228 * 3) LAG is managed by driver (currently the only option).
229 */
230 return MLX5_CAP_GEN(dev, vport_group_manager) &&
231 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
232 MLX5_CAP_GEN(dev, lag_master);
233 }
234
235 void mlx5_reload_interface(struct mlx5_core_dev *mdev, int protocol);
236 void mlx5_lag_update(struct mlx5_core_dev *dev);
237
238 enum {
239 MLX5_NIC_IFC_FULL = 0,
240 MLX5_NIC_IFC_DISABLED = 1,
241 MLX5_NIC_IFC_NO_DRAM_NIC = 2,
242 MLX5_NIC_IFC_SW_RESET = 7
243 };
244
245 u8 mlx5_get_nic_state(struct mlx5_core_dev *dev);
246 void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state);
247
248 void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup);
249 int mlx5_load_one(struct mlx5_core_dev *dev, bool boot);
250 #endif /* __MLX5_CORE_H__ */
251