1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
52 #endif
53 #include <linux/version.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
56 #include "lib/eq.h"
57 #include "fs_core.h"
58 #include "lib/mpfs.h"
59 #include "eswitch.h"
60 #include "devlink.h"
61 #include "fw_reset.h"
62 #include "lib/mlx5.h"
63 #include "fpga/core.h"
64 #include "fpga/ipsec.h"
65 #include "accel/ipsec.h"
66 #include "accel/tls.h"
67 #include "lib/clock.h"
68 #include "lib/vxlan.h"
69 #include "lib/geneve.h"
70 #include "lib/devcom.h"
71 #include "lib/pci_vsc.h"
72 #include "diag/fw_tracer.h"
73 #include "ecpf.h"
74 #include "lib/hv_vhca.h"
75 #include "diag/rsc_dump.h"
76
77 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
78 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
79 MODULE_LICENSE("Dual BSD/GPL");
80
81 unsigned int mlx5_core_debug_mask;
82 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
83 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
84
85 #define MLX5_DEFAULT_PROF 2
86 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
87 module_param_named(prof_sel, prof_sel, uint, 0444);
88 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
89
90 static u32 sw_owner_id[4];
91
92 enum {
93 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
94 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
95 };
96
97 static struct mlx5_profile profile[] = {
98 [0] = {
99 .mask = 0,
100 },
101 [1] = {
102 .mask = MLX5_PROF_MASK_QP_SIZE,
103 .log_max_qp = 12,
104 },
105 [2] = {
106 .mask = MLX5_PROF_MASK_QP_SIZE |
107 MLX5_PROF_MASK_MR_CACHE,
108 .log_max_qp = 18,
109 .mr_cache[0] = {
110 .size = 500,
111 .limit = 250
112 },
113 .mr_cache[1] = {
114 .size = 500,
115 .limit = 250
116 },
117 .mr_cache[2] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[3] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[4] = {
126 .size = 500,
127 .limit = 250
128 },
129 .mr_cache[5] = {
130 .size = 500,
131 .limit = 250
132 },
133 .mr_cache[6] = {
134 .size = 500,
135 .limit = 250
136 },
137 .mr_cache[7] = {
138 .size = 500,
139 .limit = 250
140 },
141 .mr_cache[8] = {
142 .size = 500,
143 .limit = 250
144 },
145 .mr_cache[9] = {
146 .size = 500,
147 .limit = 250
148 },
149 .mr_cache[10] = {
150 .size = 500,
151 .limit = 250
152 },
153 .mr_cache[11] = {
154 .size = 500,
155 .limit = 250
156 },
157 .mr_cache[12] = {
158 .size = 64,
159 .limit = 32
160 },
161 .mr_cache[13] = {
162 .size = 32,
163 .limit = 16
164 },
165 .mr_cache[14] = {
166 .size = 16,
167 .limit = 8
168 },
169 .mr_cache[15] = {
170 .size = 8,
171 .limit = 4
172 },
173 },
174 };
175
176 #define FW_INIT_TIMEOUT_MILI 2000
177 #define FW_INIT_WAIT_MS 2
178 #define FW_PRE_INIT_TIMEOUT_MILI 120000
179 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000
180
fw_initializing(struct mlx5_core_dev * dev)181 static int fw_initializing(struct mlx5_core_dev *dev)
182 {
183 return ioread32be(&dev->iseg->initializing) >> 31;
184 }
185
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili)186 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
187 u32 warn_time_mili)
188 {
189 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
190 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
191 int err = 0;
192
193 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL);
194
195 while (fw_initializing(dev)) {
196 if (time_after(jiffies, end)) {
197 err = -EBUSY;
198 break;
199 }
200 if (warn_time_mili && time_after(jiffies, warn)) {
201 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
202 jiffies_to_msecs(end - warn) / 1000);
203 warn = jiffies + msecs_to_jiffies(warn_time_mili);
204 }
205 msleep(FW_INIT_WAIT_MS);
206 }
207
208 return err;
209 }
210
mlx5_set_driver_version(struct mlx5_core_dev * dev)211 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
212 {
213 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
214 driver_version);
215 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
216 int remaining_size = driver_ver_sz;
217 char *string;
218
219 if (!MLX5_CAP_GEN(dev, driver_version))
220 return;
221
222 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
223
224 strncpy(string, "Linux", remaining_size);
225
226 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
227 strncat(string, ",", remaining_size);
228
229 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
230 strncat(string, KBUILD_MODNAME, remaining_size);
231
232 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
233 strncat(string, ",", remaining_size);
234
235 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
236
237 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
238 (u8)((LINUX_VERSION_CODE >> 16) & 0xff), (u8)((LINUX_VERSION_CODE >> 8) & 0xff),
239 (u16)(LINUX_VERSION_CODE & 0xffff));
240
241 /*Send the command*/
242 MLX5_SET(set_driver_version_in, in, opcode,
243 MLX5_CMD_OP_SET_DRIVER_VERSION);
244
245 mlx5_cmd_exec_in(dev, set_driver_version, in);
246 }
247
set_dma_caps(struct pci_dev * pdev)248 static int set_dma_caps(struct pci_dev *pdev)
249 {
250 int err;
251
252 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
253 if (err) {
254 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
255 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
256 if (err) {
257 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
258 return err;
259 }
260 }
261
262 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
263 if (err) {
264 dev_warn(&pdev->dev,
265 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
266 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
267 if (err) {
268 dev_err(&pdev->dev,
269 "Can't set consistent PCI DMA mask, aborting\n");
270 return err;
271 }
272 }
273
274 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
275 return err;
276 }
277
mlx5_pci_enable_device(struct mlx5_core_dev * dev)278 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
279 {
280 struct pci_dev *pdev = dev->pdev;
281 int err = 0;
282
283 mutex_lock(&dev->pci_status_mutex);
284 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
285 err = pci_enable_device(pdev);
286 if (!err)
287 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
288 }
289 mutex_unlock(&dev->pci_status_mutex);
290
291 return err;
292 }
293
mlx5_pci_disable_device(struct mlx5_core_dev * dev)294 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
295 {
296 struct pci_dev *pdev = dev->pdev;
297
298 mutex_lock(&dev->pci_status_mutex);
299 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
300 pci_disable_device(pdev);
301 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
302 }
303 mutex_unlock(&dev->pci_status_mutex);
304 }
305
request_bar(struct pci_dev * pdev)306 static int request_bar(struct pci_dev *pdev)
307 {
308 int err = 0;
309
310 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
311 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
312 return -ENODEV;
313 }
314
315 err = pci_request_regions(pdev, KBUILD_MODNAME);
316 if (err)
317 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
318
319 return err;
320 }
321
release_bar(struct pci_dev * pdev)322 static void release_bar(struct pci_dev *pdev)
323 {
324 pci_release_regions(pdev);
325 }
326
327 struct mlx5_reg_host_endianness {
328 u8 he;
329 u8 rsvd[15];
330 };
331
332 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
333
334 enum {
335 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
336 MLX5_DEV_CAP_FLAG_DCT,
337 };
338
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)339 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
340 {
341 switch (size) {
342 case 128:
343 return 0;
344 case 256:
345 return 1;
346 case 512:
347 return 2;
348 case 1024:
349 return 3;
350 case 2048:
351 return 4;
352 case 4096:
353 return 5;
354 default:
355 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
356 return 0;
357 }
358 }
359
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)360 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
361 enum mlx5_cap_type cap_type,
362 enum mlx5_cap_mode cap_mode)
363 {
364 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
365 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
366 void *out, *hca_caps;
367 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
368 int err;
369
370 memset(in, 0, sizeof(in));
371 out = kzalloc(out_sz, GFP_KERNEL);
372 if (!out)
373 return -ENOMEM;
374
375 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
376 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
377 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
378 if (err) {
379 mlx5_core_warn(dev,
380 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
381 cap_type, cap_mode, err);
382 goto query_ex;
383 }
384
385 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
386
387 switch (cap_mode) {
388 case HCA_CAP_OPMOD_GET_MAX:
389 memcpy(dev->caps.hca_max[cap_type], hca_caps,
390 MLX5_UN_SZ_BYTES(hca_cap_union));
391 break;
392 case HCA_CAP_OPMOD_GET_CUR:
393 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
394 MLX5_UN_SZ_BYTES(hca_cap_union));
395 break;
396 default:
397 mlx5_core_warn(dev,
398 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
399 cap_type, cap_mode);
400 err = -EINVAL;
401 break;
402 }
403 query_ex:
404 kfree(out);
405 return err;
406 }
407
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)408 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
409 {
410 int ret;
411
412 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
413 if (ret)
414 return ret;
415 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
416 }
417
set_caps(struct mlx5_core_dev * dev,void * in,int opmod)418 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
419 {
420 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
421 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
422 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
423 }
424
handle_hca_cap_atomic(struct mlx5_core_dev * dev,void * set_ctx)425 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
426 {
427 void *set_hca_cap;
428 int req_endianness;
429 int err;
430
431 if (!MLX5_CAP_GEN(dev, atomic))
432 return 0;
433
434 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
435 if (err)
436 return err;
437
438 req_endianness =
439 MLX5_CAP_ATOMIC(dev,
440 supported_atomic_req_8B_endianness_mode_1);
441
442 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
443 return 0;
444
445 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
446
447 /* Set requestor to host endianness */
448 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
449 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
450
451 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
452 }
453
handle_hca_cap_odp(struct mlx5_core_dev * dev,void * set_ctx)454 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
455 {
456 void *set_hca_cap;
457 bool do_set = false;
458 int err;
459
460 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
461 !MLX5_CAP_GEN(dev, pg))
462 return 0;
463
464 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
465 if (err)
466 return err;
467
468 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
469 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP],
470 MLX5_ST_SZ_BYTES(odp_cap));
471
472 #define ODP_CAP_SET_MAX(dev, field) \
473 do { \
474 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
475 if (_res) { \
476 do_set = true; \
477 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
478 } \
479 } while (0)
480
481 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
482 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
483 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
484 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
485 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
486 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
487 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
488 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
489 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
490 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
491 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
492 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
493 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
494 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
495
496 if (!do_set)
497 return 0;
498
499 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
500 }
501
handle_hca_cap(struct mlx5_core_dev * dev,void * set_ctx)502 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
503 {
504 struct mlx5_profile *prof = dev->profile;
505 void *set_hca_cap;
506 int err;
507
508 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
509 if (err)
510 return err;
511
512 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
513 capability);
514 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
515 MLX5_ST_SZ_BYTES(cmd_hca_cap));
516
517 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
518 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
519 128);
520 /* we limit the size of the pkey table to 128 entries for now */
521 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
522 to_fw_pkey_sz(dev, 128));
523
524 /* Check log_max_qp from HCA caps to set in current profile */
525 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
526 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
527 profile[prof_sel].log_max_qp,
528 MLX5_CAP_GEN_MAX(dev, log_max_qp));
529 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
530 }
531 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
532 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
533 prof->log_max_qp);
534
535 /* disable cmdif checksum */
536 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
537
538 /* Enable 4K UAR only when HCA supports it and page size is bigger
539 * than 4K.
540 */
541 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
542 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
543
544 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
545
546 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
547 MLX5_SET(cmd_hca_cap,
548 set_hca_cap,
549 cache_line_128byte,
550 cache_line_size() >= 128 ? 1 : 0);
551
552 if (MLX5_CAP_GEN_MAX(dev, dct))
553 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
554
555 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
556 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
557
558 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
559 MLX5_SET(cmd_hca_cap,
560 set_hca_cap,
561 num_vhca_ports,
562 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
563
564 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
565 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
566
567 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
568 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
569
570 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
571 }
572
handle_hca_cap_roce(struct mlx5_core_dev * dev,void * set_ctx)573 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
574 {
575 void *set_hca_cap;
576 int err;
577
578 if (!MLX5_CAP_GEN(dev, roce))
579 return 0;
580
581 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
582 if (err)
583 return err;
584
585 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
586 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
587 return 0;
588
589 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
590 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ROCE],
591 MLX5_ST_SZ_BYTES(roce_cap));
592 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
593
594 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
595 return err;
596 }
597
set_hca_cap(struct mlx5_core_dev * dev)598 static int set_hca_cap(struct mlx5_core_dev *dev)
599 {
600 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
601 void *set_ctx;
602 int err;
603
604 set_ctx = kzalloc(set_sz, GFP_KERNEL);
605 if (!set_ctx)
606 return -ENOMEM;
607
608 err = handle_hca_cap(dev, set_ctx);
609 if (err) {
610 mlx5_core_err(dev, "handle_hca_cap failed\n");
611 goto out;
612 }
613
614 memset(set_ctx, 0, set_sz);
615 err = handle_hca_cap_atomic(dev, set_ctx);
616 if (err) {
617 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
618 goto out;
619 }
620
621 memset(set_ctx, 0, set_sz);
622 err = handle_hca_cap_odp(dev, set_ctx);
623 if (err) {
624 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
625 goto out;
626 }
627
628 memset(set_ctx, 0, set_sz);
629 err = handle_hca_cap_roce(dev, set_ctx);
630 if (err) {
631 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
632 goto out;
633 }
634
635 out:
636 kfree(set_ctx);
637 return err;
638 }
639
set_hca_ctrl(struct mlx5_core_dev * dev)640 static int set_hca_ctrl(struct mlx5_core_dev *dev)
641 {
642 struct mlx5_reg_host_endianness he_in;
643 struct mlx5_reg_host_endianness he_out;
644 int err;
645
646 if (!mlx5_core_is_pf(dev))
647 return 0;
648
649 memset(&he_in, 0, sizeof(he_in));
650 he_in.he = MLX5_SET_HOST_ENDIANNESS;
651 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
652 &he_out, sizeof(he_out),
653 MLX5_REG_HOST_ENDIANNESS, 0, 1);
654 return err;
655 }
656
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)657 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
658 {
659 int ret = 0;
660
661 /* Disable local_lb by default */
662 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
663 ret = mlx5_nic_vport_update_local_lb(dev, false);
664
665 return ret;
666 }
667
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)668 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
669 {
670 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
671
672 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
673 MLX5_SET(enable_hca_in, in, function_id, func_id);
674 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
675 dev->caps.embedded_cpu);
676 return mlx5_cmd_exec_in(dev, enable_hca, in);
677 }
678
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)679 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
680 {
681 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
682
683 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
684 MLX5_SET(disable_hca_in, in, function_id, func_id);
685 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
686 dev->caps.embedded_cpu);
687 return mlx5_cmd_exec_in(dev, disable_hca, in);
688 }
689
mlx5_core_set_issi(struct mlx5_core_dev * dev)690 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
691 {
692 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
693 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
694 u32 sup_issi;
695 int err;
696
697 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
698 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
699 if (err) {
700 u32 syndrome;
701 u8 status;
702
703 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
704 if (!status || syndrome == MLX5_DRIVER_SYND) {
705 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
706 err, status, syndrome);
707 return err;
708 }
709
710 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
711 dev->issi = 0;
712 return 0;
713 }
714
715 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
716
717 if (sup_issi & (1 << 1)) {
718 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
719
720 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
721 MLX5_SET(set_issi_in, set_in, current_issi, 1);
722 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
723 if (err) {
724 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
725 err);
726 return err;
727 }
728
729 dev->issi = 1;
730
731 return 0;
732 } else if (sup_issi & (1 << 0) || !sup_issi) {
733 return 0;
734 }
735
736 return -EOPNOTSUPP;
737 }
738
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)739 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
740 const struct pci_device_id *id)
741 {
742 struct mlx5_priv *priv = &dev->priv;
743 int err = 0;
744
745 mutex_init(&dev->pci_status_mutex);
746 pci_set_drvdata(dev->pdev, dev);
747
748 dev->bar_addr = pci_resource_start(pdev, 0);
749 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
750
751 err = mlx5_pci_enable_device(dev);
752 if (err) {
753 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
754 return err;
755 }
756
757 err = request_bar(pdev);
758 if (err) {
759 mlx5_core_err(dev, "error requesting BARs, aborting\n");
760 goto err_disable;
761 }
762
763 pci_set_master(pdev);
764
765 err = set_dma_caps(pdev);
766 if (err) {
767 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
768 goto err_clr_master;
769 }
770
771 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
772 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
773 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
774 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
775
776 dev->iseg_base = dev->bar_addr;
777 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
778 if (!dev->iseg) {
779 err = -ENOMEM;
780 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
781 goto err_clr_master;
782 }
783
784 mlx5_pci_vsc_init(dev);
785 return 0;
786
787 err_clr_master:
788 pci_clear_master(dev->pdev);
789 release_bar(dev->pdev);
790 err_disable:
791 mlx5_pci_disable_device(dev);
792 return err;
793 }
794
mlx5_pci_close(struct mlx5_core_dev * dev)795 static void mlx5_pci_close(struct mlx5_core_dev *dev)
796 {
797 /* health work might still be active, and it needs pci bar in
798 * order to know the NIC state. Therefore, drain the health WQ
799 * before removing the pci bars
800 */
801 mlx5_drain_health_wq(dev);
802 iounmap(dev->iseg);
803 pci_clear_master(dev->pdev);
804 release_bar(dev->pdev);
805 mlx5_pci_disable_device(dev);
806 }
807
mlx5_init_once(struct mlx5_core_dev * dev)808 static int mlx5_init_once(struct mlx5_core_dev *dev)
809 {
810 int err;
811
812 dev->priv.devcom = mlx5_devcom_register_device(dev);
813 if (IS_ERR(dev->priv.devcom))
814 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
815 dev->priv.devcom);
816
817 err = mlx5_query_board_id(dev);
818 if (err) {
819 mlx5_core_err(dev, "query board id failed\n");
820 goto err_devcom;
821 }
822
823 err = mlx5_irq_table_init(dev);
824 if (err) {
825 mlx5_core_err(dev, "failed to initialize irq table\n");
826 goto err_devcom;
827 }
828
829 err = mlx5_eq_table_init(dev);
830 if (err) {
831 mlx5_core_err(dev, "failed to initialize eq\n");
832 goto err_irq_cleanup;
833 }
834
835 err = mlx5_events_init(dev);
836 if (err) {
837 mlx5_core_err(dev, "failed to initialize events\n");
838 goto err_eq_cleanup;
839 }
840
841 err = mlx5_fw_reset_init(dev);
842 if (err) {
843 mlx5_core_err(dev, "failed to initialize fw reset events\n");
844 goto err_events_cleanup;
845 }
846
847 mlx5_cq_debugfs_init(dev);
848
849 mlx5_init_reserved_gids(dev);
850
851 mlx5_init_clock(dev);
852
853 dev->vxlan = mlx5_vxlan_create(dev);
854 dev->geneve = mlx5_geneve_create(dev);
855
856 err = mlx5_init_rl_table(dev);
857 if (err) {
858 mlx5_core_err(dev, "Failed to init rate limiting\n");
859 goto err_tables_cleanup;
860 }
861
862 err = mlx5_mpfs_init(dev);
863 if (err) {
864 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
865 goto err_rl_cleanup;
866 }
867
868 err = mlx5_sriov_init(dev);
869 if (err) {
870 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
871 goto err_mpfs_cleanup;
872 }
873
874 err = mlx5_eswitch_init(dev);
875 if (err) {
876 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
877 goto err_sriov_cleanup;
878 }
879
880 err = mlx5_fpga_init(dev);
881 if (err) {
882 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
883 goto err_eswitch_cleanup;
884 }
885
886 dev->dm = mlx5_dm_create(dev);
887 if (IS_ERR(dev->dm))
888 mlx5_core_warn(dev, "Failed to init device memory %ld\n", PTR_ERR(dev->dm));
889
890 dev->tracer = mlx5_fw_tracer_create(dev);
891 dev->hv_vhca = mlx5_hv_vhca_create(dev);
892 dev->rsc_dump = mlx5_rsc_dump_create(dev);
893
894 return 0;
895
896 err_eswitch_cleanup:
897 mlx5_eswitch_cleanup(dev->priv.eswitch);
898 err_sriov_cleanup:
899 mlx5_sriov_cleanup(dev);
900 err_mpfs_cleanup:
901 mlx5_mpfs_cleanup(dev);
902 err_rl_cleanup:
903 mlx5_cleanup_rl_table(dev);
904 err_tables_cleanup:
905 mlx5_geneve_destroy(dev->geneve);
906 mlx5_vxlan_destroy(dev->vxlan);
907 mlx5_cleanup_clock(dev);
908 mlx5_cleanup_reserved_gids(dev);
909 mlx5_cq_debugfs_cleanup(dev);
910 mlx5_fw_reset_cleanup(dev);
911 err_events_cleanup:
912 mlx5_events_cleanup(dev);
913 err_eq_cleanup:
914 mlx5_eq_table_cleanup(dev);
915 err_irq_cleanup:
916 mlx5_irq_table_cleanup(dev);
917 err_devcom:
918 mlx5_devcom_unregister_device(dev->priv.devcom);
919
920 return err;
921 }
922
mlx5_cleanup_once(struct mlx5_core_dev * dev)923 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
924 {
925 mlx5_rsc_dump_destroy(dev);
926 mlx5_hv_vhca_destroy(dev->hv_vhca);
927 mlx5_fw_tracer_destroy(dev->tracer);
928 mlx5_dm_cleanup(dev);
929 mlx5_fpga_cleanup(dev);
930 mlx5_eswitch_cleanup(dev->priv.eswitch);
931 mlx5_sriov_cleanup(dev);
932 mlx5_mpfs_cleanup(dev);
933 mlx5_cleanup_rl_table(dev);
934 mlx5_geneve_destroy(dev->geneve);
935 mlx5_vxlan_destroy(dev->vxlan);
936 mlx5_cleanup_clock(dev);
937 mlx5_cleanup_reserved_gids(dev);
938 mlx5_cq_debugfs_cleanup(dev);
939 mlx5_fw_reset_cleanup(dev);
940 mlx5_events_cleanup(dev);
941 mlx5_eq_table_cleanup(dev);
942 mlx5_irq_table_cleanup(dev);
943 mlx5_devcom_unregister_device(dev->priv.devcom);
944 }
945
mlx5_function_setup(struct mlx5_core_dev * dev,bool boot)946 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
947 {
948 int err;
949
950 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
951 fw_rev_min(dev), fw_rev_sub(dev));
952
953 /* Only PFs hold the relevant PCIe information for this query */
954 if (mlx5_core_is_pf(dev))
955 pcie_print_link_status(dev->pdev);
956
957 /* wait for firmware to accept initialization segments configurations
958 */
959 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL);
960 if (err) {
961 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n",
962 FW_PRE_INIT_TIMEOUT_MILI);
963 return err;
964 }
965
966 err = mlx5_cmd_init(dev);
967 if (err) {
968 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
969 return err;
970 }
971
972 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0);
973 if (err) {
974 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n",
975 FW_INIT_TIMEOUT_MILI);
976 goto err_cmd_cleanup;
977 }
978
979 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
980 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
981
982 err = mlx5_core_enable_hca(dev, 0);
983 if (err) {
984 mlx5_core_err(dev, "enable hca failed\n");
985 goto err_cmd_cleanup;
986 }
987
988 err = mlx5_core_set_issi(dev);
989 if (err) {
990 mlx5_core_err(dev, "failed to set issi\n");
991 goto err_disable_hca;
992 }
993
994 err = mlx5_satisfy_startup_pages(dev, 1);
995 if (err) {
996 mlx5_core_err(dev, "failed to allocate boot pages\n");
997 goto err_disable_hca;
998 }
999
1000 err = set_hca_ctrl(dev);
1001 if (err) {
1002 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1003 goto reclaim_boot_pages;
1004 }
1005
1006 err = set_hca_cap(dev);
1007 if (err) {
1008 mlx5_core_err(dev, "set_hca_cap failed\n");
1009 goto reclaim_boot_pages;
1010 }
1011
1012 err = mlx5_satisfy_startup_pages(dev, 0);
1013 if (err) {
1014 mlx5_core_err(dev, "failed to allocate init pages\n");
1015 goto reclaim_boot_pages;
1016 }
1017
1018 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1019 if (err) {
1020 mlx5_core_err(dev, "init hca failed\n");
1021 goto reclaim_boot_pages;
1022 }
1023
1024 mlx5_set_driver_version(dev);
1025
1026 mlx5_start_health_poll(dev);
1027
1028 err = mlx5_query_hca_caps(dev);
1029 if (err) {
1030 mlx5_core_err(dev, "query hca failed\n");
1031 goto stop_health;
1032 }
1033
1034 return 0;
1035
1036 stop_health:
1037 mlx5_stop_health_poll(dev, boot);
1038 reclaim_boot_pages:
1039 mlx5_reclaim_startup_pages(dev);
1040 err_disable_hca:
1041 mlx5_core_disable_hca(dev, 0);
1042 err_cmd_cleanup:
1043 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1044 mlx5_cmd_cleanup(dev);
1045
1046 return err;
1047 }
1048
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1049 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1050 {
1051 int err;
1052
1053 mlx5_stop_health_poll(dev, boot);
1054 err = mlx5_cmd_teardown_hca(dev);
1055 if (err) {
1056 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1057 return err;
1058 }
1059 mlx5_reclaim_startup_pages(dev);
1060 mlx5_core_disable_hca(dev, 0);
1061 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1062 mlx5_cmd_cleanup(dev);
1063
1064 return 0;
1065 }
1066
mlx5_load(struct mlx5_core_dev * dev)1067 static int mlx5_load(struct mlx5_core_dev *dev)
1068 {
1069 int err;
1070
1071 dev->priv.uar = mlx5_get_uars_page(dev);
1072 if (IS_ERR(dev->priv.uar)) {
1073 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1074 err = PTR_ERR(dev->priv.uar);
1075 return err;
1076 }
1077
1078 mlx5_events_start(dev);
1079 mlx5_pagealloc_start(dev);
1080
1081 err = mlx5_irq_table_create(dev);
1082 if (err) {
1083 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1084 goto err_irq_table;
1085 }
1086
1087 err = mlx5_eq_table_create(dev);
1088 if (err) {
1089 mlx5_core_err(dev, "Failed to create EQs\n");
1090 goto err_eq_table;
1091 }
1092
1093 err = mlx5_fw_tracer_init(dev->tracer);
1094 if (err) {
1095 mlx5_core_err(dev, "Failed to init FW tracer\n");
1096 goto err_fw_tracer;
1097 }
1098
1099 mlx5_fw_reset_events_start(dev);
1100 mlx5_hv_vhca_init(dev->hv_vhca);
1101
1102 err = mlx5_rsc_dump_init(dev);
1103 if (err) {
1104 mlx5_core_err(dev, "Failed to init Resource dump\n");
1105 goto err_rsc_dump;
1106 }
1107
1108 err = mlx5_fpga_device_start(dev);
1109 if (err) {
1110 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1111 goto err_fpga_start;
1112 }
1113
1114 mlx5_accel_ipsec_init(dev);
1115
1116 err = mlx5_accel_tls_init(dev);
1117 if (err) {
1118 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1119 goto err_tls_start;
1120 }
1121
1122 err = mlx5_init_fs(dev);
1123 if (err) {
1124 mlx5_core_err(dev, "Failed to init flow steering\n");
1125 goto err_fs;
1126 }
1127
1128 err = mlx5_core_set_hca_defaults(dev);
1129 if (err) {
1130 mlx5_core_err(dev, "Failed to set hca defaults\n");
1131 goto err_sriov;
1132 }
1133
1134 err = mlx5_sriov_attach(dev);
1135 if (err) {
1136 mlx5_core_err(dev, "sriov init failed %d\n", err);
1137 goto err_sriov;
1138 }
1139
1140 err = mlx5_ec_init(dev);
1141 if (err) {
1142 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1143 goto err_ec;
1144 }
1145
1146 return 0;
1147
1148 err_ec:
1149 mlx5_sriov_detach(dev);
1150 err_sriov:
1151 mlx5_cleanup_fs(dev);
1152 err_fs:
1153 mlx5_accel_tls_cleanup(dev);
1154 err_tls_start:
1155 mlx5_accel_ipsec_cleanup(dev);
1156 mlx5_fpga_device_stop(dev);
1157 err_fpga_start:
1158 mlx5_rsc_dump_cleanup(dev);
1159 err_rsc_dump:
1160 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1161 mlx5_fw_reset_events_stop(dev);
1162 mlx5_fw_tracer_cleanup(dev->tracer);
1163 err_fw_tracer:
1164 mlx5_eq_table_destroy(dev);
1165 err_eq_table:
1166 mlx5_irq_table_destroy(dev);
1167 err_irq_table:
1168 mlx5_pagealloc_stop(dev);
1169 mlx5_events_stop(dev);
1170 mlx5_put_uars_page(dev, dev->priv.uar);
1171 return err;
1172 }
1173
mlx5_unload(struct mlx5_core_dev * dev)1174 static void mlx5_unload(struct mlx5_core_dev *dev)
1175 {
1176 mlx5_ec_cleanup(dev);
1177 mlx5_sriov_detach(dev);
1178 mlx5_cleanup_fs(dev);
1179 mlx5_accel_ipsec_cleanup(dev);
1180 mlx5_accel_tls_cleanup(dev);
1181 mlx5_fpga_device_stop(dev);
1182 mlx5_rsc_dump_cleanup(dev);
1183 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1184 mlx5_fw_reset_events_stop(dev);
1185 mlx5_fw_tracer_cleanup(dev->tracer);
1186 mlx5_eq_table_destroy(dev);
1187 mlx5_irq_table_destroy(dev);
1188 mlx5_pagealloc_stop(dev);
1189 mlx5_events_stop(dev);
1190 mlx5_put_uars_page(dev, dev->priv.uar);
1191 }
1192
mlx5_load_one(struct mlx5_core_dev * dev,bool boot)1193 int mlx5_load_one(struct mlx5_core_dev *dev, bool boot)
1194 {
1195 int err = 0;
1196
1197 mutex_lock(&dev->intf_state_mutex);
1198 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1199 mlx5_core_warn(dev, "interface is up, NOP\n");
1200 goto out;
1201 }
1202 /* remove any previous indication of internal error */
1203 dev->state = MLX5_DEVICE_STATE_UP;
1204
1205 err = mlx5_function_setup(dev, boot);
1206 if (err)
1207 goto err_function;
1208
1209 if (boot) {
1210 err = mlx5_init_once(dev);
1211 if (err) {
1212 mlx5_core_err(dev, "sw objs init failed\n");
1213 goto function_teardown;
1214 }
1215 }
1216
1217 err = mlx5_load(dev);
1218 if (err)
1219 goto err_load;
1220
1221 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1222
1223 if (boot) {
1224 err = mlx5_devlink_register(priv_to_devlink(dev), dev->device);
1225 if (err)
1226 goto err_devlink_reg;
1227 mlx5_register_device(dev);
1228 } else {
1229 mlx5_attach_device(dev);
1230 }
1231
1232 mutex_unlock(&dev->intf_state_mutex);
1233 return 0;
1234
1235 err_devlink_reg:
1236 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1237 mlx5_unload(dev);
1238 err_load:
1239 if (boot)
1240 mlx5_cleanup_once(dev);
1241 function_teardown:
1242 mlx5_function_teardown(dev, boot);
1243 err_function:
1244 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1245 out:
1246 mutex_unlock(&dev->intf_state_mutex);
1247 return err;
1248 }
1249
mlx5_unload_one(struct mlx5_core_dev * dev,bool cleanup)1250 void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup)
1251 {
1252 mutex_lock(&dev->intf_state_mutex);
1253
1254 if (cleanup) {
1255 mlx5_unregister_device(dev);
1256 mlx5_devlink_unregister(priv_to_devlink(dev));
1257 } else {
1258 mlx5_detach_device(dev);
1259 }
1260
1261 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1262 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1263 __func__);
1264 if (cleanup)
1265 mlx5_cleanup_once(dev);
1266 goto out;
1267 }
1268
1269 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1270
1271 mlx5_unload(dev);
1272
1273 if (cleanup)
1274 mlx5_cleanup_once(dev);
1275
1276 mlx5_function_teardown(dev, cleanup);
1277 out:
1278 mutex_unlock(&dev->intf_state_mutex);
1279 }
1280
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1281 static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1282 {
1283 struct mlx5_priv *priv = &dev->priv;
1284 int err;
1285
1286 dev->profile = &profile[profile_idx];
1287
1288 INIT_LIST_HEAD(&priv->ctx_list);
1289 spin_lock_init(&priv->ctx_lock);
1290 mutex_init(&dev->intf_state_mutex);
1291
1292 mutex_init(&priv->bfregs.reg_head.lock);
1293 mutex_init(&priv->bfregs.wc_head.lock);
1294 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1295 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1296
1297 mutex_init(&priv->alloc_mutex);
1298 mutex_init(&priv->pgdir_mutex);
1299 INIT_LIST_HEAD(&priv->pgdir_list);
1300
1301 priv->dbg_root = debugfs_create_dir(dev_name(dev->device),
1302 mlx5_debugfs_root);
1303 err = mlx5_health_init(dev);
1304 if (err)
1305 goto err_health_init;
1306
1307 err = mlx5_pagealloc_init(dev);
1308 if (err)
1309 goto err_pagealloc_init;
1310
1311 return 0;
1312
1313 err_pagealloc_init:
1314 mlx5_health_cleanup(dev);
1315 err_health_init:
1316 debugfs_remove(dev->priv.dbg_root);
1317 mutex_destroy(&priv->pgdir_mutex);
1318 mutex_destroy(&priv->alloc_mutex);
1319 mutex_destroy(&priv->bfregs.wc_head.lock);
1320 mutex_destroy(&priv->bfregs.reg_head.lock);
1321 mutex_destroy(&dev->intf_state_mutex);
1322 return err;
1323 }
1324
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1325 static void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1326 {
1327 struct mlx5_priv *priv = &dev->priv;
1328
1329 mlx5_pagealloc_cleanup(dev);
1330 mlx5_health_cleanup(dev);
1331 debugfs_remove_recursive(dev->priv.dbg_root);
1332 mutex_destroy(&priv->pgdir_mutex);
1333 mutex_destroy(&priv->alloc_mutex);
1334 mutex_destroy(&priv->bfregs.wc_head.lock);
1335 mutex_destroy(&priv->bfregs.reg_head.lock);
1336 mutex_destroy(&dev->intf_state_mutex);
1337 }
1338
1339 #define MLX5_IB_MOD "mlx5_ib"
init_one(struct pci_dev * pdev,const struct pci_device_id * id)1340 static int init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1341 {
1342 struct mlx5_core_dev *dev;
1343 struct devlink *devlink;
1344 int err;
1345
1346 devlink = mlx5_devlink_alloc();
1347 if (!devlink) {
1348 dev_err(&pdev->dev, "devlink alloc failed\n");
1349 return -ENOMEM;
1350 }
1351
1352 dev = devlink_priv(devlink);
1353 dev->device = &pdev->dev;
1354 dev->pdev = pdev;
1355
1356 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1357 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1358
1359 err = mlx5_mdev_init(dev, prof_sel);
1360 if (err)
1361 goto mdev_init_err;
1362
1363 err = mlx5_pci_init(dev, pdev, id);
1364 if (err) {
1365 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1366 err);
1367 goto pci_init_err;
1368 }
1369
1370 err = mlx5_load_one(dev, true);
1371 if (err) {
1372 mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n",
1373 err);
1374 goto err_load_one;
1375 }
1376
1377 request_module_nowait(MLX5_IB_MOD);
1378
1379 err = mlx5_crdump_enable(dev);
1380 if (err)
1381 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1382
1383 pci_save_state(pdev);
1384 if (!mlx5_core_is_mp_slave(dev))
1385 devlink_reload_enable(devlink);
1386 return 0;
1387
1388 err_load_one:
1389 mlx5_pci_close(dev);
1390 pci_init_err:
1391 mlx5_mdev_uninit(dev);
1392 mdev_init_err:
1393 mlx5_devlink_free(devlink);
1394
1395 return err;
1396 }
1397
remove_one(struct pci_dev * pdev)1398 static void remove_one(struct pci_dev *pdev)
1399 {
1400 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1401 struct devlink *devlink = priv_to_devlink(dev);
1402
1403 devlink_reload_disable(devlink);
1404 mlx5_crdump_disable(dev);
1405 mlx5_drain_health_wq(dev);
1406 mlx5_unload_one(dev, true);
1407 mlx5_pci_close(dev);
1408 mlx5_mdev_uninit(dev);
1409 mlx5_devlink_free(devlink);
1410 }
1411
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)1412 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1413 pci_channel_state_t state)
1414 {
1415 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1416
1417 mlx5_core_info(dev, "%s was called\n", __func__);
1418
1419 mlx5_enter_error_state(dev, false);
1420 mlx5_error_sw_reset(dev);
1421 mlx5_unload_one(dev, false);
1422 mlx5_drain_health_wq(dev);
1423 mlx5_pci_disable_device(dev);
1424
1425 return state == pci_channel_io_perm_failure ?
1426 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1427 }
1428
1429 /* wait for the device to show vital signs by waiting
1430 * for the health counter to start counting.
1431 */
wait_vital(struct pci_dev * pdev)1432 static int wait_vital(struct pci_dev *pdev)
1433 {
1434 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1435 struct mlx5_core_health *health = &dev->priv.health;
1436 const int niter = 100;
1437 u32 last_count = 0;
1438 u32 count;
1439 int i;
1440
1441 for (i = 0; i < niter; i++) {
1442 count = ioread32be(health->health_counter);
1443 if (count && count != 0xffffffff) {
1444 if (last_count && last_count != count) {
1445 mlx5_core_info(dev,
1446 "wait vital counter value 0x%x after %d iterations\n",
1447 count, i);
1448 return 0;
1449 }
1450 last_count = count;
1451 }
1452 msleep(50);
1453 }
1454
1455 return -ETIMEDOUT;
1456 }
1457
mlx5_pci_slot_reset(struct pci_dev * pdev)1458 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1459 {
1460 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1461 int err;
1462
1463 mlx5_core_info(dev, "%s was called\n", __func__);
1464
1465 err = mlx5_pci_enable_device(dev);
1466 if (err) {
1467 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1468 __func__, err);
1469 return PCI_ERS_RESULT_DISCONNECT;
1470 }
1471
1472 pci_set_master(pdev);
1473 pci_restore_state(pdev);
1474 pci_save_state(pdev);
1475
1476 if (wait_vital(pdev)) {
1477 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__);
1478 return PCI_ERS_RESULT_DISCONNECT;
1479 }
1480
1481 return PCI_ERS_RESULT_RECOVERED;
1482 }
1483
mlx5_pci_resume(struct pci_dev * pdev)1484 static void mlx5_pci_resume(struct pci_dev *pdev)
1485 {
1486 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1487 int err;
1488
1489 mlx5_core_info(dev, "%s was called\n", __func__);
1490
1491 err = mlx5_load_one(dev, false);
1492 if (err)
1493 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n",
1494 __func__, err);
1495 else
1496 mlx5_core_info(dev, "%s: device recovered\n", __func__);
1497 }
1498
1499 static const struct pci_error_handlers mlx5_err_handler = {
1500 .error_detected = mlx5_pci_err_detected,
1501 .slot_reset = mlx5_pci_slot_reset,
1502 .resume = mlx5_pci_resume
1503 };
1504
mlx5_try_fast_unload(struct mlx5_core_dev * dev)1505 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1506 {
1507 bool fast_teardown = false, force_teardown = false;
1508 int ret = 1;
1509
1510 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1511 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1512
1513 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1514 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1515
1516 if (!fast_teardown && !force_teardown)
1517 return -EOPNOTSUPP;
1518
1519 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1520 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1521 return -EAGAIN;
1522 }
1523
1524 /* Panic tear down fw command will stop the PCI bus communication
1525 * with the HCA, so the health polll is no longer needed.
1526 */
1527 mlx5_drain_health_wq(dev);
1528 mlx5_stop_health_poll(dev, false);
1529
1530 ret = mlx5_cmd_fast_teardown_hca(dev);
1531 if (!ret)
1532 goto succeed;
1533
1534 ret = mlx5_cmd_force_teardown_hca(dev);
1535 if (!ret)
1536 goto succeed;
1537
1538 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1539 mlx5_start_health_poll(dev);
1540 return ret;
1541
1542 succeed:
1543 mlx5_enter_error_state(dev, true);
1544
1545 /* Some platforms requiring freeing the IRQ's in the shutdown
1546 * flow. If they aren't freed they can't be allocated after
1547 * kexec. There is no need to cleanup the mlx5_core software
1548 * contexts.
1549 */
1550 mlx5_core_eq_free_irqs(dev);
1551
1552 return 0;
1553 }
1554
shutdown(struct pci_dev * pdev)1555 static void shutdown(struct pci_dev *pdev)
1556 {
1557 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1558 int err;
1559
1560 mlx5_core_info(dev, "Shutdown was called\n");
1561 err = mlx5_try_fast_unload(dev);
1562 if (err)
1563 mlx5_unload_one(dev, false);
1564 mlx5_pci_disable_device(dev);
1565 }
1566
mlx5_suspend(struct pci_dev * pdev,pm_message_t state)1567 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
1568 {
1569 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1570
1571 mlx5_unload_one(dev, false);
1572
1573 return 0;
1574 }
1575
mlx5_resume(struct pci_dev * pdev)1576 static int mlx5_resume(struct pci_dev *pdev)
1577 {
1578 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1579
1580 return mlx5_load_one(dev, false);
1581 }
1582
1583 static const struct pci_device_id mlx5_core_pci_table[] = {
1584 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1585 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1586 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1587 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1588 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1589 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1590 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1591 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1592 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1593 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1594 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1595 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1596 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1597 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1598 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1599 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
1600 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1601 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1602 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1603 { 0, }
1604 };
1605
1606 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1607
mlx5_disable_device(struct mlx5_core_dev * dev)1608 void mlx5_disable_device(struct mlx5_core_dev *dev)
1609 {
1610 mlx5_error_sw_reset(dev);
1611 mlx5_unload_one(dev, false);
1612 }
1613
mlx5_recover_device(struct mlx5_core_dev * dev)1614 void mlx5_recover_device(struct mlx5_core_dev *dev)
1615 {
1616 mlx5_pci_disable_device(dev);
1617 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1618 mlx5_pci_resume(dev->pdev);
1619 }
1620
1621 static struct pci_driver mlx5_core_driver = {
1622 .name = KBUILD_MODNAME,
1623 .id_table = mlx5_core_pci_table,
1624 .probe = init_one,
1625 .remove = remove_one,
1626 .suspend = mlx5_suspend,
1627 .resume = mlx5_resume,
1628 .shutdown = shutdown,
1629 .err_handler = &mlx5_err_handler,
1630 .sriov_configure = mlx5_core_sriov_configure,
1631 };
1632
mlx5_core_verify_params(void)1633 static void mlx5_core_verify_params(void)
1634 {
1635 if (prof_sel >= ARRAY_SIZE(profile)) {
1636 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1637 prof_sel,
1638 ARRAY_SIZE(profile) - 1,
1639 MLX5_DEFAULT_PROF);
1640 prof_sel = MLX5_DEFAULT_PROF;
1641 }
1642 }
1643
mlx5_init(void)1644 static int __init mlx5_init(void)
1645 {
1646 int err;
1647
1648 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
1649 "mlx5_core name not in sync with kernel module name");
1650
1651 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1652
1653 mlx5_core_verify_params();
1654 mlx5_fpga_ipsec_build_fs_cmds();
1655 mlx5_register_debugfs();
1656
1657 err = pci_register_driver(&mlx5_core_driver);
1658 if (err)
1659 goto err_debug;
1660
1661 #ifdef CONFIG_MLX5_CORE_EN
1662 mlx5e_init();
1663 #endif
1664
1665 return 0;
1666
1667 err_debug:
1668 mlx5_unregister_debugfs();
1669 return err;
1670 }
1671
mlx5_cleanup(void)1672 static void __exit mlx5_cleanup(void)
1673 {
1674 #ifdef CONFIG_MLX5_CORE_EN
1675 mlx5e_cleanup();
1676 #endif
1677 pci_unregister_driver(&mlx5_core_driver);
1678 mlx5_unregister_debugfs();
1679 }
1680
1681 module_init(mlx5_init);
1682 module_exit(mlx5_cleanup);
1683