1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015-2016 MediaTek Inc.
4 * Author: Yong Wu <yong.wu@mediatek.com>
5 */
6 #include <linux/clk.h>
7 #include <linux/component.h>
8 #include <linux/device.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_platform.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <soc/mediatek/smi.h>
17 #include <dt-bindings/memory/mt2701-larb-port.h>
18 #include <dt-bindings/memory/mtk-memory-port.h>
19
20 /* mt8173 */
21 #define SMI_LARB_MMU_EN 0xf00
22
23 /* mt8167 */
24 #define MT8167_SMI_LARB_MMU_EN 0xfc0
25
26 /* mt2701 */
27 #define REG_SMI_SECUR_CON_BASE 0x5c0
28
29 /* every register control 8 port, register offset 0x4 */
30 #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
31 #define REG_SMI_SECUR_CON_ADDR(id) \
32 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
33
34 /*
35 * every port have 4 bit to control, bit[port + 3] control virtual or physical,
36 * bit[port + 2 : port + 1] control the domain, bit[port] control the security
37 * or non-security.
38 */
39 #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
40 #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
41 /* mt2701 domain should be set to 3 */
42 #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
43
44 /* mt2712 */
45 #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
46 #define F_MMU_EN BIT(0)
47 #define BANK_SEL(id) ({ \
48 u32 _id = (id) & 0x3; \
49 (_id << 8 | _id << 10 | _id << 12 | _id << 14); \
50 })
51
52 /* SMI COMMON */
53 #define SMI_BUS_SEL 0x220
54 #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
55 /* All are MMU0 defaultly. Only specialize mmu1 here. */
56 #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
57
58 enum mtk_smi_gen {
59 MTK_SMI_GEN1,
60 MTK_SMI_GEN2
61 };
62
63 struct mtk_smi_common_plat {
64 enum mtk_smi_gen gen;
65 bool has_gals;
66 u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
67 };
68
69 struct mtk_smi_larb_gen {
70 int port_in_larb[MTK_LARB_NR_MAX + 1];
71 void (*config_port)(struct device *dev);
72 unsigned int larb_direct_to_common_mask;
73 bool has_gals;
74 };
75
76 struct mtk_smi {
77 struct device *dev;
78 struct clk *clk_apb, *clk_smi;
79 struct clk *clk_gals0, *clk_gals1;
80 struct clk *clk_async; /*only needed by mt2701*/
81 union {
82 void __iomem *smi_ao_base; /* only for gen1 */
83 void __iomem *base; /* only for gen2 */
84 };
85 const struct mtk_smi_common_plat *plat;
86 };
87
88 struct mtk_smi_larb { /* larb: local arbiter */
89 struct mtk_smi smi;
90 void __iomem *base;
91 struct device *smi_common_dev;
92 const struct mtk_smi_larb_gen *larb_gen;
93 int larbid;
94 u32 *mmu;
95 unsigned char *bank;
96 };
97
mtk_smi_clk_enable(const struct mtk_smi * smi)98 static int mtk_smi_clk_enable(const struct mtk_smi *smi)
99 {
100 int ret;
101
102 ret = clk_prepare_enable(smi->clk_apb);
103 if (ret)
104 return ret;
105
106 ret = clk_prepare_enable(smi->clk_smi);
107 if (ret)
108 goto err_disable_apb;
109
110 ret = clk_prepare_enable(smi->clk_gals0);
111 if (ret)
112 goto err_disable_smi;
113
114 ret = clk_prepare_enable(smi->clk_gals1);
115 if (ret)
116 goto err_disable_gals0;
117
118 return 0;
119
120 err_disable_gals0:
121 clk_disable_unprepare(smi->clk_gals0);
122 err_disable_smi:
123 clk_disable_unprepare(smi->clk_smi);
124 err_disable_apb:
125 clk_disable_unprepare(smi->clk_apb);
126 return ret;
127 }
128
mtk_smi_clk_disable(const struct mtk_smi * smi)129 static void mtk_smi_clk_disable(const struct mtk_smi *smi)
130 {
131 clk_disable_unprepare(smi->clk_gals1);
132 clk_disable_unprepare(smi->clk_gals0);
133 clk_disable_unprepare(smi->clk_smi);
134 clk_disable_unprepare(smi->clk_apb);
135 }
136
mtk_smi_larb_get(struct device * larbdev)137 int mtk_smi_larb_get(struct device *larbdev)
138 {
139 int ret = pm_runtime_resume_and_get(larbdev);
140
141 return (ret < 0) ? ret : 0;
142 }
143 EXPORT_SYMBOL_GPL(mtk_smi_larb_get);
144
mtk_smi_larb_put(struct device * larbdev)145 void mtk_smi_larb_put(struct device *larbdev)
146 {
147 pm_runtime_put_sync(larbdev);
148 }
149 EXPORT_SYMBOL_GPL(mtk_smi_larb_put);
150
151 static int
mtk_smi_larb_bind(struct device * dev,struct device * master,void * data)152 mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
153 {
154 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
155 struct mtk_smi_larb_iommu *larb_mmu = data;
156 unsigned int i;
157
158 for (i = 0; i < MTK_LARB_NR_MAX; i++) {
159 if (dev == larb_mmu[i].dev) {
160 larb->larbid = i;
161 larb->mmu = &larb_mmu[i].mmu;
162 larb->bank = larb_mmu[i].bank;
163 return 0;
164 }
165 }
166 return -ENODEV;
167 }
168
mtk_smi_larb_config_port_gen2_general(struct device * dev)169 static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
170 {
171 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
172 u32 reg;
173 int i;
174
175 if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
176 return;
177
178 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
179 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
180 reg |= F_MMU_EN;
181 reg |= BANK_SEL(larb->bank[i]);
182 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
183 }
184 }
185
mtk_smi_larb_config_port_mt8173(struct device * dev)186 static void mtk_smi_larb_config_port_mt8173(struct device *dev)
187 {
188 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
189
190 writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
191 }
192
mtk_smi_larb_config_port_mt8167(struct device * dev)193 static void mtk_smi_larb_config_port_mt8167(struct device *dev)
194 {
195 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
196
197 writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
198 }
199
mtk_smi_larb_config_port_gen1(struct device * dev)200 static void mtk_smi_larb_config_port_gen1(struct device *dev)
201 {
202 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
203 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
204 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
205 int i, m4u_port_id, larb_port_num;
206 u32 sec_con_val, reg_val;
207
208 m4u_port_id = larb_gen->port_in_larb[larb->larbid];
209 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
210 - larb_gen->port_in_larb[larb->larbid];
211
212 for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
213 if (*larb->mmu & BIT(i)) {
214 /* bit[port + 3] controls the virtual or physical */
215 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
216 } else {
217 /* do not need to enable m4u for this port */
218 continue;
219 }
220 reg_val = readl(common->smi_ao_base
221 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
222 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
223 reg_val |= sec_con_val;
224 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
225 writel(reg_val,
226 common->smi_ao_base
227 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
228 }
229 }
230
231 static void
mtk_smi_larb_unbind(struct device * dev,struct device * master,void * data)232 mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
233 {
234 /* Do nothing as the iommu is always enabled. */
235 }
236
237 static const struct component_ops mtk_smi_larb_component_ops = {
238 .bind = mtk_smi_larb_bind,
239 .unbind = mtk_smi_larb_unbind,
240 };
241
242 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
243 /* mt8173 do not need the port in larb */
244 .config_port = mtk_smi_larb_config_port_mt8173,
245 };
246
247 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = {
248 /* mt8167 do not need the port in larb */
249 .config_port = mtk_smi_larb_config_port_mt8167,
250 };
251
252 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
253 .port_in_larb = {
254 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
255 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
256 },
257 .config_port = mtk_smi_larb_config_port_gen1,
258 };
259
260 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
261 .config_port = mtk_smi_larb_config_port_gen2_general,
262 .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
263 };
264
265 static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = {
266 .config_port = mtk_smi_larb_config_port_gen2_general,
267 .larb_direct_to_common_mask =
268 BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13),
269 /* DUMMY | IPU0 | IPU1 | CCU | MDLA */
270 };
271
272 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
273 .has_gals = true,
274 .config_port = mtk_smi_larb_config_port_gen2_general,
275 .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
276 /* IPU0 | IPU1 | CCU */
277 };
278
279 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
280 .config_port = mtk_smi_larb_config_port_gen2_general,
281 };
282
283 static const struct of_device_id mtk_smi_larb_of_ids[] = {
284 {
285 .compatible = "mediatek,mt8167-smi-larb",
286 .data = &mtk_smi_larb_mt8167
287 },
288 {
289 .compatible = "mediatek,mt8173-smi-larb",
290 .data = &mtk_smi_larb_mt8173
291 },
292 {
293 .compatible = "mediatek,mt2701-smi-larb",
294 .data = &mtk_smi_larb_mt2701
295 },
296 {
297 .compatible = "mediatek,mt2712-smi-larb",
298 .data = &mtk_smi_larb_mt2712
299 },
300 {
301 .compatible = "mediatek,mt6779-smi-larb",
302 .data = &mtk_smi_larb_mt6779
303 },
304 {
305 .compatible = "mediatek,mt8183-smi-larb",
306 .data = &mtk_smi_larb_mt8183
307 },
308 {
309 .compatible = "mediatek,mt8192-smi-larb",
310 .data = &mtk_smi_larb_mt8192
311 },
312 {}
313 };
314
mtk_smi_larb_probe(struct platform_device * pdev)315 static int mtk_smi_larb_probe(struct platform_device *pdev)
316 {
317 struct mtk_smi_larb *larb;
318 struct resource *res;
319 struct device *dev = &pdev->dev;
320 struct device_node *smi_node;
321 struct platform_device *smi_pdev;
322
323 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
324 if (!larb)
325 return -ENOMEM;
326
327 larb->larb_gen = of_device_get_match_data(dev);
328 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
329 larb->base = devm_ioremap_resource(dev, res);
330 if (IS_ERR(larb->base))
331 return PTR_ERR(larb->base);
332
333 larb->smi.clk_apb = devm_clk_get(dev, "apb");
334 if (IS_ERR(larb->smi.clk_apb))
335 return PTR_ERR(larb->smi.clk_apb);
336
337 larb->smi.clk_smi = devm_clk_get(dev, "smi");
338 if (IS_ERR(larb->smi.clk_smi))
339 return PTR_ERR(larb->smi.clk_smi);
340
341 if (larb->larb_gen->has_gals) {
342 /* The larbs may still haven't gals even if the SoC support.*/
343 larb->smi.clk_gals0 = devm_clk_get(dev, "gals");
344 if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT)
345 larb->smi.clk_gals0 = NULL;
346 else if (IS_ERR(larb->smi.clk_gals0))
347 return PTR_ERR(larb->smi.clk_gals0);
348 }
349 larb->smi.dev = dev;
350
351 smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
352 if (!smi_node)
353 return -EINVAL;
354
355 smi_pdev = of_find_device_by_node(smi_node);
356 of_node_put(smi_node);
357 if (smi_pdev) {
358 if (!platform_get_drvdata(smi_pdev))
359 return -EPROBE_DEFER;
360 larb->smi_common_dev = &smi_pdev->dev;
361 } else {
362 dev_err(dev, "Failed to get the smi_common device\n");
363 return -EINVAL;
364 }
365
366 pm_runtime_enable(dev);
367 platform_set_drvdata(pdev, larb);
368 return component_add(dev, &mtk_smi_larb_component_ops);
369 }
370
mtk_smi_larb_remove(struct platform_device * pdev)371 static int mtk_smi_larb_remove(struct platform_device *pdev)
372 {
373 pm_runtime_disable(&pdev->dev);
374 component_del(&pdev->dev, &mtk_smi_larb_component_ops);
375 return 0;
376 }
377
mtk_smi_larb_resume(struct device * dev)378 static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
379 {
380 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
381 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
382 int ret;
383
384 /* Power on smi-common. */
385 ret = pm_runtime_resume_and_get(larb->smi_common_dev);
386 if (ret < 0) {
387 dev_err(dev, "Failed to pm get for smi-common(%d).\n", ret);
388 return ret;
389 }
390
391 ret = mtk_smi_clk_enable(&larb->smi);
392 if (ret < 0) {
393 dev_err(dev, "Failed to enable clock(%d).\n", ret);
394 pm_runtime_put_sync(larb->smi_common_dev);
395 return ret;
396 }
397
398 /* Configure the basic setting for this larb */
399 larb_gen->config_port(dev);
400
401 return 0;
402 }
403
mtk_smi_larb_suspend(struct device * dev)404 static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
405 {
406 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
407
408 mtk_smi_clk_disable(&larb->smi);
409 pm_runtime_put_sync(larb->smi_common_dev);
410 return 0;
411 }
412
413 static const struct dev_pm_ops smi_larb_pm_ops = {
414 SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
415 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
416 pm_runtime_force_resume)
417 };
418
419 static struct platform_driver mtk_smi_larb_driver = {
420 .probe = mtk_smi_larb_probe,
421 .remove = mtk_smi_larb_remove,
422 .driver = {
423 .name = "mtk-smi-larb",
424 .of_match_table = mtk_smi_larb_of_ids,
425 .pm = &smi_larb_pm_ops,
426 }
427 };
428
429 static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
430 .gen = MTK_SMI_GEN1,
431 };
432
433 static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
434 .gen = MTK_SMI_GEN2,
435 };
436
437 static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = {
438 .gen = MTK_SMI_GEN2,
439 .has_gals = true,
440 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) |
441 F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7),
442 };
443
444 static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
445 .gen = MTK_SMI_GEN2,
446 .has_gals = true,
447 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
448 F_MMU1_LARB(7),
449 };
450
451 static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
452 .gen = MTK_SMI_GEN2,
453 .has_gals = true,
454 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
455 F_MMU1_LARB(6),
456 };
457
458 static const struct of_device_id mtk_smi_common_of_ids[] = {
459 {
460 .compatible = "mediatek,mt8173-smi-common",
461 .data = &mtk_smi_common_gen2,
462 },
463 {
464 .compatible = "mediatek,mt8167-smi-common",
465 .data = &mtk_smi_common_gen2,
466 },
467 {
468 .compatible = "mediatek,mt2701-smi-common",
469 .data = &mtk_smi_common_gen1,
470 },
471 {
472 .compatible = "mediatek,mt2712-smi-common",
473 .data = &mtk_smi_common_gen2,
474 },
475 {
476 .compatible = "mediatek,mt6779-smi-common",
477 .data = &mtk_smi_common_mt6779,
478 },
479 {
480 .compatible = "mediatek,mt8183-smi-common",
481 .data = &mtk_smi_common_mt8183,
482 },
483 {
484 .compatible = "mediatek,mt8192-smi-common",
485 .data = &mtk_smi_common_mt8192,
486 },
487 {}
488 };
489
mtk_smi_common_probe(struct platform_device * pdev)490 static int mtk_smi_common_probe(struct platform_device *pdev)
491 {
492 struct device *dev = &pdev->dev;
493 struct mtk_smi *common;
494 struct resource *res;
495 int ret;
496
497 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
498 if (!common)
499 return -ENOMEM;
500 common->dev = dev;
501 common->plat = of_device_get_match_data(dev);
502
503 common->clk_apb = devm_clk_get(dev, "apb");
504 if (IS_ERR(common->clk_apb))
505 return PTR_ERR(common->clk_apb);
506
507 common->clk_smi = devm_clk_get(dev, "smi");
508 if (IS_ERR(common->clk_smi))
509 return PTR_ERR(common->clk_smi);
510
511 if (common->plat->has_gals) {
512 common->clk_gals0 = devm_clk_get(dev, "gals0");
513 if (IS_ERR(common->clk_gals0))
514 return PTR_ERR(common->clk_gals0);
515
516 common->clk_gals1 = devm_clk_get(dev, "gals1");
517 if (IS_ERR(common->clk_gals1))
518 return PTR_ERR(common->clk_gals1);
519 }
520
521 /*
522 * for mtk smi gen 1, we need to get the ao(always on) base to config
523 * m4u port, and we need to enable the aync clock for transform the smi
524 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
525 * base.
526 */
527 if (common->plat->gen == MTK_SMI_GEN1) {
528 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
529 common->smi_ao_base = devm_ioremap_resource(dev, res);
530 if (IS_ERR(common->smi_ao_base))
531 return PTR_ERR(common->smi_ao_base);
532
533 common->clk_async = devm_clk_get(dev, "async");
534 if (IS_ERR(common->clk_async))
535 return PTR_ERR(common->clk_async);
536
537 ret = clk_prepare_enable(common->clk_async);
538 if (ret)
539 return ret;
540 } else {
541 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
542 common->base = devm_ioremap_resource(dev, res);
543 if (IS_ERR(common->base))
544 return PTR_ERR(common->base);
545 }
546 pm_runtime_enable(dev);
547 platform_set_drvdata(pdev, common);
548 return 0;
549 }
550
mtk_smi_common_remove(struct platform_device * pdev)551 static int mtk_smi_common_remove(struct platform_device *pdev)
552 {
553 pm_runtime_disable(&pdev->dev);
554 return 0;
555 }
556
mtk_smi_common_resume(struct device * dev)557 static int __maybe_unused mtk_smi_common_resume(struct device *dev)
558 {
559 struct mtk_smi *common = dev_get_drvdata(dev);
560 u32 bus_sel = common->plat->bus_sel;
561 int ret;
562
563 ret = mtk_smi_clk_enable(common);
564 if (ret) {
565 dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
566 return ret;
567 }
568
569 if (common->plat->gen == MTK_SMI_GEN2 && bus_sel)
570 writel(bus_sel, common->base + SMI_BUS_SEL);
571 return 0;
572 }
573
mtk_smi_common_suspend(struct device * dev)574 static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
575 {
576 struct mtk_smi *common = dev_get_drvdata(dev);
577
578 mtk_smi_clk_disable(common);
579 return 0;
580 }
581
582 static const struct dev_pm_ops smi_common_pm_ops = {
583 SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
584 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
585 pm_runtime_force_resume)
586 };
587
588 static struct platform_driver mtk_smi_common_driver = {
589 .probe = mtk_smi_common_probe,
590 .remove = mtk_smi_common_remove,
591 .driver = {
592 .name = "mtk-smi-common",
593 .of_match_table = mtk_smi_common_of_ids,
594 .pm = &smi_common_pm_ops,
595 }
596 };
597
598 static struct platform_driver * const smidrivers[] = {
599 &mtk_smi_common_driver,
600 &mtk_smi_larb_driver,
601 };
602
mtk_smi_init(void)603 static int __init mtk_smi_init(void)
604 {
605 return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers));
606 }
607 module_init(mtk_smi_init);
608
mtk_smi_exit(void)609 static void __exit mtk_smi_exit(void)
610 {
611 platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers));
612 }
613 module_exit(mtk_smi_exit);
614
615 MODULE_DESCRIPTION("MediaTek SMI driver");
616 MODULE_LICENSE("GPL v2");
617