1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Intel IO-APIC support for multi-Pentium hosts.
4 *
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 *
7 * Many thanks to Stig Venaas for trying out countless experimental
8 * patches and reporting/debugging problems patiently!
9 *
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13 * further tested and cleaned up by Zach Brown <zab@redhat.com>
14 * and Ingo Molnar <mingo@redhat.com>
15 *
16 * Fixes
17 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
18 * thanks to Eric Gilmore
19 * and Rolf G. Tews
20 * for testing these extensively
21 * Paul Diefenbaugh : Added full ACPI support
22 *
23 * Historical information which is worth to be preserved:
24 *
25 * - SiS APIC rmw bug:
26 *
27 * We used to have a workaround for a bug in SiS chips which
28 * required to rewrite the index register for a read-modify-write
29 * operation as the chip lost the index information which was
30 * setup for the read already. We cache the data now, so that
31 * workaround has been removed.
32 */
33
34 #include <linux/mm.h>
35 #include <linux/interrupt.h>
36 #include <linux/irq.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/pci.h>
41 #include <linux/mc146818rtc.h>
42 #include <linux/compiler.h>
43 #include <linux/acpi.h>
44 #include <linux/export.h>
45 #include <linux/syscore_ops.h>
46 #include <linux/freezer.h>
47 #include <linux/kthread.h>
48 #include <linux/jiffies.h> /* time_after() */
49 #include <linux/slab.h>
50 #include <linux/memblock.h>
51
52 #include <asm/irqdomain.h>
53 #include <asm/io.h>
54 #include <asm/smp.h>
55 #include <asm/cpu.h>
56 #include <asm/desc.h>
57 #include <asm/proto.h>
58 #include <asm/acpi.h>
59 #include <asm/dma.h>
60 #include <asm/timer.h>
61 #include <asm/time.h>
62 #include <asm/i8259.h>
63 #include <asm/setup.h>
64 #include <asm/irq_remapping.h>
65 #include <asm/hw_irq.h>
66
67 #include <asm/apic.h>
68
69 #define for_each_ioapic(idx) \
70 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
71 #define for_each_ioapic_reverse(idx) \
72 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
73 #define for_each_pin(idx, pin) \
74 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
75 #define for_each_ioapic_pin(idx, pin) \
76 for_each_ioapic((idx)) \
77 for_each_pin((idx), (pin))
78 #define for_each_irq_pin(entry, head) \
79 list_for_each_entry(entry, &head, list)
80
81 static DEFINE_RAW_SPINLOCK(ioapic_lock);
82 static DEFINE_MUTEX(ioapic_mutex);
83 static unsigned int ioapic_dynirq_base;
84 static int ioapic_initialized;
85
86 struct irq_pin_list {
87 struct list_head list;
88 int apic, pin;
89 };
90
91 struct mp_chip_data {
92 struct list_head irq_2_pin;
93 struct IO_APIC_route_entry entry;
94 int trigger;
95 int polarity;
96 u32 count;
97 bool isa_irq;
98 };
99
100 struct mp_ioapic_gsi {
101 u32 gsi_base;
102 u32 gsi_end;
103 };
104
105 static struct ioapic {
106 /*
107 * # of IRQ routing registers
108 */
109 int nr_registers;
110 /*
111 * Saved state during suspend/resume, or while enabling intr-remap.
112 */
113 struct IO_APIC_route_entry *saved_registers;
114 /* I/O APIC config */
115 struct mpc_ioapic mp_config;
116 /* IO APIC gsi routing info */
117 struct mp_ioapic_gsi gsi_config;
118 struct ioapic_domain_cfg irqdomain_cfg;
119 struct irq_domain *irqdomain;
120 struct resource *iomem_res;
121 } ioapics[MAX_IO_APICS];
122
123 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
124
mpc_ioapic_id(int ioapic_idx)125 int mpc_ioapic_id(int ioapic_idx)
126 {
127 return ioapics[ioapic_idx].mp_config.apicid;
128 }
129
mpc_ioapic_addr(int ioapic_idx)130 unsigned int mpc_ioapic_addr(int ioapic_idx)
131 {
132 return ioapics[ioapic_idx].mp_config.apicaddr;
133 }
134
mp_ioapic_gsi_routing(int ioapic_idx)135 static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
136 {
137 return &ioapics[ioapic_idx].gsi_config;
138 }
139
mp_ioapic_pin_count(int ioapic)140 static inline int mp_ioapic_pin_count(int ioapic)
141 {
142 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
143
144 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
145 }
146
mp_pin_to_gsi(int ioapic,int pin)147 static inline u32 mp_pin_to_gsi(int ioapic, int pin)
148 {
149 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
150 }
151
mp_is_legacy_irq(int irq)152 static inline bool mp_is_legacy_irq(int irq)
153 {
154 return irq >= 0 && irq < nr_legacy_irqs();
155 }
156
mp_ioapic_irqdomain(int ioapic)157 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
158 {
159 return ioapics[ioapic].irqdomain;
160 }
161
162 int nr_ioapics;
163
164 /* The one past the highest gsi number used */
165 u32 gsi_top;
166
167 /* MP IRQ source entries */
168 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
169
170 /* # of MP IRQ source entries */
171 int mp_irq_entries;
172
173 #ifdef CONFIG_EISA
174 int mp_bus_id_to_type[MAX_MP_BUSSES];
175 #endif
176
177 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
178
179 int skip_ioapic_setup;
180
181 /**
182 * disable_ioapic_support() - disables ioapic support at runtime
183 */
disable_ioapic_support(void)184 void disable_ioapic_support(void)
185 {
186 #ifdef CONFIG_PCI
187 noioapicquirk = 1;
188 noioapicreroute = -1;
189 #endif
190 skip_ioapic_setup = 1;
191 }
192
parse_noapic(char * str)193 static int __init parse_noapic(char *str)
194 {
195 /* disable IO-APIC */
196 disable_ioapic_support();
197 return 0;
198 }
199 early_param("noapic", parse_noapic);
200
201 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
mp_save_irq(struct mpc_intsrc * m)202 void mp_save_irq(struct mpc_intsrc *m)
203 {
204 int i;
205
206 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
207 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
208 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
209 m->srcbusirq, m->dstapic, m->dstirq);
210
211 for (i = 0; i < mp_irq_entries; i++) {
212 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
213 return;
214 }
215
216 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
217 if (++mp_irq_entries == MAX_IRQ_SOURCES)
218 panic("Max # of irq sources exceeded!!\n");
219 }
220
alloc_ioapic_saved_registers(int idx)221 static void alloc_ioapic_saved_registers(int idx)
222 {
223 size_t size;
224
225 if (ioapics[idx].saved_registers)
226 return;
227
228 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
229 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
230 if (!ioapics[idx].saved_registers)
231 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
232 }
233
free_ioapic_saved_registers(int idx)234 static void free_ioapic_saved_registers(int idx)
235 {
236 kfree(ioapics[idx].saved_registers);
237 ioapics[idx].saved_registers = NULL;
238 }
239
arch_early_ioapic_init(void)240 int __init arch_early_ioapic_init(void)
241 {
242 int i;
243
244 if (!nr_legacy_irqs())
245 io_apic_irqs = ~0UL;
246
247 for_each_ioapic(i)
248 alloc_ioapic_saved_registers(i);
249
250 return 0;
251 }
252
253 struct io_apic {
254 unsigned int index;
255 unsigned int unused[3];
256 unsigned int data;
257 unsigned int unused2[11];
258 unsigned int eoi;
259 };
260
io_apic_base(int idx)261 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
262 {
263 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
264 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
265 }
266
io_apic_eoi(unsigned int apic,unsigned int vector)267 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
268 {
269 struct io_apic __iomem *io_apic = io_apic_base(apic);
270 writel(vector, &io_apic->eoi);
271 }
272
native_io_apic_read(unsigned int apic,unsigned int reg)273 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
274 {
275 struct io_apic __iomem *io_apic = io_apic_base(apic);
276 writel(reg, &io_apic->index);
277 return readl(&io_apic->data);
278 }
279
io_apic_write(unsigned int apic,unsigned int reg,unsigned int value)280 static void io_apic_write(unsigned int apic, unsigned int reg,
281 unsigned int value)
282 {
283 struct io_apic __iomem *io_apic = io_apic_base(apic);
284
285 writel(reg, &io_apic->index);
286 writel(value, &io_apic->data);
287 }
288
289 union entry_union {
290 struct { u32 w1, w2; };
291 struct IO_APIC_route_entry entry;
292 };
293
__ioapic_read_entry(int apic,int pin)294 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
295 {
296 union entry_union eu;
297
298 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
299 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
300
301 return eu.entry;
302 }
303
ioapic_read_entry(int apic,int pin)304 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
305 {
306 union entry_union eu;
307 unsigned long flags;
308
309 raw_spin_lock_irqsave(&ioapic_lock, flags);
310 eu.entry = __ioapic_read_entry(apic, pin);
311 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
312
313 return eu.entry;
314 }
315
316 /*
317 * When we write a new IO APIC routing entry, we need to write the high
318 * word first! If the mask bit in the low word is clear, we will enable
319 * the interrupt, and we need to make sure the entry is fully populated
320 * before that happens.
321 */
__ioapic_write_entry(int apic,int pin,struct IO_APIC_route_entry e)322 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
323 {
324 union entry_union eu = {{0, 0}};
325
326 eu.entry = e;
327 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
328 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
329 }
330
ioapic_write_entry(int apic,int pin,struct IO_APIC_route_entry e)331 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
332 {
333 unsigned long flags;
334
335 raw_spin_lock_irqsave(&ioapic_lock, flags);
336 __ioapic_write_entry(apic, pin, e);
337 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
338 }
339
340 /*
341 * When we mask an IO APIC routing entry, we need to write the low
342 * word first, in order to set the mask bit before we change the
343 * high bits!
344 */
ioapic_mask_entry(int apic,int pin)345 static void ioapic_mask_entry(int apic, int pin)
346 {
347 unsigned long flags;
348 union entry_union eu = { .entry.mask = IOAPIC_MASKED };
349
350 raw_spin_lock_irqsave(&ioapic_lock, flags);
351 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
352 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
353 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
354 }
355
356 /*
357 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
358 * shared ISA-space IRQs, so we have to support them. We are super
359 * fast in the common case, and fast for shared ISA-space IRQs.
360 */
__add_pin_to_irq_node(struct mp_chip_data * data,int node,int apic,int pin)361 static int __add_pin_to_irq_node(struct mp_chip_data *data,
362 int node, int apic, int pin)
363 {
364 struct irq_pin_list *entry;
365
366 /* don't allow duplicates */
367 for_each_irq_pin(entry, data->irq_2_pin)
368 if (entry->apic == apic && entry->pin == pin)
369 return 0;
370
371 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
372 if (!entry) {
373 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
374 node, apic, pin);
375 return -ENOMEM;
376 }
377 entry->apic = apic;
378 entry->pin = pin;
379 list_add_tail(&entry->list, &data->irq_2_pin);
380
381 return 0;
382 }
383
__remove_pin_from_irq(struct mp_chip_data * data,int apic,int pin)384 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
385 {
386 struct irq_pin_list *tmp, *entry;
387
388 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
389 if (entry->apic == apic && entry->pin == pin) {
390 list_del(&entry->list);
391 kfree(entry);
392 return;
393 }
394 }
395
add_pin_to_irq_node(struct mp_chip_data * data,int node,int apic,int pin)396 static void add_pin_to_irq_node(struct mp_chip_data *data,
397 int node, int apic, int pin)
398 {
399 if (__add_pin_to_irq_node(data, node, apic, pin))
400 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
401 }
402
403 /*
404 * Reroute an IRQ to a different pin.
405 */
replace_pin_at_irq_node(struct mp_chip_data * data,int node,int oldapic,int oldpin,int newapic,int newpin)406 static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
407 int oldapic, int oldpin,
408 int newapic, int newpin)
409 {
410 struct irq_pin_list *entry;
411
412 for_each_irq_pin(entry, data->irq_2_pin) {
413 if (entry->apic == oldapic && entry->pin == oldpin) {
414 entry->apic = newapic;
415 entry->pin = newpin;
416 /* every one is different, right? */
417 return;
418 }
419 }
420
421 /* old apic/pin didn't exist, so just add new ones */
422 add_pin_to_irq_node(data, node, newapic, newpin);
423 }
424
io_apic_modify_irq(struct mp_chip_data * data,int mask_and,int mask_or,void (* final)(struct irq_pin_list * entry))425 static void io_apic_modify_irq(struct mp_chip_data *data,
426 int mask_and, int mask_or,
427 void (*final)(struct irq_pin_list *entry))
428 {
429 union entry_union eu;
430 struct irq_pin_list *entry;
431
432 eu.entry = data->entry;
433 eu.w1 &= mask_and;
434 eu.w1 |= mask_or;
435 data->entry = eu.entry;
436
437 for_each_irq_pin(entry, data->irq_2_pin) {
438 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1);
439 if (final)
440 final(entry);
441 }
442 }
443
io_apic_sync(struct irq_pin_list * entry)444 static void io_apic_sync(struct irq_pin_list *entry)
445 {
446 /*
447 * Synchronize the IO-APIC and the CPU by doing
448 * a dummy read from the IO-APIC
449 */
450 struct io_apic __iomem *io_apic;
451
452 io_apic = io_apic_base(entry->apic);
453 readl(&io_apic->data);
454 }
455
mask_ioapic_irq(struct irq_data * irq_data)456 static void mask_ioapic_irq(struct irq_data *irq_data)
457 {
458 struct mp_chip_data *data = irq_data->chip_data;
459 unsigned long flags;
460
461 raw_spin_lock_irqsave(&ioapic_lock, flags);
462 io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
463 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
464 }
465
__unmask_ioapic(struct mp_chip_data * data)466 static void __unmask_ioapic(struct mp_chip_data *data)
467 {
468 io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL);
469 }
470
unmask_ioapic_irq(struct irq_data * irq_data)471 static void unmask_ioapic_irq(struct irq_data *irq_data)
472 {
473 struct mp_chip_data *data = irq_data->chip_data;
474 unsigned long flags;
475
476 raw_spin_lock_irqsave(&ioapic_lock, flags);
477 __unmask_ioapic(data);
478 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
479 }
480
481 /*
482 * IO-APIC versions below 0x20 don't support EOI register.
483 * For the record, here is the information about various versions:
484 * 0Xh 82489DX
485 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
486 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
487 * 30h-FFh Reserved
488 *
489 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
490 * version as 0x2. This is an error with documentation and these ICH chips
491 * use io-apic's of version 0x20.
492 *
493 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
494 * Otherwise, we simulate the EOI message manually by changing the trigger
495 * mode to edge and then back to level, with RTE being masked during this.
496 */
__eoi_ioapic_pin(int apic,int pin,int vector)497 static void __eoi_ioapic_pin(int apic, int pin, int vector)
498 {
499 if (mpc_ioapic_ver(apic) >= 0x20) {
500 io_apic_eoi(apic, vector);
501 } else {
502 struct IO_APIC_route_entry entry, entry1;
503
504 entry = entry1 = __ioapic_read_entry(apic, pin);
505
506 /*
507 * Mask the entry and change the trigger mode to edge.
508 */
509 entry1.mask = IOAPIC_MASKED;
510 entry1.trigger = IOAPIC_EDGE;
511
512 __ioapic_write_entry(apic, pin, entry1);
513
514 /*
515 * Restore the previous level triggered entry.
516 */
517 __ioapic_write_entry(apic, pin, entry);
518 }
519 }
520
eoi_ioapic_pin(int vector,struct mp_chip_data * data)521 static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
522 {
523 unsigned long flags;
524 struct irq_pin_list *entry;
525
526 raw_spin_lock_irqsave(&ioapic_lock, flags);
527 for_each_irq_pin(entry, data->irq_2_pin)
528 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
529 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
530 }
531
clear_IO_APIC_pin(unsigned int apic,unsigned int pin)532 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
533 {
534 struct IO_APIC_route_entry entry;
535
536 /* Check delivery_mode to be sure we're not clearing an SMI pin */
537 entry = ioapic_read_entry(apic, pin);
538 if (entry.delivery_mode == dest_SMI)
539 return;
540
541 /*
542 * Make sure the entry is masked and re-read the contents to check
543 * if it is a level triggered pin and if the remote-IRR is set.
544 */
545 if (entry.mask == IOAPIC_UNMASKED) {
546 entry.mask = IOAPIC_MASKED;
547 ioapic_write_entry(apic, pin, entry);
548 entry = ioapic_read_entry(apic, pin);
549 }
550
551 if (entry.irr) {
552 unsigned long flags;
553
554 /*
555 * Make sure the trigger mode is set to level. Explicit EOI
556 * doesn't clear the remote-IRR if the trigger mode is not
557 * set to level.
558 */
559 if (entry.trigger == IOAPIC_EDGE) {
560 entry.trigger = IOAPIC_LEVEL;
561 ioapic_write_entry(apic, pin, entry);
562 }
563 raw_spin_lock_irqsave(&ioapic_lock, flags);
564 __eoi_ioapic_pin(apic, pin, entry.vector);
565 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
566 }
567
568 /*
569 * Clear the rest of the bits in the IO-APIC RTE except for the mask
570 * bit.
571 */
572 ioapic_mask_entry(apic, pin);
573 entry = ioapic_read_entry(apic, pin);
574 if (entry.irr)
575 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
576 mpc_ioapic_id(apic), pin);
577 }
578
clear_IO_APIC(void)579 void clear_IO_APIC (void)
580 {
581 int apic, pin;
582
583 for_each_ioapic_pin(apic, pin)
584 clear_IO_APIC_pin(apic, pin);
585 }
586
587 #ifdef CONFIG_X86_32
588 /*
589 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
590 * specific CPU-side IRQs.
591 */
592
593 #define MAX_PIRQS 8
594 static int pirq_entries[MAX_PIRQS] = {
595 [0 ... MAX_PIRQS - 1] = -1
596 };
597
ioapic_pirq_setup(char * str)598 static int __init ioapic_pirq_setup(char *str)
599 {
600 int i, max;
601 int ints[MAX_PIRQS+1];
602
603 get_options(str, ARRAY_SIZE(ints), ints);
604
605 apic_printk(APIC_VERBOSE, KERN_INFO
606 "PIRQ redirection, working around broken MP-BIOS.\n");
607 max = MAX_PIRQS;
608 if (ints[0] < MAX_PIRQS)
609 max = ints[0];
610
611 for (i = 0; i < max; i++) {
612 apic_printk(APIC_VERBOSE, KERN_DEBUG
613 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
614 /*
615 * PIRQs are mapped upside down, usually.
616 */
617 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
618 }
619 return 1;
620 }
621
622 __setup("pirq=", ioapic_pirq_setup);
623 #endif /* CONFIG_X86_32 */
624
625 /*
626 * Saves all the IO-APIC RTE's
627 */
save_ioapic_entries(void)628 int save_ioapic_entries(void)
629 {
630 int apic, pin;
631 int err = 0;
632
633 for_each_ioapic(apic) {
634 if (!ioapics[apic].saved_registers) {
635 err = -ENOMEM;
636 continue;
637 }
638
639 for_each_pin(apic, pin)
640 ioapics[apic].saved_registers[pin] =
641 ioapic_read_entry(apic, pin);
642 }
643
644 return err;
645 }
646
647 /*
648 * Mask all IO APIC entries.
649 */
mask_ioapic_entries(void)650 void mask_ioapic_entries(void)
651 {
652 int apic, pin;
653
654 for_each_ioapic(apic) {
655 if (!ioapics[apic].saved_registers)
656 continue;
657
658 for_each_pin(apic, pin) {
659 struct IO_APIC_route_entry entry;
660
661 entry = ioapics[apic].saved_registers[pin];
662 if (entry.mask == IOAPIC_UNMASKED) {
663 entry.mask = IOAPIC_MASKED;
664 ioapic_write_entry(apic, pin, entry);
665 }
666 }
667 }
668 }
669
670 /*
671 * Restore IO APIC entries which was saved in the ioapic structure.
672 */
restore_ioapic_entries(void)673 int restore_ioapic_entries(void)
674 {
675 int apic, pin;
676
677 for_each_ioapic(apic) {
678 if (!ioapics[apic].saved_registers)
679 continue;
680
681 for_each_pin(apic, pin)
682 ioapic_write_entry(apic, pin,
683 ioapics[apic].saved_registers[pin]);
684 }
685 return 0;
686 }
687
688 /*
689 * Find the IRQ entry number of a certain pin.
690 */
find_irq_entry(int ioapic_idx,int pin,int type)691 static int find_irq_entry(int ioapic_idx, int pin, int type)
692 {
693 int i;
694
695 for (i = 0; i < mp_irq_entries; i++)
696 if (mp_irqs[i].irqtype == type &&
697 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
698 mp_irqs[i].dstapic == MP_APIC_ALL) &&
699 mp_irqs[i].dstirq == pin)
700 return i;
701
702 return -1;
703 }
704
705 /*
706 * Find the pin to which IRQ[irq] (ISA) is connected
707 */
find_isa_irq_pin(int irq,int type)708 static int __init find_isa_irq_pin(int irq, int type)
709 {
710 int i;
711
712 for (i = 0; i < mp_irq_entries; i++) {
713 int lbus = mp_irqs[i].srcbus;
714
715 if (test_bit(lbus, mp_bus_not_pci) &&
716 (mp_irqs[i].irqtype == type) &&
717 (mp_irqs[i].srcbusirq == irq))
718
719 return mp_irqs[i].dstirq;
720 }
721 return -1;
722 }
723
find_isa_irq_apic(int irq,int type)724 static int __init find_isa_irq_apic(int irq, int type)
725 {
726 int i;
727
728 for (i = 0; i < mp_irq_entries; i++) {
729 int lbus = mp_irqs[i].srcbus;
730
731 if (test_bit(lbus, mp_bus_not_pci) &&
732 (mp_irqs[i].irqtype == type) &&
733 (mp_irqs[i].srcbusirq == irq))
734 break;
735 }
736
737 if (i < mp_irq_entries) {
738 int ioapic_idx;
739
740 for_each_ioapic(ioapic_idx)
741 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
742 return ioapic_idx;
743 }
744
745 return -1;
746 }
747
748 #ifdef CONFIG_EISA
749 /*
750 * EISA Edge/Level control register, ELCR
751 */
EISA_ELCR(unsigned int irq)752 static int EISA_ELCR(unsigned int irq)
753 {
754 if (irq < nr_legacy_irqs()) {
755 unsigned int port = 0x4d0 + (irq >> 3);
756 return (inb(port) >> (irq & 7)) & 1;
757 }
758 apic_printk(APIC_VERBOSE, KERN_INFO
759 "Broken MPtable reports ISA irq %d\n", irq);
760 return 0;
761 }
762
763 #endif
764
765 /* ISA interrupts are always active high edge triggered,
766 * when listed as conforming in the MP table. */
767
768 #define default_ISA_trigger(idx) (IOAPIC_EDGE)
769 #define default_ISA_polarity(idx) (IOAPIC_POL_HIGH)
770
771 /* EISA interrupts are always polarity zero and can be edge or level
772 * trigger depending on the ELCR value. If an interrupt is listed as
773 * EISA conforming in the MP table, that means its trigger type must
774 * be read in from the ELCR */
775
776 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
777 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
778
779 /* PCI interrupts are always active low level triggered,
780 * when listed as conforming in the MP table. */
781
782 #define default_PCI_trigger(idx) (IOAPIC_LEVEL)
783 #define default_PCI_polarity(idx) (IOAPIC_POL_LOW)
784
irq_polarity(int idx)785 static int irq_polarity(int idx)
786 {
787 int bus = mp_irqs[idx].srcbus;
788
789 /*
790 * Determine IRQ line polarity (high active or low active):
791 */
792 switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
793 case MP_IRQPOL_DEFAULT:
794 /* conforms to spec, ie. bus-type dependent polarity */
795 if (test_bit(bus, mp_bus_not_pci))
796 return default_ISA_polarity(idx);
797 else
798 return default_PCI_polarity(idx);
799 case MP_IRQPOL_ACTIVE_HIGH:
800 return IOAPIC_POL_HIGH;
801 case MP_IRQPOL_RESERVED:
802 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
803 fallthrough;
804 case MP_IRQPOL_ACTIVE_LOW:
805 default: /* Pointless default required due to do gcc stupidity */
806 return IOAPIC_POL_LOW;
807 }
808 }
809
810 #ifdef CONFIG_EISA
eisa_irq_trigger(int idx,int bus,int trigger)811 static int eisa_irq_trigger(int idx, int bus, int trigger)
812 {
813 switch (mp_bus_id_to_type[bus]) {
814 case MP_BUS_PCI:
815 case MP_BUS_ISA:
816 return trigger;
817 case MP_BUS_EISA:
818 return default_EISA_trigger(idx);
819 }
820 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
821 return IOAPIC_LEVEL;
822 }
823 #else
eisa_irq_trigger(int idx,int bus,int trigger)824 static inline int eisa_irq_trigger(int idx, int bus, int trigger)
825 {
826 return trigger;
827 }
828 #endif
829
irq_trigger(int idx)830 static int irq_trigger(int idx)
831 {
832 int bus = mp_irqs[idx].srcbus;
833 int trigger;
834
835 /*
836 * Determine IRQ trigger mode (edge or level sensitive):
837 */
838 switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
839 case MP_IRQTRIG_DEFAULT:
840 /* conforms to spec, ie. bus-type dependent trigger mode */
841 if (test_bit(bus, mp_bus_not_pci))
842 trigger = default_ISA_trigger(idx);
843 else
844 trigger = default_PCI_trigger(idx);
845 /* Take EISA into account */
846 return eisa_irq_trigger(idx, bus, trigger);
847 case MP_IRQTRIG_EDGE:
848 return IOAPIC_EDGE;
849 case MP_IRQTRIG_RESERVED:
850 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
851 fallthrough;
852 case MP_IRQTRIG_LEVEL:
853 default: /* Pointless default required due to do gcc stupidity */
854 return IOAPIC_LEVEL;
855 }
856 }
857
ioapic_set_alloc_attr(struct irq_alloc_info * info,int node,int trigger,int polarity)858 void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
859 int trigger, int polarity)
860 {
861 init_irq_alloc_info(info, NULL);
862 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
863 info->ioapic.node = node;
864 info->ioapic.trigger = trigger;
865 info->ioapic.polarity = polarity;
866 info->ioapic.valid = 1;
867 }
868
869 #ifndef CONFIG_ACPI
870 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
871 #endif
872
ioapic_copy_alloc_attr(struct irq_alloc_info * dst,struct irq_alloc_info * src,u32 gsi,int ioapic_idx,int pin)873 static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
874 struct irq_alloc_info *src,
875 u32 gsi, int ioapic_idx, int pin)
876 {
877 int trigger, polarity;
878
879 copy_irq_alloc_info(dst, src);
880 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
881 dst->devid = mpc_ioapic_id(ioapic_idx);
882 dst->ioapic.pin = pin;
883 dst->ioapic.valid = 1;
884 if (src && src->ioapic.valid) {
885 dst->ioapic.node = src->ioapic.node;
886 dst->ioapic.trigger = src->ioapic.trigger;
887 dst->ioapic.polarity = src->ioapic.polarity;
888 } else {
889 dst->ioapic.node = NUMA_NO_NODE;
890 if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
891 dst->ioapic.trigger = trigger;
892 dst->ioapic.polarity = polarity;
893 } else {
894 /*
895 * PCI interrupts are always active low level
896 * triggered.
897 */
898 dst->ioapic.trigger = IOAPIC_LEVEL;
899 dst->ioapic.polarity = IOAPIC_POL_LOW;
900 }
901 }
902 }
903
ioapic_alloc_attr_node(struct irq_alloc_info * info)904 static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
905 {
906 return (info && info->ioapic.valid) ? info->ioapic.node : NUMA_NO_NODE;
907 }
908
mp_register_handler(unsigned int irq,unsigned long trigger)909 static void mp_register_handler(unsigned int irq, unsigned long trigger)
910 {
911 irq_flow_handler_t hdl;
912 bool fasteoi;
913
914 if (trigger) {
915 irq_set_status_flags(irq, IRQ_LEVEL);
916 fasteoi = true;
917 } else {
918 irq_clear_status_flags(irq, IRQ_LEVEL);
919 fasteoi = false;
920 }
921
922 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
923 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
924 }
925
mp_check_pin_attr(int irq,struct irq_alloc_info * info)926 static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
927 {
928 struct mp_chip_data *data = irq_get_chip_data(irq);
929
930 /*
931 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
932 * and polarity attirbutes. So allow the first user to reprogram the
933 * pin with real trigger and polarity attributes.
934 */
935 if (irq < nr_legacy_irqs() && data->count == 1) {
936 if (info->ioapic.trigger != data->trigger)
937 mp_register_handler(irq, info->ioapic.trigger);
938 data->entry.trigger = data->trigger = info->ioapic.trigger;
939 data->entry.polarity = data->polarity = info->ioapic.polarity;
940 }
941
942 return data->trigger == info->ioapic.trigger &&
943 data->polarity == info->ioapic.polarity;
944 }
945
alloc_irq_from_domain(struct irq_domain * domain,int ioapic,u32 gsi,struct irq_alloc_info * info)946 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
947 struct irq_alloc_info *info)
948 {
949 bool legacy = false;
950 int irq = -1;
951 int type = ioapics[ioapic].irqdomain_cfg.type;
952
953 switch (type) {
954 case IOAPIC_DOMAIN_LEGACY:
955 /*
956 * Dynamically allocate IRQ number for non-ISA IRQs in the first
957 * 16 GSIs on some weird platforms.
958 */
959 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
960 irq = gsi;
961 legacy = mp_is_legacy_irq(irq);
962 break;
963 case IOAPIC_DOMAIN_STRICT:
964 irq = gsi;
965 break;
966 case IOAPIC_DOMAIN_DYNAMIC:
967 break;
968 default:
969 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
970 return -1;
971 }
972
973 return __irq_domain_alloc_irqs(domain, irq, 1,
974 ioapic_alloc_attr_node(info),
975 info, legacy, NULL);
976 }
977
978 /*
979 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
980 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
981 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
982 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
983 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
984 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
985 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
986 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
987 */
alloc_isa_irq_from_domain(struct irq_domain * domain,int irq,int ioapic,int pin,struct irq_alloc_info * info)988 static int alloc_isa_irq_from_domain(struct irq_domain *domain,
989 int irq, int ioapic, int pin,
990 struct irq_alloc_info *info)
991 {
992 struct mp_chip_data *data;
993 struct irq_data *irq_data = irq_get_irq_data(irq);
994 int node = ioapic_alloc_attr_node(info);
995
996 /*
997 * Legacy ISA IRQ has already been allocated, just add pin to
998 * the pin list assoicated with this IRQ and program the IOAPIC
999 * entry. The IOAPIC entry
1000 */
1001 if (irq_data && irq_data->parent_data) {
1002 if (!mp_check_pin_attr(irq, info))
1003 return -EBUSY;
1004 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1005 info->ioapic.pin))
1006 return -ENOMEM;
1007 } else {
1008 info->flags |= X86_IRQ_ALLOC_LEGACY;
1009 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true,
1010 NULL);
1011 if (irq >= 0) {
1012 irq_data = irq_domain_get_irq_data(domain, irq);
1013 data = irq_data->chip_data;
1014 data->isa_irq = true;
1015 }
1016 }
1017
1018 return irq;
1019 }
1020
mp_map_pin_to_irq(u32 gsi,int idx,int ioapic,int pin,unsigned int flags,struct irq_alloc_info * info)1021 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1022 unsigned int flags, struct irq_alloc_info *info)
1023 {
1024 int irq;
1025 bool legacy = false;
1026 struct irq_alloc_info tmp;
1027 struct mp_chip_data *data;
1028 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1029
1030 if (!domain)
1031 return -ENOSYS;
1032
1033 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1034 irq = mp_irqs[idx].srcbusirq;
1035 legacy = mp_is_legacy_irq(irq);
1036 /*
1037 * IRQ2 is unusable for historical reasons on systems which
1038 * have a legacy PIC. See the comment vs. IRQ2 further down.
1039 *
1040 * If this gets removed at some point then the related code
1041 * in lapic_assign_system_vectors() needs to be adjusted as
1042 * well.
1043 */
1044 if (legacy && irq == PIC_CASCADE_IR)
1045 return -EINVAL;
1046 }
1047
1048 mutex_lock(&ioapic_mutex);
1049 if (!(flags & IOAPIC_MAP_ALLOC)) {
1050 if (!legacy) {
1051 irq = irq_find_mapping(domain, pin);
1052 if (irq == 0)
1053 irq = -ENOENT;
1054 }
1055 } else {
1056 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1057 if (legacy)
1058 irq = alloc_isa_irq_from_domain(domain, irq,
1059 ioapic, pin, &tmp);
1060 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1061 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1062 else if (!mp_check_pin_attr(irq, &tmp))
1063 irq = -EBUSY;
1064 if (irq >= 0) {
1065 data = irq_get_chip_data(irq);
1066 data->count++;
1067 }
1068 }
1069 mutex_unlock(&ioapic_mutex);
1070
1071 return irq;
1072 }
1073
pin_2_irq(int idx,int ioapic,int pin,unsigned int flags)1074 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1075 {
1076 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1077
1078 /*
1079 * Debugging check, we are in big trouble if this message pops up!
1080 */
1081 if (mp_irqs[idx].dstirq != pin)
1082 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1083
1084 #ifdef CONFIG_X86_32
1085 /*
1086 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1087 */
1088 if ((pin >= 16) && (pin <= 23)) {
1089 if (pirq_entries[pin-16] != -1) {
1090 if (!pirq_entries[pin-16]) {
1091 apic_printk(APIC_VERBOSE, KERN_DEBUG
1092 "disabling PIRQ%d\n", pin-16);
1093 } else {
1094 int irq = pirq_entries[pin-16];
1095 apic_printk(APIC_VERBOSE, KERN_DEBUG
1096 "using PIRQ%d -> IRQ %d\n",
1097 pin-16, irq);
1098 return irq;
1099 }
1100 }
1101 }
1102 #endif
1103
1104 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1105 }
1106
mp_map_gsi_to_irq(u32 gsi,unsigned int flags,struct irq_alloc_info * info)1107 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1108 {
1109 int ioapic, pin, idx;
1110
1111 ioapic = mp_find_ioapic(gsi);
1112 if (ioapic < 0)
1113 return -ENODEV;
1114
1115 pin = mp_find_ioapic_pin(ioapic, gsi);
1116 idx = find_irq_entry(ioapic, pin, mp_INT);
1117 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1118 return -ENODEV;
1119
1120 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1121 }
1122
mp_unmap_irq(int irq)1123 void mp_unmap_irq(int irq)
1124 {
1125 struct irq_data *irq_data = irq_get_irq_data(irq);
1126 struct mp_chip_data *data;
1127
1128 if (!irq_data || !irq_data->domain)
1129 return;
1130
1131 data = irq_data->chip_data;
1132 if (!data || data->isa_irq)
1133 return;
1134
1135 mutex_lock(&ioapic_mutex);
1136 if (--data->count == 0)
1137 irq_domain_free_irqs(irq, 1);
1138 mutex_unlock(&ioapic_mutex);
1139 }
1140
1141 /*
1142 * Find a specific PCI IRQ entry.
1143 * Not an __init, possibly needed by modules
1144 */
IO_APIC_get_PCI_irq_vector(int bus,int slot,int pin)1145 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1146 {
1147 int irq, i, best_ioapic = -1, best_idx = -1;
1148
1149 apic_printk(APIC_DEBUG,
1150 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1151 bus, slot, pin);
1152 if (test_bit(bus, mp_bus_not_pci)) {
1153 apic_printk(APIC_VERBOSE,
1154 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1155 return -1;
1156 }
1157
1158 for (i = 0; i < mp_irq_entries; i++) {
1159 int lbus = mp_irqs[i].srcbus;
1160 int ioapic_idx, found = 0;
1161
1162 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1163 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1164 continue;
1165
1166 for_each_ioapic(ioapic_idx)
1167 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1168 mp_irqs[i].dstapic == MP_APIC_ALL) {
1169 found = 1;
1170 break;
1171 }
1172 if (!found)
1173 continue;
1174
1175 /* Skip ISA IRQs */
1176 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1177 if (irq > 0 && !IO_APIC_IRQ(irq))
1178 continue;
1179
1180 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1181 best_idx = i;
1182 best_ioapic = ioapic_idx;
1183 goto out;
1184 }
1185
1186 /*
1187 * Use the first all-but-pin matching entry as a
1188 * best-guess fuzzy result for broken mptables.
1189 */
1190 if (best_idx < 0) {
1191 best_idx = i;
1192 best_ioapic = ioapic_idx;
1193 }
1194 }
1195 if (best_idx < 0)
1196 return -1;
1197
1198 out:
1199 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1200 IOAPIC_MAP_ALLOC);
1201 }
1202 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1203
1204 static struct irq_chip ioapic_chip, ioapic_ir_chip;
1205
setup_IO_APIC_irqs(void)1206 static void __init setup_IO_APIC_irqs(void)
1207 {
1208 unsigned int ioapic, pin;
1209 int idx;
1210
1211 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1212
1213 for_each_ioapic_pin(ioapic, pin) {
1214 idx = find_irq_entry(ioapic, pin, mp_INT);
1215 if (idx < 0)
1216 apic_printk(APIC_VERBOSE,
1217 KERN_DEBUG " apic %d pin %d not connected\n",
1218 mpc_ioapic_id(ioapic), pin);
1219 else
1220 pin_2_irq(idx, ioapic, pin,
1221 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1222 }
1223 }
1224
ioapic_zap_locks(void)1225 void ioapic_zap_locks(void)
1226 {
1227 raw_spin_lock_init(&ioapic_lock);
1228 }
1229
io_apic_print_entries(unsigned int apic,unsigned int nr_entries)1230 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1231 {
1232 int i;
1233 char buf[256];
1234 struct IO_APIC_route_entry entry;
1235 struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;
1236
1237 printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1238 for (i = 0; i <= nr_entries; i++) {
1239 entry = ioapic_read_entry(apic, i);
1240 snprintf(buf, sizeof(buf),
1241 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1242 i,
1243 entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ",
1244 entry.trigger == IOAPIC_LEVEL ? "level" : "edge ",
1245 entry.polarity == IOAPIC_POL_LOW ? "low " : "high",
1246 entry.vector, entry.irr, entry.delivery_status);
1247 if (ir_entry->format)
1248 printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
1249 buf, (ir_entry->index2 << 15) | ir_entry->index,
1250 ir_entry->zero);
1251 else
1252 printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
1253 buf,
1254 entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ?
1255 "logical " : "physical",
1256 entry.dest, entry.delivery_mode);
1257 }
1258 }
1259
print_IO_APIC(int ioapic_idx)1260 static void __init print_IO_APIC(int ioapic_idx)
1261 {
1262 union IO_APIC_reg_00 reg_00;
1263 union IO_APIC_reg_01 reg_01;
1264 union IO_APIC_reg_02 reg_02;
1265 union IO_APIC_reg_03 reg_03;
1266 unsigned long flags;
1267
1268 raw_spin_lock_irqsave(&ioapic_lock, flags);
1269 reg_00.raw = io_apic_read(ioapic_idx, 0);
1270 reg_01.raw = io_apic_read(ioapic_idx, 1);
1271 if (reg_01.bits.version >= 0x10)
1272 reg_02.raw = io_apic_read(ioapic_idx, 2);
1273 if (reg_01.bits.version >= 0x20)
1274 reg_03.raw = io_apic_read(ioapic_idx, 3);
1275 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1276
1277 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1278 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1279 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1280 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1281 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1282
1283 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1284 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1285 reg_01.bits.entries);
1286
1287 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1288 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1289 reg_01.bits.version);
1290
1291 /*
1292 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1293 * but the value of reg_02 is read as the previous read register
1294 * value, so ignore it if reg_02 == reg_01.
1295 */
1296 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1297 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1298 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1299 }
1300
1301 /*
1302 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1303 * or reg_03, but the value of reg_0[23] is read as the previous read
1304 * register value, so ignore it if reg_03 == reg_0[12].
1305 */
1306 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1307 reg_03.raw != reg_01.raw) {
1308 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1309 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1310 }
1311
1312 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1313 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1314 }
1315
print_IO_APICs(void)1316 void __init print_IO_APICs(void)
1317 {
1318 int ioapic_idx;
1319 unsigned int irq;
1320
1321 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1322 for_each_ioapic(ioapic_idx)
1323 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1324 mpc_ioapic_id(ioapic_idx),
1325 ioapics[ioapic_idx].nr_registers);
1326
1327 /*
1328 * We are a bit conservative about what we expect. We have to
1329 * know about every hardware change ASAP.
1330 */
1331 printk(KERN_INFO "testing the IO APIC.......................\n");
1332
1333 for_each_ioapic(ioapic_idx)
1334 print_IO_APIC(ioapic_idx);
1335
1336 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1337 for_each_active_irq(irq) {
1338 struct irq_pin_list *entry;
1339 struct irq_chip *chip;
1340 struct mp_chip_data *data;
1341
1342 chip = irq_get_chip(irq);
1343 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1344 continue;
1345 data = irq_get_chip_data(irq);
1346 if (!data)
1347 continue;
1348 if (list_empty(&data->irq_2_pin))
1349 continue;
1350
1351 printk(KERN_DEBUG "IRQ%d ", irq);
1352 for_each_irq_pin(entry, data->irq_2_pin)
1353 pr_cont("-> %d:%d", entry->apic, entry->pin);
1354 pr_cont("\n");
1355 }
1356
1357 printk(KERN_INFO ".................................... done.\n");
1358 }
1359
1360 /* Where if anywhere is the i8259 connect in external int mode */
1361 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1362
enable_IO_APIC(void)1363 void __init enable_IO_APIC(void)
1364 {
1365 int i8259_apic, i8259_pin;
1366 int apic, pin;
1367
1368 if (skip_ioapic_setup)
1369 nr_ioapics = 0;
1370
1371 if (!nr_legacy_irqs() || !nr_ioapics)
1372 return;
1373
1374 for_each_ioapic_pin(apic, pin) {
1375 /* See if any of the pins is in ExtINT mode */
1376 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1377
1378 /* If the interrupt line is enabled and in ExtInt mode
1379 * I have found the pin where the i8259 is connected.
1380 */
1381 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1382 ioapic_i8259.apic = apic;
1383 ioapic_i8259.pin = pin;
1384 goto found_i8259;
1385 }
1386 }
1387 found_i8259:
1388 /* Look to see what if the MP table has reported the ExtINT */
1389 /* If we could not find the appropriate pin by looking at the ioapic
1390 * the i8259 probably is not connected the ioapic but give the
1391 * mptable a chance anyway.
1392 */
1393 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1394 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1395 /* Trust the MP table if nothing is setup in the hardware */
1396 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1397 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1398 ioapic_i8259.pin = i8259_pin;
1399 ioapic_i8259.apic = i8259_apic;
1400 }
1401 /* Complain if the MP table and the hardware disagree */
1402 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1403 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1404 {
1405 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1406 }
1407
1408 /*
1409 * Do not trust the IO-APIC being empty at bootup
1410 */
1411 clear_IO_APIC();
1412 }
1413
native_restore_boot_irq_mode(void)1414 void native_restore_boot_irq_mode(void)
1415 {
1416 /*
1417 * If the i8259 is routed through an IOAPIC
1418 * Put that IOAPIC in virtual wire mode
1419 * so legacy interrupts can be delivered.
1420 */
1421 if (ioapic_i8259.pin != -1) {
1422 struct IO_APIC_route_entry entry;
1423
1424 memset(&entry, 0, sizeof(entry));
1425 entry.mask = IOAPIC_UNMASKED;
1426 entry.trigger = IOAPIC_EDGE;
1427 entry.polarity = IOAPIC_POL_HIGH;
1428 entry.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
1429 entry.delivery_mode = dest_ExtINT;
1430 entry.dest = read_apic_id();
1431
1432 /*
1433 * Add it to the IO-APIC irq-routing table:
1434 */
1435 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1436 }
1437
1438 if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1439 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1440 }
1441
restore_boot_irq_mode(void)1442 void restore_boot_irq_mode(void)
1443 {
1444 if (!nr_legacy_irqs())
1445 return;
1446
1447 x86_apic_ops.restore();
1448 }
1449
1450 #ifdef CONFIG_X86_32
1451 /*
1452 * function to set the IO-APIC physical IDs based on the
1453 * values stored in the MPC table.
1454 *
1455 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1456 */
setup_ioapic_ids_from_mpc_nocheck(void)1457 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1458 {
1459 union IO_APIC_reg_00 reg_00;
1460 physid_mask_t phys_id_present_map;
1461 int ioapic_idx;
1462 int i;
1463 unsigned char old_id;
1464 unsigned long flags;
1465
1466 /*
1467 * This is broken; anything with a real cpu count has to
1468 * circumvent this idiocy regardless.
1469 */
1470 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1471
1472 /*
1473 * Set the IOAPIC ID to the value stored in the MPC table.
1474 */
1475 for_each_ioapic(ioapic_idx) {
1476 /* Read the register 0 value */
1477 raw_spin_lock_irqsave(&ioapic_lock, flags);
1478 reg_00.raw = io_apic_read(ioapic_idx, 0);
1479 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1480
1481 old_id = mpc_ioapic_id(ioapic_idx);
1482
1483 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1484 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1485 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1486 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1487 reg_00.bits.ID);
1488 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1489 }
1490
1491 /*
1492 * Sanity check, is the ID really free? Every APIC in a
1493 * system must have a unique ID or we get lots of nice
1494 * 'stuck on smp_invalidate_needed IPI wait' messages.
1495 */
1496 if (apic->check_apicid_used(&phys_id_present_map,
1497 mpc_ioapic_id(ioapic_idx))) {
1498 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1499 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1500 for (i = 0; i < get_physical_broadcast(); i++)
1501 if (!physid_isset(i, phys_id_present_map))
1502 break;
1503 if (i >= get_physical_broadcast())
1504 panic("Max APIC ID exceeded!\n");
1505 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1506 i);
1507 physid_set(i, phys_id_present_map);
1508 ioapics[ioapic_idx].mp_config.apicid = i;
1509 } else {
1510 physid_mask_t tmp;
1511 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1512 &tmp);
1513 apic_printk(APIC_VERBOSE, "Setting %d in the "
1514 "phys_id_present_map\n",
1515 mpc_ioapic_id(ioapic_idx));
1516 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1517 }
1518
1519 /*
1520 * We need to adjust the IRQ routing table
1521 * if the ID changed.
1522 */
1523 if (old_id != mpc_ioapic_id(ioapic_idx))
1524 for (i = 0; i < mp_irq_entries; i++)
1525 if (mp_irqs[i].dstapic == old_id)
1526 mp_irqs[i].dstapic
1527 = mpc_ioapic_id(ioapic_idx);
1528
1529 /*
1530 * Update the ID register according to the right value
1531 * from the MPC table if they are different.
1532 */
1533 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1534 continue;
1535
1536 apic_printk(APIC_VERBOSE, KERN_INFO
1537 "...changing IO-APIC physical APIC ID to %d ...",
1538 mpc_ioapic_id(ioapic_idx));
1539
1540 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1541 raw_spin_lock_irqsave(&ioapic_lock, flags);
1542 io_apic_write(ioapic_idx, 0, reg_00.raw);
1543 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1544
1545 /*
1546 * Sanity check
1547 */
1548 raw_spin_lock_irqsave(&ioapic_lock, flags);
1549 reg_00.raw = io_apic_read(ioapic_idx, 0);
1550 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1551 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1552 pr_cont("could not set ID!\n");
1553 else
1554 apic_printk(APIC_VERBOSE, " ok.\n");
1555 }
1556 }
1557
setup_ioapic_ids_from_mpc(void)1558 void __init setup_ioapic_ids_from_mpc(void)
1559 {
1560
1561 if (acpi_ioapic)
1562 return;
1563 /*
1564 * Don't check I/O APIC IDs for xAPIC systems. They have
1565 * no meaning without the serial APIC bus.
1566 */
1567 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1568 || APIC_XAPIC(boot_cpu_apic_version))
1569 return;
1570 setup_ioapic_ids_from_mpc_nocheck();
1571 }
1572 #endif
1573
1574 int no_timer_check __initdata;
1575
notimercheck(char * s)1576 static int __init notimercheck(char *s)
1577 {
1578 no_timer_check = 1;
1579 return 1;
1580 }
1581 __setup("no_timer_check", notimercheck);
1582
delay_with_tsc(void)1583 static void __init delay_with_tsc(void)
1584 {
1585 unsigned long long start, now;
1586 unsigned long end = jiffies + 4;
1587
1588 start = rdtsc();
1589
1590 /*
1591 * We don't know the TSC frequency yet, but waiting for
1592 * 40000000000/HZ TSC cycles is safe:
1593 * 4 GHz == 10 jiffies
1594 * 1 GHz == 40 jiffies
1595 */
1596 do {
1597 rep_nop();
1598 now = rdtsc();
1599 } while ((now - start) < 40000000000ULL / HZ &&
1600 time_before_eq(jiffies, end));
1601 }
1602
delay_without_tsc(void)1603 static void __init delay_without_tsc(void)
1604 {
1605 unsigned long end = jiffies + 4;
1606 int band = 1;
1607
1608 /*
1609 * We don't know any frequency yet, but waiting for
1610 * 40940000000/HZ cycles is safe:
1611 * 4 GHz == 10 jiffies
1612 * 1 GHz == 40 jiffies
1613 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
1614 */
1615 do {
1616 __delay(((1U << band++) * 10000000UL) / HZ);
1617 } while (band < 12 && time_before_eq(jiffies, end));
1618 }
1619
1620 /*
1621 * There is a nasty bug in some older SMP boards, their mptable lies
1622 * about the timer IRQ. We do the following to work around the situation:
1623 *
1624 * - timer IRQ defaults to IO-APIC IRQ
1625 * - if this function detects that timer IRQs are defunct, then we fall
1626 * back to ISA timer IRQs
1627 */
timer_irq_works(void)1628 static int __init timer_irq_works(void)
1629 {
1630 unsigned long t1 = jiffies;
1631 unsigned long flags;
1632
1633 if (no_timer_check)
1634 return 1;
1635
1636 local_save_flags(flags);
1637 local_irq_enable();
1638
1639 if (boot_cpu_has(X86_FEATURE_TSC))
1640 delay_with_tsc();
1641 else
1642 delay_without_tsc();
1643
1644 local_irq_restore(flags);
1645
1646 /*
1647 * Expect a few ticks at least, to be sure some possible
1648 * glue logic does not lock up after one or two first
1649 * ticks in a non-ExtINT mode. Also the local APIC
1650 * might have cached one ExtINT interrupt. Finally, at
1651 * least one tick may be lost due to delays.
1652 */
1653
1654 /* jiffies wrap? */
1655 if (time_after(jiffies, t1 + 4))
1656 return 1;
1657 return 0;
1658 }
1659
1660 /*
1661 * In the SMP+IOAPIC case it might happen that there are an unspecified
1662 * number of pending IRQ events unhandled. These cases are very rare,
1663 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1664 * better to do it this way as thus we do not have to be aware of
1665 * 'pending' interrupts in the IRQ path, except at this point.
1666 */
1667 /*
1668 * Edge triggered needs to resend any interrupt
1669 * that was delayed but this is now handled in the device
1670 * independent code.
1671 */
1672
1673 /*
1674 * Starting up a edge-triggered IO-APIC interrupt is
1675 * nasty - we need to make sure that we get the edge.
1676 * If it is already asserted for some reason, we need
1677 * return 1 to indicate that is was pending.
1678 *
1679 * This is not complete - we should be able to fake
1680 * an edge even if it isn't on the 8259A...
1681 */
startup_ioapic_irq(struct irq_data * data)1682 static unsigned int startup_ioapic_irq(struct irq_data *data)
1683 {
1684 int was_pending = 0, irq = data->irq;
1685 unsigned long flags;
1686
1687 raw_spin_lock_irqsave(&ioapic_lock, flags);
1688 if (irq < nr_legacy_irqs()) {
1689 legacy_pic->mask(irq);
1690 if (legacy_pic->irq_pending(irq))
1691 was_pending = 1;
1692 }
1693 __unmask_ioapic(data->chip_data);
1694 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1695
1696 return was_pending;
1697 }
1698
1699 atomic_t irq_mis_count;
1700
1701 #ifdef CONFIG_GENERIC_PENDING_IRQ
io_apic_level_ack_pending(struct mp_chip_data * data)1702 static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1703 {
1704 struct irq_pin_list *entry;
1705 unsigned long flags;
1706
1707 raw_spin_lock_irqsave(&ioapic_lock, flags);
1708 for_each_irq_pin(entry, data->irq_2_pin) {
1709 unsigned int reg;
1710 int pin;
1711
1712 pin = entry->pin;
1713 reg = io_apic_read(entry->apic, 0x10 + pin*2);
1714 /* Is the remote IRR bit set? */
1715 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
1716 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1717 return true;
1718 }
1719 }
1720 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1721
1722 return false;
1723 }
1724
ioapic_prepare_move(struct irq_data * data)1725 static inline bool ioapic_prepare_move(struct irq_data *data)
1726 {
1727 /* If we are moving the IRQ we need to mask it */
1728 if (unlikely(irqd_is_setaffinity_pending(data))) {
1729 if (!irqd_irq_masked(data))
1730 mask_ioapic_irq(data);
1731 return true;
1732 }
1733 return false;
1734 }
1735
ioapic_finish_move(struct irq_data * data,bool moveit)1736 static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1737 {
1738 if (unlikely(moveit)) {
1739 /* Only migrate the irq if the ack has been received.
1740 *
1741 * On rare occasions the broadcast level triggered ack gets
1742 * delayed going to ioapics, and if we reprogram the
1743 * vector while Remote IRR is still set the irq will never
1744 * fire again.
1745 *
1746 * To prevent this scenario we read the Remote IRR bit
1747 * of the ioapic. This has two effects.
1748 * - On any sane system the read of the ioapic will
1749 * flush writes (and acks) going to the ioapic from
1750 * this cpu.
1751 * - We get to see if the ACK has actually been delivered.
1752 *
1753 * Based on failed experiments of reprogramming the
1754 * ioapic entry from outside of irq context starting
1755 * with masking the ioapic entry and then polling until
1756 * Remote IRR was clear before reprogramming the
1757 * ioapic I don't trust the Remote IRR bit to be
1758 * completey accurate.
1759 *
1760 * However there appears to be no other way to plug
1761 * this race, so if the Remote IRR bit is not
1762 * accurate and is causing problems then it is a hardware bug
1763 * and you can go talk to the chipset vendor about it.
1764 */
1765 if (!io_apic_level_ack_pending(data->chip_data))
1766 irq_move_masked_irq(data);
1767 /* If the IRQ is masked in the core, leave it: */
1768 if (!irqd_irq_masked(data))
1769 unmask_ioapic_irq(data);
1770 }
1771 }
1772 #else
ioapic_prepare_move(struct irq_data * data)1773 static inline bool ioapic_prepare_move(struct irq_data *data)
1774 {
1775 return false;
1776 }
ioapic_finish_move(struct irq_data * data,bool moveit)1777 static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1778 {
1779 }
1780 #endif
1781
ioapic_ack_level(struct irq_data * irq_data)1782 static void ioapic_ack_level(struct irq_data *irq_data)
1783 {
1784 struct irq_cfg *cfg = irqd_cfg(irq_data);
1785 unsigned long v;
1786 bool moveit;
1787 int i;
1788
1789 irq_complete_move(cfg);
1790 moveit = ioapic_prepare_move(irq_data);
1791
1792 /*
1793 * It appears there is an erratum which affects at least version 0x11
1794 * of I/O APIC (that's the 82093AA and cores integrated into various
1795 * chipsets). Under certain conditions a level-triggered interrupt is
1796 * erroneously delivered as edge-triggered one but the respective IRR
1797 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1798 * message but it will never arrive and further interrupts are blocked
1799 * from the source. The exact reason is so far unknown, but the
1800 * phenomenon was observed when two consecutive interrupt requests
1801 * from a given source get delivered to the same CPU and the source is
1802 * temporarily disabled in between.
1803 *
1804 * A workaround is to simulate an EOI message manually. We achieve it
1805 * by setting the trigger mode to edge and then to level when the edge
1806 * trigger mode gets detected in the TMR of a local APIC for a
1807 * level-triggered interrupt. We mask the source for the time of the
1808 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1809 * The idea is from Manfred Spraul. --macro
1810 *
1811 * Also in the case when cpu goes offline, fixup_irqs() will forward
1812 * any unhandled interrupt on the offlined cpu to the new cpu
1813 * destination that is handling the corresponding interrupt. This
1814 * interrupt forwarding is done via IPI's. Hence, in this case also
1815 * level-triggered io-apic interrupt will be seen as an edge
1816 * interrupt in the IRR. And we can't rely on the cpu's EOI
1817 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1818 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1819 * supporting EOI register, we do an explicit EOI to clear the
1820 * remote IRR and on IO-APIC's which don't have an EOI register,
1821 * we use the above logic (mask+edge followed by unmask+level) from
1822 * Manfred Spraul to clear the remote IRR.
1823 */
1824 i = cfg->vector;
1825 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1826
1827 /*
1828 * We must acknowledge the irq before we move it or the acknowledge will
1829 * not propagate properly.
1830 */
1831 ack_APIC_irq();
1832
1833 /*
1834 * Tail end of clearing remote IRR bit (either by delivering the EOI
1835 * message via io-apic EOI register write or simulating it using
1836 * mask+edge followed by unnask+level logic) manually when the
1837 * level triggered interrupt is seen as the edge triggered interrupt
1838 * at the cpu.
1839 */
1840 if (!(v & (1 << (i & 0x1f)))) {
1841 atomic_inc(&irq_mis_count);
1842 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1843 }
1844
1845 ioapic_finish_move(irq_data, moveit);
1846 }
1847
ioapic_ir_ack_level(struct irq_data * irq_data)1848 static void ioapic_ir_ack_level(struct irq_data *irq_data)
1849 {
1850 struct mp_chip_data *data = irq_data->chip_data;
1851
1852 /*
1853 * Intr-remapping uses pin number as the virtual vector
1854 * in the RTE. Actual vector is programmed in
1855 * intr-remapping table entry. Hence for the io-apic
1856 * EOI we use the pin number.
1857 */
1858 apic_ack_irq(irq_data);
1859 eoi_ioapic_pin(data->entry.vector, data);
1860 }
1861
ioapic_configure_entry(struct irq_data * irqd)1862 static void ioapic_configure_entry(struct irq_data *irqd)
1863 {
1864 struct mp_chip_data *mpd = irqd->chip_data;
1865 struct irq_cfg *cfg = irqd_cfg(irqd);
1866 struct irq_pin_list *entry;
1867
1868 /*
1869 * Only update when the parent is the vector domain, don't touch it
1870 * if the parent is the remapping domain. Check the installed
1871 * ioapic chip to verify that.
1872 */
1873 if (irqd->chip == &ioapic_chip) {
1874 mpd->entry.dest = cfg->dest_apicid;
1875 mpd->entry.vector = cfg->vector;
1876 }
1877 for_each_irq_pin(entry, mpd->irq_2_pin)
1878 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
1879 }
1880
ioapic_set_affinity(struct irq_data * irq_data,const struct cpumask * mask,bool force)1881 static int ioapic_set_affinity(struct irq_data *irq_data,
1882 const struct cpumask *mask, bool force)
1883 {
1884 struct irq_data *parent = irq_data->parent_data;
1885 unsigned long flags;
1886 int ret;
1887
1888 ret = parent->chip->irq_set_affinity(parent, mask, force);
1889 raw_spin_lock_irqsave(&ioapic_lock, flags);
1890 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
1891 ioapic_configure_entry(irq_data);
1892 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1893
1894 return ret;
1895 }
1896
1897 /*
1898 * Interrupt shutdown masks the ioapic pin, but the interrupt might already
1899 * be in flight, but not yet serviced by the target CPU. That means
1900 * __synchronize_hardirq() would return and claim that everything is calmed
1901 * down. So free_irq() would proceed and deactivate the interrupt and free
1902 * resources.
1903 *
1904 * Once the target CPU comes around to service it it will find a cleared
1905 * vector and complain. While the spurious interrupt is harmless, the full
1906 * release of resources might prevent the interrupt from being acknowledged
1907 * which keeps the hardware in a weird state.
1908 *
1909 * Verify that the corresponding Remote-IRR bits are clear.
1910 */
ioapic_irq_get_chip_state(struct irq_data * irqd,enum irqchip_irq_state which,bool * state)1911 static int ioapic_irq_get_chip_state(struct irq_data *irqd,
1912 enum irqchip_irq_state which,
1913 bool *state)
1914 {
1915 struct mp_chip_data *mcd = irqd->chip_data;
1916 struct IO_APIC_route_entry rentry;
1917 struct irq_pin_list *p;
1918
1919 if (which != IRQCHIP_STATE_ACTIVE)
1920 return -EINVAL;
1921
1922 *state = false;
1923 raw_spin_lock(&ioapic_lock);
1924 for_each_irq_pin(p, mcd->irq_2_pin) {
1925 rentry = __ioapic_read_entry(p->apic, p->pin);
1926 /*
1927 * The remote IRR is only valid in level trigger mode. It's
1928 * meaning is undefined for edge triggered interrupts and
1929 * irrelevant because the IO-APIC treats them as fire and
1930 * forget.
1931 */
1932 if (rentry.irr && rentry.trigger) {
1933 *state = true;
1934 break;
1935 }
1936 }
1937 raw_spin_unlock(&ioapic_lock);
1938 return 0;
1939 }
1940
1941 static struct irq_chip ioapic_chip __read_mostly = {
1942 .name = "IO-APIC",
1943 .irq_startup = startup_ioapic_irq,
1944 .irq_mask = mask_ioapic_irq,
1945 .irq_unmask = unmask_ioapic_irq,
1946 .irq_ack = irq_chip_ack_parent,
1947 .irq_eoi = ioapic_ack_level,
1948 .irq_set_affinity = ioapic_set_affinity,
1949 .irq_retrigger = irq_chip_retrigger_hierarchy,
1950 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1951 .flags = IRQCHIP_SKIP_SET_WAKE |
1952 IRQCHIP_AFFINITY_PRE_STARTUP,
1953 };
1954
1955 static struct irq_chip ioapic_ir_chip __read_mostly = {
1956 .name = "IR-IO-APIC",
1957 .irq_startup = startup_ioapic_irq,
1958 .irq_mask = mask_ioapic_irq,
1959 .irq_unmask = unmask_ioapic_irq,
1960 .irq_ack = irq_chip_ack_parent,
1961 .irq_eoi = ioapic_ir_ack_level,
1962 .irq_set_affinity = ioapic_set_affinity,
1963 .irq_retrigger = irq_chip_retrigger_hierarchy,
1964 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1965 .flags = IRQCHIP_SKIP_SET_WAKE |
1966 IRQCHIP_AFFINITY_PRE_STARTUP,
1967 };
1968
init_IO_APIC_traps(void)1969 static inline void init_IO_APIC_traps(void)
1970 {
1971 struct irq_cfg *cfg;
1972 unsigned int irq;
1973
1974 for_each_active_irq(irq) {
1975 cfg = irq_cfg(irq);
1976 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1977 /*
1978 * Hmm.. We don't have an entry for this,
1979 * so default to an old-fashioned 8259
1980 * interrupt if we can..
1981 */
1982 if (irq < nr_legacy_irqs())
1983 legacy_pic->make_irq(irq);
1984 else
1985 /* Strange. Oh, well.. */
1986 irq_set_chip(irq, &no_irq_chip);
1987 }
1988 }
1989 }
1990
1991 /*
1992 * The local APIC irq-chip implementation:
1993 */
1994
mask_lapic_irq(struct irq_data * data)1995 static void mask_lapic_irq(struct irq_data *data)
1996 {
1997 unsigned long v;
1998
1999 v = apic_read(APIC_LVT0);
2000 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2001 }
2002
unmask_lapic_irq(struct irq_data * data)2003 static void unmask_lapic_irq(struct irq_data *data)
2004 {
2005 unsigned long v;
2006
2007 v = apic_read(APIC_LVT0);
2008 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2009 }
2010
ack_lapic_irq(struct irq_data * data)2011 static void ack_lapic_irq(struct irq_data *data)
2012 {
2013 ack_APIC_irq();
2014 }
2015
2016 static struct irq_chip lapic_chip __read_mostly = {
2017 .name = "local-APIC",
2018 .irq_mask = mask_lapic_irq,
2019 .irq_unmask = unmask_lapic_irq,
2020 .irq_ack = ack_lapic_irq,
2021 };
2022
lapic_register_intr(int irq)2023 static void lapic_register_intr(int irq)
2024 {
2025 irq_clear_status_flags(irq, IRQ_LEVEL);
2026 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2027 "edge");
2028 }
2029
2030 /*
2031 * This looks a bit hackish but it's about the only one way of sending
2032 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2033 * not support the ExtINT mode, unfortunately. We need to send these
2034 * cycles as some i82489DX-based boards have glue logic that keeps the
2035 * 8259A interrupt line asserted until INTA. --macro
2036 */
unlock_ExtINT_logic(void)2037 static inline void __init unlock_ExtINT_logic(void)
2038 {
2039 int apic, pin, i;
2040 struct IO_APIC_route_entry entry0, entry1;
2041 unsigned char save_control, save_freq_select;
2042
2043 pin = find_isa_irq_pin(8, mp_INT);
2044 if (pin == -1) {
2045 WARN_ON_ONCE(1);
2046 return;
2047 }
2048 apic = find_isa_irq_apic(8, mp_INT);
2049 if (apic == -1) {
2050 WARN_ON_ONCE(1);
2051 return;
2052 }
2053
2054 entry0 = ioapic_read_entry(apic, pin);
2055 clear_IO_APIC_pin(apic, pin);
2056
2057 memset(&entry1, 0, sizeof(entry1));
2058
2059 entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
2060 entry1.mask = IOAPIC_UNMASKED;
2061 entry1.dest = hard_smp_processor_id();
2062 entry1.delivery_mode = dest_ExtINT;
2063 entry1.polarity = entry0.polarity;
2064 entry1.trigger = IOAPIC_EDGE;
2065 entry1.vector = 0;
2066
2067 ioapic_write_entry(apic, pin, entry1);
2068
2069 save_control = CMOS_READ(RTC_CONTROL);
2070 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2071 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2072 RTC_FREQ_SELECT);
2073 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2074
2075 i = 100;
2076 while (i-- > 0) {
2077 mdelay(10);
2078 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2079 i -= 10;
2080 }
2081
2082 CMOS_WRITE(save_control, RTC_CONTROL);
2083 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2084 clear_IO_APIC_pin(apic, pin);
2085
2086 ioapic_write_entry(apic, pin, entry0);
2087 }
2088
2089 static int disable_timer_pin_1 __initdata;
2090 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
disable_timer_pin_setup(char * arg)2091 static int __init disable_timer_pin_setup(char *arg)
2092 {
2093 disable_timer_pin_1 = 1;
2094 return 0;
2095 }
2096 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2097
mp_alloc_timer_irq(int ioapic,int pin)2098 static int mp_alloc_timer_irq(int ioapic, int pin)
2099 {
2100 int irq = -1;
2101 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2102
2103 if (domain) {
2104 struct irq_alloc_info info;
2105
2106 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2107 info.devid = mpc_ioapic_id(ioapic);
2108 info.ioapic.pin = pin;
2109 mutex_lock(&ioapic_mutex);
2110 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2111 mutex_unlock(&ioapic_mutex);
2112 }
2113
2114 return irq;
2115 }
2116
2117 /*
2118 * This code may look a bit paranoid, but it's supposed to cooperate with
2119 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2120 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2121 * fanatically on his truly buggy board.
2122 *
2123 * FIXME: really need to revamp this for all platforms.
2124 */
check_timer(void)2125 static inline void __init check_timer(void)
2126 {
2127 struct irq_data *irq_data = irq_get_irq_data(0);
2128 struct mp_chip_data *data = irq_data->chip_data;
2129 struct irq_cfg *cfg = irqd_cfg(irq_data);
2130 int node = cpu_to_node(0);
2131 int apic1, pin1, apic2, pin2;
2132 unsigned long flags;
2133 int no_pin1 = 0;
2134
2135 if (!global_clock_event)
2136 return;
2137
2138 local_irq_save(flags);
2139
2140 /*
2141 * get/set the timer IRQ vector:
2142 */
2143 legacy_pic->mask(0);
2144
2145 /*
2146 * As IRQ0 is to be enabled in the 8259A, the virtual
2147 * wire has to be disabled in the local APIC. Also
2148 * timer interrupts need to be acknowledged manually in
2149 * the 8259A for the i82489DX when using the NMI
2150 * watchdog as that APIC treats NMIs as level-triggered.
2151 * The AEOI mode will finish them in the 8259A
2152 * automatically.
2153 */
2154 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2155 legacy_pic->init(1);
2156
2157 pin1 = find_isa_irq_pin(0, mp_INT);
2158 apic1 = find_isa_irq_apic(0, mp_INT);
2159 pin2 = ioapic_i8259.pin;
2160 apic2 = ioapic_i8259.apic;
2161
2162 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2163 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2164 cfg->vector, apic1, pin1, apic2, pin2);
2165
2166 /*
2167 * Some BIOS writers are clueless and report the ExtINTA
2168 * I/O APIC input from the cascaded 8259A as the timer
2169 * interrupt input. So just in case, if only one pin
2170 * was found above, try it both directly and through the
2171 * 8259A.
2172 */
2173 if (pin1 == -1) {
2174 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2175 pin1 = pin2;
2176 apic1 = apic2;
2177 no_pin1 = 1;
2178 } else if (pin2 == -1) {
2179 pin2 = pin1;
2180 apic2 = apic1;
2181 }
2182
2183 if (pin1 != -1) {
2184 /* Ok, does IRQ0 through the IOAPIC work? */
2185 if (no_pin1) {
2186 mp_alloc_timer_irq(apic1, pin1);
2187 } else {
2188 /*
2189 * for edge trigger, it's already unmasked,
2190 * so only need to unmask if it is level-trigger
2191 * do we really have level trigger timer?
2192 */
2193 int idx;
2194 idx = find_irq_entry(apic1, pin1, mp_INT);
2195 if (idx != -1 && irq_trigger(idx))
2196 unmask_ioapic_irq(irq_get_irq_data(0));
2197 }
2198 irq_domain_deactivate_irq(irq_data);
2199 irq_domain_activate_irq(irq_data, false);
2200 if (timer_irq_works()) {
2201 if (disable_timer_pin_1 > 0)
2202 clear_IO_APIC_pin(0, pin1);
2203 goto out;
2204 }
2205 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2206 local_irq_disable();
2207 clear_IO_APIC_pin(apic1, pin1);
2208 if (!no_pin1)
2209 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2210 "8254 timer not connected to IO-APIC\n");
2211
2212 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2213 "(IRQ0) through the 8259A ...\n");
2214 apic_printk(APIC_QUIET, KERN_INFO
2215 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2216 /*
2217 * legacy devices should be connected to IO APIC #0
2218 */
2219 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2220 irq_domain_deactivate_irq(irq_data);
2221 irq_domain_activate_irq(irq_data, false);
2222 legacy_pic->unmask(0);
2223 if (timer_irq_works()) {
2224 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2225 goto out;
2226 }
2227 /*
2228 * Cleanup, just in case ...
2229 */
2230 local_irq_disable();
2231 legacy_pic->mask(0);
2232 clear_IO_APIC_pin(apic2, pin2);
2233 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2234 }
2235
2236 apic_printk(APIC_QUIET, KERN_INFO
2237 "...trying to set up timer as Virtual Wire IRQ...\n");
2238
2239 lapic_register_intr(0);
2240 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2241 legacy_pic->unmask(0);
2242
2243 if (timer_irq_works()) {
2244 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2245 goto out;
2246 }
2247 local_irq_disable();
2248 legacy_pic->mask(0);
2249 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2250 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2251
2252 apic_printk(APIC_QUIET, KERN_INFO
2253 "...trying to set up timer as ExtINT IRQ...\n");
2254
2255 legacy_pic->init(0);
2256 legacy_pic->make_irq(0);
2257 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2258 legacy_pic->unmask(0);
2259
2260 unlock_ExtINT_logic();
2261
2262 if (timer_irq_works()) {
2263 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2264 goto out;
2265 }
2266 local_irq_disable();
2267 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2268 if (apic_is_x2apic_enabled())
2269 apic_printk(APIC_QUIET, KERN_INFO
2270 "Perhaps problem with the pre-enabled x2apic mode\n"
2271 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2272 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2273 "report. Then try booting with the 'noapic' option.\n");
2274 out:
2275 local_irq_restore(flags);
2276 }
2277
2278 /*
2279 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2280 * to devices. However there may be an I/O APIC pin available for
2281 * this interrupt regardless. The pin may be left unconnected, but
2282 * typically it will be reused as an ExtINT cascade interrupt for
2283 * the master 8259A. In the MPS case such a pin will normally be
2284 * reported as an ExtINT interrupt in the MP table. With ACPI
2285 * there is no provision for ExtINT interrupts, and in the absence
2286 * of an override it would be treated as an ordinary ISA I/O APIC
2287 * interrupt, that is edge-triggered and unmasked by default. We
2288 * used to do this, but it caused problems on some systems because
2289 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2290 * the same ExtINT cascade interrupt to drive the local APIC of the
2291 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2292 * the I/O APIC in all cases now. No actual device should request
2293 * it anyway. --macro
2294 */
2295 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2296
mp_irqdomain_create(int ioapic)2297 static int mp_irqdomain_create(int ioapic)
2298 {
2299 struct irq_alloc_info info;
2300 struct irq_domain *parent;
2301 int hwirqs = mp_ioapic_pin_count(ioapic);
2302 struct ioapic *ip = &ioapics[ioapic];
2303 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2304 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2305 struct fwnode_handle *fn;
2306 char *name = "IO-APIC";
2307
2308 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2309 return 0;
2310
2311 init_irq_alloc_info(&info, NULL);
2312 info.type = X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT;
2313 info.devid = mpc_ioapic_id(ioapic);
2314 parent = irq_remapping_get_irq_domain(&info);
2315 if (!parent)
2316 parent = x86_vector_domain;
2317 else
2318 name = "IO-APIC-IR";
2319
2320 /* Handle device tree enumerated APICs proper */
2321 if (cfg->dev) {
2322 fn = of_node_to_fwnode(cfg->dev);
2323 } else {
2324 fn = irq_domain_alloc_named_id_fwnode(name, ioapic);
2325 if (!fn)
2326 return -ENOMEM;
2327 }
2328
2329 ip->irqdomain = irq_domain_create_linear(fn, hwirqs, cfg->ops,
2330 (void *)(long)ioapic);
2331
2332 if (!ip->irqdomain) {
2333 /* Release fw handle if it was allocated above */
2334 if (!cfg->dev)
2335 irq_domain_free_fwnode(fn);
2336 return -ENOMEM;
2337 }
2338
2339 ip->irqdomain->parent = parent;
2340
2341 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2342 cfg->type == IOAPIC_DOMAIN_STRICT)
2343 ioapic_dynirq_base = max(ioapic_dynirq_base,
2344 gsi_cfg->gsi_end + 1);
2345
2346 return 0;
2347 }
2348
ioapic_destroy_irqdomain(int idx)2349 static void ioapic_destroy_irqdomain(int idx)
2350 {
2351 struct ioapic_domain_cfg *cfg = &ioapics[idx].irqdomain_cfg;
2352 struct fwnode_handle *fn = ioapics[idx].irqdomain->fwnode;
2353
2354 if (ioapics[idx].irqdomain) {
2355 irq_domain_remove(ioapics[idx].irqdomain);
2356 if (!cfg->dev)
2357 irq_domain_free_fwnode(fn);
2358 ioapics[idx].irqdomain = NULL;
2359 }
2360 }
2361
setup_IO_APIC(void)2362 void __init setup_IO_APIC(void)
2363 {
2364 int ioapic;
2365
2366 if (skip_ioapic_setup || !nr_ioapics)
2367 return;
2368
2369 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2370
2371 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2372 for_each_ioapic(ioapic)
2373 BUG_ON(mp_irqdomain_create(ioapic));
2374
2375 /*
2376 * Set up IO-APIC IRQ routing.
2377 */
2378 x86_init.mpparse.setup_ioapic_ids();
2379
2380 sync_Arb_IDs();
2381 setup_IO_APIC_irqs();
2382 init_IO_APIC_traps();
2383 if (nr_legacy_irqs())
2384 check_timer();
2385
2386 ioapic_initialized = 1;
2387 }
2388
resume_ioapic_id(int ioapic_idx)2389 static void resume_ioapic_id(int ioapic_idx)
2390 {
2391 unsigned long flags;
2392 union IO_APIC_reg_00 reg_00;
2393
2394 raw_spin_lock_irqsave(&ioapic_lock, flags);
2395 reg_00.raw = io_apic_read(ioapic_idx, 0);
2396 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2397 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2398 io_apic_write(ioapic_idx, 0, reg_00.raw);
2399 }
2400 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2401 }
2402
ioapic_resume(void)2403 static void ioapic_resume(void)
2404 {
2405 int ioapic_idx;
2406
2407 for_each_ioapic_reverse(ioapic_idx)
2408 resume_ioapic_id(ioapic_idx);
2409
2410 restore_ioapic_entries();
2411 }
2412
2413 static struct syscore_ops ioapic_syscore_ops = {
2414 .suspend = save_ioapic_entries,
2415 .resume = ioapic_resume,
2416 };
2417
ioapic_init_ops(void)2418 static int __init ioapic_init_ops(void)
2419 {
2420 register_syscore_ops(&ioapic_syscore_ops);
2421
2422 return 0;
2423 }
2424
2425 device_initcall(ioapic_init_ops);
2426
io_apic_get_redir_entries(int ioapic)2427 static int io_apic_get_redir_entries(int ioapic)
2428 {
2429 union IO_APIC_reg_01 reg_01;
2430 unsigned long flags;
2431
2432 raw_spin_lock_irqsave(&ioapic_lock, flags);
2433 reg_01.raw = io_apic_read(ioapic, 1);
2434 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2435
2436 /* The register returns the maximum index redir index
2437 * supported, which is one less than the total number of redir
2438 * entries.
2439 */
2440 return reg_01.bits.entries + 1;
2441 }
2442
arch_dynirq_lower_bound(unsigned int from)2443 unsigned int arch_dynirq_lower_bound(unsigned int from)
2444 {
2445 unsigned int ret;
2446
2447 /*
2448 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2449 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2450 */
2451 ret = ioapic_dynirq_base ? : gsi_top;
2452
2453 /*
2454 * For DT enabled machines ioapic_dynirq_base is irrelevant and
2455 * always 0. gsi_top can be 0 if there is no IO/APIC registered.
2456 * 0 is an invalid interrupt number for dynamic allocations. Return
2457 * @from instead.
2458 */
2459 return ret ? : from;
2460 }
2461
2462 #ifdef CONFIG_X86_32
io_apic_get_unique_id(int ioapic,int apic_id)2463 static int io_apic_get_unique_id(int ioapic, int apic_id)
2464 {
2465 union IO_APIC_reg_00 reg_00;
2466 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2467 physid_mask_t tmp;
2468 unsigned long flags;
2469 int i = 0;
2470
2471 /*
2472 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2473 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2474 * supports up to 16 on one shared APIC bus.
2475 *
2476 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2477 * advantage of new APIC bus architecture.
2478 */
2479
2480 if (physids_empty(apic_id_map))
2481 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2482
2483 raw_spin_lock_irqsave(&ioapic_lock, flags);
2484 reg_00.raw = io_apic_read(ioapic, 0);
2485 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2486
2487 if (apic_id >= get_physical_broadcast()) {
2488 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2489 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2490 apic_id = reg_00.bits.ID;
2491 }
2492
2493 /*
2494 * Every APIC in a system must have a unique ID or we get lots of nice
2495 * 'stuck on smp_invalidate_needed IPI wait' messages.
2496 */
2497 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2498
2499 for (i = 0; i < get_physical_broadcast(); i++) {
2500 if (!apic->check_apicid_used(&apic_id_map, i))
2501 break;
2502 }
2503
2504 if (i == get_physical_broadcast())
2505 panic("Max apic_id exceeded!\n");
2506
2507 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2508 "trying %d\n", ioapic, apic_id, i);
2509
2510 apic_id = i;
2511 }
2512
2513 apic->apicid_to_cpu_present(apic_id, &tmp);
2514 physids_or(apic_id_map, apic_id_map, tmp);
2515
2516 if (reg_00.bits.ID != apic_id) {
2517 reg_00.bits.ID = apic_id;
2518
2519 raw_spin_lock_irqsave(&ioapic_lock, flags);
2520 io_apic_write(ioapic, 0, reg_00.raw);
2521 reg_00.raw = io_apic_read(ioapic, 0);
2522 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2523
2524 /* Sanity check */
2525 if (reg_00.bits.ID != apic_id) {
2526 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2527 ioapic);
2528 return -1;
2529 }
2530 }
2531
2532 apic_printk(APIC_VERBOSE, KERN_INFO
2533 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2534
2535 return apic_id;
2536 }
2537
io_apic_unique_id(int idx,u8 id)2538 static u8 io_apic_unique_id(int idx, u8 id)
2539 {
2540 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2541 !APIC_XAPIC(boot_cpu_apic_version))
2542 return io_apic_get_unique_id(idx, id);
2543 else
2544 return id;
2545 }
2546 #else
io_apic_unique_id(int idx,u8 id)2547 static u8 io_apic_unique_id(int idx, u8 id)
2548 {
2549 union IO_APIC_reg_00 reg_00;
2550 DECLARE_BITMAP(used, 256);
2551 unsigned long flags;
2552 u8 new_id;
2553 int i;
2554
2555 bitmap_zero(used, 256);
2556 for_each_ioapic(i)
2557 __set_bit(mpc_ioapic_id(i), used);
2558
2559 /* Hand out the requested id if available */
2560 if (!test_bit(id, used))
2561 return id;
2562
2563 /*
2564 * Read the current id from the ioapic and keep it if
2565 * available.
2566 */
2567 raw_spin_lock_irqsave(&ioapic_lock, flags);
2568 reg_00.raw = io_apic_read(idx, 0);
2569 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2570 new_id = reg_00.bits.ID;
2571 if (!test_bit(new_id, used)) {
2572 apic_printk(APIC_VERBOSE, KERN_INFO
2573 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2574 idx, new_id, id);
2575 return new_id;
2576 }
2577
2578 /*
2579 * Get the next free id and write it to the ioapic.
2580 */
2581 new_id = find_first_zero_bit(used, 256);
2582 reg_00.bits.ID = new_id;
2583 raw_spin_lock_irqsave(&ioapic_lock, flags);
2584 io_apic_write(idx, 0, reg_00.raw);
2585 reg_00.raw = io_apic_read(idx, 0);
2586 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2587 /* Sanity check */
2588 BUG_ON(reg_00.bits.ID != new_id);
2589
2590 return new_id;
2591 }
2592 #endif
2593
io_apic_get_version(int ioapic)2594 static int io_apic_get_version(int ioapic)
2595 {
2596 union IO_APIC_reg_01 reg_01;
2597 unsigned long flags;
2598
2599 raw_spin_lock_irqsave(&ioapic_lock, flags);
2600 reg_01.raw = io_apic_read(ioapic, 1);
2601 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2602
2603 return reg_01.bits.version;
2604 }
2605
acpi_get_override_irq(u32 gsi,int * trigger,int * polarity)2606 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
2607 {
2608 int ioapic, pin, idx;
2609
2610 if (skip_ioapic_setup)
2611 return -1;
2612
2613 ioapic = mp_find_ioapic(gsi);
2614 if (ioapic < 0)
2615 return -1;
2616
2617 pin = mp_find_ioapic_pin(ioapic, gsi);
2618 if (pin < 0)
2619 return -1;
2620
2621 idx = find_irq_entry(ioapic, pin, mp_INT);
2622 if (idx < 0)
2623 return -1;
2624
2625 *trigger = irq_trigger(idx);
2626 *polarity = irq_polarity(idx);
2627 return 0;
2628 }
2629
2630 /*
2631 * This function updates target affinity of IOAPIC interrupts to include
2632 * the CPUs which came online during SMP bringup.
2633 */
2634 #define IOAPIC_RESOURCE_NAME_SIZE 11
2635
2636 static struct resource *ioapic_resources;
2637
ioapic_setup_resources(void)2638 static struct resource * __init ioapic_setup_resources(void)
2639 {
2640 unsigned long n;
2641 struct resource *res;
2642 char *mem;
2643 int i;
2644
2645 if (nr_ioapics == 0)
2646 return NULL;
2647
2648 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2649 n *= nr_ioapics;
2650
2651 mem = memblock_alloc(n, SMP_CACHE_BYTES);
2652 if (!mem)
2653 panic("%s: Failed to allocate %lu bytes\n", __func__, n);
2654 res = (void *)mem;
2655
2656 mem += sizeof(struct resource) * nr_ioapics;
2657
2658 for_each_ioapic(i) {
2659 res[i].name = mem;
2660 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2661 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2662 mem += IOAPIC_RESOURCE_NAME_SIZE;
2663 ioapics[i].iomem_res = &res[i];
2664 }
2665
2666 ioapic_resources = res;
2667
2668 return res;
2669 }
2670
io_apic_init_mappings(void)2671 void __init io_apic_init_mappings(void)
2672 {
2673 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2674 struct resource *ioapic_res;
2675 int i;
2676
2677 ioapic_res = ioapic_setup_resources();
2678 for_each_ioapic(i) {
2679 if (smp_found_config) {
2680 ioapic_phys = mpc_ioapic_addr(i);
2681 #ifdef CONFIG_X86_32
2682 if (!ioapic_phys) {
2683 printk(KERN_ERR
2684 "WARNING: bogus zero IO-APIC "
2685 "address found in MPTABLE, "
2686 "disabling IO/APIC support!\n");
2687 smp_found_config = 0;
2688 skip_ioapic_setup = 1;
2689 goto fake_ioapic_page;
2690 }
2691 #endif
2692 } else {
2693 #ifdef CONFIG_X86_32
2694 fake_ioapic_page:
2695 #endif
2696 ioapic_phys = (unsigned long)memblock_alloc(PAGE_SIZE,
2697 PAGE_SIZE);
2698 if (!ioapic_phys)
2699 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
2700 __func__, PAGE_SIZE, PAGE_SIZE);
2701 ioapic_phys = __pa(ioapic_phys);
2702 }
2703 set_fixmap_nocache(idx, ioapic_phys);
2704 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2705 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2706 ioapic_phys);
2707 idx++;
2708
2709 ioapic_res->start = ioapic_phys;
2710 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2711 ioapic_res++;
2712 }
2713 }
2714
ioapic_insert_resources(void)2715 void __init ioapic_insert_resources(void)
2716 {
2717 int i;
2718 struct resource *r = ioapic_resources;
2719
2720 if (!r) {
2721 if (nr_ioapics > 0)
2722 printk(KERN_ERR
2723 "IO APIC resources couldn't be allocated.\n");
2724 return;
2725 }
2726
2727 for_each_ioapic(i) {
2728 insert_resource(&iomem_resource, r);
2729 r++;
2730 }
2731 }
2732
mp_find_ioapic(u32 gsi)2733 int mp_find_ioapic(u32 gsi)
2734 {
2735 int i;
2736
2737 if (nr_ioapics == 0)
2738 return -1;
2739
2740 /* Find the IOAPIC that manages this GSI. */
2741 for_each_ioapic(i) {
2742 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2743 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2744 return i;
2745 }
2746
2747 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2748 return -1;
2749 }
2750
mp_find_ioapic_pin(int ioapic,u32 gsi)2751 int mp_find_ioapic_pin(int ioapic, u32 gsi)
2752 {
2753 struct mp_ioapic_gsi *gsi_cfg;
2754
2755 if (WARN_ON(ioapic < 0))
2756 return -1;
2757
2758 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2759 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2760 return -1;
2761
2762 return gsi - gsi_cfg->gsi_base;
2763 }
2764
bad_ioapic_register(int idx)2765 static int bad_ioapic_register(int idx)
2766 {
2767 union IO_APIC_reg_00 reg_00;
2768 union IO_APIC_reg_01 reg_01;
2769 union IO_APIC_reg_02 reg_02;
2770
2771 reg_00.raw = io_apic_read(idx, 0);
2772 reg_01.raw = io_apic_read(idx, 1);
2773 reg_02.raw = io_apic_read(idx, 2);
2774
2775 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2776 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2777 mpc_ioapic_addr(idx));
2778 return 1;
2779 }
2780
2781 return 0;
2782 }
2783
find_free_ioapic_entry(void)2784 static int find_free_ioapic_entry(void)
2785 {
2786 int idx;
2787
2788 for (idx = 0; idx < MAX_IO_APICS; idx++)
2789 if (ioapics[idx].nr_registers == 0)
2790 return idx;
2791
2792 return MAX_IO_APICS;
2793 }
2794
2795 /**
2796 * mp_register_ioapic - Register an IOAPIC device
2797 * @id: hardware IOAPIC ID
2798 * @address: physical address of IOAPIC register area
2799 * @gsi_base: base of GSI associated with the IOAPIC
2800 * @cfg: configuration information for the IOAPIC
2801 */
mp_register_ioapic(int id,u32 address,u32 gsi_base,struct ioapic_domain_cfg * cfg)2802 int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2803 struct ioapic_domain_cfg *cfg)
2804 {
2805 bool hotplug = !!ioapic_initialized;
2806 struct mp_ioapic_gsi *gsi_cfg;
2807 int idx, ioapic, entries;
2808 u32 gsi_end;
2809
2810 if (!address) {
2811 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2812 return -EINVAL;
2813 }
2814 for_each_ioapic(ioapic)
2815 if (ioapics[ioapic].mp_config.apicaddr == address) {
2816 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2817 address, ioapic);
2818 return -EEXIST;
2819 }
2820
2821 idx = find_free_ioapic_entry();
2822 if (idx >= MAX_IO_APICS) {
2823 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2824 MAX_IO_APICS, idx);
2825 return -ENOSPC;
2826 }
2827
2828 ioapics[idx].mp_config.type = MP_IOAPIC;
2829 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2830 ioapics[idx].mp_config.apicaddr = address;
2831
2832 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2833 if (bad_ioapic_register(idx)) {
2834 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2835 return -ENODEV;
2836 }
2837
2838 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2839 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2840
2841 /*
2842 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2843 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2844 */
2845 entries = io_apic_get_redir_entries(idx);
2846 gsi_end = gsi_base + entries - 1;
2847 for_each_ioapic(ioapic) {
2848 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2849 if ((gsi_base >= gsi_cfg->gsi_base &&
2850 gsi_base <= gsi_cfg->gsi_end) ||
2851 (gsi_end >= gsi_cfg->gsi_base &&
2852 gsi_end <= gsi_cfg->gsi_end)) {
2853 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2854 gsi_base, gsi_end,
2855 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2856 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2857 return -ENOSPC;
2858 }
2859 }
2860 gsi_cfg = mp_ioapic_gsi_routing(idx);
2861 gsi_cfg->gsi_base = gsi_base;
2862 gsi_cfg->gsi_end = gsi_end;
2863
2864 ioapics[idx].irqdomain = NULL;
2865 ioapics[idx].irqdomain_cfg = *cfg;
2866
2867 /*
2868 * If mp_register_ioapic() is called during early boot stage when
2869 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
2870 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2871 */
2872 if (hotplug) {
2873 if (mp_irqdomain_create(idx)) {
2874 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2875 return -ENOMEM;
2876 }
2877 alloc_ioapic_saved_registers(idx);
2878 }
2879
2880 if (gsi_cfg->gsi_end >= gsi_top)
2881 gsi_top = gsi_cfg->gsi_end + 1;
2882 if (nr_ioapics <= idx)
2883 nr_ioapics = idx + 1;
2884
2885 /* Set nr_registers to mark entry present */
2886 ioapics[idx].nr_registers = entries;
2887
2888 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2889 idx, mpc_ioapic_id(idx),
2890 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2891 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2892
2893 return 0;
2894 }
2895
mp_unregister_ioapic(u32 gsi_base)2896 int mp_unregister_ioapic(u32 gsi_base)
2897 {
2898 int ioapic, pin;
2899 int found = 0;
2900
2901 for_each_ioapic(ioapic)
2902 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2903 found = 1;
2904 break;
2905 }
2906 if (!found) {
2907 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2908 return -ENODEV;
2909 }
2910
2911 for_each_pin(ioapic, pin) {
2912 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2913 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2914 struct mp_chip_data *data;
2915
2916 if (irq >= 0) {
2917 data = irq_get_chip_data(irq);
2918 if (data && data->count) {
2919 pr_warn("pin%d on IOAPIC%d is still in use.\n",
2920 pin, ioapic);
2921 return -EBUSY;
2922 }
2923 }
2924 }
2925
2926 /* Mark entry not present */
2927 ioapics[ioapic].nr_registers = 0;
2928 ioapic_destroy_irqdomain(ioapic);
2929 free_ioapic_saved_registers(ioapic);
2930 if (ioapics[ioapic].iomem_res)
2931 release_resource(ioapics[ioapic].iomem_res);
2932 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2933 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2934
2935 return 0;
2936 }
2937
mp_ioapic_registered(u32 gsi_base)2938 int mp_ioapic_registered(u32 gsi_base)
2939 {
2940 int ioapic;
2941
2942 for_each_ioapic(ioapic)
2943 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2944 return 1;
2945
2946 return 0;
2947 }
2948
mp_irqdomain_get_attr(u32 gsi,struct mp_chip_data * data,struct irq_alloc_info * info)2949 static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2950 struct irq_alloc_info *info)
2951 {
2952 if (info && info->ioapic.valid) {
2953 data->trigger = info->ioapic.trigger;
2954 data->polarity = info->ioapic.polarity;
2955 } else if (acpi_get_override_irq(gsi, &data->trigger,
2956 &data->polarity) < 0) {
2957 /* PCI interrupts are always active low level triggered. */
2958 data->trigger = IOAPIC_LEVEL;
2959 data->polarity = IOAPIC_POL_LOW;
2960 }
2961 }
2962
mp_setup_entry(struct irq_cfg * cfg,struct mp_chip_data * data,struct IO_APIC_route_entry * entry)2963 static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
2964 struct IO_APIC_route_entry *entry)
2965 {
2966 memset(entry, 0, sizeof(*entry));
2967 entry->delivery_mode = apic->irq_delivery_mode;
2968 entry->dest_mode = apic->irq_dest_mode;
2969 entry->dest = cfg->dest_apicid;
2970 entry->vector = cfg->vector;
2971 entry->trigger = data->trigger;
2972 entry->polarity = data->polarity;
2973 /*
2974 * Mask level triggered irqs. Edge triggered irqs are masked
2975 * by the irq core code in case they fire.
2976 */
2977 if (data->trigger == IOAPIC_LEVEL)
2978 entry->mask = IOAPIC_MASKED;
2979 else
2980 entry->mask = IOAPIC_UNMASKED;
2981 }
2982
mp_irqdomain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)2983 int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2984 unsigned int nr_irqs, void *arg)
2985 {
2986 int ret, ioapic, pin;
2987 struct irq_cfg *cfg;
2988 struct irq_data *irq_data;
2989 struct mp_chip_data *data;
2990 struct irq_alloc_info *info = arg;
2991 unsigned long flags;
2992
2993 if (!info || nr_irqs > 1)
2994 return -EINVAL;
2995 irq_data = irq_domain_get_irq_data(domain, virq);
2996 if (!irq_data)
2997 return -EINVAL;
2998
2999 ioapic = mp_irqdomain_ioapic_idx(domain);
3000 pin = info->ioapic.pin;
3001 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
3002 return -EEXIST;
3003
3004 data = kzalloc(sizeof(*data), GFP_KERNEL);
3005 if (!data)
3006 return -ENOMEM;
3007
3008 info->ioapic.entry = &data->entry;
3009 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
3010 if (ret < 0) {
3011 kfree(data);
3012 return ret;
3013 }
3014
3015 INIT_LIST_HEAD(&data->irq_2_pin);
3016 irq_data->hwirq = info->ioapic.pin;
3017 irq_data->chip = (domain->parent == x86_vector_domain) ?
3018 &ioapic_chip : &ioapic_ir_chip;
3019 irq_data->chip_data = data;
3020 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
3021
3022 cfg = irqd_cfg(irq_data);
3023 add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
3024
3025 local_irq_save(flags);
3026 if (info->ioapic.entry)
3027 mp_setup_entry(cfg, data, info->ioapic.entry);
3028 mp_register_handler(virq, data->trigger);
3029 if (virq < nr_legacy_irqs())
3030 legacy_pic->mask(virq);
3031 local_irq_restore(flags);
3032
3033 apic_printk(APIC_VERBOSE, KERN_DEBUG
3034 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
3035 ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector,
3036 virq, data->trigger, data->polarity, cfg->dest_apicid);
3037
3038 return 0;
3039 }
3040
mp_irqdomain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)3041 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
3042 unsigned int nr_irqs)
3043 {
3044 struct irq_data *irq_data;
3045 struct mp_chip_data *data;
3046
3047 BUG_ON(nr_irqs != 1);
3048 irq_data = irq_domain_get_irq_data(domain, virq);
3049 if (irq_data && irq_data->chip_data) {
3050 data = irq_data->chip_data;
3051 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
3052 (int)irq_data->hwirq);
3053 WARN_ON(!list_empty(&data->irq_2_pin));
3054 kfree(irq_data->chip_data);
3055 }
3056 irq_domain_free_irqs_top(domain, virq, nr_irqs);
3057 }
3058
mp_irqdomain_activate(struct irq_domain * domain,struct irq_data * irq_data,bool reserve)3059 int mp_irqdomain_activate(struct irq_domain *domain,
3060 struct irq_data *irq_data, bool reserve)
3061 {
3062 unsigned long flags;
3063
3064 raw_spin_lock_irqsave(&ioapic_lock, flags);
3065 ioapic_configure_entry(irq_data);
3066 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3067 return 0;
3068 }
3069
mp_irqdomain_deactivate(struct irq_domain * domain,struct irq_data * irq_data)3070 void mp_irqdomain_deactivate(struct irq_domain *domain,
3071 struct irq_data *irq_data)
3072 {
3073 /* It won't be called for IRQ with multiple IOAPIC pins associated */
3074 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3075 (int)irq_data->hwirq);
3076 }
3077
mp_irqdomain_ioapic_idx(struct irq_domain * domain)3078 int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3079 {
3080 return (int)(long)domain->host_data;
3081 }
3082
3083 const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3084 .alloc = mp_irqdomain_alloc,
3085 .free = mp_irqdomain_free,
3086 .activate = mp_irqdomain_activate,
3087 .deactivate = mp_irqdomain_deactivate,
3088 };
3089