1 /*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "disp.h"
25 #include "atom.h"
26 #include "core.h"
27 #include "head.h"
28 #include "wndw.h"
29 #include "handles.h"
30
31 #include <linux/dma-mapping.h>
32 #include <linux/hdmi.h>
33 #include <linux/component.h>
34
35 #include <drm/drm_atomic_helper.h>
36 #include <drm/drm_dp_helper.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_fb_helper.h>
39 #include <drm/drm_plane_helper.h>
40 #include <drm/drm_probe_helper.h>
41 #include <drm/drm_scdc_helper.h>
42 #include <drm/drm_vblank.h>
43
44 #include <nvif/push507c.h>
45
46 #include <nvif/class.h>
47 #include <nvif/cl0002.h>
48 #include <nvif/cl5070.h>
49 #include <nvif/cl507d.h>
50 #include <nvif/event.h>
51 #include <nvif/timer.h>
52
53 #include <nvhw/class/cl507c.h>
54 #include <nvhw/class/cl507d.h>
55 #include <nvhw/class/cl837d.h>
56 #include <nvhw/class/cl887d.h>
57 #include <nvhw/class/cl907d.h>
58 #include <nvhw/class/cl917d.h>
59
60 #include "nouveau_drv.h"
61 #include "nouveau_dma.h"
62 #include "nouveau_gem.h"
63 #include "nouveau_connector.h"
64 #include "nouveau_encoder.h"
65 #include "nouveau_fence.h"
66 #include "nouveau_fbcon.h"
67
68 #include <subdev/bios/dp.h>
69
70 /******************************************************************************
71 * EVO channel
72 *****************************************************************************/
73
74 static int
nv50_chan_create(struct nvif_device * device,struct nvif_object * disp,const s32 * oclass,u8 head,void * data,u32 size,struct nv50_chan * chan)75 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
76 const s32 *oclass, u8 head, void *data, u32 size,
77 struct nv50_chan *chan)
78 {
79 struct nvif_sclass *sclass;
80 int ret, i, n;
81
82 chan->device = device;
83
84 ret = n = nvif_object_sclass_get(disp, &sclass);
85 if (ret < 0)
86 return ret;
87
88 while (oclass[0]) {
89 for (i = 0; i < n; i++) {
90 if (sclass[i].oclass == oclass[0]) {
91 ret = nvif_object_ctor(disp, "kmsChan", 0,
92 oclass[0], data, size,
93 &chan->user);
94 if (ret == 0)
95 nvif_object_map(&chan->user, NULL, 0);
96 nvif_object_sclass_put(&sclass);
97 return ret;
98 }
99 }
100 oclass++;
101 }
102
103 nvif_object_sclass_put(&sclass);
104 return -ENOSYS;
105 }
106
107 static void
nv50_chan_destroy(struct nv50_chan * chan)108 nv50_chan_destroy(struct nv50_chan *chan)
109 {
110 nvif_object_dtor(&chan->user);
111 }
112
113 /******************************************************************************
114 * DMA EVO channel
115 *****************************************************************************/
116
117 void
nv50_dmac_destroy(struct nv50_dmac * dmac)118 nv50_dmac_destroy(struct nv50_dmac *dmac)
119 {
120 nvif_object_dtor(&dmac->vram);
121 nvif_object_dtor(&dmac->sync);
122
123 nv50_chan_destroy(&dmac->base);
124
125 nvif_mem_dtor(&dmac->_push.mem);
126 }
127
128 static void
nv50_dmac_kick(struct nvif_push * push)129 nv50_dmac_kick(struct nvif_push *push)
130 {
131 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
132
133 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr;
134 if (dmac->put != dmac->cur) {
135 /* Push buffer fetches are not coherent with BAR1, we need to ensure
136 * writes have been flushed right through to VRAM before writing PUT.
137 */
138 if (dmac->push->mem.type & NVIF_MEM_VRAM) {
139 struct nvif_device *device = dmac->base.device;
140 nvif_wr32(&device->object, 0x070000, 0x00000001);
141 nvif_msec(device, 2000,
142 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
143 break;
144 );
145 }
146
147 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur);
148 dmac->put = dmac->cur;
149 }
150
151 push->bgn = push->cur;
152 }
153
154 static int
nv50_dmac_free(struct nv50_dmac * dmac)155 nv50_dmac_free(struct nv50_dmac *dmac)
156 {
157 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
158 if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */
159 return get - dmac->cur - 5;
160 return dmac->max - dmac->cur;
161 }
162
163 static int
nv50_dmac_wind(struct nv50_dmac * dmac)164 nv50_dmac_wind(struct nv50_dmac *dmac)
165 {
166 /* Wait for GET to depart from the beginning of the push buffer to
167 * prevent writing PUT == GET, which would be ignored by HW.
168 */
169 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
170 if (get == 0) {
171 /* Corner-case, HW idle, but non-committed work pending. */
172 if (dmac->put == 0)
173 nv50_dmac_kick(dmac->push);
174
175 if (nvif_msec(dmac->base.device, 2000,
176 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0))
177 break;
178 ) < 0)
179 return -ETIMEDOUT;
180 }
181
182 PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0));
183 dmac->cur = 0;
184 return 0;
185 }
186
187 static int
nv50_dmac_wait(struct nvif_push * push,u32 size)188 nv50_dmac_wait(struct nvif_push *push, u32 size)
189 {
190 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
191 int free;
192
193 if (WARN_ON(size > dmac->max))
194 return -EINVAL;
195
196 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr;
197 if (dmac->cur + size >= dmac->max) {
198 int ret = nv50_dmac_wind(dmac);
199 if (ret)
200 return ret;
201
202 push->cur = dmac->_push.mem.object.map.ptr;
203 push->cur = push->cur + dmac->cur;
204 nv50_dmac_kick(push);
205 }
206
207 if (nvif_msec(dmac->base.device, 2000,
208 if ((free = nv50_dmac_free(dmac)) >= size)
209 break;
210 ) < 0) {
211 WARN_ON(1);
212 return -ETIMEDOUT;
213 }
214
215 push->bgn = dmac->_push.mem.object.map.ptr;
216 push->bgn = push->bgn + dmac->cur;
217 push->cur = push->bgn;
218 push->end = push->cur + free;
219 return 0;
220 }
221
222 int
nv50_dmac_create(struct nvif_device * device,struct nvif_object * disp,const s32 * oclass,u8 head,void * data,u32 size,s64 syncbuf,struct nv50_dmac * dmac)223 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
224 const s32 *oclass, u8 head, void *data, u32 size, s64 syncbuf,
225 struct nv50_dmac *dmac)
226 {
227 struct nouveau_cli *cli = (void *)device->object.client;
228 struct nv50_disp_core_channel_dma_v0 *args = data;
229 u8 type = NVIF_MEM_COHERENT;
230 int ret;
231
232 mutex_init(&dmac->lock);
233
234 /* Pascal added support for 47-bit physical addresses, but some
235 * parts of EVO still only accept 40-bit PAs.
236 *
237 * To avoid issues on systems with large amounts of RAM, and on
238 * systems where an IOMMU maps pages at a high address, we need
239 * to allocate push buffers in VRAM instead.
240 *
241 * This appears to match NVIDIA's behaviour on Pascal.
242 */
243 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
244 type |= NVIF_MEM_VRAM;
245
246 ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000,
247 &dmac->_push.mem);
248 if (ret)
249 return ret;
250
251 dmac->ptr = dmac->_push.mem.object.map.ptr;
252 dmac->_push.wait = nv50_dmac_wait;
253 dmac->_push.kick = nv50_dmac_kick;
254 dmac->push = &dmac->_push;
255 dmac->push->bgn = dmac->_push.mem.object.map.ptr;
256 dmac->push->cur = dmac->push->bgn;
257 dmac->push->end = dmac->push->bgn;
258 dmac->max = 0x1000/4 - 1;
259
260 /* EVO channels are affected by a HW bug where the last 12 DWORDs
261 * of the push buffer aren't able to be used safely.
262 */
263 if (disp->oclass < GV100_DISP)
264 dmac->max -= 12;
265
266 args->pushbuf = nvif_handle(&dmac->_push.mem.object);
267
268 ret = nv50_chan_create(device, disp, oclass, head, data, size,
269 &dmac->base);
270 if (ret)
271 return ret;
272
273 if (syncbuf < 0)
274 return 0;
275
276 ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,
277 NV_DMA_IN_MEMORY,
278 &(struct nv_dma_v0) {
279 .target = NV_DMA_V0_TARGET_VRAM,
280 .access = NV_DMA_V0_ACCESS_RDWR,
281 .start = syncbuf + 0x0000,
282 .limit = syncbuf + 0x0fff,
283 }, sizeof(struct nv_dma_v0),
284 &dmac->sync);
285 if (ret)
286 return ret;
287
288 ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM,
289 NV_DMA_IN_MEMORY,
290 &(struct nv_dma_v0) {
291 .target = NV_DMA_V0_TARGET_VRAM,
292 .access = NV_DMA_V0_ACCESS_RDWR,
293 .start = 0,
294 .limit = device->info.ram_user - 1,
295 }, sizeof(struct nv_dma_v0),
296 &dmac->vram);
297 if (ret)
298 return ret;
299
300 return ret;
301 }
302
303 /******************************************************************************
304 * Output path helpers
305 *****************************************************************************/
306 static void
nv50_outp_release(struct nouveau_encoder * nv_encoder)307 nv50_outp_release(struct nouveau_encoder *nv_encoder)
308 {
309 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
310 struct {
311 struct nv50_disp_mthd_v1 base;
312 } args = {
313 .base.version = 1,
314 .base.method = NV50_DISP_MTHD_V1_RELEASE,
315 .base.hasht = nv_encoder->dcb->hasht,
316 .base.hashm = nv_encoder->dcb->hashm,
317 };
318
319 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
320 nv_encoder->or = -1;
321 nv_encoder->link = 0;
322 }
323
324 static int
nv50_outp_acquire(struct nouveau_encoder * nv_encoder,bool hda)325 nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda)
326 {
327 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
328 struct nv50_disp *disp = nv50_disp(drm->dev);
329 struct {
330 struct nv50_disp_mthd_v1 base;
331 struct nv50_disp_acquire_v0 info;
332 } args = {
333 .base.version = 1,
334 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
335 .base.hasht = nv_encoder->dcb->hasht,
336 .base.hashm = nv_encoder->dcb->hashm,
337 .info.hda = hda,
338 };
339 int ret;
340
341 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
342 if (ret) {
343 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
344 return ret;
345 }
346
347 nv_encoder->or = args.info.or;
348 nv_encoder->link = args.info.link;
349 return 0;
350 }
351
352 static int
nv50_outp_atomic_check_view(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,struct drm_display_mode * native_mode)353 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
354 struct drm_crtc_state *crtc_state,
355 struct drm_connector_state *conn_state,
356 struct drm_display_mode *native_mode)
357 {
358 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
359 struct drm_display_mode *mode = &crtc_state->mode;
360 struct drm_connector *connector = conn_state->connector;
361 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
362 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
363
364 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
365 asyc->scaler.full = false;
366 if (!native_mode)
367 return 0;
368
369 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
370 switch (connector->connector_type) {
371 case DRM_MODE_CONNECTOR_LVDS:
372 case DRM_MODE_CONNECTOR_eDP:
373 /* Don't force scaler for EDID modes with
374 * same size as the native one (e.g. different
375 * refresh rate)
376 */
377 if (mode->hdisplay == native_mode->hdisplay &&
378 mode->vdisplay == native_mode->vdisplay &&
379 mode->type & DRM_MODE_TYPE_DRIVER)
380 break;
381 mode = native_mode;
382 asyc->scaler.full = true;
383 break;
384 default:
385 break;
386 }
387 } else {
388 mode = native_mode;
389 }
390
391 if (!drm_mode_equal(adjusted_mode, mode)) {
392 drm_mode_copy(adjusted_mode, mode);
393 crtc_state->mode_changed = true;
394 }
395
396 return 0;
397 }
398
399 static void
nv50_outp_atomic_fix_depth(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state)400 nv50_outp_atomic_fix_depth(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state)
401 {
402 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
403 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
404 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
405 unsigned int max_rate, mode_rate;
406
407 switch (nv_encoder->dcb->type) {
408 case DCB_OUTPUT_DP:
409 max_rate = nv_encoder->dp.link_nr * nv_encoder->dp.link_bw;
410
411 /* we don't support more than 10 anyway */
412 asyh->or.bpc = min_t(u8, asyh->or.bpc, 10);
413
414 /* reduce the bpc until it works out */
415 while (asyh->or.bpc > 6) {
416 mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8);
417 if (mode_rate <= max_rate)
418 break;
419
420 asyh->or.bpc -= 2;
421 }
422 break;
423 default:
424 break;
425 }
426 }
427
428 static int
nv50_outp_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)429 nv50_outp_atomic_check(struct drm_encoder *encoder,
430 struct drm_crtc_state *crtc_state,
431 struct drm_connector_state *conn_state)
432 {
433 struct drm_connector *connector = conn_state->connector;
434 struct nouveau_connector *nv_connector = nouveau_connector(connector);
435 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
436 int ret;
437
438 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
439 nv_connector->native_mode);
440 if (ret)
441 return ret;
442
443 if (crtc_state->mode_changed || crtc_state->connectors_changed)
444 asyh->or.bpc = connector->display_info.bpc;
445
446 /* We might have to reduce the bpc */
447 nv50_outp_atomic_fix_depth(encoder, crtc_state);
448
449 return 0;
450 }
451
452 struct nouveau_connector *
nv50_outp_get_new_connector(struct nouveau_encoder * outp,struct drm_atomic_state * state)453 nv50_outp_get_new_connector(struct nouveau_encoder *outp,
454 struct drm_atomic_state *state)
455 {
456 struct drm_connector *connector;
457 struct drm_connector_state *connector_state;
458 struct drm_encoder *encoder = to_drm_encoder(outp);
459 int i;
460
461 for_each_new_connector_in_state(state, connector, connector_state, i) {
462 if (connector_state->best_encoder == encoder)
463 return nouveau_connector(connector);
464 }
465
466 return NULL;
467 }
468
469 struct nouveau_connector *
nv50_outp_get_old_connector(struct nouveau_encoder * outp,struct drm_atomic_state * state)470 nv50_outp_get_old_connector(struct nouveau_encoder *outp,
471 struct drm_atomic_state *state)
472 {
473 struct drm_connector *connector;
474 struct drm_connector_state *connector_state;
475 struct drm_encoder *encoder = to_drm_encoder(outp);
476 int i;
477
478 for_each_old_connector_in_state(state, connector, connector_state, i) {
479 if (connector_state->best_encoder == encoder)
480 return nouveau_connector(connector);
481 }
482
483 return NULL;
484 }
485
486 /******************************************************************************
487 * DAC
488 *****************************************************************************/
489 static void
nv50_dac_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)490 nv50_dac_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
491 {
492 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
493 struct nv50_core *core = nv50_disp(encoder->dev)->core;
494 const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE);
495 if (nv_encoder->crtc)
496 core->func->dac->ctrl(core, nv_encoder->or, ctrl, NULL);
497 nv_encoder->crtc = NULL;
498 nv50_outp_release(nv_encoder);
499 }
500
501 static void
nv50_dac_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)502 nv50_dac_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
503 {
504 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
505 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
506 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
507 struct nv50_core *core = nv50_disp(encoder->dev)->core;
508 u32 ctrl = 0;
509
510 switch (nv_crtc->index) {
511 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break;
512 case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break;
513 case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break;
514 case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break;
515 default:
516 WARN_ON(1);
517 break;
518 }
519
520 ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT);
521
522 nv50_outp_acquire(nv_encoder, false);
523
524 core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh);
525 asyh->or.depth = 0;
526
527 nv_encoder->crtc = encoder->crtc;
528 }
529
530 static enum drm_connector_status
nv50_dac_detect(struct drm_encoder * encoder,struct drm_connector * connector)531 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
532 {
533 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
534 struct nv50_disp *disp = nv50_disp(encoder->dev);
535 struct {
536 struct nv50_disp_mthd_v1 base;
537 struct nv50_disp_dac_load_v0 load;
538 } args = {
539 .base.version = 1,
540 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
541 .base.hasht = nv_encoder->dcb->hasht,
542 .base.hashm = nv_encoder->dcb->hashm,
543 };
544 int ret;
545
546 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
547 if (args.load.data == 0)
548 args.load.data = 340;
549
550 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
551 if (ret || !args.load.load)
552 return connector_status_disconnected;
553
554 return connector_status_connected;
555 }
556
557 static const struct drm_encoder_helper_funcs
558 nv50_dac_help = {
559 .atomic_check = nv50_outp_atomic_check,
560 .atomic_enable = nv50_dac_enable,
561 .atomic_disable = nv50_dac_disable,
562 .detect = nv50_dac_detect
563 };
564
565 static void
nv50_dac_destroy(struct drm_encoder * encoder)566 nv50_dac_destroy(struct drm_encoder *encoder)
567 {
568 drm_encoder_cleanup(encoder);
569 kfree(encoder);
570 }
571
572 static const struct drm_encoder_funcs
573 nv50_dac_func = {
574 .destroy = nv50_dac_destroy,
575 };
576
577 static int
nv50_dac_create(struct drm_connector * connector,struct dcb_output * dcbe)578 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
579 {
580 struct nouveau_drm *drm = nouveau_drm(connector->dev);
581 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
582 struct nvkm_i2c_bus *bus;
583 struct nouveau_encoder *nv_encoder;
584 struct drm_encoder *encoder;
585 int type = DRM_MODE_ENCODER_DAC;
586
587 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
588 if (!nv_encoder)
589 return -ENOMEM;
590 nv_encoder->dcb = dcbe;
591
592 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
593 if (bus)
594 nv_encoder->i2c = &bus->i2c;
595
596 encoder = to_drm_encoder(nv_encoder);
597 encoder->possible_crtcs = dcbe->heads;
598 encoder->possible_clones = 0;
599 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
600 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
601 drm_encoder_helper_add(encoder, &nv50_dac_help);
602
603 drm_connector_attach_encoder(connector, encoder);
604 return 0;
605 }
606
607 /*
608 * audio component binding for ELD notification
609 */
610 static void
nv50_audio_component_eld_notify(struct drm_audio_component * acomp,int port,int dev_id)611 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
612 int dev_id)
613 {
614 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
615 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
616 port, dev_id);
617 }
618
619 static int
nv50_audio_component_get_eld(struct device * kdev,int port,int dev_id,bool * enabled,unsigned char * buf,int max_bytes)620 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
621 bool *enabled, unsigned char *buf, int max_bytes)
622 {
623 struct drm_device *drm_dev = dev_get_drvdata(kdev);
624 struct nouveau_drm *drm = nouveau_drm(drm_dev);
625 struct drm_encoder *encoder;
626 struct nouveau_encoder *nv_encoder;
627 struct drm_connector *connector;
628 struct nouveau_crtc *nv_crtc;
629 struct drm_connector_list_iter conn_iter;
630 int ret = 0;
631
632 *enabled = false;
633
634 drm_for_each_encoder(encoder, drm->dev) {
635 struct nouveau_connector *nv_connector = NULL;
636
637 nv_encoder = nouveau_encoder(encoder);
638
639 drm_connector_list_iter_begin(drm_dev, &conn_iter);
640 drm_for_each_connector_iter(connector, &conn_iter) {
641 if (connector->state->best_encoder == encoder) {
642 nv_connector = nouveau_connector(connector);
643 break;
644 }
645 }
646 drm_connector_list_iter_end(&conn_iter);
647 if (!nv_connector)
648 continue;
649
650 nv_crtc = nouveau_crtc(encoder->crtc);
651 if (!nv_crtc || nv_encoder->or != port ||
652 nv_crtc->index != dev_id)
653 continue;
654 *enabled = nv_encoder->audio;
655 if (*enabled) {
656 ret = drm_eld_size(nv_connector->base.eld);
657 memcpy(buf, nv_connector->base.eld,
658 min(max_bytes, ret));
659 }
660 break;
661 }
662
663 return ret;
664 }
665
666 static const struct drm_audio_component_ops nv50_audio_component_ops = {
667 .get_eld = nv50_audio_component_get_eld,
668 };
669
670 static int
nv50_audio_component_bind(struct device * kdev,struct device * hda_kdev,void * data)671 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev,
672 void *data)
673 {
674 struct drm_device *drm_dev = dev_get_drvdata(kdev);
675 struct nouveau_drm *drm = nouveau_drm(drm_dev);
676 struct drm_audio_component *acomp = data;
677
678 if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
679 return -ENOMEM;
680
681 drm_modeset_lock_all(drm_dev);
682 acomp->ops = &nv50_audio_component_ops;
683 acomp->dev = kdev;
684 drm->audio.component = acomp;
685 drm_modeset_unlock_all(drm_dev);
686 return 0;
687 }
688
689 static void
nv50_audio_component_unbind(struct device * kdev,struct device * hda_kdev,void * data)690 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev,
691 void *data)
692 {
693 struct drm_device *drm_dev = dev_get_drvdata(kdev);
694 struct nouveau_drm *drm = nouveau_drm(drm_dev);
695 struct drm_audio_component *acomp = data;
696
697 drm_modeset_lock_all(drm_dev);
698 drm->audio.component = NULL;
699 acomp->ops = NULL;
700 acomp->dev = NULL;
701 drm_modeset_unlock_all(drm_dev);
702 }
703
704 static const struct component_ops nv50_audio_component_bind_ops = {
705 .bind = nv50_audio_component_bind,
706 .unbind = nv50_audio_component_unbind,
707 };
708
709 static void
nv50_audio_component_init(struct nouveau_drm * drm)710 nv50_audio_component_init(struct nouveau_drm *drm)
711 {
712 if (!component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
713 drm->audio.component_registered = true;
714 }
715
716 static void
nv50_audio_component_fini(struct nouveau_drm * drm)717 nv50_audio_component_fini(struct nouveau_drm *drm)
718 {
719 if (drm->audio.component_registered) {
720 component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
721 drm->audio.component_registered = false;
722 }
723 }
724
725 /******************************************************************************
726 * Audio
727 *****************************************************************************/
728 static void
nv50_audio_disable(struct drm_encoder * encoder,struct nouveau_crtc * nv_crtc)729 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
730 {
731 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
732 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
733 struct nv50_disp *disp = nv50_disp(encoder->dev);
734 struct {
735 struct nv50_disp_mthd_v1 base;
736 struct nv50_disp_sor_hda_eld_v0 eld;
737 } args = {
738 .base.version = 1,
739 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
740 .base.hasht = nv_encoder->dcb->hasht,
741 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
742 (0x0100 << nv_crtc->index),
743 };
744
745 if (!nv_encoder->audio)
746 return;
747
748 nv_encoder->audio = false;
749 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
750
751 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
752 nv_crtc->index);
753 }
754
755 static void
nv50_audio_enable(struct drm_encoder * encoder,struct drm_atomic_state * state,struct drm_display_mode * mode)756 nv50_audio_enable(struct drm_encoder *encoder, struct drm_atomic_state *state,
757 struct drm_display_mode *mode)
758 {
759 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
760 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
761 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
762 struct nouveau_connector *nv_connector;
763 struct nv50_disp *disp = nv50_disp(encoder->dev);
764 struct __packed {
765 struct {
766 struct nv50_disp_mthd_v1 mthd;
767 struct nv50_disp_sor_hda_eld_v0 eld;
768 } base;
769 u8 data[sizeof(nv_connector->base.eld)];
770 } args = {
771 .base.mthd.version = 1,
772 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
773 .base.mthd.hasht = nv_encoder->dcb->hasht,
774 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
775 (0x0100 << nv_crtc->index),
776 };
777
778 nv_connector = nv50_outp_get_new_connector(nv_encoder, state);
779 if (!drm_detect_monitor_audio(nv_connector->edid))
780 return;
781
782 memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
783
784 nvif_mthd(&disp->disp->object, 0, &args,
785 sizeof(args.base) + drm_eld_size(args.data));
786 nv_encoder->audio = true;
787
788 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
789 nv_crtc->index);
790 }
791
792 /******************************************************************************
793 * HDMI
794 *****************************************************************************/
795 static void
nv50_hdmi_disable(struct drm_encoder * encoder,struct nouveau_crtc * nv_crtc)796 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
797 {
798 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
799 struct nv50_disp *disp = nv50_disp(encoder->dev);
800 struct {
801 struct nv50_disp_mthd_v1 base;
802 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
803 } args = {
804 .base.version = 1,
805 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
806 .base.hasht = nv_encoder->dcb->hasht,
807 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
808 (0x0100 << nv_crtc->index),
809 };
810
811 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
812 }
813
814 static void
nv50_hdmi_enable(struct drm_encoder * encoder,struct drm_atomic_state * state,struct drm_display_mode * mode)815 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_atomic_state *state,
816 struct drm_display_mode *mode)
817 {
818 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
819 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
820 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
821 struct nv50_disp *disp = nv50_disp(encoder->dev);
822 struct {
823 struct nv50_disp_mthd_v1 base;
824 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
825 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
826 } args = {
827 .base.version = 1,
828 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
829 .base.hasht = nv_encoder->dcb->hasht,
830 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
831 (0x0100 << nv_crtc->index),
832 .pwr.state = 1,
833 .pwr.rekey = 56, /* binary driver, and tegra, constant */
834 };
835 struct nouveau_connector *nv_connector;
836 struct drm_hdmi_info *hdmi;
837 u32 max_ac_packet;
838 union hdmi_infoframe avi_frame;
839 union hdmi_infoframe vendor_frame;
840 bool high_tmds_clock_ratio = false, scrambling = false;
841 u8 config;
842 int ret;
843 int size;
844
845 nv_connector = nv50_outp_get_new_connector(nv_encoder, state);
846 if (!drm_detect_hdmi_monitor(nv_connector->edid))
847 return;
848
849 hdmi = &nv_connector->base.display_info.hdmi;
850
851 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
852 &nv_connector->base, mode);
853 if (!ret) {
854 /* We have an AVI InfoFrame, populate it to the display */
855 args.pwr.avi_infoframe_length
856 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
857 }
858
859 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
860 &nv_connector->base, mode);
861 if (!ret) {
862 /* We have a Vendor InfoFrame, populate it to the display */
863 args.pwr.vendor_infoframe_length
864 = hdmi_infoframe_pack(&vendor_frame,
865 args.infoframes
866 + args.pwr.avi_infoframe_length,
867 17);
868 }
869
870 max_ac_packet = mode->htotal - mode->hdisplay;
871 max_ac_packet -= args.pwr.rekey;
872 max_ac_packet -= 18; /* constant from tegra */
873 args.pwr.max_ac_packet = max_ac_packet / 32;
874
875 if (hdmi->scdc.scrambling.supported) {
876 high_tmds_clock_ratio = mode->clock > 340000;
877 scrambling = high_tmds_clock_ratio ||
878 hdmi->scdc.scrambling.low_rates;
879 }
880
881 args.pwr.scdc =
882 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
883 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
884
885 size = sizeof(args.base)
886 + sizeof(args.pwr)
887 + args.pwr.avi_infoframe_length
888 + args.pwr.vendor_infoframe_length;
889 nvif_mthd(&disp->disp->object, 0, &args, size);
890
891 nv50_audio_enable(encoder, state, mode);
892
893 /* If SCDC is supported by the downstream monitor, update
894 * divider / scrambling settings to what we programmed above.
895 */
896 if (!hdmi->scdc.scrambling.supported)
897 return;
898
899 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
900 if (ret < 0) {
901 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
902 return;
903 }
904 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
905 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
906 config |= SCDC_SCRAMBLING_ENABLE * scrambling;
907 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
908 if (ret < 0)
909 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
910 config, ret);
911 }
912
913 /******************************************************************************
914 * MST
915 *****************************************************************************/
916 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
917 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
918 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
919
920 struct nv50_mstc {
921 struct nv50_mstm *mstm;
922 struct drm_dp_mst_port *port;
923 struct drm_connector connector;
924
925 struct drm_display_mode *native;
926 struct edid *edid;
927 };
928
929 struct nv50_msto {
930 struct drm_encoder encoder;
931
932 struct nv50_head *head;
933 struct nv50_mstc *mstc;
934 bool disabled;
935 };
936
nv50_real_outp(struct drm_encoder * encoder)937 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder)
938 {
939 struct nv50_msto *msto;
940
941 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
942 return nouveau_encoder(encoder);
943
944 msto = nv50_msto(encoder);
945 if (!msto->mstc)
946 return NULL;
947 return msto->mstc->mstm->outp;
948 }
949
950 static struct drm_dp_payload *
nv50_msto_payload(struct nv50_msto * msto)951 nv50_msto_payload(struct nv50_msto *msto)
952 {
953 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
954 struct nv50_mstc *mstc = msto->mstc;
955 struct nv50_mstm *mstm = mstc->mstm;
956 int vcpi = mstc->port->vcpi.vcpi, i;
957
958 WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
959
960 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
961 for (i = 0; i < mstm->mgr.max_payloads; i++) {
962 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
963 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
964 mstm->outp->base.base.name, i, payload->vcpi,
965 payload->start_slot, payload->num_slots);
966 }
967
968 for (i = 0; i < mstm->mgr.max_payloads; i++) {
969 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
970 if (payload->vcpi == vcpi)
971 return payload;
972 }
973
974 return NULL;
975 }
976
977 static void
nv50_msto_cleanup(struct nv50_msto * msto)978 nv50_msto_cleanup(struct nv50_msto *msto)
979 {
980 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
981 struct nv50_mstc *mstc = msto->mstc;
982 struct nv50_mstm *mstm = mstc->mstm;
983
984 if (!msto->disabled)
985 return;
986
987 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
988
989 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
990
991 msto->mstc = NULL;
992 msto->disabled = false;
993 }
994
995 static void
nv50_msto_prepare(struct nv50_msto * msto)996 nv50_msto_prepare(struct nv50_msto *msto)
997 {
998 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
999 struct nv50_mstc *mstc = msto->mstc;
1000 struct nv50_mstm *mstm = mstc->mstm;
1001 struct {
1002 struct nv50_disp_mthd_v1 base;
1003 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
1004 } args = {
1005 .base.version = 1,
1006 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
1007 .base.hasht = mstm->outp->dcb->hasht,
1008 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) |
1009 (0x0100 << msto->head->base.index),
1010 };
1011
1012 mutex_lock(&mstm->mgr.payload_lock);
1013
1014 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
1015 if (mstc->port->vcpi.vcpi > 0) {
1016 struct drm_dp_payload *payload = nv50_msto_payload(msto);
1017 if (payload) {
1018 args.vcpi.start_slot = payload->start_slot;
1019 args.vcpi.num_slots = payload->num_slots;
1020 args.vcpi.pbn = mstc->port->vcpi.pbn;
1021 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
1022 }
1023 }
1024
1025 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
1026 msto->encoder.name, msto->head->base.base.name,
1027 args.vcpi.start_slot, args.vcpi.num_slots,
1028 args.vcpi.pbn, args.vcpi.aligned_pbn);
1029
1030 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
1031 mutex_unlock(&mstm->mgr.payload_lock);
1032 }
1033
1034 static int
nv50_msto_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1035 nv50_msto_atomic_check(struct drm_encoder *encoder,
1036 struct drm_crtc_state *crtc_state,
1037 struct drm_connector_state *conn_state)
1038 {
1039 struct drm_atomic_state *state = crtc_state->state;
1040 struct drm_connector *connector = conn_state->connector;
1041 struct nv50_mstc *mstc = nv50_mstc(connector);
1042 struct nv50_mstm *mstm = mstc->mstm;
1043 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
1044 int slots;
1045 int ret;
1046
1047 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
1048 mstc->native);
1049 if (ret)
1050 return ret;
1051
1052 if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
1053 return 0;
1054
1055 /*
1056 * When restoring duplicated states, we need to make sure that the bw
1057 * remains the same and avoid recalculating it, as the connector's bpc
1058 * may have changed after the state was duplicated
1059 */
1060 if (!state->duplicated) {
1061 const int clock = crtc_state->adjusted_mode.clock;
1062
1063 asyh->or.bpc = connector->display_info.bpc;
1064 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
1065 false);
1066 }
1067
1068 slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
1069 asyh->dp.pbn, 0);
1070 if (slots < 0)
1071 return slots;
1072
1073 asyh->dp.tu = slots;
1074
1075 return 0;
1076 }
1077
1078 static u8
nv50_dp_bpc_to_depth(unsigned int bpc)1079 nv50_dp_bpc_to_depth(unsigned int bpc)
1080 {
1081 switch (bpc) {
1082 case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444;
1083 case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444;
1084 case 10:
1085 default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444;
1086 }
1087 }
1088
1089 static void
nv50_msto_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1090 nv50_msto_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1091 {
1092 struct nv50_head *head = nv50_head(encoder->crtc);
1093 struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
1094 struct nv50_msto *msto = nv50_msto(encoder);
1095 struct nv50_mstc *mstc = NULL;
1096 struct nv50_mstm *mstm = NULL;
1097 struct drm_connector *connector;
1098 struct drm_connector_list_iter conn_iter;
1099 u8 proto;
1100 bool r;
1101
1102 drm_connector_list_iter_begin(encoder->dev, &conn_iter);
1103 drm_for_each_connector_iter(connector, &conn_iter) {
1104 if (connector->state->best_encoder == &msto->encoder) {
1105 mstc = nv50_mstc(connector);
1106 mstm = mstc->mstm;
1107 break;
1108 }
1109 }
1110 drm_connector_list_iter_end(&conn_iter);
1111
1112 if (WARN_ON(!mstc))
1113 return;
1114
1115 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
1116 armh->dp.tu);
1117 if (!r)
1118 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
1119
1120 if (!mstm->links++)
1121 nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/);
1122
1123 if (mstm->outp->link & 1)
1124 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1125 else
1126 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1127
1128 mstm->outp->update(mstm->outp, head->base.index, armh, proto,
1129 nv50_dp_bpc_to_depth(armh->or.bpc));
1130
1131 msto->mstc = mstc;
1132 mstm->modified = true;
1133 }
1134
1135 static void
nv50_msto_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)1136 nv50_msto_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1137 {
1138 struct nv50_msto *msto = nv50_msto(encoder);
1139 struct nv50_mstc *mstc = msto->mstc;
1140 struct nv50_mstm *mstm = mstc->mstm;
1141
1142 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
1143
1144 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
1145 mstm->modified = true;
1146 if (!--mstm->links)
1147 mstm->disabled = true;
1148 msto->disabled = true;
1149 }
1150
1151 static const struct drm_encoder_helper_funcs
1152 nv50_msto_help = {
1153 .atomic_disable = nv50_msto_disable,
1154 .atomic_enable = nv50_msto_enable,
1155 .atomic_check = nv50_msto_atomic_check,
1156 };
1157
1158 static void
nv50_msto_destroy(struct drm_encoder * encoder)1159 nv50_msto_destroy(struct drm_encoder *encoder)
1160 {
1161 struct nv50_msto *msto = nv50_msto(encoder);
1162 drm_encoder_cleanup(&msto->encoder);
1163 kfree(msto);
1164 }
1165
1166 static const struct drm_encoder_funcs
1167 nv50_msto = {
1168 .destroy = nv50_msto_destroy,
1169 };
1170
1171 static struct nv50_msto *
nv50_msto_new(struct drm_device * dev,struct nv50_head * head,int id)1172 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id)
1173 {
1174 struct nv50_msto *msto;
1175 int ret;
1176
1177 msto = kzalloc(sizeof(*msto), GFP_KERNEL);
1178 if (!msto)
1179 return ERR_PTR(-ENOMEM);
1180
1181 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
1182 DRM_MODE_ENCODER_DPMST, "mst-%d", id);
1183 if (ret) {
1184 kfree(msto);
1185 return ERR_PTR(ret);
1186 }
1187
1188 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
1189 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
1190 msto->head = head;
1191 return msto;
1192 }
1193
1194 static struct drm_encoder *
nv50_mstc_atomic_best_encoder(struct drm_connector * connector,struct drm_connector_state * connector_state)1195 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
1196 struct drm_connector_state *connector_state)
1197 {
1198 struct nv50_mstc *mstc = nv50_mstc(connector);
1199 struct drm_crtc *crtc = connector_state->crtc;
1200
1201 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1202 return NULL;
1203
1204 return &nv50_head(crtc)->msto->encoder;
1205 }
1206
1207 static enum drm_mode_status
nv50_mstc_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1208 nv50_mstc_mode_valid(struct drm_connector *connector,
1209 struct drm_display_mode *mode)
1210 {
1211 struct nv50_mstc *mstc = nv50_mstc(connector);
1212 struct nouveau_encoder *outp = mstc->mstm->outp;
1213
1214 /* TODO: calculate the PBN from the dotclock and validate against the
1215 * MSTB's max possible PBN
1216 */
1217
1218 return nv50_dp_mode_valid(connector, outp, mode, NULL);
1219 }
1220
1221 static int
nv50_mstc_get_modes(struct drm_connector * connector)1222 nv50_mstc_get_modes(struct drm_connector *connector)
1223 {
1224 struct nv50_mstc *mstc = nv50_mstc(connector);
1225 int ret = 0;
1226
1227 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
1228 drm_connector_update_edid_property(&mstc->connector, mstc->edid);
1229 if (mstc->edid)
1230 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
1231
1232 /*
1233 * XXX: Since we don't use HDR in userspace quite yet, limit the bpc
1234 * to 8 to save bandwidth on the topology. In the future, we'll want
1235 * to properly fix this by dynamically selecting the highest possible
1236 * bpc that would fit in the topology
1237 */
1238 if (connector->display_info.bpc)
1239 connector->display_info.bpc =
1240 clamp(connector->display_info.bpc, 6U, 8U);
1241 else
1242 connector->display_info.bpc = 8;
1243
1244 if (mstc->native)
1245 drm_mode_destroy(mstc->connector.dev, mstc->native);
1246 mstc->native = nouveau_conn_native_mode(&mstc->connector);
1247 return ret;
1248 }
1249
1250 static int
nv50_mstc_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)1251 nv50_mstc_atomic_check(struct drm_connector *connector,
1252 struct drm_atomic_state *state)
1253 {
1254 struct nv50_mstc *mstc = nv50_mstc(connector);
1255 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
1256 struct drm_connector_state *new_conn_state =
1257 drm_atomic_get_new_connector_state(state, connector);
1258 struct drm_connector_state *old_conn_state =
1259 drm_atomic_get_old_connector_state(state, connector);
1260 struct drm_crtc_state *crtc_state;
1261 struct drm_crtc *new_crtc = new_conn_state->crtc;
1262
1263 if (!old_conn_state->crtc)
1264 return 0;
1265
1266 /* We only want to free VCPI if this state disables the CRTC on this
1267 * connector
1268 */
1269 if (new_crtc) {
1270 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
1271
1272 if (!crtc_state ||
1273 !drm_atomic_crtc_needs_modeset(crtc_state) ||
1274 crtc_state->enable)
1275 return 0;
1276 }
1277
1278 return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
1279 }
1280
1281 static int
nv50_mstc_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)1282 nv50_mstc_detect(struct drm_connector *connector,
1283 struct drm_modeset_acquire_ctx *ctx, bool force)
1284 {
1285 struct nv50_mstc *mstc = nv50_mstc(connector);
1286 int ret;
1287
1288 if (drm_connector_is_unregistered(connector))
1289 return connector_status_disconnected;
1290
1291 ret = pm_runtime_get_sync(connector->dev->dev);
1292 if (ret < 0 && ret != -EACCES) {
1293 pm_runtime_put_autosuspend(connector->dev->dev);
1294 return connector_status_disconnected;
1295 }
1296
1297 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1298 mstc->port);
1299 if (ret != connector_status_connected)
1300 goto out;
1301
1302 out:
1303 pm_runtime_mark_last_busy(connector->dev->dev);
1304 pm_runtime_put_autosuspend(connector->dev->dev);
1305 return ret;
1306 }
1307
1308 static const struct drm_connector_helper_funcs
1309 nv50_mstc_help = {
1310 .get_modes = nv50_mstc_get_modes,
1311 .mode_valid = nv50_mstc_mode_valid,
1312 .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1313 .atomic_check = nv50_mstc_atomic_check,
1314 .detect_ctx = nv50_mstc_detect,
1315 };
1316
1317 static void
nv50_mstc_destroy(struct drm_connector * connector)1318 nv50_mstc_destroy(struct drm_connector *connector)
1319 {
1320 struct nv50_mstc *mstc = nv50_mstc(connector);
1321
1322 drm_connector_cleanup(&mstc->connector);
1323 drm_dp_mst_put_port_malloc(mstc->port);
1324
1325 kfree(mstc);
1326 }
1327
1328 static const struct drm_connector_funcs
1329 nv50_mstc = {
1330 .reset = nouveau_conn_reset,
1331 .fill_modes = drm_helper_probe_single_connector_modes,
1332 .destroy = nv50_mstc_destroy,
1333 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1334 .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1335 .atomic_set_property = nouveau_conn_atomic_set_property,
1336 .atomic_get_property = nouveau_conn_atomic_get_property,
1337 };
1338
1339 static int
nv50_mstc_new(struct nv50_mstm * mstm,struct drm_dp_mst_port * port,const char * path,struct nv50_mstc ** pmstc)1340 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1341 const char *path, struct nv50_mstc **pmstc)
1342 {
1343 struct drm_device *dev = mstm->outp->base.base.dev;
1344 struct drm_crtc *crtc;
1345 struct nv50_mstc *mstc;
1346 int ret;
1347
1348 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1349 return -ENOMEM;
1350 mstc->mstm = mstm;
1351 mstc->port = port;
1352
1353 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1354 DRM_MODE_CONNECTOR_DisplayPort);
1355 if (ret) {
1356 kfree(*pmstc);
1357 *pmstc = NULL;
1358 return ret;
1359 }
1360
1361 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1362
1363 mstc->connector.funcs->reset(&mstc->connector);
1364 nouveau_conn_attach_properties(&mstc->connector);
1365
1366 drm_for_each_crtc(crtc, dev) {
1367 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1368 continue;
1369
1370 drm_connector_attach_encoder(&mstc->connector,
1371 &nv50_head(crtc)->msto->encoder);
1372 }
1373
1374 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1375 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1376 drm_connector_set_path_property(&mstc->connector, path);
1377 drm_dp_mst_get_port_malloc(port);
1378 return 0;
1379 }
1380
1381 static void
nv50_mstm_cleanup(struct nv50_mstm * mstm)1382 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1383 {
1384 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1385 struct drm_encoder *encoder;
1386 int ret;
1387
1388 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1389 ret = drm_dp_check_act_status(&mstm->mgr);
1390
1391 ret = drm_dp_update_payload_part2(&mstm->mgr);
1392
1393 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1394 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1395 struct nv50_msto *msto = nv50_msto(encoder);
1396 struct nv50_mstc *mstc = msto->mstc;
1397 if (mstc && mstc->mstm == mstm)
1398 nv50_msto_cleanup(msto);
1399 }
1400 }
1401
1402 mstm->modified = false;
1403 }
1404
1405 static void
nv50_mstm_prepare(struct nv50_mstm * mstm)1406 nv50_mstm_prepare(struct nv50_mstm *mstm)
1407 {
1408 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1409 struct drm_encoder *encoder;
1410 int ret;
1411
1412 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1413 ret = drm_dp_update_payload_part1(&mstm->mgr);
1414
1415 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1416 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1417 struct nv50_msto *msto = nv50_msto(encoder);
1418 struct nv50_mstc *mstc = msto->mstc;
1419 if (mstc && mstc->mstm == mstm)
1420 nv50_msto_prepare(msto);
1421 }
1422 }
1423
1424 if (mstm->disabled) {
1425 if (!mstm->links)
1426 nv50_outp_release(mstm->outp);
1427 mstm->disabled = false;
1428 }
1429 }
1430
1431 static struct drm_connector *
nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr * mgr,struct drm_dp_mst_port * port,const char * path)1432 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1433 struct drm_dp_mst_port *port, const char *path)
1434 {
1435 struct nv50_mstm *mstm = nv50_mstm(mgr);
1436 struct nv50_mstc *mstc;
1437 int ret;
1438
1439 ret = nv50_mstc_new(mstm, port, path, &mstc);
1440 if (ret)
1441 return NULL;
1442
1443 return &mstc->connector;
1444 }
1445
1446 static const struct drm_dp_mst_topology_cbs
1447 nv50_mstm = {
1448 .add_connector = nv50_mstm_add_connector,
1449 };
1450
1451 bool
nv50_mstm_service(struct nouveau_drm * drm,struct nouveau_connector * nv_connector,struct nv50_mstm * mstm)1452 nv50_mstm_service(struct nouveau_drm *drm,
1453 struct nouveau_connector *nv_connector,
1454 struct nv50_mstm *mstm)
1455 {
1456 struct drm_dp_aux *aux = &nv_connector->aux;
1457 bool handled = true, ret = true;
1458 int rc;
1459 u8 esi[8] = {};
1460
1461 while (handled) {
1462 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1463 if (rc != 8) {
1464 ret = false;
1465 break;
1466 }
1467
1468 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1469 if (!handled)
1470 break;
1471
1472 rc = drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1],
1473 3);
1474 if (rc != 3) {
1475 ret = false;
1476 break;
1477 }
1478 }
1479
1480 if (!ret)
1481 NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n",
1482 nv_connector->base.name, rc);
1483
1484 return ret;
1485 }
1486
1487 void
nv50_mstm_remove(struct nv50_mstm * mstm)1488 nv50_mstm_remove(struct nv50_mstm *mstm)
1489 {
1490 mstm->is_mst = false;
1491 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1492 }
1493
1494 static int
nv50_mstm_enable(struct nv50_mstm * mstm,int state)1495 nv50_mstm_enable(struct nv50_mstm *mstm, int state)
1496 {
1497 struct nouveau_encoder *outp = mstm->outp;
1498 struct {
1499 struct nv50_disp_mthd_v1 base;
1500 struct nv50_disp_sor_dp_mst_link_v0 mst;
1501 } args = {
1502 .base.version = 1,
1503 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1504 .base.hasht = outp->dcb->hasht,
1505 .base.hashm = outp->dcb->hashm,
1506 .mst.state = state,
1507 };
1508 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1509 struct nvif_object *disp = &drm->display->disp.object;
1510
1511 return nvif_mthd(disp, 0, &args, sizeof(args));
1512 }
1513
1514 int
nv50_mstm_detect(struct nouveau_encoder * outp)1515 nv50_mstm_detect(struct nouveau_encoder *outp)
1516 {
1517 struct nv50_mstm *mstm = outp->dp.mstm;
1518 struct drm_dp_aux *aux;
1519 int ret;
1520
1521 if (!mstm || !mstm->can_mst)
1522 return 0;
1523
1524 aux = mstm->mgr.aux;
1525
1526 /* Clear any leftover MST state we didn't set ourselves by first
1527 * disabling MST if it was already enabled
1528 */
1529 ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1530 if (ret < 0)
1531 return ret;
1532
1533 /* And start enabling */
1534 ret = nv50_mstm_enable(mstm, true);
1535 if (ret)
1536 return ret;
1537
1538 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true);
1539 if (ret) {
1540 nv50_mstm_enable(mstm, false);
1541 return ret;
1542 }
1543
1544 mstm->is_mst = true;
1545 return 1;
1546 }
1547
1548 static void
nv50_mstm_fini(struct nouveau_encoder * outp)1549 nv50_mstm_fini(struct nouveau_encoder *outp)
1550 {
1551 struct nv50_mstm *mstm = outp->dp.mstm;
1552
1553 if (!mstm)
1554 return;
1555
1556 /* Don't change the MST state of this connector until we've finished
1557 * resuming, since we can't safely grab hpd_irq_lock in our resume
1558 * path to protect mstm->is_mst without potentially deadlocking
1559 */
1560 mutex_lock(&outp->dp.hpd_irq_lock);
1561 mstm->suspended = true;
1562 mutex_unlock(&outp->dp.hpd_irq_lock);
1563
1564 if (mstm->is_mst)
1565 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1566 }
1567
1568 static void
nv50_mstm_init(struct nouveau_encoder * outp,bool runtime)1569 nv50_mstm_init(struct nouveau_encoder *outp, bool runtime)
1570 {
1571 struct nv50_mstm *mstm = outp->dp.mstm;
1572 int ret = 0;
1573
1574 if (!mstm)
1575 return;
1576
1577 if (mstm->is_mst) {
1578 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1579 if (ret == -1)
1580 nv50_mstm_remove(mstm);
1581 }
1582
1583 mutex_lock(&outp->dp.hpd_irq_lock);
1584 mstm->suspended = false;
1585 mutex_unlock(&outp->dp.hpd_irq_lock);
1586
1587 if (ret == -1)
1588 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1589 }
1590
1591 static void
nv50_mstm_del(struct nv50_mstm ** pmstm)1592 nv50_mstm_del(struct nv50_mstm **pmstm)
1593 {
1594 struct nv50_mstm *mstm = *pmstm;
1595 if (mstm) {
1596 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1597 kfree(*pmstm);
1598 *pmstm = NULL;
1599 }
1600 }
1601
1602 static int
nv50_mstm_new(struct nouveau_encoder * outp,struct drm_dp_aux * aux,int aux_max,int conn_base_id,struct nv50_mstm ** pmstm)1603 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1604 int conn_base_id, struct nv50_mstm **pmstm)
1605 {
1606 const int max_payloads = hweight8(outp->dcb->heads);
1607 struct drm_device *dev = outp->base.base.dev;
1608 struct nv50_mstm *mstm;
1609 int ret;
1610
1611 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1612 return -ENOMEM;
1613 mstm->outp = outp;
1614 mstm->mgr.cbs = &nv50_mstm;
1615
1616 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1617 max_payloads, conn_base_id);
1618 if (ret)
1619 return ret;
1620
1621 return 0;
1622 }
1623
1624 /******************************************************************************
1625 * SOR
1626 *****************************************************************************/
1627 static void
nv50_sor_update(struct nouveau_encoder * nv_encoder,u8 head,struct nv50_head_atom * asyh,u8 proto,u8 depth)1628 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1629 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1630 {
1631 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1632 struct nv50_core *core = disp->core;
1633
1634 if (!asyh) {
1635 nv_encoder->ctrl &= ~BIT(head);
1636 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE))
1637 nv_encoder->ctrl = 0;
1638 } else {
1639 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto);
1640 nv_encoder->ctrl |= BIT(head);
1641 asyh->or.depth = depth;
1642 }
1643
1644 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1645 }
1646
1647 static void
nv50_sor_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)1648 nv50_sor_disable(struct drm_encoder *encoder,
1649 struct drm_atomic_state *state)
1650 {
1651 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1652 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1653 struct nouveau_connector *nv_connector =
1654 nv50_outp_get_old_connector(nv_encoder, state);
1655
1656 nv_encoder->crtc = NULL;
1657
1658 if (nv_crtc) {
1659 struct drm_dp_aux *aux = &nv_connector->aux;
1660 u8 pwr;
1661
1662 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1663 int ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr);
1664
1665 if (ret == 0) {
1666 pwr &= ~DP_SET_POWER_MASK;
1667 pwr |= DP_SET_POWER_D3;
1668 drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr);
1669 }
1670 }
1671
1672 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1673 nv50_audio_disable(encoder, nv_crtc);
1674 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1675 nv50_outp_release(nv_encoder);
1676 }
1677 }
1678
1679 static void
nv50_sor_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1680 nv50_sor_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1681 {
1682 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1683 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1684 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1685 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1686 struct {
1687 struct nv50_disp_mthd_v1 base;
1688 struct nv50_disp_sor_lvds_script_v0 lvds;
1689 } lvds = {
1690 .base.version = 1,
1691 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1692 .base.hasht = nv_encoder->dcb->hasht,
1693 .base.hashm = nv_encoder->dcb->hashm,
1694 };
1695 struct nv50_disp *disp = nv50_disp(encoder->dev);
1696 struct drm_device *dev = encoder->dev;
1697 struct nouveau_drm *drm = nouveau_drm(dev);
1698 struct nouveau_connector *nv_connector;
1699 struct nvbios *bios = &drm->vbios;
1700 bool hda = false;
1701 u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
1702 u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT;
1703
1704 nv_connector = nv50_outp_get_new_connector(nv_encoder, state);
1705 nv_encoder->crtc = encoder->crtc;
1706
1707 if ((disp->disp->object.oclass == GT214_DISP ||
1708 disp->disp->object.oclass >= GF110_DISP) &&
1709 drm_detect_monitor_audio(nv_connector->edid))
1710 hda = true;
1711 nv50_outp_acquire(nv_encoder, hda);
1712
1713 switch (nv_encoder->dcb->type) {
1714 case DCB_OUTPUT_TMDS:
1715 if (nv_encoder->link & 1) {
1716 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
1717 /* Only enable dual-link if:
1718 * - Need to (i.e. rate > 165MHz)
1719 * - DCB says we can
1720 * - Not an HDMI monitor, since there's no dual-link
1721 * on HDMI.
1722 */
1723 if (mode->clock >= 165000 &&
1724 nv_encoder->dcb->duallink_possible &&
1725 !drm_detect_hdmi_monitor(nv_connector->edid))
1726 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
1727 } else {
1728 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
1729 }
1730
1731 nv50_hdmi_enable(&nv_encoder->base.base, state, mode);
1732 break;
1733 case DCB_OUTPUT_LVDS:
1734 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM;
1735
1736 if (bios->fp_no_ddc) {
1737 if (bios->fp.dual_link)
1738 lvds.lvds.script |= 0x0100;
1739 if (bios->fp.if_is_24bit)
1740 lvds.lvds.script |= 0x0200;
1741 } else {
1742 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1743 if (((u8 *)nv_connector->edid)[121] == 2)
1744 lvds.lvds.script |= 0x0100;
1745 } else
1746 if (mode->clock >= bios->fp.duallink_transition_clk) {
1747 lvds.lvds.script |= 0x0100;
1748 }
1749
1750 if (lvds.lvds.script & 0x0100) {
1751 if (bios->fp.strapless_is_24bit & 2)
1752 lvds.lvds.script |= 0x0200;
1753 } else {
1754 if (bios->fp.strapless_is_24bit & 1)
1755 lvds.lvds.script |= 0x0200;
1756 }
1757
1758 if (asyh->or.bpc == 8)
1759 lvds.lvds.script |= 0x0200;
1760 }
1761
1762 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1763 break;
1764 case DCB_OUTPUT_DP:
1765 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1766
1767 if (nv_encoder->link & 1)
1768 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1769 else
1770 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1771
1772 nv50_audio_enable(encoder, state, mode);
1773 break;
1774 default:
1775 BUG();
1776 break;
1777 }
1778
1779 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1780 }
1781
1782 static const struct drm_encoder_helper_funcs
1783 nv50_sor_help = {
1784 .atomic_check = nv50_outp_atomic_check,
1785 .atomic_enable = nv50_sor_enable,
1786 .atomic_disable = nv50_sor_disable,
1787 };
1788
1789 static void
nv50_sor_destroy(struct drm_encoder * encoder)1790 nv50_sor_destroy(struct drm_encoder *encoder)
1791 {
1792 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1793 nv50_mstm_del(&nv_encoder->dp.mstm);
1794 drm_encoder_cleanup(encoder);
1795
1796 if (nv_encoder->dcb->type == DCB_OUTPUT_DP)
1797 mutex_destroy(&nv_encoder->dp.hpd_irq_lock);
1798
1799 kfree(encoder);
1800 }
1801
1802 static const struct drm_encoder_funcs
1803 nv50_sor_func = {
1804 .destroy = nv50_sor_destroy,
1805 };
1806
nv50_has_mst(struct nouveau_drm * drm)1807 static bool nv50_has_mst(struct nouveau_drm *drm)
1808 {
1809 struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1810 u32 data;
1811 u8 ver, hdr, cnt, len;
1812
1813 data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len);
1814 return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
1815 }
1816
1817 static int
nv50_sor_create(struct drm_connector * connector,struct dcb_output * dcbe)1818 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1819 {
1820 struct nouveau_connector *nv_connector = nouveau_connector(connector);
1821 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1822 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1823 struct nouveau_encoder *nv_encoder;
1824 struct drm_encoder *encoder;
1825 struct nv50_disp *disp = nv50_disp(connector->dev);
1826 int type, ret;
1827
1828 switch (dcbe->type) {
1829 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1830 case DCB_OUTPUT_TMDS:
1831 case DCB_OUTPUT_DP:
1832 default:
1833 type = DRM_MODE_ENCODER_TMDS;
1834 break;
1835 }
1836
1837 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1838 if (!nv_encoder)
1839 return -ENOMEM;
1840 nv_encoder->dcb = dcbe;
1841 nv_encoder->update = nv50_sor_update;
1842
1843 encoder = to_drm_encoder(nv_encoder);
1844 encoder->possible_crtcs = dcbe->heads;
1845 encoder->possible_clones = 0;
1846 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1847 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1848 drm_encoder_helper_add(encoder, &nv50_sor_help);
1849
1850 drm_connector_attach_encoder(connector, encoder);
1851
1852 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1853
1854 if (dcbe->type == DCB_OUTPUT_DP) {
1855 struct nvkm_i2c_aux *aux =
1856 nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1857
1858 mutex_init(&nv_encoder->dp.hpd_irq_lock);
1859
1860 if (aux) {
1861 if (disp->disp->object.oclass < GF110_DISP) {
1862 /* HW has no support for address-only
1863 * transactions, so we're required to
1864 * use custom I2C-over-AUX code.
1865 */
1866 nv_encoder->i2c = &aux->i2c;
1867 } else {
1868 nv_encoder->i2c = &nv_connector->aux.ddc;
1869 }
1870 nv_encoder->aux = aux;
1871 }
1872
1873 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1874 nv50_has_mst(drm)) {
1875 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
1876 16, nv_connector->base.base.id,
1877 &nv_encoder->dp.mstm);
1878 if (ret)
1879 return ret;
1880 }
1881 } else {
1882 struct nvkm_i2c_bus *bus =
1883 nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1884 if (bus)
1885 nv_encoder->i2c = &bus->i2c;
1886 }
1887
1888 return 0;
1889 }
1890
1891 /******************************************************************************
1892 * PIOR
1893 *****************************************************************************/
1894 static int
nv50_pior_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1895 nv50_pior_atomic_check(struct drm_encoder *encoder,
1896 struct drm_crtc_state *crtc_state,
1897 struct drm_connector_state *conn_state)
1898 {
1899 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1900 if (ret)
1901 return ret;
1902 crtc_state->adjusted_mode.clock *= 2;
1903 return 0;
1904 }
1905
1906 static void
nv50_pior_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)1907 nv50_pior_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1908 {
1909 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1910 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1911 const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE);
1912 if (nv_encoder->crtc)
1913 core->func->pior->ctrl(core, nv_encoder->or, ctrl, NULL);
1914 nv_encoder->crtc = NULL;
1915 nv50_outp_release(nv_encoder);
1916 }
1917
1918 static void
nv50_pior_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)1919 nv50_pior_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1920 {
1921 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1922 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1923 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1924 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1925 u32 ctrl = 0;
1926
1927 switch (nv_crtc->index) {
1928 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break;
1929 case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break;
1930 default:
1931 WARN_ON(1);
1932 break;
1933 }
1934
1935 nv50_outp_acquire(nv_encoder, false);
1936
1937 switch (asyh->or.bpc) {
1938 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
1939 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
1940 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
1941 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
1942 }
1943
1944 switch (nv_encoder->dcb->type) {
1945 case DCB_OUTPUT_TMDS:
1946 case DCB_OUTPUT_DP:
1947 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
1948 break;
1949 default:
1950 BUG();
1951 break;
1952 }
1953
1954 core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh);
1955 nv_encoder->crtc = &nv_crtc->base;
1956 }
1957
1958 static const struct drm_encoder_helper_funcs
1959 nv50_pior_help = {
1960 .atomic_check = nv50_pior_atomic_check,
1961 .atomic_enable = nv50_pior_enable,
1962 .atomic_disable = nv50_pior_disable,
1963 };
1964
1965 static void
nv50_pior_destroy(struct drm_encoder * encoder)1966 nv50_pior_destroy(struct drm_encoder *encoder)
1967 {
1968 drm_encoder_cleanup(encoder);
1969 kfree(encoder);
1970 }
1971
1972 static const struct drm_encoder_funcs
1973 nv50_pior_func = {
1974 .destroy = nv50_pior_destroy,
1975 };
1976
1977 static int
nv50_pior_create(struct drm_connector * connector,struct dcb_output * dcbe)1978 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1979 {
1980 struct drm_device *dev = connector->dev;
1981 struct nouveau_drm *drm = nouveau_drm(dev);
1982 struct nv50_disp *disp = nv50_disp(dev);
1983 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1984 struct nvkm_i2c_bus *bus = NULL;
1985 struct nvkm_i2c_aux *aux = NULL;
1986 struct i2c_adapter *ddc;
1987 struct nouveau_encoder *nv_encoder;
1988 struct drm_encoder *encoder;
1989 int type;
1990
1991 switch (dcbe->type) {
1992 case DCB_OUTPUT_TMDS:
1993 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1994 ddc = bus ? &bus->i2c : NULL;
1995 type = DRM_MODE_ENCODER_TMDS;
1996 break;
1997 case DCB_OUTPUT_DP:
1998 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1999 ddc = aux ? &aux->i2c : NULL;
2000 type = DRM_MODE_ENCODER_TMDS;
2001 break;
2002 default:
2003 return -ENODEV;
2004 }
2005
2006 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2007 if (!nv_encoder)
2008 return -ENOMEM;
2009 nv_encoder->dcb = dcbe;
2010 nv_encoder->i2c = ddc;
2011 nv_encoder->aux = aux;
2012
2013 encoder = to_drm_encoder(nv_encoder);
2014 encoder->possible_crtcs = dcbe->heads;
2015 encoder->possible_clones = 0;
2016 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
2017 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
2018 drm_encoder_helper_add(encoder, &nv50_pior_help);
2019
2020 drm_connector_attach_encoder(connector, encoder);
2021
2022 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
2023
2024 return 0;
2025 }
2026
2027 /******************************************************************************
2028 * Atomic
2029 *****************************************************************************/
2030
2031 static void
nv50_disp_atomic_commit_core(struct drm_atomic_state * state,u32 * interlock)2032 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
2033 {
2034 struct nouveau_drm *drm = nouveau_drm(state->dev);
2035 struct nv50_disp *disp = nv50_disp(drm->dev);
2036 struct nv50_core *core = disp->core;
2037 struct nv50_mstm *mstm;
2038 struct drm_encoder *encoder;
2039
2040 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
2041
2042 drm_for_each_encoder(encoder, drm->dev) {
2043 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2044 mstm = nouveau_encoder(encoder)->dp.mstm;
2045 if (mstm && mstm->modified)
2046 nv50_mstm_prepare(mstm);
2047 }
2048 }
2049
2050 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
2051 core->func->update(core, interlock, true);
2052 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
2053 disp->core->chan.base.device))
2054 NV_ERROR(drm, "core notifier timeout\n");
2055
2056 drm_for_each_encoder(encoder, drm->dev) {
2057 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2058 mstm = nouveau_encoder(encoder)->dp.mstm;
2059 if (mstm && mstm->modified)
2060 nv50_mstm_cleanup(mstm);
2061 }
2062 }
2063 }
2064
2065 static void
nv50_disp_atomic_commit_wndw(struct drm_atomic_state * state,u32 * interlock)2066 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
2067 {
2068 struct drm_plane_state *new_plane_state;
2069 struct drm_plane *plane;
2070 int i;
2071
2072 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2073 struct nv50_wndw *wndw = nv50_wndw(plane);
2074 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
2075 if (wndw->func->update)
2076 wndw->func->update(wndw, interlock);
2077 }
2078 }
2079 }
2080
2081 static void
nv50_disp_atomic_commit_tail(struct drm_atomic_state * state)2082 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
2083 {
2084 struct drm_device *dev = state->dev;
2085 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
2086 struct drm_crtc *crtc;
2087 struct drm_plane_state *new_plane_state;
2088 struct drm_plane *plane;
2089 struct nouveau_drm *drm = nouveau_drm(dev);
2090 struct nv50_disp *disp = nv50_disp(dev);
2091 struct nv50_atom *atom = nv50_atom(state);
2092 struct nv50_core *core = disp->core;
2093 struct nv50_outp_atom *outp, *outt;
2094 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
2095 int i;
2096 bool flushed = false;
2097
2098 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
2099 nv50_crc_atomic_stop_reporting(state);
2100 drm_atomic_helper_wait_for_fences(dev, state, false);
2101 drm_atomic_helper_wait_for_dependencies(state);
2102 drm_atomic_helper_update_legacy_modeset_state(dev, state);
2103 drm_atomic_helper_calc_timestamping_constants(state);
2104
2105 if (atom->lock_core)
2106 mutex_lock(&disp->mutex);
2107
2108 /* Disable head(s). */
2109 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2110 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2111 struct nv50_head *head = nv50_head(crtc);
2112
2113 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
2114 asyh->clr.mask, asyh->set.mask);
2115
2116 if (old_crtc_state->active && !new_crtc_state->active) {
2117 pm_runtime_put_noidle(dev->dev);
2118 drm_crtc_vblank_off(crtc);
2119 }
2120
2121 if (asyh->clr.mask) {
2122 nv50_head_flush_clr(head, asyh, atom->flush_disable);
2123 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2124 }
2125 }
2126
2127 /* Disable plane(s). */
2128 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2129 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2130 struct nv50_wndw *wndw = nv50_wndw(plane);
2131
2132 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
2133 asyw->clr.mask, asyw->set.mask);
2134 if (!asyw->clr.mask)
2135 continue;
2136
2137 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
2138 }
2139
2140 /* Disable output path(s). */
2141 list_for_each_entry(outp, &atom->outp, head) {
2142 const struct drm_encoder_helper_funcs *help;
2143 struct drm_encoder *encoder;
2144
2145 encoder = outp->encoder;
2146 help = encoder->helper_private;
2147
2148 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
2149 outp->clr.mask, outp->set.mask);
2150
2151 if (outp->clr.mask) {
2152 help->atomic_disable(encoder, state);
2153 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2154 if (outp->flush_disable) {
2155 nv50_disp_atomic_commit_wndw(state, interlock);
2156 nv50_disp_atomic_commit_core(state, interlock);
2157 memset(interlock, 0x00, sizeof(interlock));
2158
2159 flushed = true;
2160 }
2161 }
2162 }
2163
2164 /* Flush disable. */
2165 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2166 if (atom->flush_disable) {
2167 nv50_disp_atomic_commit_wndw(state, interlock);
2168 nv50_disp_atomic_commit_core(state, interlock);
2169 memset(interlock, 0x00, sizeof(interlock));
2170
2171 flushed = true;
2172 }
2173 }
2174
2175 if (flushed)
2176 nv50_crc_atomic_release_notifier_contexts(state);
2177 nv50_crc_atomic_init_notifier_contexts(state);
2178
2179 /* Update output path(s). */
2180 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2181 const struct drm_encoder_helper_funcs *help;
2182 struct drm_encoder *encoder;
2183
2184 encoder = outp->encoder;
2185 help = encoder->helper_private;
2186
2187 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
2188 outp->set.mask, outp->clr.mask);
2189
2190 if (outp->set.mask) {
2191 help->atomic_enable(encoder, state);
2192 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2193 }
2194
2195 list_del(&outp->head);
2196 kfree(outp);
2197 }
2198
2199 /* Update head(s). */
2200 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2201 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2202 struct nv50_head *head = nv50_head(crtc);
2203
2204 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2205 asyh->set.mask, asyh->clr.mask);
2206
2207 if (asyh->set.mask) {
2208 nv50_head_flush_set(head, asyh);
2209 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2210 }
2211
2212 if (new_crtc_state->active) {
2213 if (!old_crtc_state->active) {
2214 drm_crtc_vblank_on(crtc);
2215 pm_runtime_get_noresume(dev->dev);
2216 }
2217 if (new_crtc_state->event)
2218 drm_crtc_vblank_get(crtc);
2219 }
2220 }
2221
2222 /* Update window->head assignment.
2223 *
2224 * This has to happen in an update that's not interlocked with
2225 * any window channels to avoid hitting HW error checks.
2226 *
2227 *TODO: Proper handling of window ownership (Turing apparently
2228 * supports non-fixed mappings).
2229 */
2230 if (core->assign_windows) {
2231 core->func->wndw.owner(core);
2232 nv50_disp_atomic_commit_core(state, interlock);
2233 core->assign_windows = false;
2234 interlock[NV50_DISP_INTERLOCK_CORE] = 0;
2235 }
2236
2237 /* Finish updating head(s)...
2238 *
2239 * NVD is rather picky about both where window assignments can change,
2240 * *and* about certain core and window channel states matching.
2241 *
2242 * The EFI GOP driver on newer GPUs configures window channels with a
2243 * different output format to what we do, and the core channel update
2244 * in the assign_windows case above would result in a state mismatch.
2245 *
2246 * Delay some of the head update until after that point to workaround
2247 * the issue. This only affects the initial modeset.
2248 *
2249 * TODO: handle this better when adding flexible window mapping
2250 */
2251 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2252 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2253 struct nv50_head *head = nv50_head(crtc);
2254
2255 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2256 asyh->set.mask, asyh->clr.mask);
2257
2258 if (asyh->set.mask) {
2259 nv50_head_flush_set_wndw(head, asyh);
2260 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2261 }
2262 }
2263
2264 /* Update plane(s). */
2265 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2266 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2267 struct nv50_wndw *wndw = nv50_wndw(plane);
2268
2269 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
2270 asyw->set.mask, asyw->clr.mask);
2271 if ( !asyw->set.mask &&
2272 (!asyw->clr.mask || atom->flush_disable))
2273 continue;
2274
2275 nv50_wndw_flush_set(wndw, interlock, asyw);
2276 }
2277
2278 /* Flush update. */
2279 nv50_disp_atomic_commit_wndw(state, interlock);
2280
2281 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2282 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
2283 interlock[NV50_DISP_INTERLOCK_OVLY] ||
2284 interlock[NV50_DISP_INTERLOCK_WNDW] ||
2285 !atom->state.legacy_cursor_update)
2286 nv50_disp_atomic_commit_core(state, interlock);
2287 else
2288 disp->core->func->update(disp->core, interlock, false);
2289 }
2290
2291 if (atom->lock_core)
2292 mutex_unlock(&disp->mutex);
2293
2294 /* Wait for HW to signal completion. */
2295 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2296 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2297 struct nv50_wndw *wndw = nv50_wndw(plane);
2298 int ret = nv50_wndw_wait_armed(wndw, asyw);
2299 if (ret)
2300 NV_ERROR(drm, "%s: timeout\n", plane->name);
2301 }
2302
2303 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2304 if (new_crtc_state->event) {
2305 unsigned long flags;
2306 /* Get correct count/ts if racing with vblank irq */
2307 if (new_crtc_state->active)
2308 drm_crtc_accurate_vblank_count(crtc);
2309 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2310 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
2311 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2312
2313 new_crtc_state->event = NULL;
2314 if (new_crtc_state->active)
2315 drm_crtc_vblank_put(crtc);
2316 }
2317 }
2318
2319 nv50_crc_atomic_start_reporting(state);
2320 if (!flushed)
2321 nv50_crc_atomic_release_notifier_contexts(state);
2322 drm_atomic_helper_commit_hw_done(state);
2323 drm_atomic_helper_cleanup_planes(dev, state);
2324 drm_atomic_helper_commit_cleanup_done(state);
2325 drm_atomic_state_put(state);
2326
2327 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2328 pm_runtime_mark_last_busy(dev->dev);
2329 pm_runtime_put_autosuspend(dev->dev);
2330 }
2331
2332 static void
nv50_disp_atomic_commit_work(struct work_struct * work)2333 nv50_disp_atomic_commit_work(struct work_struct *work)
2334 {
2335 struct drm_atomic_state *state =
2336 container_of(work, typeof(*state), commit_work);
2337 nv50_disp_atomic_commit_tail(state);
2338 }
2339
2340 static int
nv50_disp_atomic_commit(struct drm_device * dev,struct drm_atomic_state * state,bool nonblock)2341 nv50_disp_atomic_commit(struct drm_device *dev,
2342 struct drm_atomic_state *state, bool nonblock)
2343 {
2344 struct drm_plane_state *new_plane_state;
2345 struct drm_plane *plane;
2346 int ret, i;
2347
2348 ret = pm_runtime_get_sync(dev->dev);
2349 if (ret < 0 && ret != -EACCES) {
2350 pm_runtime_put_autosuspend(dev->dev);
2351 return ret;
2352 }
2353
2354 ret = drm_atomic_helper_setup_commit(state, nonblock);
2355 if (ret)
2356 goto done;
2357
2358 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2359
2360 ret = drm_atomic_helper_prepare_planes(dev, state);
2361 if (ret)
2362 goto done;
2363
2364 if (!nonblock) {
2365 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2366 if (ret)
2367 goto err_cleanup;
2368 }
2369
2370 ret = drm_atomic_helper_swap_state(state, true);
2371 if (ret)
2372 goto err_cleanup;
2373
2374 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2375 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2376 struct nv50_wndw *wndw = nv50_wndw(plane);
2377
2378 if (asyw->set.image)
2379 nv50_wndw_ntfy_enable(wndw, asyw);
2380 }
2381
2382 drm_atomic_state_get(state);
2383
2384 /*
2385 * Grab another RPM ref for the commit tail, which will release the
2386 * ref when it's finished
2387 */
2388 pm_runtime_get_noresume(dev->dev);
2389
2390 if (nonblock)
2391 queue_work(system_unbound_wq, &state->commit_work);
2392 else
2393 nv50_disp_atomic_commit_tail(state);
2394
2395 err_cleanup:
2396 if (ret)
2397 drm_atomic_helper_cleanup_planes(dev, state);
2398 done:
2399 pm_runtime_put_autosuspend(dev->dev);
2400 return ret;
2401 }
2402
2403 static struct nv50_outp_atom *
nv50_disp_outp_atomic_add(struct nv50_atom * atom,struct drm_encoder * encoder)2404 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2405 {
2406 struct nv50_outp_atom *outp;
2407
2408 list_for_each_entry(outp, &atom->outp, head) {
2409 if (outp->encoder == encoder)
2410 return outp;
2411 }
2412
2413 outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2414 if (!outp)
2415 return ERR_PTR(-ENOMEM);
2416
2417 list_add(&outp->head, &atom->outp);
2418 outp->encoder = encoder;
2419 return outp;
2420 }
2421
2422 static int
nv50_disp_outp_atomic_check_clr(struct nv50_atom * atom,struct drm_connector_state * old_connector_state)2423 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2424 struct drm_connector_state *old_connector_state)
2425 {
2426 struct drm_encoder *encoder = old_connector_state->best_encoder;
2427 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2428 struct drm_crtc *crtc;
2429 struct nv50_outp_atom *outp;
2430
2431 if (!(crtc = old_connector_state->crtc))
2432 return 0;
2433
2434 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2435 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2436 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2437 outp = nv50_disp_outp_atomic_add(atom, encoder);
2438 if (IS_ERR(outp))
2439 return PTR_ERR(outp);
2440
2441 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2442 outp->flush_disable = true;
2443 atom->flush_disable = true;
2444 }
2445 outp->clr.ctrl = true;
2446 atom->lock_core = true;
2447 }
2448
2449 return 0;
2450 }
2451
2452 static int
nv50_disp_outp_atomic_check_set(struct nv50_atom * atom,struct drm_connector_state * connector_state)2453 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2454 struct drm_connector_state *connector_state)
2455 {
2456 struct drm_encoder *encoder = connector_state->best_encoder;
2457 struct drm_crtc_state *new_crtc_state;
2458 struct drm_crtc *crtc;
2459 struct nv50_outp_atom *outp;
2460
2461 if (!(crtc = connector_state->crtc))
2462 return 0;
2463
2464 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2465 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2466 outp = nv50_disp_outp_atomic_add(atom, encoder);
2467 if (IS_ERR(outp))
2468 return PTR_ERR(outp);
2469
2470 outp->set.ctrl = true;
2471 atom->lock_core = true;
2472 }
2473
2474 return 0;
2475 }
2476
2477 static int
nv50_disp_atomic_check(struct drm_device * dev,struct drm_atomic_state * state)2478 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2479 {
2480 struct nv50_atom *atom = nv50_atom(state);
2481 struct nv50_core *core = nv50_disp(dev)->core;
2482 struct drm_connector_state *old_connector_state, *new_connector_state;
2483 struct drm_connector *connector;
2484 struct drm_crtc_state *new_crtc_state;
2485 struct drm_crtc *crtc;
2486 struct nv50_head *head;
2487 struct nv50_head_atom *asyh;
2488 int ret, i;
2489
2490 if (core->assign_windows && core->func->head->static_wndw_map) {
2491 drm_for_each_crtc(crtc, dev) {
2492 new_crtc_state = drm_atomic_get_crtc_state(state,
2493 crtc);
2494 if (IS_ERR(new_crtc_state))
2495 return PTR_ERR(new_crtc_state);
2496
2497 head = nv50_head(crtc);
2498 asyh = nv50_head_atom(new_crtc_state);
2499 core->func->head->static_wndw_map(head, asyh);
2500 }
2501 }
2502
2503 /* We need to handle colour management on a per-plane basis. */
2504 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2505 if (new_crtc_state->color_mgmt_changed) {
2506 ret = drm_atomic_add_affected_planes(state, crtc);
2507 if (ret)
2508 return ret;
2509 }
2510 }
2511
2512 ret = drm_atomic_helper_check(dev, state);
2513 if (ret)
2514 return ret;
2515
2516 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2517 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2518 if (ret)
2519 return ret;
2520
2521 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2522 if (ret)
2523 return ret;
2524 }
2525
2526 ret = drm_dp_mst_atomic_check(state);
2527 if (ret)
2528 return ret;
2529
2530 nv50_crc_atomic_check_outp(atom);
2531
2532 return 0;
2533 }
2534
2535 static void
nv50_disp_atomic_state_clear(struct drm_atomic_state * state)2536 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2537 {
2538 struct nv50_atom *atom = nv50_atom(state);
2539 struct nv50_outp_atom *outp, *outt;
2540
2541 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2542 list_del(&outp->head);
2543 kfree(outp);
2544 }
2545
2546 drm_atomic_state_default_clear(state);
2547 }
2548
2549 static void
nv50_disp_atomic_state_free(struct drm_atomic_state * state)2550 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2551 {
2552 struct nv50_atom *atom = nv50_atom(state);
2553 drm_atomic_state_default_release(&atom->state);
2554 kfree(atom);
2555 }
2556
2557 static struct drm_atomic_state *
nv50_disp_atomic_state_alloc(struct drm_device * dev)2558 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2559 {
2560 struct nv50_atom *atom;
2561 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2562 drm_atomic_state_init(dev, &atom->state) < 0) {
2563 kfree(atom);
2564 return NULL;
2565 }
2566 INIT_LIST_HEAD(&atom->outp);
2567 return &atom->state;
2568 }
2569
2570 static const struct drm_mode_config_funcs
2571 nv50_disp_func = {
2572 .fb_create = nouveau_user_framebuffer_create,
2573 .output_poll_changed = nouveau_fbcon_output_poll_changed,
2574 .atomic_check = nv50_disp_atomic_check,
2575 .atomic_commit = nv50_disp_atomic_commit,
2576 .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2577 .atomic_state_clear = nv50_disp_atomic_state_clear,
2578 .atomic_state_free = nv50_disp_atomic_state_free,
2579 };
2580
2581 /******************************************************************************
2582 * Init
2583 *****************************************************************************/
2584
2585 static void
nv50_display_fini(struct drm_device * dev,bool runtime,bool suspend)2586 nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend)
2587 {
2588 struct nouveau_drm *drm = nouveau_drm(dev);
2589 struct drm_encoder *encoder;
2590
2591 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2592 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
2593 nv50_mstm_fini(nouveau_encoder(encoder));
2594 }
2595
2596 if (!runtime)
2597 cancel_work_sync(&drm->hpd_work);
2598 }
2599
2600 static int
nv50_display_init(struct drm_device * dev,bool resume,bool runtime)2601 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2602 {
2603 struct nv50_core *core = nv50_disp(dev)->core;
2604 struct drm_encoder *encoder;
2605
2606 if (resume || runtime)
2607 core->func->init(core);
2608
2609 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2610 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2611 struct nouveau_encoder *nv_encoder =
2612 nouveau_encoder(encoder);
2613 nv50_mstm_init(nv_encoder, runtime);
2614 }
2615 }
2616
2617 return 0;
2618 }
2619
2620 static void
nv50_display_destroy(struct drm_device * dev)2621 nv50_display_destroy(struct drm_device *dev)
2622 {
2623 struct nv50_disp *disp = nv50_disp(dev);
2624
2625 nv50_audio_component_fini(nouveau_drm(dev));
2626
2627 nvif_object_unmap(&disp->caps);
2628 nvif_object_dtor(&disp->caps);
2629 nv50_core_del(&disp->core);
2630
2631 nouveau_bo_unmap(disp->sync);
2632 if (disp->sync)
2633 nouveau_bo_unpin(disp->sync);
2634 nouveau_bo_ref(NULL, &disp->sync);
2635
2636 nouveau_display(dev)->priv = NULL;
2637 kfree(disp);
2638 }
2639
2640 int
nv50_display_create(struct drm_device * dev)2641 nv50_display_create(struct drm_device *dev)
2642 {
2643 struct nvif_device *device = &nouveau_drm(dev)->client.device;
2644 struct nouveau_drm *drm = nouveau_drm(dev);
2645 struct dcb_table *dcb = &drm->vbios.dcb;
2646 struct drm_connector *connector, *tmp;
2647 struct nv50_disp *disp;
2648 struct dcb_output *dcbe;
2649 int crtcs, ret, i;
2650 bool has_mst = nv50_has_mst(drm);
2651
2652 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2653 if (!disp)
2654 return -ENOMEM;
2655
2656 mutex_init(&disp->mutex);
2657
2658 nouveau_display(dev)->priv = disp;
2659 nouveau_display(dev)->dtor = nv50_display_destroy;
2660 nouveau_display(dev)->init = nv50_display_init;
2661 nouveau_display(dev)->fini = nv50_display_fini;
2662 disp->disp = &nouveau_display(dev)->disp;
2663 dev->mode_config.funcs = &nv50_disp_func;
2664 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2665 dev->mode_config.normalize_zpos = true;
2666
2667 /* small shared memory area we use for notifiers and semaphores */
2668 ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
2669 NOUVEAU_GEM_DOMAIN_VRAM,
2670 0, 0x0000, NULL, NULL, &disp->sync);
2671 if (!ret) {
2672 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true);
2673 if (!ret) {
2674 ret = nouveau_bo_map(disp->sync);
2675 if (ret)
2676 nouveau_bo_unpin(disp->sync);
2677 }
2678 if (ret)
2679 nouveau_bo_ref(NULL, &disp->sync);
2680 }
2681
2682 if (ret)
2683 goto out;
2684
2685 /* allocate master evo channel */
2686 ret = nv50_core_new(drm, &disp->core);
2687 if (ret)
2688 goto out;
2689
2690 disp->core->func->init(disp->core);
2691 if (disp->core->func->caps_init) {
2692 ret = disp->core->func->caps_init(drm, disp);
2693 if (ret)
2694 goto out;
2695 }
2696
2697 /* Assign the correct format modifiers */
2698 if (disp->disp->object.oclass >= TU102_DISP)
2699 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
2700 else
2701 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
2702 nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
2703 else
2704 nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
2705
2706 /* create crtc objects to represent the hw heads */
2707 if (disp->disp->object.oclass >= GV100_DISP)
2708 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2709 else
2710 if (disp->disp->object.oclass >= GF110_DISP)
2711 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2712 else
2713 crtcs = 0x3;
2714
2715 for (i = 0; i < fls(crtcs); i++) {
2716 struct nv50_head *head;
2717
2718 if (!(crtcs & (1 << i)))
2719 continue;
2720
2721 head = nv50_head_create(dev, i);
2722 if (IS_ERR(head)) {
2723 ret = PTR_ERR(head);
2724 goto out;
2725 }
2726
2727 if (has_mst) {
2728 head->msto = nv50_msto_new(dev, head, i);
2729 if (IS_ERR(head->msto)) {
2730 ret = PTR_ERR(head->msto);
2731 head->msto = NULL;
2732 goto out;
2733 }
2734
2735 /*
2736 * FIXME: This is a hack to workaround the following
2737 * issues:
2738 *
2739 * https://gitlab.gnome.org/GNOME/mutter/issues/759
2740 * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
2741 *
2742 * Once these issues are closed, this should be
2743 * removed
2744 */
2745 head->msto->encoder.possible_crtcs = crtcs;
2746 }
2747 }
2748
2749 /* create encoder/connector objects based on VBIOS DCB table */
2750 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2751 connector = nouveau_connector_create(dev, dcbe);
2752 if (IS_ERR(connector))
2753 continue;
2754
2755 if (dcbe->location == DCB_LOC_ON_CHIP) {
2756 switch (dcbe->type) {
2757 case DCB_OUTPUT_TMDS:
2758 case DCB_OUTPUT_LVDS:
2759 case DCB_OUTPUT_DP:
2760 ret = nv50_sor_create(connector, dcbe);
2761 break;
2762 case DCB_OUTPUT_ANALOG:
2763 ret = nv50_dac_create(connector, dcbe);
2764 break;
2765 default:
2766 ret = -ENODEV;
2767 break;
2768 }
2769 } else {
2770 ret = nv50_pior_create(connector, dcbe);
2771 }
2772
2773 if (ret) {
2774 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2775 dcbe->location, dcbe->type,
2776 ffs(dcbe->or) - 1, ret);
2777 ret = 0;
2778 }
2779 }
2780
2781 /* cull any connectors we created that don't have an encoder */
2782 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2783 if (connector->possible_encoders)
2784 continue;
2785
2786 NV_WARN(drm, "%s has no encoders, removing\n",
2787 connector->name);
2788 connector->funcs->destroy(connector);
2789 }
2790
2791 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2792 dev->vblank_disable_immediate = true;
2793
2794 nv50_audio_component_init(drm);
2795
2796 out:
2797 if (ret)
2798 nv50_display_destroy(dev);
2799 return ret;
2800 }
2801
2802 /******************************************************************************
2803 * Format modifiers
2804 *****************************************************************************/
2805
2806 /****************************************************************
2807 * Log2(block height) ----------------------------+ *
2808 * Page Kind ----------------------------------+ | *
2809 * Gob Height/Page Kind Generation ------+ | | *
2810 * Sector layout -------+ | | | *
2811 * Compression ------+ | | | | */
2812 const u64 disp50xx_modifiers[] = { /* | | | | | */
2813 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
2814 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
2815 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
2816 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
2817 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
2818 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
2819 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
2820 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
2821 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
2822 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
2823 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
2824 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
2825 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
2826 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
2827 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
2828 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
2829 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
2830 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
2831 DRM_FORMAT_MOD_LINEAR,
2832 DRM_FORMAT_MOD_INVALID
2833 };
2834
2835 /****************************************************************
2836 * Log2(block height) ----------------------------+ *
2837 * Page Kind ----------------------------------+ | *
2838 * Gob Height/Page Kind Generation ------+ | | *
2839 * Sector layout -------+ | | | *
2840 * Compression ------+ | | | | */
2841 const u64 disp90xx_modifiers[] = { /* | | | | | */
2842 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
2843 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
2844 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
2845 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
2846 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
2847 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),
2848 DRM_FORMAT_MOD_LINEAR,
2849 DRM_FORMAT_MOD_INVALID
2850 };
2851