1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2017 IBM Corp.
3 #include <linux/pci.h>
4 #include <asm/pnv-ocxl.h>
5 #include <misc/ocxl-config.h>
6 #include "ocxl_internal.h"
7
8 #define EXTRACT_BIT(val, bit) (!!(val & BIT(bit)))
9 #define EXTRACT_BITS(val, s, e) ((val & GENMASK(e, s)) >> s)
10
11 #define OCXL_DVSEC_AFU_IDX_MASK GENMASK(5, 0)
12 #define OCXL_DVSEC_ACTAG_MASK GENMASK(11, 0)
13 #define OCXL_DVSEC_PASID_MASK GENMASK(19, 0)
14 #define OCXL_DVSEC_PASID_LOG_MASK GENMASK(4, 0)
15
16 #define OCXL_DVSEC_TEMPL_VERSION 0x0
17 #define OCXL_DVSEC_TEMPL_NAME 0x4
18 #define OCXL_DVSEC_TEMPL_AFU_VERSION 0x1C
19 #define OCXL_DVSEC_TEMPL_MMIO_GLOBAL 0x20
20 #define OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ 0x28
21 #define OCXL_DVSEC_TEMPL_MMIO_PP 0x30
22 #define OCXL_DVSEC_TEMPL_MMIO_PP_SZ 0x38
23 #define OCXL_DVSEC_TEMPL_ALL_MEM_SZ 0x3C
24 #define OCXL_DVSEC_TEMPL_LPC_MEM_START 0x40
25 #define OCXL_DVSEC_TEMPL_WWID 0x48
26 #define OCXL_DVSEC_TEMPL_LPC_MEM_SZ 0x58
27
28 #define OCXL_MAX_AFU_PER_FUNCTION 64
29 #define OCXL_TEMPL_LEN_1_0 0x58
30 #define OCXL_TEMPL_LEN_1_1 0x60
31 #define OCXL_TEMPL_NAME_LEN 24
32 #define OCXL_CFG_TIMEOUT 3
33
find_dvsec(struct pci_dev * dev,int dvsec_id)34 static int find_dvsec(struct pci_dev *dev, int dvsec_id)
35 {
36 int vsec = 0;
37 u16 vendor, id;
38
39 while ((vsec = pci_find_next_ext_capability(dev, vsec,
40 OCXL_EXT_CAP_ID_DVSEC))) {
41 pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
42 &vendor);
43 pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
44 if (vendor == PCI_VENDOR_ID_IBM && id == dvsec_id)
45 return vsec;
46 }
47 return 0;
48 }
49
find_dvsec_afu_ctrl(struct pci_dev * dev,u8 afu_idx)50 static int find_dvsec_afu_ctrl(struct pci_dev *dev, u8 afu_idx)
51 {
52 int vsec = 0;
53 u16 vendor, id;
54 u8 idx;
55
56 while ((vsec = pci_find_next_ext_capability(dev, vsec,
57 OCXL_EXT_CAP_ID_DVSEC))) {
58 pci_read_config_word(dev, vsec + OCXL_DVSEC_VENDOR_OFFSET,
59 &vendor);
60 pci_read_config_word(dev, vsec + OCXL_DVSEC_ID_OFFSET, &id);
61
62 if (vendor == PCI_VENDOR_ID_IBM &&
63 id == OCXL_DVSEC_AFU_CTRL_ID) {
64 pci_read_config_byte(dev,
65 vsec + OCXL_DVSEC_AFU_CTRL_AFU_IDX,
66 &idx);
67 if (idx == afu_idx)
68 return vsec;
69 }
70 }
71 return 0;
72 }
73
74 /**
75 * get_function_0() - Find a related PCI device (function 0)
76 * @device: PCI device to match
77 *
78 * Returns a pointer to the related device, or null if not found
79 */
get_function_0(struct pci_dev * dev)80 static struct pci_dev *get_function_0(struct pci_dev *dev)
81 {
82 unsigned int devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
83
84 return pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus),
85 dev->bus->number, devfn);
86 }
87
read_pasid(struct pci_dev * dev,struct ocxl_fn_config * fn)88 static void read_pasid(struct pci_dev *dev, struct ocxl_fn_config *fn)
89 {
90 u16 val;
91 int pos;
92
93 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PASID);
94 if (!pos) {
95 /*
96 * PASID capability is not mandatory, but there
97 * shouldn't be any AFU
98 */
99 dev_dbg(&dev->dev, "Function doesn't require any PASID\n");
100 fn->max_pasid_log = -1;
101 goto out;
102 }
103 pci_read_config_word(dev, pos + PCI_PASID_CAP, &val);
104 fn->max_pasid_log = EXTRACT_BITS(val, 8, 12);
105
106 out:
107 dev_dbg(&dev->dev, "PASID capability:\n");
108 dev_dbg(&dev->dev, " Max PASID log = %d\n", fn->max_pasid_log);
109 }
110
read_dvsec_tl(struct pci_dev * dev,struct ocxl_fn_config * fn)111 static int read_dvsec_tl(struct pci_dev *dev, struct ocxl_fn_config *fn)
112 {
113 int pos;
114
115 pos = find_dvsec(dev, OCXL_DVSEC_TL_ID);
116 if (!pos && PCI_FUNC(dev->devfn) == 0) {
117 dev_err(&dev->dev, "Can't find TL DVSEC\n");
118 return -ENODEV;
119 }
120 if (pos && PCI_FUNC(dev->devfn) != 0) {
121 dev_err(&dev->dev, "TL DVSEC is only allowed on function 0\n");
122 return -ENODEV;
123 }
124 fn->dvsec_tl_pos = pos;
125 return 0;
126 }
127
read_dvsec_function(struct pci_dev * dev,struct ocxl_fn_config * fn)128 static int read_dvsec_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
129 {
130 int pos, afu_present;
131 u32 val;
132
133 pos = find_dvsec(dev, OCXL_DVSEC_FUNC_ID);
134 if (!pos) {
135 dev_err(&dev->dev, "Can't find function DVSEC\n");
136 return -ENODEV;
137 }
138 fn->dvsec_function_pos = pos;
139
140 pci_read_config_dword(dev, pos + OCXL_DVSEC_FUNC_OFF_INDEX, &val);
141 afu_present = EXTRACT_BIT(val, 31);
142 if (!afu_present) {
143 fn->max_afu_index = -1;
144 dev_dbg(&dev->dev, "Function doesn't define any AFU\n");
145 goto out;
146 }
147 fn->max_afu_index = EXTRACT_BITS(val, 24, 29);
148
149 out:
150 dev_dbg(&dev->dev, "Function DVSEC:\n");
151 dev_dbg(&dev->dev, " Max AFU index = %d\n", fn->max_afu_index);
152 return 0;
153 }
154
read_dvsec_afu_info(struct pci_dev * dev,struct ocxl_fn_config * fn)155 static int read_dvsec_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn)
156 {
157 int pos;
158
159 if (fn->max_afu_index < 0) {
160 fn->dvsec_afu_info_pos = -1;
161 return 0;
162 }
163
164 pos = find_dvsec(dev, OCXL_DVSEC_AFU_INFO_ID);
165 if (!pos) {
166 dev_err(&dev->dev, "Can't find AFU information DVSEC\n");
167 return -ENODEV;
168 }
169 fn->dvsec_afu_info_pos = pos;
170 return 0;
171 }
172
read_dvsec_vendor(struct pci_dev * dev)173 static int read_dvsec_vendor(struct pci_dev *dev)
174 {
175 int pos;
176 u32 cfg, tlx, dlx, reset_reload;
177
178 /*
179 * vendor specific DVSEC, for IBM images only. Some older
180 * images may not have it
181 *
182 * It's only used on function 0 to specify the version of some
183 * logic blocks and to give access to special registers to
184 * enable host-based flashing.
185 */
186 if (PCI_FUNC(dev->devfn) != 0)
187 return 0;
188
189 pos = find_dvsec(dev, OCXL_DVSEC_VENDOR_ID);
190 if (!pos)
191 return 0;
192
193 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_CFG_VERS, &cfg);
194 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_TLX_VERS, &tlx);
195 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_DLX_VERS, &dlx);
196 pci_read_config_dword(dev, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
197 &reset_reload);
198
199 dev_dbg(&dev->dev, "Vendor specific DVSEC:\n");
200 dev_dbg(&dev->dev, " CFG version = 0x%x\n", cfg);
201 dev_dbg(&dev->dev, " TLX version = 0x%x\n", tlx);
202 dev_dbg(&dev->dev, " DLX version = 0x%x\n", dlx);
203 dev_dbg(&dev->dev, " ResetReload = 0x%x\n", reset_reload);
204 return 0;
205 }
206
207 /**
208 * get_dvsec_vendor0() - Find a related PCI device (function 0)
209 * @dev: PCI device to match
210 * @dev0: The PCI device (function 0) found
211 * @out_pos: The position of PCI device (function 0)
212 *
213 * Returns 0 on success, negative on failure.
214 *
215 * NOTE: If it's successful, the reference of dev0 is increased,
216 * so after using it, the callers must call pci_dev_put() to give
217 * up the reference.
218 */
get_dvsec_vendor0(struct pci_dev * dev,struct pci_dev ** dev0,int * out_pos)219 static int get_dvsec_vendor0(struct pci_dev *dev, struct pci_dev **dev0,
220 int *out_pos)
221 {
222 int pos;
223
224 if (PCI_FUNC(dev->devfn) != 0) {
225 dev = get_function_0(dev);
226 if (!dev)
227 return -1;
228 } else {
229 dev = pci_dev_get(dev);
230 }
231 pos = find_dvsec(dev, OCXL_DVSEC_VENDOR_ID);
232 if (!pos) {
233 pci_dev_put(dev);
234 return -1;
235 }
236 *dev0 = dev;
237 *out_pos = pos;
238 return 0;
239 }
240
ocxl_config_get_reset_reload(struct pci_dev * dev,int * val)241 int ocxl_config_get_reset_reload(struct pci_dev *dev, int *val)
242 {
243 struct pci_dev *dev0;
244 u32 reset_reload;
245 int pos;
246
247 if (get_dvsec_vendor0(dev, &dev0, &pos))
248 return -1;
249
250 pci_read_config_dword(dev0, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
251 &reset_reload);
252 pci_dev_put(dev0);
253 *val = !!(reset_reload & BIT(0));
254 return 0;
255 }
256
ocxl_config_set_reset_reload(struct pci_dev * dev,int val)257 int ocxl_config_set_reset_reload(struct pci_dev *dev, int val)
258 {
259 struct pci_dev *dev0;
260 u32 reset_reload;
261 int pos;
262
263 if (get_dvsec_vendor0(dev, &dev0, &pos))
264 return -1;
265
266 pci_read_config_dword(dev0, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
267 &reset_reload);
268 if (val)
269 reset_reload |= BIT(0);
270 else
271 reset_reload &= ~BIT(0);
272 pci_write_config_dword(dev0, pos + OCXL_DVSEC_VENDOR_RESET_RELOAD,
273 reset_reload);
274 pci_dev_put(dev0);
275 return 0;
276 }
277
validate_function(struct pci_dev * dev,struct ocxl_fn_config * fn)278 static int validate_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
279 {
280 if (fn->max_pasid_log == -1 && fn->max_afu_index >= 0) {
281 dev_err(&dev->dev,
282 "AFUs are defined but no PASIDs are requested\n");
283 return -EINVAL;
284 }
285
286 if (fn->max_afu_index > OCXL_MAX_AFU_PER_FUNCTION) {
287 dev_err(&dev->dev,
288 "Max AFU index out of architectural limit (%d vs %d)\n",
289 fn->max_afu_index, OCXL_MAX_AFU_PER_FUNCTION);
290 return -EINVAL;
291 }
292 return 0;
293 }
294
ocxl_config_read_function(struct pci_dev * dev,struct ocxl_fn_config * fn)295 int ocxl_config_read_function(struct pci_dev *dev, struct ocxl_fn_config *fn)
296 {
297 int rc;
298
299 read_pasid(dev, fn);
300
301 rc = read_dvsec_tl(dev, fn);
302 if (rc) {
303 dev_err(&dev->dev,
304 "Invalid Transaction Layer DVSEC configuration: %d\n",
305 rc);
306 return -ENODEV;
307 }
308
309 rc = read_dvsec_function(dev, fn);
310 if (rc) {
311 dev_err(&dev->dev,
312 "Invalid Function DVSEC configuration: %d\n", rc);
313 return -ENODEV;
314 }
315
316 rc = read_dvsec_afu_info(dev, fn);
317 if (rc) {
318 dev_err(&dev->dev, "Invalid AFU configuration: %d\n", rc);
319 return -ENODEV;
320 }
321
322 rc = read_dvsec_vendor(dev);
323 if (rc) {
324 dev_err(&dev->dev,
325 "Invalid vendor specific DVSEC configuration: %d\n",
326 rc);
327 return -ENODEV;
328 }
329
330 rc = validate_function(dev, fn);
331 return rc;
332 }
333 EXPORT_SYMBOL_GPL(ocxl_config_read_function);
334
read_afu_info(struct pci_dev * dev,struct ocxl_fn_config * fn,int offset,u32 * data)335 static int read_afu_info(struct pci_dev *dev, struct ocxl_fn_config *fn,
336 int offset, u32 *data)
337 {
338 u32 val;
339 unsigned long timeout = jiffies + (HZ * OCXL_CFG_TIMEOUT);
340 int pos = fn->dvsec_afu_info_pos;
341
342 /* Protect 'data valid' bit */
343 if (EXTRACT_BIT(offset, 31)) {
344 dev_err(&dev->dev, "Invalid offset in AFU info DVSEC\n");
345 return -EINVAL;
346 }
347
348 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, offset);
349 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
350 while (!EXTRACT_BIT(val, 31)) {
351 if (time_after_eq(jiffies, timeout)) {
352 dev_err(&dev->dev,
353 "Timeout while reading AFU info DVSEC (offset=%d)\n",
354 offset);
355 return -EBUSY;
356 }
357 cpu_relax();
358 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_OFF, &val);
359 }
360 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_INFO_DATA, data);
361 return 0;
362 }
363
364 /**
365 * read_template_version() - Read the template version from the AFU
366 * @dev: the device for the AFU
367 * @fn: the AFU offsets
368 * @len: outputs the template length
369 * @version: outputs the major<<8,minor version
370 *
371 * Returns 0 on success, negative on failure
372 */
read_template_version(struct pci_dev * dev,struct ocxl_fn_config * fn,u16 * len,u16 * version)373 static int read_template_version(struct pci_dev *dev, struct ocxl_fn_config *fn,
374 u16 *len, u16 *version)
375 {
376 u32 val32;
377 u8 major, minor;
378 int rc;
379
380 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_VERSION, &val32);
381 if (rc)
382 return rc;
383
384 *len = EXTRACT_BITS(val32, 16, 31);
385 major = EXTRACT_BITS(val32, 8, 15);
386 minor = EXTRACT_BITS(val32, 0, 7);
387 *version = (major << 8) + minor;
388 return 0;
389 }
390
ocxl_config_check_afu_index(struct pci_dev * dev,struct ocxl_fn_config * fn,int afu_idx)391 int ocxl_config_check_afu_index(struct pci_dev *dev,
392 struct ocxl_fn_config *fn, int afu_idx)
393 {
394 int rc;
395 u16 templ_version;
396 u16 len, expected_len;
397
398 pci_write_config_byte(dev,
399 fn->dvsec_afu_info_pos + OCXL_DVSEC_AFU_INFO_AFU_IDX,
400 afu_idx);
401
402 rc = read_template_version(dev, fn, &len, &templ_version);
403 if (rc)
404 return rc;
405
406 /* AFU index map can have holes, in which case we read all 0's */
407 if (!templ_version && !len)
408 return 0;
409
410 dev_dbg(&dev->dev, "AFU descriptor template version %d.%d\n",
411 templ_version >> 8, templ_version & 0xFF);
412
413 switch (templ_version) {
414 case 0x0005: // v0.5 was used prior to the spec approval
415 case 0x0100:
416 expected_len = OCXL_TEMPL_LEN_1_0;
417 break;
418 case 0x0101:
419 expected_len = OCXL_TEMPL_LEN_1_1;
420 break;
421 default:
422 dev_warn(&dev->dev, "Unknown AFU template version %#x\n",
423 templ_version);
424 expected_len = len;
425 }
426 if (len != expected_len)
427 dev_warn(&dev->dev,
428 "Unexpected template length %#x in AFU information, expected %#x for version %#x\n",
429 len, expected_len, templ_version);
430 return 1;
431 }
432
read_afu_name(struct pci_dev * dev,struct ocxl_fn_config * fn,struct ocxl_afu_config * afu)433 static int read_afu_name(struct pci_dev *dev, struct ocxl_fn_config *fn,
434 struct ocxl_afu_config *afu)
435 {
436 int i, rc;
437 u32 val, *ptr;
438
439 BUILD_BUG_ON(OCXL_AFU_NAME_SZ < OCXL_TEMPL_NAME_LEN);
440 for (i = 0; i < OCXL_TEMPL_NAME_LEN; i += 4) {
441 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_NAME + i, &val);
442 if (rc)
443 return rc;
444 ptr = (u32 *) &afu->name[i];
445 *ptr = le32_to_cpu((__force __le32) val);
446 }
447 afu->name[OCXL_AFU_NAME_SZ - 1] = '\0'; /* play safe */
448 return 0;
449 }
450
read_afu_mmio(struct pci_dev * dev,struct ocxl_fn_config * fn,struct ocxl_afu_config * afu)451 static int read_afu_mmio(struct pci_dev *dev, struct ocxl_fn_config *fn,
452 struct ocxl_afu_config *afu)
453 {
454 int rc;
455 u32 val;
456
457 /*
458 * Global MMIO
459 */
460 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL, &val);
461 if (rc)
462 return rc;
463 afu->global_mmio_bar = EXTRACT_BITS(val, 0, 2);
464 afu->global_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
465
466 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL + 4, &val);
467 if (rc)
468 return rc;
469 afu->global_mmio_offset += (u64) val << 32;
470
471 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ, &val);
472 if (rc)
473 return rc;
474 afu->global_mmio_size = val;
475
476 /*
477 * Per-process MMIO
478 */
479 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP, &val);
480 if (rc)
481 return rc;
482 afu->pp_mmio_bar = EXTRACT_BITS(val, 0, 2);
483 afu->pp_mmio_offset = EXTRACT_BITS(val, 16, 31) << 16;
484
485 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP + 4, &val);
486 if (rc)
487 return rc;
488 afu->pp_mmio_offset += (u64) val << 32;
489
490 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_MMIO_PP_SZ, &val);
491 if (rc)
492 return rc;
493 afu->pp_mmio_stride = val;
494
495 return 0;
496 }
497
read_afu_control(struct pci_dev * dev,struct ocxl_afu_config * afu)498 static int read_afu_control(struct pci_dev *dev, struct ocxl_afu_config *afu)
499 {
500 int pos;
501 u8 val8;
502 u16 val16;
503
504 pos = find_dvsec_afu_ctrl(dev, afu->idx);
505 if (!pos) {
506 dev_err(&dev->dev, "Can't find AFU control DVSEC for AFU %d\n",
507 afu->idx);
508 return -ENODEV;
509 }
510 afu->dvsec_afu_control_pos = pos;
511
512 pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_SUP, &val8);
513 afu->pasid_supported_log = EXTRACT_BITS(val8, 0, 4);
514
515 pci_read_config_word(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_SUP, &val16);
516 afu->actag_supported = EXTRACT_BITS(val16, 0, 11);
517 return 0;
518 }
519
char_allowed(int c)520 static bool char_allowed(int c)
521 {
522 /*
523 * Permitted Characters : Alphanumeric, hyphen, underscore, comma
524 */
525 if ((c >= 0x30 && c <= 0x39) /* digits */ ||
526 (c >= 0x41 && c <= 0x5A) /* upper case */ ||
527 (c >= 0x61 && c <= 0x7A) /* lower case */ ||
528 c == 0 /* NULL */ ||
529 c == 0x2D /* - */ ||
530 c == 0x5F /* _ */ ||
531 c == 0x2C /* , */)
532 return true;
533 return false;
534 }
535
validate_afu(struct pci_dev * dev,struct ocxl_afu_config * afu)536 static int validate_afu(struct pci_dev *dev, struct ocxl_afu_config *afu)
537 {
538 int i;
539
540 if (!afu->name[0]) {
541 dev_err(&dev->dev, "Empty AFU name\n");
542 return -EINVAL;
543 }
544 for (i = 0; i < OCXL_TEMPL_NAME_LEN; i++) {
545 if (!char_allowed(afu->name[i])) {
546 dev_err(&dev->dev,
547 "Invalid character in AFU name\n");
548 return -EINVAL;
549 }
550 }
551
552 if (afu->global_mmio_bar != 0 &&
553 afu->global_mmio_bar != 2 &&
554 afu->global_mmio_bar != 4) {
555 dev_err(&dev->dev, "Invalid global MMIO bar number\n");
556 return -EINVAL;
557 }
558 if (afu->pp_mmio_bar != 0 &&
559 afu->pp_mmio_bar != 2 &&
560 afu->pp_mmio_bar != 4) {
561 dev_err(&dev->dev, "Invalid per-process MMIO bar number\n");
562 return -EINVAL;
563 }
564 return 0;
565 }
566
567 /**
568 * read_afu_lpc_memory_info() - Populate AFU metadata regarding LPC memory
569 * @dev: the device for the AFU
570 * @fn: the AFU offsets
571 * @afu: the AFU struct to populate the LPC metadata into
572 *
573 * Returns 0 on success, negative on failure
574 */
read_afu_lpc_memory_info(struct pci_dev * dev,struct ocxl_fn_config * fn,struct ocxl_afu_config * afu)575 static int read_afu_lpc_memory_info(struct pci_dev *dev,
576 struct ocxl_fn_config *fn,
577 struct ocxl_afu_config *afu)
578 {
579 int rc;
580 u32 val32;
581 u16 templ_version;
582 u16 templ_len;
583 u64 total_mem_size = 0;
584 u64 lpc_mem_size = 0;
585
586 afu->lpc_mem_offset = 0;
587 afu->lpc_mem_size = 0;
588 afu->special_purpose_mem_offset = 0;
589 afu->special_purpose_mem_size = 0;
590 /*
591 * For AFUs following template v1.0, the LPC memory covers the
592 * total memory. Its size is a power of 2.
593 *
594 * For AFUs with template >= v1.01, the total memory size is
595 * still a power of 2, but it is split in 2 parts:
596 * - the LPC memory, whose size can now be anything
597 * - the remainder memory is a special purpose memory, whose
598 * definition is AFU-dependent. It is not accessible through
599 * the usual commands for LPC memory
600 */
601 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_ALL_MEM_SZ, &val32);
602 if (rc)
603 return rc;
604
605 val32 = EXTRACT_BITS(val32, 0, 7);
606 if (!val32)
607 return 0; /* No LPC memory */
608
609 /*
610 * The configuration space spec allows for a memory size of up
611 * to 2^255 bytes.
612 *
613 * Current generation hardware uses 56-bit physical addresses,
614 * but we won't be able to get near close to that, as we won't
615 * have a hole big enough in the memory map. Let it pass in
616 * the driver for now. We'll get an error from the firmware
617 * when trying to configure something too big.
618 */
619 total_mem_size = 1ull << val32;
620
621 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_LPC_MEM_START, &val32);
622 if (rc)
623 return rc;
624
625 afu->lpc_mem_offset = val32;
626
627 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_LPC_MEM_START + 4, &val32);
628 if (rc)
629 return rc;
630
631 afu->lpc_mem_offset |= (u64) val32 << 32;
632
633 rc = read_template_version(dev, fn, &templ_len, &templ_version);
634 if (rc)
635 return rc;
636
637 if (templ_version >= 0x0101) {
638 rc = read_afu_info(dev, fn,
639 OCXL_DVSEC_TEMPL_LPC_MEM_SZ, &val32);
640 if (rc)
641 return rc;
642 lpc_mem_size = val32;
643
644 rc = read_afu_info(dev, fn,
645 OCXL_DVSEC_TEMPL_LPC_MEM_SZ + 4, &val32);
646 if (rc)
647 return rc;
648 lpc_mem_size |= (u64) val32 << 32;
649 } else {
650 lpc_mem_size = total_mem_size;
651 }
652 afu->lpc_mem_size = lpc_mem_size;
653
654 if (lpc_mem_size < total_mem_size) {
655 afu->special_purpose_mem_offset =
656 afu->lpc_mem_offset + lpc_mem_size;
657 afu->special_purpose_mem_size =
658 total_mem_size - lpc_mem_size;
659 }
660 return 0;
661 }
662
ocxl_config_read_afu(struct pci_dev * dev,struct ocxl_fn_config * fn,struct ocxl_afu_config * afu,u8 afu_idx)663 int ocxl_config_read_afu(struct pci_dev *dev, struct ocxl_fn_config *fn,
664 struct ocxl_afu_config *afu, u8 afu_idx)
665 {
666 int rc;
667 u32 val32;
668
669 /*
670 * First, we need to write the AFU idx for the AFU we want to
671 * access.
672 */
673 WARN_ON((afu_idx & OCXL_DVSEC_AFU_IDX_MASK) != afu_idx);
674 afu->idx = afu_idx;
675 pci_write_config_byte(dev,
676 fn->dvsec_afu_info_pos + OCXL_DVSEC_AFU_INFO_AFU_IDX,
677 afu->idx);
678
679 rc = read_afu_name(dev, fn, afu);
680 if (rc)
681 return rc;
682
683 rc = read_afu_info(dev, fn, OCXL_DVSEC_TEMPL_AFU_VERSION, &val32);
684 if (rc)
685 return rc;
686 afu->version_major = EXTRACT_BITS(val32, 24, 31);
687 afu->version_minor = EXTRACT_BITS(val32, 16, 23);
688 afu->afuc_type = EXTRACT_BITS(val32, 14, 15);
689 afu->afum_type = EXTRACT_BITS(val32, 12, 13);
690 afu->profile = EXTRACT_BITS(val32, 0, 7);
691
692 rc = read_afu_mmio(dev, fn, afu);
693 if (rc)
694 return rc;
695
696 rc = read_afu_lpc_memory_info(dev, fn, afu);
697 if (rc)
698 return rc;
699
700 rc = read_afu_control(dev, afu);
701 if (rc)
702 return rc;
703
704 dev_dbg(&dev->dev, "AFU configuration:\n");
705 dev_dbg(&dev->dev, " name = %s\n", afu->name);
706 dev_dbg(&dev->dev, " version = %d.%d\n", afu->version_major,
707 afu->version_minor);
708 dev_dbg(&dev->dev, " global mmio bar = %hhu\n", afu->global_mmio_bar);
709 dev_dbg(&dev->dev, " global mmio offset = %#llx\n",
710 afu->global_mmio_offset);
711 dev_dbg(&dev->dev, " global mmio size = %#x\n", afu->global_mmio_size);
712 dev_dbg(&dev->dev, " pp mmio bar = %hhu\n", afu->pp_mmio_bar);
713 dev_dbg(&dev->dev, " pp mmio offset = %#llx\n", afu->pp_mmio_offset);
714 dev_dbg(&dev->dev, " pp mmio stride = %#x\n", afu->pp_mmio_stride);
715 dev_dbg(&dev->dev, " lpc_mem offset = %#llx\n", afu->lpc_mem_offset);
716 dev_dbg(&dev->dev, " lpc_mem size = %#llx\n", afu->lpc_mem_size);
717 dev_dbg(&dev->dev, " special purpose mem offset = %#llx\n",
718 afu->special_purpose_mem_offset);
719 dev_dbg(&dev->dev, " special purpose mem size = %#llx\n",
720 afu->special_purpose_mem_size);
721 dev_dbg(&dev->dev, " pasid supported (log) = %u\n",
722 afu->pasid_supported_log);
723 dev_dbg(&dev->dev, " actag supported = %u\n",
724 afu->actag_supported);
725
726 rc = validate_afu(dev, afu);
727 return rc;
728 }
729 EXPORT_SYMBOL_GPL(ocxl_config_read_afu);
730
ocxl_config_get_actag_info(struct pci_dev * dev,u16 * base,u16 * enabled,u16 * supported)731 int ocxl_config_get_actag_info(struct pci_dev *dev, u16 *base, u16 *enabled,
732 u16 *supported)
733 {
734 int rc;
735
736 /*
737 * This is really a simple wrapper for the kernel API, to
738 * avoid an external driver using ocxl as a library to call
739 * platform-dependent code
740 */
741 rc = pnv_ocxl_get_actag(dev, base, enabled, supported);
742 if (rc) {
743 dev_err(&dev->dev, "Can't get actag for device: %d\n", rc);
744 return rc;
745 }
746 return 0;
747 }
748 EXPORT_SYMBOL_GPL(ocxl_config_get_actag_info);
749
ocxl_config_set_afu_actag(struct pci_dev * dev,int pos,int actag_base,int actag_count)750 void ocxl_config_set_afu_actag(struct pci_dev *dev, int pos, int actag_base,
751 int actag_count)
752 {
753 u16 val;
754
755 val = actag_count & OCXL_DVSEC_ACTAG_MASK;
756 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_EN, val);
757
758 val = actag_base & OCXL_DVSEC_ACTAG_MASK;
759 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_ACTAG_BASE, val);
760 }
761 EXPORT_SYMBOL_GPL(ocxl_config_set_afu_actag);
762
ocxl_config_get_pasid_info(struct pci_dev * dev,int * count)763 int ocxl_config_get_pasid_info(struct pci_dev *dev, int *count)
764 {
765 return pnv_ocxl_get_pasid_count(dev, count);
766 }
767
ocxl_config_set_afu_pasid(struct pci_dev * dev,int pos,int pasid_base,u32 pasid_count_log)768 void ocxl_config_set_afu_pasid(struct pci_dev *dev, int pos, int pasid_base,
769 u32 pasid_count_log)
770 {
771 u8 val8;
772 u32 val32;
773
774 val8 = pasid_count_log & OCXL_DVSEC_PASID_LOG_MASK;
775 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_EN, val8);
776
777 pci_read_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
778 &val32);
779 val32 &= ~OCXL_DVSEC_PASID_MASK;
780 val32 |= pasid_base & OCXL_DVSEC_PASID_MASK;
781 pci_write_config_dword(dev, pos + OCXL_DVSEC_AFU_CTRL_PASID_BASE,
782 val32);
783 }
784 EXPORT_SYMBOL_GPL(ocxl_config_set_afu_pasid);
785
ocxl_config_set_afu_state(struct pci_dev * dev,int pos,int enable)786 void ocxl_config_set_afu_state(struct pci_dev *dev, int pos, int enable)
787 {
788 u8 val;
789
790 pci_read_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, &val);
791 if (enable)
792 val |= 1;
793 else
794 val &= 0xFE;
795 pci_write_config_byte(dev, pos + OCXL_DVSEC_AFU_CTRL_ENABLE, val);
796 }
797 EXPORT_SYMBOL_GPL(ocxl_config_set_afu_state);
798
ocxl_config_set_TL(struct pci_dev * dev,int tl_dvsec)799 int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec)
800 {
801 u32 val;
802 __be32 *be32ptr;
803 u8 timers;
804 int i, rc;
805 long recv_cap;
806 char *recv_rate;
807
808 /*
809 * Skip on function != 0, as the TL can only be defined on 0
810 */
811 if (PCI_FUNC(dev->devfn) != 0)
812 return 0;
813
814 recv_rate = kzalloc(PNV_OCXL_TL_RATE_BUF_SIZE, GFP_KERNEL);
815 if (!recv_rate)
816 return -ENOMEM;
817 /*
818 * The spec defines 64 templates for messages in the
819 * Transaction Layer (TL).
820 *
821 * The host and device each support a subset, so we need to
822 * configure the transmitters on each side to send only
823 * templates the receiver understands, at a rate the receiver
824 * can process. Per the spec, template 0 must be supported by
825 * everybody. That's the template which has been used by the
826 * host and device so far.
827 *
828 * The sending rate limit must be set before the template is
829 * enabled.
830 */
831
832 /*
833 * Device -> host
834 */
835 rc = pnv_ocxl_get_tl_cap(dev, &recv_cap, recv_rate,
836 PNV_OCXL_TL_RATE_BUF_SIZE);
837 if (rc)
838 goto out;
839
840 for (i = 0; i < PNV_OCXL_TL_RATE_BUF_SIZE; i += 4) {
841 be32ptr = (__be32 *) &recv_rate[i];
842 pci_write_config_dword(dev,
843 tl_dvsec + OCXL_DVSEC_TL_SEND_RATE + i,
844 be32_to_cpu(*be32ptr));
845 }
846 val = recv_cap >> 32;
847 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP, val);
848 val = recv_cap & GENMASK(31, 0);
849 pci_write_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_SEND_CAP + 4, val);
850
851 /*
852 * Host -> device
853 */
854 for (i = 0; i < PNV_OCXL_TL_RATE_BUF_SIZE; i += 4) {
855 pci_read_config_dword(dev,
856 tl_dvsec + OCXL_DVSEC_TL_RECV_RATE + i,
857 &val);
858 be32ptr = (__be32 *) &recv_rate[i];
859 *be32ptr = cpu_to_be32(val);
860 }
861 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP, &val);
862 recv_cap = (long) val << 32;
863 pci_read_config_dword(dev, tl_dvsec + OCXL_DVSEC_TL_RECV_CAP + 4, &val);
864 recv_cap |= val;
865
866 rc = pnv_ocxl_set_tl_conf(dev, recv_cap, __pa(recv_rate),
867 PNV_OCXL_TL_RATE_BUF_SIZE);
868 if (rc)
869 goto out;
870
871 /*
872 * Opencapi commands needing to be retried are classified per
873 * the TL in 2 groups: short and long commands.
874 *
875 * The short back off timer it not used for now. It will be
876 * for opencapi 4.0.
877 *
878 * The long back off timer is typically used when an AFU hits
879 * a page fault but the NPU is already processing one. So the
880 * AFU needs to wait before it can resubmit. Having a value
881 * too low doesn't break anything, but can generate extra
882 * traffic on the link.
883 * We set it to 1.6 us for now. It's shorter than, but in the
884 * same order of magnitude as the time spent to process a page
885 * fault.
886 */
887 timers = 0x2 << 4; /* long timer = 1.6 us */
888 pci_write_config_byte(dev, tl_dvsec + OCXL_DVSEC_TL_BACKOFF_TIMERS,
889 timers);
890
891 rc = 0;
892 out:
893 kfree(recv_rate);
894 return rc;
895 }
896 EXPORT_SYMBOL_GPL(ocxl_config_set_TL);
897
ocxl_config_terminate_pasid(struct pci_dev * dev,int afu_control,int pasid)898 int ocxl_config_terminate_pasid(struct pci_dev *dev, int afu_control, int pasid)
899 {
900 u32 val;
901 unsigned long timeout;
902
903 pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
904 &val);
905 if (EXTRACT_BIT(val, 20)) {
906 dev_err(&dev->dev,
907 "Can't terminate PASID %#x, previous termination didn't complete\n",
908 pasid);
909 return -EBUSY;
910 }
911
912 val &= ~OCXL_DVSEC_PASID_MASK;
913 val |= pasid & OCXL_DVSEC_PASID_MASK;
914 val |= BIT(20);
915 pci_write_config_dword(dev,
916 afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
917 val);
918
919 timeout = jiffies + (HZ * OCXL_CFG_TIMEOUT);
920 pci_read_config_dword(dev, afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
921 &val);
922 while (EXTRACT_BIT(val, 20)) {
923 if (time_after_eq(jiffies, timeout)) {
924 dev_err(&dev->dev,
925 "Timeout while waiting for AFU to terminate PASID %#x\n",
926 pasid);
927 return -EBUSY;
928 }
929 cpu_relax();
930 pci_read_config_dword(dev,
931 afu_control + OCXL_DVSEC_AFU_CTRL_TERM_PASID,
932 &val);
933 }
934 return 0;
935 }
936 EXPORT_SYMBOL_GPL(ocxl_config_terminate_pasid);
937
ocxl_config_set_actag(struct pci_dev * dev,int func_dvsec,u32 tag_first,u32 tag_count)938 void ocxl_config_set_actag(struct pci_dev *dev, int func_dvsec, u32 tag_first,
939 u32 tag_count)
940 {
941 u32 val;
942
943 val = (tag_first & OCXL_DVSEC_ACTAG_MASK) << 16;
944 val |= tag_count & OCXL_DVSEC_ACTAG_MASK;
945 pci_write_config_dword(dev, func_dvsec + OCXL_DVSEC_FUNC_OFF_ACTAG,
946 val);
947 }
948 EXPORT_SYMBOL_GPL(ocxl_config_set_actag);
949