1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7
8 #include "odm_precomp.h"
9 #include "phy.h"
10
11 u32 GlobalDebugLevel;
12
13 /* avoid to warn in FreeBSD ==> To DO modify */
14 static u32 EDCAParam[HT_IOT_PEER_MAX][3] = {
15 /* UL DL */
16 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */
17 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */
18 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */
19 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */
20 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */
21 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */
22 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */
23 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */
24 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP=> 92U AP */
25 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */
26 };
27
28 /* Global var */
29 u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = {
30 0x7f8001fe, /* 0, +6.0dB */
31 0x788001e2, /* 1, +5.5dB */
32 0x71c001c7, /* 2, +5.0dB */
33 0x6b8001ae, /* 3, +4.5dB */
34 0x65400195, /* 4, +4.0dB */
35 0x5fc0017f, /* 5, +3.5dB */
36 0x5a400169, /* 6, +3.0dB */
37 0x55400155, /* 7, +2.5dB */
38 0x50800142, /* 8, +2.0dB */
39 0x4c000130, /* 9, +1.5dB */
40 0x47c0011f, /* 10, +1.0dB */
41 0x43c0010f, /* 11, +0.5dB */
42 0x40000100, /* 12, +0dB */
43 0x3c8000f2, /* 13, -0.5dB */
44 0x390000e4, /* 14, -1.0dB */
45 0x35c000d7, /* 15, -1.5dB */
46 0x32c000cb, /* 16, -2.0dB */
47 0x300000c0, /* 17, -2.5dB */
48 0x2d4000b5, /* 18, -3.0dB */
49 0x2ac000ab, /* 19, -3.5dB */
50 0x288000a2, /* 20, -4.0dB */
51 0x26000098, /* 21, -4.5dB */
52 0x24000090, /* 22, -5.0dB */
53 0x22000088, /* 23, -5.5dB */
54 0x20000080, /* 24, -6.0dB */
55 0x1e400079, /* 25, -6.5dB */
56 0x1c800072, /* 26, -7.0dB */
57 0x1b00006c, /* 27. -7.5dB */
58 0x19800066, /* 28, -8.0dB */
59 0x18000060, /* 29, -8.5dB */
60 0x16c0005b, /* 30, -9.0dB */
61 0x15800056, /* 31, -9.5dB */
62 0x14400051, /* 32, -10.0dB */
63 0x1300004c, /* 33, -10.5dB */
64 0x12000048, /* 34, -11.0dB */
65 0x11000044, /* 35, -11.5dB */
66 0x10000040, /* 36, -12.0dB */
67 0x0f00003c,/* 37, -12.5dB */
68 0x0e400039,/* 38, -13.0dB */
69 0x0d800036,/* 39, -13.5dB */
70 0x0cc00033,/* 40, -14.0dB */
71 0x0c000030,/* 41, -14.5dB */
72 0x0b40002d,/* 42, -15.0dB */
73 };
74
75 u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
76 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
77 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
78 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
79 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
80 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
81 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
82 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
83 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
84 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
85 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
86 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
87 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
88 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
89 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
90 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
91 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
92 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
93 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
94 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
95 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
96 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
97 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
98 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
99 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
100 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
101 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
102 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
103 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
104 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
105 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
106 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
107 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
108 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
109 };
110
111 u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = {
112 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
113 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
114 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
115 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
116 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
117 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
118 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
119 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
120 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
121 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
122 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
123 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
124 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */
125 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
126 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
127 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
128 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
129 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
130 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
131 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
132 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
133 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
134 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
135 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
136 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
137 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
138 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
139 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
140 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
141 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
142 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
143 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
144 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
145 };
146
147 #define RxDefaultAnt1 0x65a9
148 #define RxDefaultAnt2 0x569a
149
ODM_InitDebugSetting(struct odm_dm_struct * pDM_Odm)150 void ODM_InitDebugSetting(struct odm_dm_struct *pDM_Odm)
151 {
152 pDM_Odm->DebugLevel = ODM_DBG_TRACE;
153
154 pDM_Odm->DebugComponents = 0;
155 }
156
157 /* 3 Export Interface */
158
159 /* 2011/09/21 MH Add to describe different team necessary resource allocate?? */
ODM_DMInit(struct odm_dm_struct * pDM_Odm)160 void ODM_DMInit(struct odm_dm_struct *pDM_Odm)
161 {
162 /* 2012.05.03 Luke: For all IC series */
163 odm_CommonInfoSelfInit(pDM_Odm);
164 odm_CmnInfoInit_Debug(pDM_Odm);
165 odm_DIGInit(pDM_Odm);
166 odm_RateAdaptiveMaskInit(pDM_Odm);
167
168 odm_DynamicTxPowerInit(pDM_Odm);
169 odm_TXPowerTrackingInit(pDM_Odm);
170 ODM_EdcaTurboInit(pDM_Odm);
171 ODM_RAInfo_Init_all(pDM_Odm);
172 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||
173 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
174 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
175 odm_InitHybridAntDiv(pDM_Odm);
176 }
177
178 /* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
179 /* You can not add any dummy function here, be care, you can only use DM structure */
180 /* to perform any new ODM_DM. */
ODM_DMWatchdog(struct odm_dm_struct * pDM_Odm)181 void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm)
182 {
183 /* 2012.05.03 Luke: For all IC series */
184 odm_CmnInfoHook_Debug(pDM_Odm);
185 odm_CmnInfoUpdate_Debug(pDM_Odm);
186 odm_CommonInfoSelfUpdate(pDM_Odm);
187 odm_FalseAlarmCounterStatistics(pDM_Odm);
188 odm_RSSIMonitorCheck(pDM_Odm);
189
190 /* Fix Leave LPS issue */
191 odm_DIG(pDM_Odm);
192 odm_CCKPacketDetectionThresh(pDM_Odm);
193
194 if (*pDM_Odm->pbPowerSaving)
195 return;
196
197 odm_RefreshRateAdaptiveMask(pDM_Odm);
198
199 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||
200 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
201 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
202 odm_HwAntDiv(pDM_Odm);
203
204 ODM_TXPowerTrackingCheck(pDM_Odm);
205 odm_EdcaTurboCheck(pDM_Odm);
206 }
207
ODM_CmnInfoPtrArrayHook(struct odm_dm_struct * pDM_Odm,enum odm_common_info_def CmnInfo,u16 Index,void * pValue)208 void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u16 Index, void *pValue)
209 {
210 if (CmnInfo == ODM_CMNINFO_STA_STATUS)
211 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue;
212 }
213
odm_CommonInfoSelfInit(struct odm_dm_struct * pDM_Odm)214 void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm)
215 {
216 struct adapter *adapter = pDM_Odm->Adapter;
217
218 pDM_Odm->bCckHighPower = (bool)phy_query_bb_reg(adapter, 0x824, BIT(9));
219 pDM_Odm->RFPathRxEnable = (u8)phy_query_bb_reg(adapter, 0xc04, 0x0F);
220
221 ODM_InitDebugSetting(pDM_Odm);
222 }
223
odm_CommonInfoSelfUpdate(struct odm_dm_struct * pDM_Odm)224 void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm)
225 {
226 u8 EntryCnt = 0;
227 u8 i;
228 struct sta_info *pEntry;
229
230 if (*pDM_Odm->pBandWidth == ODM_BW40M) {
231 if (*pDM_Odm->pSecChOffset == 1)
232 pDM_Odm->ControlChannel = *pDM_Odm->pChannel - 2;
233 else if (*pDM_Odm->pSecChOffset == 2)
234 pDM_Odm->ControlChannel = *pDM_Odm->pChannel + 2;
235 } else {
236 pDM_Odm->ControlChannel = *pDM_Odm->pChannel;
237 }
238
239 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
240 pEntry = pDM_Odm->pODM_StaInfo[i];
241 if (IS_STA_VALID(pEntry))
242 EntryCnt++;
243 }
244 if (EntryCnt == 1)
245 pDM_Odm->bOneEntryOnly = true;
246 else
247 pDM_Odm->bOneEntryOnly = false;
248 }
249
odm_CmnInfoInit_Debug(struct odm_dm_struct * pDM_Odm)250 void odm_CmnInfoInit_Debug(struct odm_dm_struct *pDM_Odm)
251 {
252 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("%s==>\n", __func__));
253 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n", pDM_Odm->SupportPlatform));
254 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n", pDM_Odm->SupportAbility));
255 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n", pDM_Odm->SupportInterface));
256 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n", pDM_Odm->SupportICType));
257 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n", pDM_Odm->CutVersion));
258 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n", pDM_Odm->BoardType));
259 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n", pDM_Odm->ExtLNA));
260 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n", pDM_Odm->ExtPA));
261 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n", pDM_Odm->ExtTRSW));
262 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n", pDM_Odm->PatchID));
263 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n", pDM_Odm->bInHctTest));
264 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n", pDM_Odm->bWIFITest));
265 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n", pDM_Odm->bDualMacSmartConcurrent));
266 }
267
odm_CmnInfoHook_Debug(struct odm_dm_struct * pDM_Odm)268 void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm)
269 {
270 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("%s==>\n", __func__));
271 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n", *pDM_Odm->pNumTxBytesUnicast));
272 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n", *pDM_Odm->pNumRxBytesUnicast));
273 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n", *pDM_Odm->pWirelessMode));
274 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n", *pDM_Odm->pSecChOffset));
275 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n", *pDM_Odm->pSecurity));
276 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n", *pDM_Odm->pBandWidth));
277 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n", *pDM_Odm->pChannel));
278
279 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n", *pDM_Odm->pbScanInProcess));
280 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n", *pDM_Odm->pbPowerSaving));
281 }
282
odm_CmnInfoUpdate_Debug(struct odm_dm_struct * pDM_Odm)283 void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm)
284 {
285 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("%s==>\n", __func__));
286 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n", pDM_Odm->bWIFI_Direct));
287 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n", pDM_Odm->bWIFI_Display));
288 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n", pDM_Odm->bLinked));
289 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n", pDM_Odm->RSSI_Min));
290 }
291
ODM_Write_DIG(struct odm_dm_struct * pDM_Odm,u8 CurrentIGI)292 void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI)
293 {
294 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
295 struct adapter *adapter = pDM_Odm->Adapter;
296
297 if (pDM_DigTable->CurIGValue != CurrentIGI) {
298 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N, CurrentIGI);
299 pDM_DigTable->CurIGValue = CurrentIGI;
300 }
301 }
302
odm_DIGInit(struct odm_dm_struct * pDM_Odm)303 void odm_DIGInit(struct odm_dm_struct *pDM_Odm)
304 {
305 struct adapter *adapter = pDM_Odm->Adapter;
306 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
307
308 pDM_DigTable->CurIGValue = (u8)phy_query_bb_reg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N);
309 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW;
310 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH;
311 pDM_DigTable->FALowThresh = DM_false_ALARM_THRESH_LOW;
312 pDM_DigTable->FAHighThresh = DM_false_ALARM_THRESH_HIGH;
313 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
314 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
315 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
316 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
317 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
318 pDM_DigTable->PreCCK_CCAThres = 0xFF;
319 pDM_DigTable->CurCCK_CCAThres = 0x83;
320 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
321 pDM_DigTable->LargeFAHit = 0;
322 pDM_DigTable->Recover_cnt = 0;
323 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
324 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
325 pDM_DigTable->bMediaConnect_0 = false;
326 pDM_DigTable->bMediaConnect_1 = false;
327
328 /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */
329 pDM_Odm->bDMInitialGainEnable = true;
330 }
331
odm_DIG(struct odm_dm_struct * pDM_Odm)332 void odm_DIG(struct odm_dm_struct *pDM_Odm)
333 {
334 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
335 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
336 u8 DIG_Dynamic_MIN;
337 u8 DIG_MaxOfMin;
338 bool FirstConnect, FirstDisConnect;
339 u8 dm_dig_max, dm_dig_min;
340 u8 CurrentIGI = pDM_DigTable->CurIGValue;
341
342 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("%s()==>\n", __func__));
343 if ((!(pDM_Odm->SupportAbility & ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))) {
344 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
345 ("%s() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n", __func__));
346 return;
347 }
348
349 if (*pDM_Odm->pbScanInProcess) {
350 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("%s() Return: In Scan Progress\n", __func__));
351 return;
352 }
353
354 /* add by Neil Chen to avoid PSD is processing */
355 if (!pDM_Odm->bDMInitialGainEnable) {
356 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("%s() Return: PSD is Processing\n", __func__));
357 return;
358 }
359
360 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
361 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
362 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
363
364 /* 1 Boundary Decision */
365 dm_dig_max = DM_DIG_MAX_NIC;
366 dm_dig_min = DM_DIG_MIN_NIC;
367 DIG_MaxOfMin = DM_DIG_MAX_AP;
368
369 if (pDM_Odm->bLinked) {
370 /* 2 Modify DIG upper bound */
371 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
372 pDM_DigTable->rx_gain_range_max = dm_dig_max;
373 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min)
374 pDM_DigTable->rx_gain_range_max = dm_dig_min;
375 else
376 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
377 /* 2 Modify DIG lower bound */
378 if (pDM_Odm->bOneEntryOnly) {
379 if (pDM_Odm->RSSI_Min < dm_dig_min)
380 DIG_Dynamic_MIN = dm_dig_min;
381 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
382 DIG_Dynamic_MIN = DIG_MaxOfMin;
383 else
384 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
385 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
386 ("%s() : bOneEntryOnly=true, DIG_Dynamic_MIN=0x%x\n",
387 __func__, DIG_Dynamic_MIN));
388 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
389 ("%s() : pDM_Odm->RSSI_Min=%d\n",
390 __func__, pDM_Odm->RSSI_Min));
391 } else if (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) {
392 /* 1 Lower Bound for 88E AntDiv */
393 if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) {
394 DIG_Dynamic_MIN = (u8)pDM_DigTable->AntDiv_RSSI_max;
395 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
396 ("%s(): pDM_DigTable->AntDiv_RSSI_max=%d\n",
397 __func__, pDM_DigTable->AntDiv_RSSI_max));
398 }
399 } else {
400 DIG_Dynamic_MIN = dm_dig_min;
401 }
402 } else {
403 pDM_DigTable->rx_gain_range_max = dm_dig_max;
404 DIG_Dynamic_MIN = dm_dig_min;
405 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("%s() : No Link\n", __func__));
406 }
407
408 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */
409 if (pFalseAlmCnt->Cnt_all > 10000) {
410 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnormally false alarm case.\n"));
411
412 if (pDM_DigTable->LargeFAHit != 3)
413 pDM_DigTable->LargeFAHit++;
414 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) {
415 pDM_DigTable->ForbiddenIGI = CurrentIGI;
416 pDM_DigTable->LargeFAHit = 1;
417 }
418
419 if (pDM_DigTable->LargeFAHit >= 3) {
420 if ((pDM_DigTable->ForbiddenIGI + 1) > pDM_DigTable->rx_gain_range_max)
421 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
422 else
423 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
424 pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */
425 }
426
427 } else {
428 /* Recovery mechanism for IGI lower bound */
429 if (pDM_DigTable->Recover_cnt != 0) {
430 pDM_DigTable->Recover_cnt--;
431 } else {
432 if (pDM_DigTable->LargeFAHit < 3) {
433 if ((pDM_DigTable->ForbiddenIGI - 1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */
434 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
435 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
436 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("%s(): Normal Case: At Lower Bound\n", __func__));
437 } else {
438 pDM_DigTable->ForbiddenIGI--;
439 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
440 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("%s(): Normal Case: Approach Lower Bound\n", __func__));
441 }
442 } else {
443 pDM_DigTable->LargeFAHit = 0;
444 }
445 }
446 }
447 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
448 ("%s(): pDM_DigTable->LargeFAHit=%d\n",
449 __func__, pDM_DigTable->LargeFAHit));
450
451 /* 1 Adjust initial gain by false alarm */
452 if (pDM_Odm->bLinked) {
453 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("%s(): DIG AfterLink\n", __func__));
454 if (FirstConnect) {
455 CurrentIGI = pDM_Odm->RSSI_Min;
456 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
457 } else {
458 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
459 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
460 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
461 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
462 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
463 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
464 }
465 } else {
466 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("%s(): DIG BeforeLink\n", __func__));
467 if (FirstDisConnect) {
468 CurrentIGI = pDM_DigTable->rx_gain_range_min;
469 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("%s(): First DisConnect\n", __func__));
470 } else {
471 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */
472 if (pFalseAlmCnt->Cnt_all > 10000)
473 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
474 else if (pFalseAlmCnt->Cnt_all > 8000)
475 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
476 else if (pFalseAlmCnt->Cnt_all < 500)
477 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
478 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("%s(): England DIG\n", __func__));
479 }
480 }
481 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("%s(): DIG End Adjust IGI\n", __func__));
482 /* 1 Check initial gain by upper/lower bound */
483 if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
484 CurrentIGI = pDM_DigTable->rx_gain_range_max;
485 if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
486 CurrentIGI = pDM_DigTable->rx_gain_range_min;
487
488 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
489 ("%s(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n",
490 __func__, pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
491 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("%s(): TotalFA=%d\n", __func__, pFalseAlmCnt->Cnt_all));
492 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("%s(): CurIGValue=0x%x\n", __func__, CurrentIGI));
493
494 /* 2 High power RSSI threshold */
495
496 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */
497 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
498 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
499 }
500
501 /* 3============================================================ */
502 /* 3 FASLE ALARM CHECK */
503 /* 3============================================================ */
504
odm_FalseAlarmCounterStatistics(struct odm_dm_struct * pDM_Odm)505 void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm)
506 {
507 struct adapter *adapter = pDM_Odm->Adapter;
508 u32 ret_value;
509 struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
510
511 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
512 return;
513
514 /* hold ofdm counter */
515 phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */
516 phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */
517
518 ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
519 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value & 0xffff);
520 FalseAlmCnt->Cnt_SB_Search_fail = (ret_value & 0xffff0000) >> 16;
521 ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
522 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value & 0xffff);
523 FalseAlmCnt->Cnt_Parity_Fail = (ret_value & 0xffff0000) >> 16;
524 ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
525 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value & 0xffff);
526 FalseAlmCnt->Cnt_Crc8_fail = (ret_value & 0xffff0000) >> 16;
527 ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
528 FalseAlmCnt->Cnt_Mcs_fail = (ret_value & 0xffff);
529
530 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal +
531 FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail +
532 FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail;
533
534 ret_value = phy_query_bb_reg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord);
535 FalseAlmCnt->Cnt_BW_LSC = (ret_value & 0xffff);
536 FalseAlmCnt->Cnt_BW_USC = (ret_value & 0xffff0000) >> 16;
537
538 /* hold cck counter */
539 phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
540 phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
541
542 ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
543 FalseAlmCnt->Cnt_Cck_fail = ret_value;
544 ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
545 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff) << 8;
546
547 ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
548 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value & 0xFF) << 8) | ((ret_value & 0xFF00) >> 8);
549
550 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
551 FalseAlmCnt->Cnt_SB_Search_fail +
552 FalseAlmCnt->Cnt_Parity_Fail +
553 FalseAlmCnt->Cnt_Rate_Illegal +
554 FalseAlmCnt->Cnt_Crc8_fail +
555 FalseAlmCnt->Cnt_Mcs_fail +
556 FalseAlmCnt->Cnt_Cck_fail);
557
558 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
559
560 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter %s\n", __func__));
561 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
562 ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n",
563 FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail));
564 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
565 ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n",
566 FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal));
567 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
568 ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n",
569 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
570 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail));
571 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail));
572 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all));
573 }
574
575 /* 3============================================================ */
576 /* 3 CCK Packet Detect Threshold */
577 /* 3============================================================ */
578
odm_CCKPacketDetectionThresh(struct odm_dm_struct * pDM_Odm)579 void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm)
580 {
581 u8 CurCCK_CCAThres;
582 struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
583
584 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD | ODM_BB_FA_CNT)))
585 return;
586 if (pDM_Odm->ExtLNA)
587 return;
588 if (pDM_Odm->bLinked) {
589 if (pDM_Odm->RSSI_Min > 25) {
590 CurCCK_CCAThres = 0xcd;
591 } else if (pDM_Odm->RSSI_Min > 10) {
592 CurCCK_CCAThres = 0x83;
593 } else {
594 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
595 CurCCK_CCAThres = 0x83;
596 else
597 CurCCK_CCAThres = 0x40;
598 }
599 } else {
600 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
601 CurCCK_CCAThres = 0x83;
602 else
603 CurCCK_CCAThres = 0x40;
604 }
605 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres);
606 }
607
ODM_Write_CCK_CCA_Thres(struct odm_dm_struct * pDM_Odm,u8 CurCCK_CCAThres)608 void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres)
609 {
610 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable;
611 struct adapter *adapt = pDM_Odm->Adapter;
612
613 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */
614 usb_write8(adapt, ODM_REG_CCK_CCA_11N, CurCCK_CCAThres);
615 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
616 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
617 }
618
ODM_RF_Saving(struct odm_dm_struct * pDM_Odm,u8 bForceInNormal)619 void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal)
620 {
621 struct adapter *adapter = pDM_Odm->Adapter;
622 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable;
623 u8 Rssi_Up_bound = 30;
624 u8 Rssi_Low_bound = 25;
625
626 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
627 Rssi_Up_bound = 50;
628 Rssi_Low_bound = 45;
629 }
630 if (pDM_PSTable->initialize == 0) {
631 pDM_PSTable->Reg874 = (phy_query_bb_reg(adapter, 0x874, bMaskDWord) & 0x1CC000) >> 14;
632 pDM_PSTable->RegC70 = (phy_query_bb_reg(adapter, 0xc70, bMaskDWord) & BIT(3)) >> 3;
633 pDM_PSTable->Reg85C = (phy_query_bb_reg(adapter, 0x85c, bMaskDWord) & 0xFF000000) >> 24;
634 pDM_PSTable->RegA74 = (phy_query_bb_reg(adapter, 0xa74, bMaskDWord) & 0xF000) >> 12;
635 pDM_PSTable->initialize = 1;
636 }
637
638 if (!bForceInNormal) {
639 if (pDM_Odm->RSSI_Min != 0xFF) {
640 if (pDM_PSTable->PreRFState == RF_Normal) {
641 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
642 pDM_PSTable->CurRFState = RF_Save;
643 else
644 pDM_PSTable->CurRFState = RF_Normal;
645 } else {
646 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
647 pDM_PSTable->CurRFState = RF_Normal;
648 else
649 pDM_PSTable->CurRFState = RF_Save;
650 }
651 } else {
652 pDM_PSTable->CurRFState = RF_MAX;
653 }
654 } else {
655 pDM_PSTable->CurRFState = RF_Normal;
656 }
657
658 if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
659 if (pDM_PSTable->CurRFState == RF_Save) {
660 phy_set_bb_reg(adapter, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */
661 phy_set_bb_reg(adapter, 0xc70, BIT(3), 0); /* RegC70[3]=1'b0 */
662 phy_set_bb_reg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */
663 phy_set_bb_reg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */
664 phy_set_bb_reg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */
665 phy_set_bb_reg(adapter, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */
666 phy_set_bb_reg(adapter, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */
667 } else {
668 phy_set_bb_reg(adapter, 0x874, 0x1CC000, pDM_PSTable->Reg874);
669 phy_set_bb_reg(adapter, 0xc70, BIT(3), pDM_PSTable->RegC70);
670 phy_set_bb_reg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
671 phy_set_bb_reg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74);
672 phy_set_bb_reg(adapter, 0x818, BIT(28), 0x0);
673 }
674 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
675 }
676 }
677
678 /* 3============================================================ */
679 /* 3 RATR MASK */
680 /* 3============================================================ */
681 /* 3============================================================ */
682 /* 3 Rate Adaptive */
683 /* 3============================================================ */
684
odm_RateAdaptiveMaskInit(struct odm_dm_struct * pDM_Odm)685 void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm)
686 {
687 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive;
688
689 pOdmRA->Type = DM_Type_ByDriver;
690 if (pOdmRA->Type == DM_Type_ByDriver)
691 pDM_Odm->bUseRAMask = true;
692 else
693 pDM_Odm->bUseRAMask = false;
694
695 pOdmRA->RATRState = DM_RATR_STA_INIT;
696 pOdmRA->HighRSSIThresh = 50;
697 pOdmRA->LowRSSIThresh = 20;
698 }
699
ODM_Get_Rate_Bitmap(struct odm_dm_struct * pDM_Odm,u32 macid,u32 ra_mask,u8 rssi_level)700 u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level)
701 {
702 struct sta_info *pEntry;
703 u32 rate_bitmap = 0x0fffffff;
704 u8 WirelessMode;
705
706 pEntry = pDM_Odm->pODM_StaInfo[macid];
707 if (!IS_STA_VALID(pEntry))
708 return ra_mask;
709
710 WirelessMode = pEntry->wireless_mode;
711
712 switch (WirelessMode) {
713 case ODM_WM_B:
714 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */
715 rate_bitmap = 0x0000000d;
716 else
717 rate_bitmap = 0x0000000f;
718 break;
719 case (ODM_WM_A | ODM_WM_G):
720 if (rssi_level == DM_RATR_STA_HIGH)
721 rate_bitmap = 0x00000f00;
722 else
723 rate_bitmap = 0x00000ff0;
724 break;
725 case (ODM_WM_B | ODM_WM_G):
726 if (rssi_level == DM_RATR_STA_HIGH)
727 rate_bitmap = 0x00000f00;
728 else if (rssi_level == DM_RATR_STA_MIDDLE)
729 rate_bitmap = 0x00000ff0;
730 else
731 rate_bitmap = 0x00000ff5;
732 break;
733 case (ODM_WM_B | ODM_WM_G | ODM_WM_N24G):
734 case (ODM_WM_A | ODM_WM_B | ODM_WM_G | ODM_WM_N24G):
735 if (rssi_level == DM_RATR_STA_HIGH) {
736 rate_bitmap = 0x000f0000;
737 } else if (rssi_level == DM_RATR_STA_MIDDLE) {
738 rate_bitmap = 0x000ff000;
739 } else {
740 if (*pDM_Odm->pBandWidth == ODM_BW40M)
741 rate_bitmap = 0x000ff015;
742 else
743 rate_bitmap = 0x000ff005;
744 }
745 break;
746 default:
747 /* case WIRELESS_11_24N: */
748 /* case WIRELESS_11_5N: */
749 rate_bitmap = 0x0fffffff;
750 break;
751 }
752
753 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
754 (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n",
755 rssi_level, WirelessMode, rate_bitmap));
756
757 return rate_bitmap;
758 }
759
760 /* Update rate table mask according to rssi */
odm_RefreshRateAdaptiveMask(struct odm_dm_struct * pDM_Odm)761 void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm)
762 {
763 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
764 return;
765 /* */
766 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
767 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
768 /* HW dynamic mechanism. */
769 /* */
770 odm_RefreshRateAdaptiveMaskCE(pDM_Odm);
771 }
772
odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct * pDM_Odm)773 void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm)
774 {
775 u8 i;
776 struct adapter *pAdapter = pDM_Odm->Adapter;
777
778 if (pAdapter->bDriverStopped) {
779 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n"));
780 return;
781 }
782
783 if (!pDM_Odm->bUseRAMask) {
784 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n"));
785 return;
786 }
787
788 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
789 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
790
791 if (IS_STA_VALID(pstat)) {
792 if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level)) {
793 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
794 ("RSSI:%d, RSSI_LEVEL:%d\n",
795 pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level));
796 rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level);
797 }
798 }
799 }
800 }
801
802 /* Return Value: bool */
803 /* - true: RATRState is changed. */
ODM_RAStateCheck(struct odm_dm_struct * pDM_Odm,s32 RSSI,bool bForceUpdate,u8 * pRATRState)804 bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState)
805 {
806 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive;
807 const u8 GoUpGap = 5;
808 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
809 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
810 u8 RATRState;
811
812 /* Threshold Adjustment: */
813 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */
814 /* Here GoUpGap is added to solve the boundary's level alternation issue. */
815 switch (*pRATRState) {
816 case DM_RATR_STA_INIT:
817 case DM_RATR_STA_HIGH:
818 break;
819 case DM_RATR_STA_MIDDLE:
820 HighRSSIThreshForRA += GoUpGap;
821 break;
822 case DM_RATR_STA_LOW:
823 HighRSSIThreshForRA += GoUpGap;
824 LowRSSIThreshForRA += GoUpGap;
825 break;
826 default:
827 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState));
828 break;
829 }
830
831 /* Decide RATRState by RSSI. */
832 if (HighRSSIThreshForRA < RSSI)
833 RATRState = DM_RATR_STA_HIGH;
834 else if (LowRSSIThreshForRA < RSSI)
835 RATRState = DM_RATR_STA_MIDDLE;
836 else
837 RATRState = DM_RATR_STA_LOW;
838
839 if (*pRATRState != RATRState || bForceUpdate) {
840 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState));
841 *pRATRState = RATRState;
842 return true;
843 }
844 return false;
845 }
846
847 /* 3============================================================ */
848 /* 3 Dynamic Tx Power */
849 /* 3============================================================ */
850
odm_DynamicTxPowerInit(struct odm_dm_struct * pDM_Odm)851 void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm)
852 {
853 struct adapter *Adapter = pDM_Odm->Adapter;
854 struct dm_priv *pdmpriv = &Adapter->HalData->dmpriv;
855
856 pdmpriv->bDynamicTxPowerEnable = false;
857 pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
858 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
859 }
860
861 /* 3============================================================ */
862 /* 3 RSSI Monitor */
863 /* 3============================================================ */
864
odm_RSSIMonitorCheck(struct odm_dm_struct * pDM_Odm)865 void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm)
866 {
867 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
868 return;
869
870 /* */
871 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
872 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
873 /* HW dynamic mechanism. */
874 /* */
875 odm_RSSIMonitorCheckCE(pDM_Odm);
876 } /* odm_RSSIMonitorCheck */
877
FindMinimumRSSI(struct adapter * pAdapter)878 static void FindMinimumRSSI(struct adapter *pAdapter)
879 {
880 struct dm_priv *pdmpriv = &pAdapter->HalData->dmpriv;
881
882 /* 1 1.Unconditionally set RSSI */
883 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
884 }
885
odm_RSSIMonitorCheckCE(struct odm_dm_struct * pDM_Odm)886 void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm)
887 {
888 struct adapter *Adapter = pDM_Odm->Adapter;
889 struct dm_priv *pdmpriv = &Adapter->HalData->dmpriv;
890 int i;
891 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff;
892 u8 sta_cnt = 0;
893 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */
894 struct sta_info *psta;
895 u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
896
897 if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED))
898 return;
899
900 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
901 psta = pDM_Odm->pODM_StaInfo[i];
902 if (IS_STA_VALID(psta) &&
903 (psta->state & WIFI_ASOC_STATE) &&
904 memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) &&
905 memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) {
906 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
907 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
908
909 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
910 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
911 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1))
912 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB << 16));
913 }
914 }
915
916 for (i = 0; i < sta_cnt; i++) {
917 if (PWDB_rssi[i] != 0) {
918 ODM_RA_SetRSSI_8188E(&Adapter->HalData->odmpriv,
919 PWDB_rssi[i] & 0xFF,
920 (PWDB_rssi[i] >> 16) & 0xFF);
921 }
922 }
923
924 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */
925 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
926 else
927 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
928
929 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */
930 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
931 else
932 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
933
934 FindMinimumRSSI(Adapter);
935 Adapter->HalData->odmpriv.RSSI_Min = pdmpriv->MinUndecoratedPWDBForDM;
936 }
937
938 /* 3============================================================ */
939 /* 3 Tx Power Tracking */
940 /* 3============================================================ */
941
odm_TXPowerTrackingInit(struct odm_dm_struct * pDM_Odm)942 void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm)
943 {
944 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true;
945 pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
946 if (*pDM_Odm->mp_mode != 1)
947 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
948 MSG_88E("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl);
949
950 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
951 }
952
ODM_TXPowerTrackingCheck(struct odm_dm_struct * pDM_Odm)953 void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm)
954 {
955 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
956 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
957 /* HW dynamic mechanism. */
958 struct adapter *Adapter = pDM_Odm->Adapter;
959
960 if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK))
961 return;
962
963 if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */
964 phy_set_rf_reg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
965
966 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;
967 return;
968 }
969
970 rtl88eu_dm_txpower_tracking_callback_thermalmeter(Adapter);
971 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0;
972 }
973
974 /* 3============================================================ */
975 /* 3 SW Antenna Diversity */
976 /* 3============================================================ */
977
odm_InitHybridAntDiv(struct odm_dm_struct * pDM_Odm)978 void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm)
979 {
980 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) {
981 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n"));
982 return;
983 }
984
985 rtl88eu_dm_antenna_div_init(pDM_Odm);
986 }
987
odm_HwAntDiv(struct odm_dm_struct * pDM_Odm)988 void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm)
989 {
990 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) {
991 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n"));
992 return;
993 }
994
995 rtl88eu_dm_antenna_diversity(pDM_Odm);
996 }
997
998 /* EDCA Turbo */
ODM_EdcaTurboInit(struct odm_dm_struct * pDM_Odm)999 void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm)
1000 {
1001 struct adapter *Adapter = pDM_Odm->Adapter;
1002
1003 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1004 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
1005 Adapter->recvpriv.bIsAnyNonBEPkts = false;
1006
1007 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Original VO PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_VO_PARAM)));
1008 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Original VI PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_VI_PARAM)));
1009 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Original BE PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_BE_PARAM)));
1010 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Original BK PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_BK_PARAM)));
1011 } /* ODM_InitEdcaTurbo */
1012
odm_EdcaTurboCheck(struct odm_dm_struct * pDM_Odm)1013 void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm)
1014 {
1015 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1016 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1017 /* HW dynamic mechanism. */
1018 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("%s========================>\n", __func__));
1019
1020 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO))
1021 return;
1022
1023 odm_EdcaTurboCheckCE(pDM_Odm);
1024 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================%s\n", __func__));
1025 } /* odm_CheckEdcaTurbo */
1026
odm_EdcaTurboCheckCE(struct odm_dm_struct * pDM_Odm)1027 void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm)
1028 {
1029 struct adapter *Adapter = pDM_Odm->Adapter;
1030 u32 trafficIndex;
1031 u32 edca_param;
1032 u64 cur_tx_bytes = 0;
1033 u64 cur_rx_bytes = 0;
1034 u8 bbtchange = false;
1035 struct xmit_priv *pxmitpriv = &Adapter->xmitpriv;
1036 struct recv_priv *precvpriv = &Adapter->recvpriv;
1037 struct registry_priv *pregpriv = &Adapter->registrypriv;
1038 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1039 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1040
1041 if (pregpriv->wifi_spec == 1) /* (pmlmeinfo->HT_enable == 0)) */
1042 goto dm_CheckEdcaTurbo_EXIT;
1043
1044 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX)
1045 goto dm_CheckEdcaTurbo_EXIT;
1046
1047 /* Check if the status needs to be changed. */
1048 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) {
1049 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
1050 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
1051
1052 /* traffic, TX or RX */
1053 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) ||
1054 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) {
1055 if (cur_tx_bytes > (cur_rx_bytes << 2)) {
1056 /* Uplink TP is present. */
1057 trafficIndex = UP_LINK;
1058 } else {
1059 /* Balance TP is present. */
1060 trafficIndex = DOWN_LINK;
1061 }
1062 } else {
1063 if (cur_rx_bytes > (cur_tx_bytes << 2)) {
1064 /* Downlink TP is present. */
1065 trafficIndex = DOWN_LINK;
1066 } else {
1067 /* Balance TP is present. */
1068 trafficIndex = UP_LINK;
1069 }
1070 }
1071
1072 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) {
1073 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
1074 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
1075 else
1076 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
1077
1078 usb_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
1079
1080 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
1081 }
1082
1083 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
1084 } else {
1085 /* Turn Off EDCA turbo here. */
1086 /* Restore original EDCA according to the declaration of AP. */
1087 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
1088 usb_write32(Adapter, REG_EDCA_BE_PARAM,
1089 Adapter->HalData->AcParam_BE);
1090 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1091 }
1092 }
1093
1094 dm_CheckEdcaTurbo_EXIT:
1095 /* Set variables for next time. */
1096 precvpriv->bIsAnyNonBEPkts = false;
1097 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
1098 precvpriv->last_rx_bytes = precvpriv->rx_bytes;
1099 }
1100