1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2019, Mellanox Technologies */
3
4 #ifndef _DR_TYPES_
5 #define _DR_TYPES_
6
7 #include <linux/mlx5/driver.h>
8 #include <linux/refcount.h>
9 #include "fs_core.h"
10 #include "wq.h"
11 #include "lib/mlx5.h"
12 #include "mlx5_ifc_dr.h"
13 #include "mlx5dr.h"
14
15 #define DR_RULE_MAX_STES 17
16 #define DR_ACTION_MAX_STES 5
17 #define WIRE_PORT 0xFFFF
18 #define DR_STE_SVLAN 0x1
19 #define DR_STE_CVLAN 0x2
20
21 #define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg)
22 #define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg)
23 #define mlx5dr_dbg(dmn, arg...) mlx5_core_dbg((dmn)->mdev, ##arg)
24
25 enum mlx5dr_icm_chunk_size {
26 DR_CHUNK_SIZE_1,
27 DR_CHUNK_SIZE_MIN = DR_CHUNK_SIZE_1, /* keep updated when changing */
28 DR_CHUNK_SIZE_2,
29 DR_CHUNK_SIZE_4,
30 DR_CHUNK_SIZE_8,
31 DR_CHUNK_SIZE_16,
32 DR_CHUNK_SIZE_32,
33 DR_CHUNK_SIZE_64,
34 DR_CHUNK_SIZE_128,
35 DR_CHUNK_SIZE_256,
36 DR_CHUNK_SIZE_512,
37 DR_CHUNK_SIZE_1K,
38 DR_CHUNK_SIZE_2K,
39 DR_CHUNK_SIZE_4K,
40 DR_CHUNK_SIZE_8K,
41 DR_CHUNK_SIZE_16K,
42 DR_CHUNK_SIZE_32K,
43 DR_CHUNK_SIZE_64K,
44 DR_CHUNK_SIZE_128K,
45 DR_CHUNK_SIZE_256K,
46 DR_CHUNK_SIZE_512K,
47 DR_CHUNK_SIZE_1024K,
48 DR_CHUNK_SIZE_2048K,
49 DR_CHUNK_SIZE_MAX,
50 };
51
52 enum mlx5dr_icm_type {
53 DR_ICM_TYPE_STE,
54 DR_ICM_TYPE_MODIFY_ACTION,
55 };
56
57 static inline enum mlx5dr_icm_chunk_size
mlx5dr_icm_next_higher_chunk(enum mlx5dr_icm_chunk_size chunk)58 mlx5dr_icm_next_higher_chunk(enum mlx5dr_icm_chunk_size chunk)
59 {
60 chunk += 2;
61 if (chunk < DR_CHUNK_SIZE_MAX)
62 return chunk;
63
64 return DR_CHUNK_SIZE_MAX;
65 }
66
67 enum {
68 DR_STE_SIZE = 64,
69 DR_STE_SIZE_CTRL = 32,
70 DR_STE_SIZE_TAG = 16,
71 DR_STE_SIZE_MASK = 16,
72 };
73
74 enum {
75 DR_STE_SIZE_REDUCED = DR_STE_SIZE - DR_STE_SIZE_MASK,
76 };
77
78 enum {
79 DR_MODIFY_ACTION_SIZE = 8,
80 };
81
82 enum mlx5dr_matcher_criteria {
83 DR_MATCHER_CRITERIA_EMPTY = 0,
84 DR_MATCHER_CRITERIA_OUTER = 1 << 0,
85 DR_MATCHER_CRITERIA_MISC = 1 << 1,
86 DR_MATCHER_CRITERIA_INNER = 1 << 2,
87 DR_MATCHER_CRITERIA_MISC2 = 1 << 3,
88 DR_MATCHER_CRITERIA_MISC3 = 1 << 4,
89 DR_MATCHER_CRITERIA_MAX = 1 << 5,
90 };
91
92 enum mlx5dr_action_type {
93 DR_ACTION_TYP_TNL_L2_TO_L2,
94 DR_ACTION_TYP_L2_TO_TNL_L2,
95 DR_ACTION_TYP_TNL_L3_TO_L2,
96 DR_ACTION_TYP_L2_TO_TNL_L3,
97 DR_ACTION_TYP_DROP,
98 DR_ACTION_TYP_QP,
99 DR_ACTION_TYP_FT,
100 DR_ACTION_TYP_CTR,
101 DR_ACTION_TYP_TAG,
102 DR_ACTION_TYP_MODIFY_HDR,
103 DR_ACTION_TYP_VPORT,
104 DR_ACTION_TYP_POP_VLAN,
105 DR_ACTION_TYP_PUSH_VLAN,
106 DR_ACTION_TYP_MAX,
107 };
108
109 enum mlx5dr_ipv {
110 DR_RULE_IPV4,
111 DR_RULE_IPV6,
112 DR_RULE_IPV_MAX,
113 };
114
115 struct mlx5dr_icm_pool;
116 struct mlx5dr_icm_chunk;
117 struct mlx5dr_icm_bucket;
118 struct mlx5dr_ste_htbl;
119 struct mlx5dr_match_param;
120 struct mlx5dr_cmd_caps;
121 struct mlx5dr_matcher_rx_tx;
122
123 struct mlx5dr_ste {
124 u8 *hw_ste;
125 /* refcount: indicates the num of rules that using this ste */
126 u32 refcount;
127
128 /* attached to the miss_list head at each htbl entry */
129 struct list_head miss_list_node;
130
131 /* each rule member that uses this ste attached here */
132 struct list_head rule_list;
133
134 /* this ste is member of htbl */
135 struct mlx5dr_ste_htbl *htbl;
136
137 struct mlx5dr_ste_htbl *next_htbl;
138
139 /* this ste is part of a rule, located in ste's chain */
140 u8 ste_chain_location;
141 };
142
143 struct mlx5dr_ste_htbl_ctrl {
144 /* total number of valid entries belonging to this hash table. This
145 * includes the non collision and collision entries
146 */
147 unsigned int num_of_valid_entries;
148
149 /* total number of collisions entries attached to this table */
150 unsigned int num_of_collisions;
151 unsigned int increase_threshold;
152 u8 may_grow:1;
153 };
154
155 struct mlx5dr_ste_htbl {
156 u8 lu_type;
157 u16 byte_mask;
158 u32 refcount;
159 struct mlx5dr_icm_chunk *chunk;
160 struct mlx5dr_ste *ste_arr;
161 u8 *hw_ste_arr;
162
163 struct list_head *miss_list;
164
165 enum mlx5dr_icm_chunk_size chunk_size;
166 struct mlx5dr_ste *pointing_ste;
167
168 struct mlx5dr_ste_htbl_ctrl ctrl;
169 };
170
171 struct mlx5dr_ste_send_info {
172 struct mlx5dr_ste *ste;
173 struct list_head send_list;
174 u16 size;
175 u16 offset;
176 u8 data_cont[DR_STE_SIZE];
177 u8 *data;
178 };
179
180 void mlx5dr_send_fill_and_append_ste_send_info(struct mlx5dr_ste *ste, u16 size,
181 u16 offset, u8 *data,
182 struct mlx5dr_ste_send_info *ste_info,
183 struct list_head *send_list,
184 bool copy_data);
185
186 struct mlx5dr_ste_build {
187 u8 inner:1;
188 u8 rx:1;
189 u8 vhca_id_valid:1;
190 struct mlx5dr_domain *dmn;
191 struct mlx5dr_cmd_caps *caps;
192 u8 lu_type;
193 u16 byte_mask;
194 u8 bit_mask[DR_STE_SIZE_MASK];
195 int (*ste_build_tag_func)(struct mlx5dr_match_param *spec,
196 struct mlx5dr_ste_build *sb,
197 u8 *tag);
198 };
199
200 struct mlx5dr_ste_htbl *
201 mlx5dr_ste_htbl_alloc(struct mlx5dr_icm_pool *pool,
202 enum mlx5dr_icm_chunk_size chunk_size,
203 u8 lu_type, u16 byte_mask);
204
205 int mlx5dr_ste_htbl_free(struct mlx5dr_ste_htbl *htbl);
206
mlx5dr_htbl_put(struct mlx5dr_ste_htbl * htbl)207 static inline void mlx5dr_htbl_put(struct mlx5dr_ste_htbl *htbl)
208 {
209 htbl->refcount--;
210 if (!htbl->refcount)
211 mlx5dr_ste_htbl_free(htbl);
212 }
213
mlx5dr_htbl_get(struct mlx5dr_ste_htbl * htbl)214 static inline void mlx5dr_htbl_get(struct mlx5dr_ste_htbl *htbl)
215 {
216 htbl->refcount++;
217 }
218
219 /* STE utils */
220 u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl);
221 void mlx5dr_ste_init(u8 *hw_ste_p, u8 lu_type, u8 entry_type, u16 gvmi);
222 void mlx5dr_ste_always_hit_htbl(struct mlx5dr_ste *ste,
223 struct mlx5dr_ste_htbl *next_htbl);
224 void mlx5dr_ste_set_miss_addr(u8 *hw_ste, u64 miss_addr);
225 u64 mlx5dr_ste_get_miss_addr(u8 *hw_ste);
226 void mlx5dr_ste_set_hit_gvmi(u8 *hw_ste_p, u16 gvmi);
227 void mlx5dr_ste_set_hit_addr(u8 *hw_ste, u64 icm_addr, u32 ht_size);
228 void mlx5dr_ste_always_miss_addr(struct mlx5dr_ste *ste, u64 miss_addr);
229 void mlx5dr_ste_set_bit_mask(u8 *hw_ste_p, u8 *bit_mask);
230 bool mlx5dr_ste_is_last_in_rule(struct mlx5dr_matcher_rx_tx *nic_matcher,
231 u8 ste_location);
232 void mlx5dr_ste_rx_set_flow_tag(u8 *hw_ste_p, u32 flow_tag);
233 void mlx5dr_ste_set_counter_id(u8 *hw_ste_p, u32 ctr_id);
234 void mlx5dr_ste_set_tx_encap(void *hw_ste_p, u32 reformat_id,
235 int size, bool encap_l3);
236 void mlx5dr_ste_set_rx_decap(u8 *hw_ste_p);
237 void mlx5dr_ste_set_rx_decap_l3(u8 *hw_ste_p, bool vlan);
238 void mlx5dr_ste_set_rx_pop_vlan(u8 *hw_ste_p);
239 void mlx5dr_ste_set_tx_push_vlan(u8 *hw_ste_p, u32 vlan_tpid_pcp_dei_vid,
240 bool go_back);
241 void mlx5dr_ste_set_entry_type(u8 *hw_ste_p, u8 entry_type);
242 u8 mlx5dr_ste_get_entry_type(u8 *hw_ste_p);
243 void mlx5dr_ste_set_rewrite_actions(u8 *hw_ste_p, u16 num_of_actions,
244 u32 re_write_index);
245 void mlx5dr_ste_set_go_back_bit(u8 *hw_ste_p);
246 u64 mlx5dr_ste_get_icm_addr(struct mlx5dr_ste *ste);
247 u64 mlx5dr_ste_get_mr_addr(struct mlx5dr_ste *ste);
248 struct list_head *mlx5dr_ste_get_miss_list(struct mlx5dr_ste *ste);
249
250 void mlx5dr_ste_free(struct mlx5dr_ste *ste,
251 struct mlx5dr_matcher *matcher,
252 struct mlx5dr_matcher_rx_tx *nic_matcher);
mlx5dr_ste_put(struct mlx5dr_ste * ste,struct mlx5dr_matcher * matcher,struct mlx5dr_matcher_rx_tx * nic_matcher)253 static inline void mlx5dr_ste_put(struct mlx5dr_ste *ste,
254 struct mlx5dr_matcher *matcher,
255 struct mlx5dr_matcher_rx_tx *nic_matcher)
256 {
257 ste->refcount--;
258 if (!ste->refcount)
259 mlx5dr_ste_free(ste, matcher, nic_matcher);
260 }
261
262 /* initial as 0, increased only when ste appears in a new rule */
mlx5dr_ste_get(struct mlx5dr_ste * ste)263 static inline void mlx5dr_ste_get(struct mlx5dr_ste *ste)
264 {
265 ste->refcount++;
266 }
267
mlx5dr_ste_is_not_used(struct mlx5dr_ste * ste)268 static inline bool mlx5dr_ste_is_not_used(struct mlx5dr_ste *ste)
269 {
270 return !ste->refcount;
271 }
272
273 void mlx5dr_ste_set_hit_addr_by_next_htbl(u8 *hw_ste,
274 struct mlx5dr_ste_htbl *next_htbl);
275 bool mlx5dr_ste_equal_tag(void *src, void *dst);
276 int mlx5dr_ste_create_next_htbl(struct mlx5dr_matcher *matcher,
277 struct mlx5dr_matcher_rx_tx *nic_matcher,
278 struct mlx5dr_ste *ste,
279 u8 *cur_hw_ste,
280 enum mlx5dr_icm_chunk_size log_table_size);
281
282 /* STE build functions */
283 int mlx5dr_ste_build_pre_check(struct mlx5dr_domain *dmn,
284 u8 match_criteria,
285 struct mlx5dr_match_param *mask,
286 struct mlx5dr_match_param *value);
287 int mlx5dr_ste_build_ste_arr(struct mlx5dr_matcher *matcher,
288 struct mlx5dr_matcher_rx_tx *nic_matcher,
289 struct mlx5dr_match_param *value,
290 u8 *ste_arr);
291 void mlx5dr_ste_build_eth_l2_src_des(struct mlx5dr_ste_build *builder,
292 struct mlx5dr_match_param *mask,
293 bool inner, bool rx);
294 void mlx5dr_ste_build_eth_l3_ipv4_5_tuple(struct mlx5dr_ste_build *sb,
295 struct mlx5dr_match_param *mask,
296 bool inner, bool rx);
297 void mlx5dr_ste_build_eth_l3_ipv4_misc(struct mlx5dr_ste_build *sb,
298 struct mlx5dr_match_param *mask,
299 bool inner, bool rx);
300 void mlx5dr_ste_build_eth_l3_ipv6_dst(struct mlx5dr_ste_build *sb,
301 struct mlx5dr_match_param *mask,
302 bool inner, bool rx);
303 void mlx5dr_ste_build_eth_l3_ipv6_src(struct mlx5dr_ste_build *sb,
304 struct mlx5dr_match_param *mask,
305 bool inner, bool rx);
306 void mlx5dr_ste_build_eth_l2_src(struct mlx5dr_ste_build *sb,
307 struct mlx5dr_match_param *mask,
308 bool inner, bool rx);
309 void mlx5dr_ste_build_eth_l2_dst(struct mlx5dr_ste_build *sb,
310 struct mlx5dr_match_param *mask,
311 bool inner, bool rx);
312 void mlx5dr_ste_build_eth_l2_tnl(struct mlx5dr_ste_build *sb,
313 struct mlx5dr_match_param *mask,
314 bool inner, bool rx);
315 void mlx5dr_ste_build_ipv6_l3_l4(struct mlx5dr_ste_build *sb,
316 struct mlx5dr_match_param *mask,
317 bool inner, bool rx);
318 void mlx5dr_ste_build_eth_l4_misc(struct mlx5dr_ste_build *sb,
319 struct mlx5dr_match_param *mask,
320 bool inner, bool rx);
321 void mlx5dr_ste_build_gre(struct mlx5dr_ste_build *sb,
322 struct mlx5dr_match_param *mask,
323 bool inner, bool rx);
324 void mlx5dr_ste_build_mpls(struct mlx5dr_ste_build *sb,
325 struct mlx5dr_match_param *mask,
326 bool inner, bool rx);
327 void mlx5dr_ste_build_flex_parser_0(struct mlx5dr_ste_build *sb,
328 struct mlx5dr_match_param *mask,
329 bool inner, bool rx);
330 int mlx5dr_ste_build_flex_parser_1(struct mlx5dr_ste_build *sb,
331 struct mlx5dr_match_param *mask,
332 struct mlx5dr_cmd_caps *caps,
333 bool inner, bool rx);
334 void mlx5dr_ste_build_flex_parser_tnl_vxlan_gpe(struct mlx5dr_ste_build *sb,
335 struct mlx5dr_match_param *mask,
336 bool inner, bool rx);
337 void mlx5dr_ste_build_flex_parser_tnl_geneve(struct mlx5dr_ste_build *sb,
338 struct mlx5dr_match_param *mask,
339 bool inner, bool rx);
340 void mlx5dr_ste_build_general_purpose(struct mlx5dr_ste_build *sb,
341 struct mlx5dr_match_param *mask,
342 bool inner, bool rx);
343 void mlx5dr_ste_build_register_0(struct mlx5dr_ste_build *sb,
344 struct mlx5dr_match_param *mask,
345 bool inner, bool rx);
346 void mlx5dr_ste_build_register_1(struct mlx5dr_ste_build *sb,
347 struct mlx5dr_match_param *mask,
348 bool inner, bool rx);
349 void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_build *sb,
350 struct mlx5dr_match_param *mask,
351 struct mlx5dr_domain *dmn,
352 bool inner, bool rx);
353 void mlx5dr_ste_build_empty_always_hit(struct mlx5dr_ste_build *sb, bool rx);
354
355 /* Actions utils */
356 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher,
357 struct mlx5dr_matcher_rx_tx *nic_matcher,
358 struct mlx5dr_action *actions[],
359 u32 num_actions,
360 u8 *ste_arr,
361 u32 *new_hw_ste_arr_sz);
362
363 struct mlx5dr_match_spec {
364 u32 smac_47_16; /* Source MAC address of incoming packet */
365 /* Incoming packet Ethertype - this is the Ethertype
366 * following the last VLAN tag of the packet
367 */
368 u32 ethertype:16;
369 u32 smac_15_0:16; /* Source MAC address of incoming packet */
370 u32 dmac_47_16; /* Destination MAC address of incoming packet */
371 /* VLAN ID of first VLAN tag in the incoming packet.
372 * Valid only when cvlan_tag==1 or svlan_tag==1
373 */
374 u32 first_vid:12;
375 /* CFI bit of first VLAN tag in the incoming packet.
376 * Valid only when cvlan_tag==1 or svlan_tag==1
377 */
378 u32 first_cfi:1;
379 /* Priority of first VLAN tag in the incoming packet.
380 * Valid only when cvlan_tag==1 or svlan_tag==1
381 */
382 u32 first_prio:3;
383 u32 dmac_15_0:16; /* Destination MAC address of incoming packet */
384 /* TCP flags. ;Bit 0: FIN;Bit 1: SYN;Bit 2: RST;Bit 3: PSH;Bit 4: ACK;
385 * Bit 5: URG;Bit 6: ECE;Bit 7: CWR;Bit 8: NS
386 */
387 u32 tcp_flags:9;
388 u32 ip_version:4; /* IP version */
389 u32 frag:1; /* Packet is an IP fragment */
390 /* The first vlan in the packet is s-vlan (0x8a88).
391 * cvlan_tag and svlan_tag cannot be set together
392 */
393 u32 svlan_tag:1;
394 /* The first vlan in the packet is c-vlan (0x8100).
395 * cvlan_tag and svlan_tag cannot be set together
396 */
397 u32 cvlan_tag:1;
398 /* Explicit Congestion Notification derived from
399 * Traffic Class/TOS field of IPv6/v4
400 */
401 u32 ip_ecn:2;
402 /* Differentiated Services Code Point derived from
403 * Traffic Class/TOS field of IPv6/v4
404 */
405 u32 ip_dscp:6;
406 u32 ip_protocol:8; /* IP protocol */
407 /* TCP destination port.
408 * tcp and udp sport/dport are mutually exclusive
409 */
410 u32 tcp_dport:16;
411 /* TCP source port.;tcp and udp sport/dport are mutually exclusive */
412 u32 tcp_sport:16;
413 u32 ttl_hoplimit:8;
414 u32 reserved:24;
415 /* UDP destination port.;tcp and udp sport/dport are mutually exclusive */
416 u32 udp_dport:16;
417 /* UDP source port.;tcp and udp sport/dport are mutually exclusive */
418 u32 udp_sport:16;
419 /* IPv6 source address of incoming packets
420 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
421 * This field should be qualified by an appropriate ethertype
422 */
423 u32 src_ip_127_96;
424 /* IPv6 source address of incoming packets
425 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
426 * This field should be qualified by an appropriate ethertype
427 */
428 u32 src_ip_95_64;
429 /* IPv6 source address of incoming packets
430 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
431 * This field should be qualified by an appropriate ethertype
432 */
433 u32 src_ip_63_32;
434 /* IPv6 source address of incoming packets
435 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
436 * This field should be qualified by an appropriate ethertype
437 */
438 u32 src_ip_31_0;
439 /* IPv6 destination address of incoming packets
440 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
441 * This field should be qualified by an appropriate ethertype
442 */
443 u32 dst_ip_127_96;
444 /* IPv6 destination address of incoming packets
445 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
446 * This field should be qualified by an appropriate ethertype
447 */
448 u32 dst_ip_95_64;
449 /* IPv6 destination address of incoming packets
450 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
451 * This field should be qualified by an appropriate ethertype
452 */
453 u32 dst_ip_63_32;
454 /* IPv6 destination address of incoming packets
455 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
456 * This field should be qualified by an appropriate ethertype
457 */
458 u32 dst_ip_31_0;
459 };
460
461 struct mlx5dr_match_misc {
462 u32 source_sqn:24; /* Source SQN */
463 u32 source_vhca_port:4;
464 /* used with GRE, sequence number exist when gre_s_present == 1 */
465 u32 gre_s_present:1;
466 /* used with GRE, key exist when gre_k_present == 1 */
467 u32 gre_k_present:1;
468 u32 reserved_auto1:1;
469 /* used with GRE, checksum exist when gre_c_present == 1 */
470 u32 gre_c_present:1;
471 /* Source port.;0xffff determines wire port */
472 u32 source_port:16;
473 u32 source_eswitch_owner_vhca_id:16;
474 /* VLAN ID of first VLAN tag the inner header of the incoming packet.
475 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1
476 */
477 u32 inner_second_vid:12;
478 /* CFI bit of first VLAN tag in the inner header of the incoming packet.
479 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1
480 */
481 u32 inner_second_cfi:1;
482 /* Priority of second VLAN tag in the inner header of the incoming packet.
483 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1
484 */
485 u32 inner_second_prio:3;
486 /* VLAN ID of first VLAN tag the outer header of the incoming packet.
487 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1
488 */
489 u32 outer_second_vid:12;
490 /* CFI bit of first VLAN tag in the outer header of the incoming packet.
491 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1
492 */
493 u32 outer_second_cfi:1;
494 /* Priority of second VLAN tag in the outer header of the incoming packet.
495 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1
496 */
497 u32 outer_second_prio:3;
498 u32 gre_protocol:16; /* GRE Protocol (outer) */
499 u32 reserved_auto3:12;
500 /* The second vlan in the inner header of the packet is s-vlan (0x8a88).
501 * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together
502 */
503 u32 inner_second_svlan_tag:1;
504 /* The second vlan in the outer header of the packet is s-vlan (0x8a88).
505 * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together
506 */
507 u32 outer_second_svlan_tag:1;
508 /* The second vlan in the inner header of the packet is c-vlan (0x8100).
509 * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together
510 */
511 u32 inner_second_cvlan_tag:1;
512 /* The second vlan in the outer header of the packet is c-vlan (0x8100).
513 * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together
514 */
515 u32 outer_second_cvlan_tag:1;
516 u32 gre_key_l:8; /* GRE Key [7:0] (outer) */
517 u32 gre_key_h:24; /* GRE Key[31:8] (outer) */
518 u32 reserved_auto4:8;
519 u32 vxlan_vni:24; /* VXLAN VNI (outer) */
520 u32 geneve_oam:1; /* GENEVE OAM field (outer) */
521 u32 reserved_auto5:7;
522 u32 geneve_vni:24; /* GENEVE VNI field (outer) */
523 u32 outer_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (outer) */
524 u32 reserved_auto6:12;
525 u32 inner_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (inner) */
526 u32 reserved_auto7:12;
527 u32 geneve_protocol_type:16; /* GENEVE protocol type (outer) */
528 u32 geneve_opt_len:6; /* GENEVE OptLen (outer) */
529 u32 reserved_auto8:10;
530 u32 bth_dst_qp:24; /* Destination QP in BTH header */
531 u32 reserved_auto9:8;
532 u8 reserved_auto10[20];
533 };
534
535 struct mlx5dr_match_misc2 {
536 u32 outer_first_mpls_ttl:8; /* First MPLS TTL (outer) */
537 u32 outer_first_mpls_s_bos:1; /* First MPLS S_BOS (outer) */
538 u32 outer_first_mpls_exp:3; /* First MPLS EXP (outer) */
539 u32 outer_first_mpls_label:20; /* First MPLS LABEL (outer) */
540 u32 inner_first_mpls_ttl:8; /* First MPLS TTL (inner) */
541 u32 inner_first_mpls_s_bos:1; /* First MPLS S_BOS (inner) */
542 u32 inner_first_mpls_exp:3; /* First MPLS EXP (inner) */
543 u32 inner_first_mpls_label:20; /* First MPLS LABEL (inner) */
544 u32 outer_first_mpls_over_gre_ttl:8; /* last MPLS TTL (outer) */
545 u32 outer_first_mpls_over_gre_s_bos:1; /* last MPLS S_BOS (outer) */
546 u32 outer_first_mpls_over_gre_exp:3; /* last MPLS EXP (outer) */
547 u32 outer_first_mpls_over_gre_label:20; /* last MPLS LABEL (outer) */
548 u32 outer_first_mpls_over_udp_ttl:8; /* last MPLS TTL (outer) */
549 u32 outer_first_mpls_over_udp_s_bos:1; /* last MPLS S_BOS (outer) */
550 u32 outer_first_mpls_over_udp_exp:3; /* last MPLS EXP (outer) */
551 u32 outer_first_mpls_over_udp_label:20; /* last MPLS LABEL (outer) */
552 u32 metadata_reg_c_7; /* metadata_reg_c_7 */
553 u32 metadata_reg_c_6; /* metadata_reg_c_6 */
554 u32 metadata_reg_c_5; /* metadata_reg_c_5 */
555 u32 metadata_reg_c_4; /* metadata_reg_c_4 */
556 u32 metadata_reg_c_3; /* metadata_reg_c_3 */
557 u32 metadata_reg_c_2; /* metadata_reg_c_2 */
558 u32 metadata_reg_c_1; /* metadata_reg_c_1 */
559 u32 metadata_reg_c_0; /* metadata_reg_c_0 */
560 u32 metadata_reg_a; /* metadata_reg_a */
561 u8 reserved_auto2[12];
562 };
563
564 struct mlx5dr_match_misc3 {
565 u32 inner_tcp_seq_num;
566 u32 outer_tcp_seq_num;
567 u32 inner_tcp_ack_num;
568 u32 outer_tcp_ack_num;
569 u32 outer_vxlan_gpe_vni:24;
570 u32 reserved_auto1:8;
571 u32 reserved_auto2:16;
572 u32 outer_vxlan_gpe_flags:8;
573 u32 outer_vxlan_gpe_next_protocol:8;
574 u32 icmpv4_header_data;
575 u32 icmpv6_header_data;
576 u32 icmpv6_code:8;
577 u32 icmpv6_type:8;
578 u32 icmpv4_code:8;
579 u32 icmpv4_type:8;
580 u8 reserved_auto3[0x1c];
581 };
582
583 struct mlx5dr_match_param {
584 struct mlx5dr_match_spec outer;
585 struct mlx5dr_match_misc misc;
586 struct mlx5dr_match_spec inner;
587 struct mlx5dr_match_misc2 misc2;
588 struct mlx5dr_match_misc3 misc3;
589 };
590
591 #define DR_MASK_IS_FLEX_PARSER_ICMPV4_SET(_misc3) ((_misc3)->icmpv4_type || \
592 (_misc3)->icmpv4_code || \
593 (_misc3)->icmpv4_header_data)
594
595 struct mlx5dr_esw_caps {
596 u64 drop_icm_address_rx;
597 u64 drop_icm_address_tx;
598 u64 uplink_icm_address_rx;
599 u64 uplink_icm_address_tx;
600 u8 sw_owner:1;
601 u8 sw_owner_v2:1;
602 };
603
604 struct mlx5dr_cmd_vport_cap {
605 u16 vport_gvmi;
606 u16 vhca_gvmi;
607 u64 icm_address_rx;
608 u64 icm_address_tx;
609 u32 num;
610 };
611
612 struct mlx5dr_cmd_caps {
613 u16 gvmi;
614 u64 nic_rx_drop_address;
615 u64 nic_tx_drop_address;
616 u64 nic_tx_allow_address;
617 u64 esw_rx_drop_address;
618 u64 esw_tx_drop_address;
619 u32 log_icm_size;
620 u64 hdr_modify_icm_addr;
621 u32 flex_protocols;
622 u8 flex_parser_id_icmp_dw0;
623 u8 flex_parser_id_icmp_dw1;
624 u8 flex_parser_id_icmpv6_dw0;
625 u8 flex_parser_id_icmpv6_dw1;
626 u8 max_ft_level;
627 u16 roce_min_src_udp;
628 u8 num_esw_ports;
629 u8 sw_format_ver;
630 bool eswitch_manager;
631 bool rx_sw_owner;
632 bool tx_sw_owner;
633 bool fdb_sw_owner;
634 u8 rx_sw_owner_v2:1;
635 u8 tx_sw_owner_v2:1;
636 u8 fdb_sw_owner_v2:1;
637 u32 num_vports;
638 struct mlx5dr_esw_caps esw_caps;
639 struct mlx5dr_cmd_vport_cap *vports_caps;
640 bool prio_tag_required;
641 };
642
643 struct mlx5dr_domain_rx_tx {
644 u64 drop_icm_addr;
645 u64 default_icm_addr;
646 enum mlx5dr_ste_entry_type ste_type;
647 struct mutex mutex; /* protect rx/tx domain */
648 };
649
650 struct mlx5dr_domain_info {
651 bool supp_sw_steering;
652 u32 max_inline_size;
653 u32 max_send_wr;
654 u32 max_log_sw_icm_sz;
655 u32 max_log_action_icm_sz;
656 struct mlx5dr_domain_rx_tx rx;
657 struct mlx5dr_domain_rx_tx tx;
658 struct mlx5dr_cmd_caps caps;
659 };
660
661 struct mlx5dr_domain_cache {
662 struct mlx5dr_fw_recalc_cs_ft **recalc_cs_ft;
663 };
664
665 struct mlx5dr_domain {
666 struct mlx5dr_domain *peer_dmn;
667 struct mlx5_core_dev *mdev;
668 u32 pdn;
669 struct mlx5_uars_page *uar;
670 enum mlx5dr_domain_type type;
671 refcount_t refcount;
672 struct mlx5dr_icm_pool *ste_icm_pool;
673 struct mlx5dr_icm_pool *action_icm_pool;
674 struct mlx5dr_send_ring *send_ring;
675 struct mlx5dr_domain_info info;
676 struct mlx5dr_domain_cache cache;
677 };
678
679 struct mlx5dr_table_rx_tx {
680 struct mlx5dr_ste_htbl *s_anchor;
681 struct mlx5dr_domain_rx_tx *nic_dmn;
682 u64 default_icm_addr;
683 };
684
685 struct mlx5dr_table {
686 struct mlx5dr_domain *dmn;
687 struct mlx5dr_table_rx_tx rx;
688 struct mlx5dr_table_rx_tx tx;
689 u32 level;
690 u32 table_type;
691 u32 table_id;
692 u32 flags;
693 struct list_head matcher_list;
694 struct mlx5dr_action *miss_action;
695 refcount_t refcount;
696 };
697
698 struct mlx5dr_matcher_rx_tx {
699 struct mlx5dr_ste_htbl *s_htbl;
700 struct mlx5dr_ste_htbl *e_anchor;
701 struct mlx5dr_ste_build *ste_builder;
702 struct mlx5dr_ste_build ste_builder_arr[DR_RULE_IPV_MAX]
703 [DR_RULE_IPV_MAX]
704 [DR_RULE_MAX_STES];
705 u8 num_of_builders;
706 u8 num_of_builders_arr[DR_RULE_IPV_MAX][DR_RULE_IPV_MAX];
707 u64 default_icm_addr;
708 struct mlx5dr_table_rx_tx *nic_tbl;
709 };
710
711 struct mlx5dr_matcher {
712 struct mlx5dr_table *tbl;
713 struct mlx5dr_matcher_rx_tx rx;
714 struct mlx5dr_matcher_rx_tx tx;
715 struct list_head matcher_list;
716 u32 prio;
717 struct mlx5dr_match_param mask;
718 u8 match_criteria;
719 refcount_t refcount;
720 struct mlx5dv_flow_matcher *dv_matcher;
721 };
722
723 struct mlx5dr_rule_member {
724 struct mlx5dr_ste *ste;
725 /* attached to mlx5dr_rule via this */
726 struct list_head list;
727 /* attached to mlx5dr_ste via this */
728 struct list_head use_ste_list;
729 };
730
731 struct mlx5dr_action {
732 enum mlx5dr_action_type action_type;
733 refcount_t refcount;
734 union {
735 struct {
736 struct mlx5dr_domain *dmn;
737 struct mlx5dr_icm_chunk *chunk;
738 u8 *data;
739 u32 data_size;
740 u16 num_of_actions;
741 u32 index;
742 u8 allow_rx:1;
743 u8 allow_tx:1;
744 u8 modify_ttl:1;
745 } rewrite;
746 struct {
747 struct mlx5dr_domain *dmn;
748 u32 reformat_id;
749 u32 reformat_size;
750 } reformat;
751 struct {
752 u8 is_fw_tbl:1;
753 union {
754 struct mlx5dr_table *tbl;
755 struct {
756 struct mlx5dr_domain *dmn;
757 u32 id;
758 u32 group_id;
759 enum fs_flow_table_type type;
760 u64 rx_icm_addr;
761 u64 tx_icm_addr;
762 struct mlx5dr_action **ref_actions;
763 u32 num_of_ref_actions;
764 } fw_tbl;
765 };
766 } dest_tbl;
767 struct {
768 u32 ctr_id;
769 u32 offeset;
770 } ctr;
771 struct {
772 struct mlx5dr_domain *dmn;
773 struct mlx5dr_cmd_vport_cap *caps;
774 } vport;
775 struct {
776 u32 vlan_hdr; /* tpid_pcp_dei_vid */
777 } push_vlan;
778 u32 flow_tag;
779 };
780 };
781
782 enum mlx5dr_connect_type {
783 CONNECT_HIT = 1,
784 CONNECT_MISS = 2,
785 };
786
787 struct mlx5dr_htbl_connect_info {
788 enum mlx5dr_connect_type type;
789 union {
790 struct mlx5dr_ste_htbl *hit_next_htbl;
791 u64 miss_icm_addr;
792 };
793 };
794
795 struct mlx5dr_rule_rx_tx {
796 struct list_head rule_members_list;
797 struct mlx5dr_matcher_rx_tx *nic_matcher;
798 };
799
800 struct mlx5dr_rule {
801 struct mlx5dr_matcher *matcher;
802 struct mlx5dr_rule_rx_tx rx;
803 struct mlx5dr_rule_rx_tx tx;
804 struct list_head rule_actions_list;
805 u32 flow_source;
806 };
807
808 void mlx5dr_rule_update_rule_member(struct mlx5dr_ste *new_ste,
809 struct mlx5dr_ste *ste);
810
811 struct mlx5dr_icm_chunk {
812 struct mlx5dr_icm_bucket *bucket;
813 struct list_head chunk_list;
814 u32 rkey;
815 u32 num_of_entries;
816 u32 byte_size;
817 u64 icm_addr;
818 u64 mr_addr;
819
820 /* Memory optimisation */
821 struct mlx5dr_ste *ste_arr;
822 u8 *hw_ste_arr;
823 struct list_head *miss_list;
824 };
825
mlx5dr_domain_nic_lock(struct mlx5dr_domain_rx_tx * nic_dmn)826 static inline void mlx5dr_domain_nic_lock(struct mlx5dr_domain_rx_tx *nic_dmn)
827 {
828 mutex_lock(&nic_dmn->mutex);
829 }
830
mlx5dr_domain_nic_unlock(struct mlx5dr_domain_rx_tx * nic_dmn)831 static inline void mlx5dr_domain_nic_unlock(struct mlx5dr_domain_rx_tx *nic_dmn)
832 {
833 mutex_unlock(&nic_dmn->mutex);
834 }
835
mlx5dr_domain_lock(struct mlx5dr_domain * dmn)836 static inline void mlx5dr_domain_lock(struct mlx5dr_domain *dmn)
837 {
838 mlx5dr_domain_nic_lock(&dmn->info.rx);
839 mlx5dr_domain_nic_lock(&dmn->info.tx);
840 }
841
mlx5dr_domain_unlock(struct mlx5dr_domain * dmn)842 static inline void mlx5dr_domain_unlock(struct mlx5dr_domain *dmn)
843 {
844 mlx5dr_domain_nic_unlock(&dmn->info.tx);
845 mlx5dr_domain_nic_unlock(&dmn->info.rx);
846 }
847
848 static inline int
mlx5dr_matcher_supp_flex_parser_icmp_v4(struct mlx5dr_cmd_caps * caps)849 mlx5dr_matcher_supp_flex_parser_icmp_v4(struct mlx5dr_cmd_caps *caps)
850 {
851 return caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V4_ENABLED;
852 }
853
854 static inline int
mlx5dr_matcher_supp_flex_parser_icmp_v6(struct mlx5dr_cmd_caps * caps)855 mlx5dr_matcher_supp_flex_parser_icmp_v6(struct mlx5dr_cmd_caps *caps)
856 {
857 return caps->flex_protocols & MLX5_FLEX_PARSER_ICMP_V6_ENABLED;
858 }
859
860 int mlx5dr_matcher_select_builders(struct mlx5dr_matcher *matcher,
861 struct mlx5dr_matcher_rx_tx *nic_matcher,
862 enum mlx5dr_ipv outer_ipv,
863 enum mlx5dr_ipv inner_ipv);
864
865 static inline u32
mlx5dr_icm_pool_chunk_size_to_entries(enum mlx5dr_icm_chunk_size chunk_size)866 mlx5dr_icm_pool_chunk_size_to_entries(enum mlx5dr_icm_chunk_size chunk_size)
867 {
868 return 1 << chunk_size;
869 }
870
871 static inline int
mlx5dr_icm_pool_chunk_size_to_byte(enum mlx5dr_icm_chunk_size chunk_size,enum mlx5dr_icm_type icm_type)872 mlx5dr_icm_pool_chunk_size_to_byte(enum mlx5dr_icm_chunk_size chunk_size,
873 enum mlx5dr_icm_type icm_type)
874 {
875 int num_of_entries;
876 int entry_size;
877
878 if (icm_type == DR_ICM_TYPE_STE)
879 entry_size = DR_STE_SIZE;
880 else
881 entry_size = DR_MODIFY_ACTION_SIZE;
882
883 num_of_entries = mlx5dr_icm_pool_chunk_size_to_entries(chunk_size);
884
885 return entry_size * num_of_entries;
886 }
887
888 static inline struct mlx5dr_cmd_vport_cap *
mlx5dr_get_vport_cap(struct mlx5dr_cmd_caps * caps,u32 vport)889 mlx5dr_get_vport_cap(struct mlx5dr_cmd_caps *caps, u32 vport)
890 {
891 if (!caps->vports_caps ||
892 (vport >= caps->num_vports && vport != WIRE_PORT))
893 return NULL;
894
895 if (vport == WIRE_PORT)
896 vport = caps->num_vports;
897
898 return &caps->vports_caps[vport];
899 }
900
901 struct mlx5dr_cmd_query_flow_table_details {
902 u8 status;
903 u8 level;
904 u64 sw_owner_icm_root_1;
905 u64 sw_owner_icm_root_0;
906 };
907
908 struct mlx5dr_cmd_create_flow_table_attr {
909 u32 table_type;
910 u64 icm_addr_rx;
911 u64 icm_addr_tx;
912 u8 level;
913 bool sw_owner;
914 bool term_tbl;
915 bool decap_en;
916 bool reformat_en;
917 };
918
919 /* internal API functions */
920 int mlx5dr_cmd_query_device(struct mlx5_core_dev *mdev,
921 struct mlx5dr_cmd_caps *caps);
922 int mlx5dr_cmd_query_esw_vport_context(struct mlx5_core_dev *mdev,
923 bool other_vport, u16 vport_number,
924 u64 *icm_address_rx,
925 u64 *icm_address_tx);
926 int mlx5dr_cmd_query_gvmi(struct mlx5_core_dev *mdev,
927 bool other_vport, u16 vport_number, u16 *gvmi);
928 int mlx5dr_cmd_query_esw_caps(struct mlx5_core_dev *mdev,
929 struct mlx5dr_esw_caps *caps);
930 int mlx5dr_cmd_sync_steering(struct mlx5_core_dev *mdev);
931 int mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev *mdev,
932 u32 table_type,
933 u32 table_id,
934 u32 group_id,
935 u32 modify_header_id,
936 u32 vport_id);
937 int mlx5dr_cmd_del_flow_table_entry(struct mlx5_core_dev *mdev,
938 u32 table_type,
939 u32 table_id);
940 int mlx5dr_cmd_alloc_modify_header(struct mlx5_core_dev *mdev,
941 u32 table_type,
942 u8 num_of_actions,
943 u64 *actions,
944 u32 *modify_header_id);
945 int mlx5dr_cmd_dealloc_modify_header(struct mlx5_core_dev *mdev,
946 u32 modify_header_id);
947 int mlx5dr_cmd_create_empty_flow_group(struct mlx5_core_dev *mdev,
948 u32 table_type,
949 u32 table_id,
950 u32 *group_id);
951 int mlx5dr_cmd_destroy_flow_group(struct mlx5_core_dev *mdev,
952 u32 table_type,
953 u32 table_id,
954 u32 group_id);
955 int mlx5dr_cmd_create_flow_table(struct mlx5_core_dev *mdev,
956 struct mlx5dr_cmd_create_flow_table_attr *attr,
957 u64 *fdb_rx_icm_addr,
958 u32 *table_id);
959 int mlx5dr_cmd_destroy_flow_table(struct mlx5_core_dev *mdev,
960 u32 table_id,
961 u32 table_type);
962 int mlx5dr_cmd_query_flow_table(struct mlx5_core_dev *dev,
963 enum fs_flow_table_type type,
964 u32 table_id,
965 struct mlx5dr_cmd_query_flow_table_details *output);
966 int mlx5dr_cmd_create_reformat_ctx(struct mlx5_core_dev *mdev,
967 enum mlx5_reformat_ctx_type rt,
968 size_t reformat_size,
969 void *reformat_data,
970 u32 *reformat_id);
971 void mlx5dr_cmd_destroy_reformat_ctx(struct mlx5_core_dev *mdev,
972 u32 reformat_id);
973
974 struct mlx5dr_cmd_gid_attr {
975 u8 gid[16];
976 u8 mac[6];
977 u32 roce_ver;
978 };
979
980 struct mlx5dr_cmd_qp_create_attr {
981 u32 page_id;
982 u32 pdn;
983 u32 cqn;
984 u32 pm_state;
985 u32 service_type;
986 u32 buff_umem_id;
987 u32 db_umem_id;
988 u32 sq_wqe_cnt;
989 u32 rq_wqe_cnt;
990 u32 rq_wqe_shift;
991 };
992
993 int mlx5dr_cmd_query_gid(struct mlx5_core_dev *mdev, u8 vhca_port_num,
994 u16 index, struct mlx5dr_cmd_gid_attr *attr);
995
996 struct mlx5dr_icm_pool *mlx5dr_icm_pool_create(struct mlx5dr_domain *dmn,
997 enum mlx5dr_icm_type icm_type);
998 void mlx5dr_icm_pool_destroy(struct mlx5dr_icm_pool *pool);
999
1000 struct mlx5dr_icm_chunk *
1001 mlx5dr_icm_alloc_chunk(struct mlx5dr_icm_pool *pool,
1002 enum mlx5dr_icm_chunk_size chunk_size);
1003 void mlx5dr_icm_free_chunk(struct mlx5dr_icm_chunk *chunk);
1004 int mlx5dr_ste_htbl_init_and_postsend(struct mlx5dr_domain *dmn,
1005 struct mlx5dr_domain_rx_tx *nic_dmn,
1006 struct mlx5dr_ste_htbl *htbl,
1007 struct mlx5dr_htbl_connect_info *connect_info,
1008 bool update_hw_ste);
1009 void mlx5dr_ste_set_formatted_ste(u16 gvmi,
1010 struct mlx5dr_domain_rx_tx *nic_dmn,
1011 struct mlx5dr_ste_htbl *htbl,
1012 u8 *formatted_ste,
1013 struct mlx5dr_htbl_connect_info *connect_info);
1014 void mlx5dr_ste_copy_param(u8 match_criteria,
1015 struct mlx5dr_match_param *set_param,
1016 struct mlx5dr_match_parameters *mask);
1017
1018 struct mlx5dr_qp {
1019 struct mlx5_core_dev *mdev;
1020 struct mlx5_wq_qp wq;
1021 struct mlx5_uars_page *uar;
1022 struct mlx5_wq_ctrl wq_ctrl;
1023 u32 qpn;
1024 struct {
1025 unsigned int pc;
1026 unsigned int cc;
1027 unsigned int size;
1028 unsigned int *wqe_head;
1029 unsigned int wqe_cnt;
1030 } sq;
1031 struct {
1032 unsigned int pc;
1033 unsigned int cc;
1034 unsigned int size;
1035 unsigned int wqe_cnt;
1036 } rq;
1037 int max_inline_data;
1038 };
1039
1040 struct mlx5dr_cq {
1041 struct mlx5_core_dev *mdev;
1042 struct mlx5_cqwq wq;
1043 struct mlx5_wq_ctrl wq_ctrl;
1044 struct mlx5_core_cq mcq;
1045 struct mlx5dr_qp *qp;
1046 };
1047
1048 struct mlx5dr_mr {
1049 struct mlx5_core_dev *mdev;
1050 struct mlx5_core_mkey mkey;
1051 dma_addr_t dma_addr;
1052 void *addr;
1053 size_t size;
1054 };
1055
1056 #define MAX_SEND_CQE 64
1057 #define MIN_READ_SYNC 64
1058
1059 struct mlx5dr_send_ring {
1060 struct mlx5dr_cq *cq;
1061 struct mlx5dr_qp *qp;
1062 struct mlx5dr_mr *mr;
1063 /* How much wqes are waiting for completion */
1064 u32 pending_wqe;
1065 /* Signal request per this trash hold value */
1066 u16 signal_th;
1067 /* Each post_send_size less than max_post_send_size */
1068 u32 max_post_send_size;
1069 /* manage the send queue */
1070 u32 tx_head;
1071 void *buf;
1072 u32 buf_size;
1073 struct ib_wc wc[MAX_SEND_CQE];
1074 u8 sync_buff[MIN_READ_SYNC];
1075 struct mlx5dr_mr *sync_mr;
1076 spinlock_t lock; /* Protect the data path of the send ring */
1077 };
1078
1079 int mlx5dr_send_ring_alloc(struct mlx5dr_domain *dmn);
1080 void mlx5dr_send_ring_free(struct mlx5dr_domain *dmn,
1081 struct mlx5dr_send_ring *send_ring);
1082 int mlx5dr_send_ring_force_drain(struct mlx5dr_domain *dmn);
1083 int mlx5dr_send_postsend_ste(struct mlx5dr_domain *dmn,
1084 struct mlx5dr_ste *ste,
1085 u8 *data,
1086 u16 size,
1087 u16 offset);
1088 int mlx5dr_send_postsend_htbl(struct mlx5dr_domain *dmn,
1089 struct mlx5dr_ste_htbl *htbl,
1090 u8 *formatted_ste, u8 *mask);
1091 int mlx5dr_send_postsend_formatted_htbl(struct mlx5dr_domain *dmn,
1092 struct mlx5dr_ste_htbl *htbl,
1093 u8 *ste_init_data,
1094 bool update_hw_ste);
1095 int mlx5dr_send_postsend_action(struct mlx5dr_domain *dmn,
1096 struct mlx5dr_action *action);
1097
1098 struct mlx5dr_cmd_ft_info {
1099 u32 id;
1100 u16 vport;
1101 enum fs_flow_table_type type;
1102 };
1103
1104 struct mlx5dr_cmd_flow_destination_hw_info {
1105 enum mlx5_flow_destination_type type;
1106 union {
1107 u32 tir_num;
1108 u32 ft_num;
1109 u32 ft_id;
1110 u32 counter_id;
1111 struct {
1112 u16 num;
1113 u16 vhca_id;
1114 u32 reformat_id;
1115 u8 flags;
1116 } vport;
1117 };
1118 };
1119
1120 struct mlx5dr_cmd_fte_info {
1121 u32 dests_size;
1122 u32 index;
1123 struct mlx5_flow_context flow_context;
1124 u32 *val;
1125 struct mlx5_flow_act action;
1126 struct mlx5dr_cmd_flow_destination_hw_info *dest_arr;
1127 };
1128
1129 int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev,
1130 int opmod, int modify_mask,
1131 struct mlx5dr_cmd_ft_info *ft,
1132 u32 group_id,
1133 struct mlx5dr_cmd_fte_info *fte);
1134
1135 struct mlx5dr_fw_recalc_cs_ft {
1136 u64 rx_icm_addr;
1137 u32 table_id;
1138 u32 group_id;
1139 u32 modify_hdr_id;
1140 };
1141
1142 struct mlx5dr_fw_recalc_cs_ft *
1143 mlx5dr_fw_create_recalc_cs_ft(struct mlx5dr_domain *dmn, u32 vport_num);
1144 void mlx5dr_fw_destroy_recalc_cs_ft(struct mlx5dr_domain *dmn,
1145 struct mlx5dr_fw_recalc_cs_ft *recalc_cs_ft);
1146 int mlx5dr_domain_cache_get_recalc_cs_ft_addr(struct mlx5dr_domain *dmn,
1147 u32 vport_num,
1148 u64 *rx_icm_addr);
1149 int mlx5dr_fw_create_md_tbl(struct mlx5dr_domain *dmn,
1150 struct mlx5dr_cmd_flow_destination_hw_info *dest,
1151 int num_dest,
1152 bool reformat_req,
1153 u32 *tbl_id,
1154 u32 *group_id);
1155 void mlx5dr_fw_destroy_md_tbl(struct mlx5dr_domain *dmn, u32 tbl_id,
1156 u32 group_id);
1157 #endif /* _DR_TYPES_H_ */
1158