1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_STREAM_H_ 27 #define DC_STREAM_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 32 /******************************************************************************* 33 * Stream Interfaces 34 ******************************************************************************/ 35 struct timing_sync_info { 36 int group_id; 37 int group_size; 38 bool master; 39 }; 40 41 struct dc_stream_status { 42 int primary_otg_inst; 43 int stream_enc_inst; 44 int plane_count; 45 int audio_inst; 46 struct timing_sync_info timing_sync_info; 47 struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; 48 }; 49 50 // TODO: References to this needs to be removed.. 51 struct freesync_context { 52 bool dummy; 53 }; 54 55 enum hubp_dmdata_mode { 56 DMDATA_SW_MODE, 57 DMDATA_HW_MODE 58 }; 59 60 struct dc_dmdata_attributes { 61 /* Specifies whether dynamic meta data will be updated by software 62 * or has to be fetched by hardware (DMA mode) 63 */ 64 enum hubp_dmdata_mode dmdata_mode; 65 /* Specifies if current dynamic meta data is to be used only for the current frame */ 66 bool dmdata_repeat; 67 /* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */ 68 uint32_t dmdata_size; 69 /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */ 70 bool dmdata_updated; 71 /* If hardware mode is used, the base address where DMDATA surface is located */ 72 PHYSICAL_ADDRESS_LOC address; 73 /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */ 74 bool dmdata_qos_mode; 75 /* If qos_mode = 1, this is the QOS value to be used: */ 76 uint32_t dmdata_qos_level; 77 /* Specifies the value in unit of REFCLK cycles to be added to the 78 * current time to produce the Amortized deadline for Dynamic Metadata chunk request 79 */ 80 uint32_t dmdata_dl_delta; 81 /* An unbounded array of uint32s, represents software dmdata to be loaded */ 82 uint32_t *dmdata_sw_data; 83 }; 84 85 struct dc_writeback_info { 86 bool wb_enabled; 87 int dwb_pipe_inst; 88 struct dc_dwb_params dwb_params; 89 struct mcif_buf_params mcif_buf_params; 90 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 91 struct mcif_warmup_params mcif_warmup_params; 92 /* the plane that is the input to TOP_MUX for MPCC that is the DWB source */ 93 struct dc_plane_state *writeback_source_plane; 94 /* source MPCC instance. for use by internally by dc */ 95 int mpcc_inst; 96 #endif 97 }; 98 99 struct dc_writeback_update { 100 unsigned int num_wb_info; 101 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 102 }; 103 104 enum vertical_interrupt_ref_point { 105 START_V_UPDATE = 0, 106 START_V_SYNC, 107 INVALID_POINT 108 109 //For now, only v_update interrupt is used. 110 //START_V_BLANK, 111 //START_V_ACTIVE 112 }; 113 114 struct periodic_interrupt_config { 115 enum vertical_interrupt_ref_point ref_point; 116 int lines_offset; 117 }; 118 119 union stream_update_flags { 120 struct { 121 uint32_t scaling:1; 122 uint32_t out_tf:1; 123 uint32_t out_csc:1; 124 uint32_t abm_level:1; 125 uint32_t dpms_off:1; 126 uint32_t gamut_remap:1; 127 uint32_t wb_update:1; 128 uint32_t dsc_changed : 1; 129 } bits; 130 131 uint32_t raw; 132 }; 133 134 struct dc_stream_state { 135 // sink is deprecated, new code should not reference 136 // this pointer 137 struct dc_sink *sink; 138 139 struct dc_link *link; 140 struct dc_panel_patch sink_patches; 141 union display_content_support content_support; 142 struct dc_crtc_timing timing; 143 struct dc_crtc_timing_adjust adjust; 144 struct dc_info_packet vrr_infopacket; 145 struct dc_info_packet vsc_infopacket; 146 struct dc_info_packet vsp_infopacket; 147 148 struct rect src; /* composition area */ 149 struct rect dst; /* stream addressable area */ 150 151 // TODO: References to this needs to be removed.. 152 struct freesync_context freesync_ctx; 153 154 struct audio_info audio_info; 155 156 struct dc_info_packet hdr_static_metadata; 157 PHYSICAL_ADDRESS_LOC dmdata_address; 158 bool use_dynamic_meta; 159 160 struct dc_transfer_func *out_transfer_func; 161 struct colorspace_transform gamut_remap_matrix; 162 struct dc_csc_transform csc_color_matrix; 163 164 enum dc_color_space output_color_space; 165 enum dc_dither_option dither_option; 166 167 enum view_3d_format view_format; 168 169 bool use_vsc_sdp_for_colorimetry; 170 bool ignore_msa_timing_param; 171 bool converter_disable_audio; 172 uint8_t qs_bit; 173 uint8_t qy_bit; 174 175 /* TODO: custom INFO packets */ 176 /* TODO: ABM info (DMCU) */ 177 /* TODO: CEA VIC */ 178 179 /* DMCU info */ 180 unsigned int abm_level; 181 182 struct periodic_interrupt_config periodic_interrupt; 183 184 /* from core_stream struct */ 185 struct dc_context *ctx; 186 187 /* used by DCP and FMT */ 188 struct bit_depth_reduction_params bit_depth_params; 189 struct clamping_and_pixel_encoding_params clamping; 190 191 int phy_pix_clk; 192 enum signal_type signal; 193 bool dpms_off; 194 195 void *dm_stream_context; 196 197 struct dc_cursor_attributes cursor_attributes; 198 struct dc_cursor_position cursor_position; 199 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode 200 201 /* from stream struct */ 202 struct kref refcount; 203 204 struct crtc_trigger_info triggered_crtc_reset; 205 206 /* writeback */ 207 unsigned int num_wb_info; 208 struct dc_writeback_info writeback_info[MAX_DWB_PIPES]; 209 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 210 const struct dc_transfer_func *func_shaper; 211 const struct dc_3dlut *lut3d_func; 212 #endif 213 /* Computed state bits */ 214 bool mode_changed : 1; 215 216 /* Output from DC when stream state is committed or altered 217 * DC may only access these values during: 218 * dc_commit_state, dc_commit_state_no_check, dc_commit_streams 219 * values may not change outside of those calls 220 */ 221 struct { 222 // For interrupt management, some hardware instance 223 // offsets need to be exposed to DM 224 uint8_t otg_offset; 225 } out; 226 227 bool apply_edp_fast_boot_optimization; 228 bool apply_seamless_boot_optimization; 229 230 uint32_t stream_id; 231 bool is_dsc_enabled; 232 union stream_update_flags update_flags; 233 }; 234 235 #define ABM_LEVEL_IMMEDIATE_DISABLE 255 236 237 struct dc_stream_update { 238 struct dc_stream_state *stream; 239 240 struct rect src; 241 struct rect dst; 242 struct dc_transfer_func *out_transfer_func; 243 struct dc_info_packet *hdr_static_metadata; 244 unsigned int *abm_level; 245 246 struct periodic_interrupt_config *periodic_interrupt; 247 248 struct dc_info_packet *vrr_infopacket; 249 struct dc_info_packet *vsc_infopacket; 250 struct dc_info_packet *vsp_infopacket; 251 252 bool *dpms_off; 253 bool integer_scaling_update; 254 255 struct colorspace_transform *gamut_remap; 256 enum dc_color_space *output_color_space; 257 enum dc_dither_option *dither_option; 258 259 struct dc_csc_transform *output_csc_transform; 260 261 struct dc_writeback_update *wb_update; 262 struct dc_dsc_config *dsc_config; 263 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 264 struct dc_transfer_func *func_shaper; 265 struct dc_3dlut *lut3d_func; 266 #endif 267 }; 268 269 bool dc_is_stream_unchanged( 270 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 271 bool dc_is_stream_scaling_unchanged( 272 struct dc_stream_state *old_stream, struct dc_stream_state *stream); 273 274 /* 275 * Set up surface attributes and associate to a stream 276 * The surfaces parameter is an absolute set of all surface active for the stream. 277 * If no surfaces are provided, the stream will be blanked; no memory read. 278 * Any flip related attribute changes must be done through this interface. 279 * 280 * After this call: 281 * Surfaces attributes are programmed and configured to be composed into stream. 282 * This does not trigger a flip. No surface address is programmed. 283 */ 284 285 void dc_commit_updates_for_stream(struct dc *dc, 286 struct dc_surface_update *srf_updates, 287 int surface_count, 288 struct dc_stream_state *stream, 289 struct dc_stream_update *stream_update, 290 struct dc_state *state); 291 /* 292 * Log the current stream state. 293 */ 294 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream); 295 296 uint8_t dc_get_current_stream_count(struct dc *dc); 297 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); 298 struct dc_stream_state *dc_stream_find_from_link(const struct dc_link *link); 299 300 /* 301 * Return the current frame counter. 302 */ 303 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); 304 305 /* 306 * Send dp sdp message. 307 */ 308 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream, 309 const uint8_t *custom_sdp_message, 310 unsigned int sdp_message_size); 311 312 /* TODO: Return parsed values rather than direct register read 313 * This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos) 314 * being refactored properly to be dce-specific 315 */ 316 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, 317 uint32_t *v_blank_start, 318 uint32_t *v_blank_end, 319 uint32_t *h_position, 320 uint32_t *v_position); 321 322 enum dc_status dc_add_stream_to_ctx( 323 struct dc *dc, 324 struct dc_state *new_ctx, 325 struct dc_stream_state *stream); 326 327 enum dc_status dc_remove_stream_from_ctx( 328 struct dc *dc, 329 struct dc_state *new_ctx, 330 struct dc_stream_state *stream); 331 332 333 bool dc_add_plane_to_context( 334 const struct dc *dc, 335 struct dc_stream_state *stream, 336 struct dc_plane_state *plane_state, 337 struct dc_state *context); 338 339 bool dc_remove_plane_from_context( 340 const struct dc *dc, 341 struct dc_stream_state *stream, 342 struct dc_plane_state *plane_state, 343 struct dc_state *context); 344 345 bool dc_rem_all_planes_for_stream( 346 const struct dc *dc, 347 struct dc_stream_state *stream, 348 struct dc_state *context); 349 350 bool dc_add_all_planes_for_stream( 351 const struct dc *dc, 352 struct dc_stream_state *stream, 353 struct dc_plane_state * const *plane_states, 354 int plane_count, 355 struct dc_state *context); 356 357 bool dc_stream_add_writeback(struct dc *dc, 358 struct dc_stream_state *stream, 359 struct dc_writeback_info *wb_info); 360 361 bool dc_stream_remove_writeback(struct dc *dc, 362 struct dc_stream_state *stream, 363 uint32_t dwb_pipe_inst); 364 365 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, 366 struct dc_state *state, 367 struct dc_stream_state *stream); 368 369 bool dc_stream_warmup_writeback(struct dc *dc, 370 int num_dwb, 371 struct dc_writeback_info *wb_info); 372 373 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream); 374 375 bool dc_stream_set_dynamic_metadata(struct dc *dc, 376 struct dc_stream_state *stream, 377 struct dc_dmdata_attributes *dmdata_attr); 378 379 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); 380 381 /* 382 * Set up streams and links associated to drive sinks 383 * The streams parameter is an absolute set of all active streams. 384 * 385 * After this call: 386 * Phy, Encoder, Timing Generator are programmed and enabled. 387 * New streams are enabled with blank stream; no memory read. 388 */ 389 /* 390 * Enable stereo when commit_streams is not required, 391 * for example, frame alternate. 392 */ 393 bool dc_enable_stereo( 394 struct dc *dc, 395 struct dc_state *context, 396 struct dc_stream_state *streams[], 397 uint8_t stream_count); 398 399 /* Triggers multi-stream synchronization. */ 400 void dc_trigger_sync(struct dc *dc, struct dc_state *context); 401 402 enum surface_update_type dc_check_update_surfaces_for_stream( 403 struct dc *dc, 404 struct dc_surface_update *updates, 405 int surface_count, 406 struct dc_stream_update *stream_update, 407 const struct dc_stream_status *stream_status); 408 409 /** 410 * Create a new default stream for the requested sink 411 */ 412 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); 413 414 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream); 415 416 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink); 417 418 void dc_stream_retain(struct dc_stream_state *dc_stream); 419 void dc_stream_release(struct dc_stream_state *dc_stream); 420 421 struct dc_stream_status *dc_stream_get_status_from_state( 422 struct dc_state *state, 423 struct dc_stream_state *stream); 424 struct dc_stream_status *dc_stream_get_status( 425 struct dc_stream_state *dc_stream); 426 427 #ifndef TRIM_FSFT 428 bool dc_optimize_timing_for_fsft( 429 struct dc_stream_state *pStream, 430 unsigned int max_input_rate_in_khz); 431 #endif 432 433 /******************************************************************************* 434 * Cursor interfaces - To manages the cursor within a stream 435 ******************************************************************************/ 436 /* TODO: Deprecated once we switch to dc_set_cursor_position */ 437 bool dc_stream_set_cursor_attributes( 438 struct dc_stream_state *stream, 439 const struct dc_cursor_attributes *attributes); 440 441 bool dc_stream_set_cursor_position( 442 struct dc_stream_state *stream, 443 const struct dc_cursor_position *position); 444 445 446 bool dc_stream_adjust_vmin_vmax(struct dc *dc, 447 struct dc_stream_state *stream, 448 struct dc_crtc_timing_adjust *adjust); 449 450 bool dc_stream_get_crtc_position(struct dc *dc, 451 struct dc_stream_state **stream, 452 int num_streams, 453 unsigned int *v_pos, 454 unsigned int *nom_v_pos); 455 456 bool dc_stream_configure_crc(struct dc *dc, 457 struct dc_stream_state *stream, 458 bool enable, 459 bool continuous); 460 461 bool dc_stream_get_crc(struct dc *dc, 462 struct dc_stream_state *stream, 463 uint32_t *r_cr, 464 uint32_t *g_y, 465 uint32_t *b_cb); 466 467 void dc_stream_set_static_screen_params(struct dc *dc, 468 struct dc_stream_state **stream, 469 int num_streams, 470 const struct dc_static_screen_params *params); 471 472 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream, 473 enum dc_dynamic_expansion option); 474 475 void dc_stream_set_dither_option(struct dc_stream_state *stream, 476 enum dc_dither_option option); 477 478 bool dc_stream_set_gamut_remap(struct dc *dc, 479 const struct dc_stream_state *stream); 480 481 bool dc_stream_program_csc_matrix(struct dc *dc, 482 struct dc_stream_state *stream); 483 484 bool dc_stream_get_crtc_position(struct dc *dc, 485 struct dc_stream_state **stream, 486 int num_streams, 487 unsigned int *v_pos, 488 unsigned int *nom_v_pos); 489 490 #endif /* DC_STREAM_H_ */ 491