1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/opp.h" 32 #include "inc/hw/link_encoder.h" 33 #include "core_status.h" 34 35 struct pipe_ctx; 36 struct dc_state; 37 struct dc_stream_status; 38 struct dc_writeback_info; 39 struct dchub_init_data; 40 struct dc_static_screen_params; 41 struct resource_pool; 42 struct dc_phy_addr_space_config; 43 struct dc_virtual_addr_space_config; 44 struct dpp; 45 struct dce_hwseq; 46 47 struct hw_sequencer_funcs { 48 /* Embedded Display Related */ 49 void (*edp_power_control)(struct dc_link *link, bool enable); 50 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 51 52 /* Pipe Programming Related */ 53 void (*init_hw)(struct dc *dc); 54 void (*power_down_on_boot)(struct dc *dc); 55 void (*enable_accelerated_mode)(struct dc *dc, 56 struct dc_state *context); 57 enum dc_status (*apply_ctx_to_hw)(struct dc *dc, 58 struct dc_state *context); 59 void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx); 60 void (*apply_ctx_for_surface)(struct dc *dc, 61 const struct dc_stream_state *stream, 62 int num_planes, struct dc_state *context); 63 void (*program_front_end_for_ctx)(struct dc *dc, 64 struct dc_state *context); 65 bool (*disconnect_pipes)(struct dc *dc, 66 struct dc_state *context); 67 void (*wait_for_pending_cleared)(struct dc *dc, 68 struct dc_state *context); 69 void (*post_unlock_program_front_end)(struct dc *dc, 70 struct dc_state *context); 71 void (*update_plane_addr)(const struct dc *dc, 72 struct pipe_ctx *pipe_ctx); 73 void (*update_dchub)(struct dce_hwseq *hws, 74 struct dchub_init_data *dh_data); 75 void (*wait_for_mpcc_disconnect)(struct dc *dc, 76 struct resource_pool *res_pool, 77 struct pipe_ctx *pipe_ctx); 78 void (*edp_backlight_control)( 79 struct dc_link *link, 80 bool enable); 81 void (*program_triplebuffer)(const struct dc *dc, 82 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 83 void (*update_pending_status)(struct pipe_ctx *pipe_ctx); 84 void (*power_down)(struct dc *dc); 85 86 /* Pipe Lock Related */ 87 void (*pipe_control_lock)(struct dc *dc, 88 struct pipe_ctx *pipe, bool lock); 89 void (*interdependent_update_lock)(struct dc *dc, 90 struct dc_state *context, bool lock); 91 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx, 92 bool flip_immediate); 93 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock); 94 95 /* Timing Related */ 96 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 97 struct crtc_position *position); 98 int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); 99 void (*calc_vupdate_position)( 100 struct dc *dc, 101 struct pipe_ctx *pipe_ctx, 102 uint32_t *start_line, 103 uint32_t *end_line); 104 void (*enable_per_frame_crtc_position_reset)(struct dc *dc, 105 int group_size, struct pipe_ctx *grouped_pipes[]); 106 void (*enable_timing_synchronization)(struct dc *dc, 107 int group_index, int group_size, 108 struct pipe_ctx *grouped_pipes[]); 109 void (*setup_periodic_interrupt)(struct dc *dc, 110 struct pipe_ctx *pipe_ctx); 111 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 112 unsigned int vmin, unsigned int vmax, 113 unsigned int vmid, unsigned int vmid_frame_number); 114 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 115 int num_pipes, 116 const struct dc_static_screen_params *events); 117 #ifndef TRIM_FSFT 118 bool (*optimize_timing_for_fsft)(struct dc *dc, 119 struct dc_crtc_timing *timing, 120 unsigned int max_input_rate_in_khz); 121 #endif 122 123 /* Stream Related */ 124 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 125 void (*disable_stream)(struct pipe_ctx *pipe_ctx); 126 void (*blank_stream)(struct pipe_ctx *pipe_ctx); 127 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 128 struct dc_link_settings *link_settings); 129 130 /* Bandwidth Related */ 131 void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context); 132 bool (*update_bandwidth)(struct dc *dc, struct dc_state *context); 133 void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context); 134 135 /* Infopacket Related */ 136 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 137 void (*send_immediate_sdp_message)( 138 struct pipe_ctx *pipe_ctx, 139 const uint8_t *custom_sdp_message, 140 unsigned int sdp_message_size); 141 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 142 void (*set_dmdata_attributes)(struct pipe_ctx *pipe); 143 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); 144 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); 145 146 /* Cursor Related */ 147 void (*set_cursor_position)(struct pipe_ctx *pipe); 148 void (*set_cursor_attribute)(struct pipe_ctx *pipe); 149 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); 150 151 /* Colour Related */ 152 void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); 153 void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, 154 enum dc_color_space colorspace, 155 uint16_t *matrix, int opp_id); 156 157 /* VM Related */ 158 int (*init_sys_ctx)(struct dce_hwseq *hws, 159 struct dc *dc, 160 struct dc_phy_addr_space_config *pa_config); 161 void (*init_vm_ctx)(struct dce_hwseq *hws, 162 struct dc *dc, 163 struct dc_virtual_addr_space_config *va_config, 164 int vmid); 165 166 /* Writeback Related */ 167 void (*update_writeback)(struct dc *dc, 168 struct dc_writeback_info *wb_info, 169 struct dc_state *context); 170 void (*enable_writeback)(struct dc *dc, 171 struct dc_writeback_info *wb_info, 172 struct dc_state *context); 173 void (*disable_writeback)(struct dc *dc, 174 unsigned int dwb_pipe_inst); 175 176 bool (*mmhubbub_warmup)(struct dc *dc, 177 unsigned int num_dwb, 178 struct dc_writeback_info *wb_info); 179 180 /* Clock Related */ 181 enum dc_status (*set_clock)(struct dc *dc, 182 enum dc_clock_type clock_type, 183 uint32_t clk_khz, uint32_t stepping); 184 void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type, 185 struct dc_clock_config *clock_cfg); 186 void (*optimize_pwr_state)(const struct dc *dc, 187 struct dc_state *context); 188 void (*exit_optimized_pwr_state)(const struct dc *dc, 189 struct dc_state *context); 190 191 /* Audio Related */ 192 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); 193 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); 194 195 /* Stereo 3D Related */ 196 void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc); 197 198 /* HW State Logging Related */ 199 void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx); 200 void (*get_hw_state)(struct dc *dc, char *pBuf, 201 unsigned int bufSize, unsigned int mask); 202 void (*clear_status_bits)(struct dc *dc, unsigned int mask); 203 204 bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx, 205 uint32_t backlight_pwm_u16_16, 206 uint32_t frame_ramp); 207 208 void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx); 209 210 void (*set_pipe)(struct pipe_ctx *pipe_ctx); 211 212 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 213 /* Idle Optimization Related */ 214 bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable); 215 #endif 216 217 }; 218 219 void color_space_to_black_color( 220 const struct dc *dc, 221 enum dc_color_space colorspace, 222 struct tg_color *black_color); 223 224 bool hwss_wait_for_blank_complete( 225 struct timing_generator *tg); 226 227 const uint16_t *find_color_matrix( 228 enum dc_color_space color_space, 229 uint32_t *array_size); 230 231 #endif /* __DC_HW_SEQUENCER_H__ */ 232