1 /**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8 /*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32
33 #include <linux/compat.h>
34 #include <linux/console.h>
35 #include <linux/module.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/vga_switcheroo.h>
38 #include <linux/mmu_notifier.h>
39 #include <linux/pci.h>
40
41 #include <drm/drm_agpsupport.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_drv.h>
44 #include <drm/drm_fb_helper.h>
45 #include <drm/drm_file.h>
46 #include <drm/drm_gem.h>
47 #include <drm/drm_ioctl.h>
48 #include <drm/drm_pciids.h>
49 #include <drm/drm_probe_helper.h>
50 #include <drm/drm_vblank.h>
51 #include <drm/radeon_drm.h>
52
53 #include "radeon_drv.h"
54
55 /*
56 * KMS wrapper.
57 * - 2.0.0 - initial interface
58 * - 2.1.0 - add square tiling interface
59 * - 2.2.0 - add r6xx/r7xx const buffer support
60 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
61 * - 2.4.0 - add crtc id query
62 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
63 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
64 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
65 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
66 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
67 * 2.10.0 - fusion 2D tiling
68 * 2.11.0 - backend map, initial compute support for the CS checker
69 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
70 * 2.13.0 - virtual memory support, streamout
71 * 2.14.0 - add evergreen tiling informations
72 * 2.15.0 - add max_pipes query
73 * 2.16.0 - fix evergreen 2D tiled surface calculation
74 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
75 * 2.18.0 - r600-eg: allow "invalid" DB formats
76 * 2.19.0 - r600-eg: MSAA textures
77 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
78 * 2.21.0 - r600-r700: FMASK and CMASK
79 * 2.22.0 - r600 only: RESOLVE_BOX allowed
80 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
81 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
82 * 2.25.0 - eg+: new info request for num SE and num SH
83 * 2.26.0 - r600-eg: fix htile size computation
84 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
85 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
86 * 2.29.0 - R500 FP16 color clear registers
87 * 2.30.0 - fix for FMASK texturing
88 * 2.31.0 - Add fastfb support for rs690
89 * 2.32.0 - new info request for rings working
90 * 2.33.0 - Add SI tiling mode array query
91 * 2.34.0 - Add CIK tiling mode array query
92 * 2.35.0 - Add CIK macrotile mode array query
93 * 2.36.0 - Fix CIK DCE tiling setup
94 * 2.37.0 - allow GS ring setup on r6xx/r7xx
95 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
96 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
97 * 2.39.0 - Add INFO query for number of active CUs
98 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
99 * CS to GPU on >= r600
100 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
101 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
102 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
103 * 2.44.0 - SET_APPEND_CNT packet3 support
104 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
105 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
106 * 2.47.0 - Add UVD_NO_OP register support
107 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
108 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
109 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
110 */
111 #define KMS_DRIVER_MAJOR 2
112 #define KMS_DRIVER_MINOR 50
113 #define KMS_DRIVER_PATCHLEVEL 0
114 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
115 void radeon_driver_unload_kms(struct drm_device *dev);
116 void radeon_driver_lastclose_kms(struct drm_device *dev);
117 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
118 void radeon_driver_postclose_kms(struct drm_device *dev,
119 struct drm_file *file_priv);
120 int radeon_suspend_kms(struct drm_device *dev, bool suspend,
121 bool fbcon, bool freeze);
122 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
123 void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
124 int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
125 void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
126 irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
127 void radeon_gem_object_free(struct drm_gem_object *obj);
128 int radeon_gem_object_open(struct drm_gem_object *obj,
129 struct drm_file *file_priv);
130 void radeon_gem_object_close(struct drm_gem_object *obj,
131 struct drm_file *file_priv);
132 struct dma_buf *radeon_gem_prime_export(struct drm_gem_object *gobj,
133 int flags);
134 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
135 unsigned int flags, int *vpos, int *hpos,
136 ktime_t *stime, ktime_t *etime,
137 const struct drm_display_mode *mode);
138 extern bool radeon_is_px(struct drm_device *dev);
139 extern const struct drm_ioctl_desc radeon_ioctls_kms[];
140 extern int radeon_max_kms_ioctl;
141 int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
142 int radeon_mode_dumb_mmap(struct drm_file *filp,
143 struct drm_device *dev,
144 uint32_t handle, uint64_t *offset_p);
145 int radeon_mode_dumb_create(struct drm_file *file_priv,
146 struct drm_device *dev,
147 struct drm_mode_create_dumb *args);
148 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
149 struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
150 struct dma_buf_attachment *,
151 struct sg_table *sg);
152 int radeon_gem_prime_pin(struct drm_gem_object *obj);
153 void radeon_gem_prime_unpin(struct drm_gem_object *obj);
154 void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
155 void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
156
157 /* atpx handler */
158 #if defined(CONFIG_VGA_SWITCHEROO)
159 void radeon_register_atpx_handler(void);
160 void radeon_unregister_atpx_handler(void);
161 bool radeon_has_atpx_dgpu_power_cntl(void);
162 bool radeon_is_atpx_hybrid(void);
163 #else
radeon_register_atpx_handler(void)164 static inline void radeon_register_atpx_handler(void) {}
radeon_unregister_atpx_handler(void)165 static inline void radeon_unregister_atpx_handler(void) {}
radeon_has_atpx_dgpu_power_cntl(void)166 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
radeon_is_atpx_hybrid(void)167 static inline bool radeon_is_atpx_hybrid(void) { return false; }
168 #endif
169
170 int radeon_no_wb;
171 int radeon_modeset = -1;
172 int radeon_dynclks = -1;
173 int radeon_r4xx_atom = 0;
174 int radeon_agpmode = -1;
175 int radeon_vram_limit = 0;
176 int radeon_gart_size = -1; /* auto */
177 int radeon_benchmarking = 0;
178 int radeon_testing = 0;
179 int radeon_connector_table = 0;
180 int radeon_tv = 1;
181 int radeon_audio = -1;
182 int radeon_disp_priority = 0;
183 int radeon_hw_i2c = 0;
184 int radeon_pcie_gen2 = -1;
185 int radeon_msi = -1;
186 int radeon_lockup_timeout = 10000;
187 int radeon_fastfb = 0;
188 int radeon_dpm = -1;
189 int radeon_aspm = -1;
190 int radeon_runtime_pm = -1;
191 int radeon_hard_reset = 0;
192 int radeon_vm_size = 8;
193 int radeon_vm_block_size = -1;
194 int radeon_deep_color = 0;
195 int radeon_use_pflipirq = 2;
196 int radeon_bapm = -1;
197 int radeon_backlight = -1;
198 int radeon_auxch = -1;
199 int radeon_mst = 0;
200 int radeon_uvd = 1;
201 int radeon_vce = 1;
202
203 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
204 module_param_named(no_wb, radeon_no_wb, int, 0444);
205
206 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
207 module_param_named(modeset, radeon_modeset, int, 0400);
208
209 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
210 module_param_named(dynclks, radeon_dynclks, int, 0444);
211
212 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
213 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
214
215 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
216 module_param_named(vramlimit, radeon_vram_limit, int, 0600);
217
218 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
219 module_param_named(agpmode, radeon_agpmode, int, 0444);
220
221 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
222 module_param_named(gartsize, radeon_gart_size, int, 0600);
223
224 MODULE_PARM_DESC(benchmark, "Run benchmark");
225 module_param_named(benchmark, radeon_benchmarking, int, 0444);
226
227 MODULE_PARM_DESC(test, "Run tests");
228 module_param_named(test, radeon_testing, int, 0444);
229
230 MODULE_PARM_DESC(connector_table, "Force connector table");
231 module_param_named(connector_table, radeon_connector_table, int, 0444);
232
233 MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
234 module_param_named(tv, radeon_tv, int, 0444);
235
236 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
237 module_param_named(audio, radeon_audio, int, 0444);
238
239 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
240 module_param_named(disp_priority, radeon_disp_priority, int, 0444);
241
242 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
243 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
244
245 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
246 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
247
248 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
249 module_param_named(msi, radeon_msi, int, 0444);
250
251 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
252 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
253
254 MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
255 module_param_named(fastfb, radeon_fastfb, int, 0444);
256
257 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
258 module_param_named(dpm, radeon_dpm, int, 0444);
259
260 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
261 module_param_named(aspm, radeon_aspm, int, 0444);
262
263 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
264 module_param_named(runpm, radeon_runtime_pm, int, 0444);
265
266 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
267 module_param_named(hard_reset, radeon_hard_reset, int, 0444);
268
269 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
270 module_param_named(vm_size, radeon_vm_size, int, 0444);
271
272 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
273 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
274
275 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
276 module_param_named(deep_color, radeon_deep_color, int, 0444);
277
278 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
279 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
280
281 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
282 module_param_named(bapm, radeon_bapm, int, 0444);
283
284 MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
285 module_param_named(backlight, radeon_backlight, int, 0444);
286
287 MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
288 module_param_named(auxch, radeon_auxch, int, 0444);
289
290 MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
291 module_param_named(mst, radeon_mst, int, 0444);
292
293 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
294 module_param_named(uvd, radeon_uvd, int, 0444);
295
296 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
297 module_param_named(vce, radeon_vce, int, 0444);
298
299 int radeon_si_support = 1;
300 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
301 module_param_named(si_support, radeon_si_support, int, 0444);
302
303 int radeon_cik_support = 1;
304 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
305 module_param_named(cik_support, radeon_cik_support, int, 0444);
306
307 static struct pci_device_id pciidlist[] = {
308 radeon_PCI_IDS
309 };
310
311 MODULE_DEVICE_TABLE(pci, pciidlist);
312
313 static struct drm_driver kms_driver;
314
315 bool radeon_device_is_virtual(void);
316
radeon_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)317 static int radeon_pci_probe(struct pci_dev *pdev,
318 const struct pci_device_id *ent)
319 {
320 unsigned long flags = 0;
321 struct drm_device *dev;
322 int ret;
323
324 if (!ent)
325 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */
326
327 flags = ent->driver_data;
328
329 if (!radeon_si_support) {
330 switch (flags & RADEON_FAMILY_MASK) {
331 case CHIP_TAHITI:
332 case CHIP_PITCAIRN:
333 case CHIP_VERDE:
334 case CHIP_OLAND:
335 case CHIP_HAINAN:
336 dev_info(&pdev->dev,
337 "SI support disabled by module param\n");
338 return -ENODEV;
339 }
340 }
341 if (!radeon_cik_support) {
342 switch (flags & RADEON_FAMILY_MASK) {
343 case CHIP_KAVERI:
344 case CHIP_BONAIRE:
345 case CHIP_HAWAII:
346 case CHIP_KABINI:
347 case CHIP_MULLINS:
348 dev_info(&pdev->dev,
349 "CIK support disabled by module param\n");
350 return -ENODEV;
351 }
352 }
353
354 if (vga_switcheroo_client_probe_defer(pdev))
355 return -EPROBE_DEFER;
356
357 /* Get rid of things like offb */
358 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "radeondrmfb");
359 if (ret)
360 return ret;
361
362 dev = drm_dev_alloc(&kms_driver, &pdev->dev);
363 if (IS_ERR(dev))
364 return PTR_ERR(dev);
365
366 ret = pci_enable_device(pdev);
367 if (ret)
368 goto err_free;
369
370 dev->pdev = pdev;
371 #ifdef __alpha__
372 dev->hose = pdev->sysdata;
373 #endif
374
375 pci_set_drvdata(pdev, dev);
376
377 if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP))
378 dev->agp = drm_agp_init(dev);
379 if (dev->agp) {
380 dev->agp->agp_mtrr = arch_phys_wc_add(
381 dev->agp->agp_info.aper_base,
382 dev->agp->agp_info.aper_size *
383 1024 * 1024);
384 }
385
386 ret = drm_dev_register(dev, ent->driver_data);
387 if (ret)
388 goto err_agp;
389
390 return 0;
391
392 err_agp:
393 if (dev->agp)
394 arch_phys_wc_del(dev->agp->agp_mtrr);
395 kfree(dev->agp);
396 pci_disable_device(pdev);
397 err_free:
398 drm_dev_put(dev);
399 return ret;
400 }
401
402 static void
radeon_pci_remove(struct pci_dev * pdev)403 radeon_pci_remove(struct pci_dev *pdev)
404 {
405 struct drm_device *dev = pci_get_drvdata(pdev);
406
407 drm_put_dev(dev);
408 }
409
410 static void
radeon_pci_shutdown(struct pci_dev * pdev)411 radeon_pci_shutdown(struct pci_dev *pdev)
412 {
413 /* if we are running in a VM, make sure the device
414 * torn down properly on reboot/shutdown
415 */
416 if (radeon_device_is_virtual())
417 radeon_pci_remove(pdev);
418
419 #if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64)
420 /*
421 * Some adapters need to be suspended before a
422 * shutdown occurs in order to prevent an error
423 * during kexec, shutdown or reboot.
424 * Make this power and Loongson specific because
425 * it breaks some other boards.
426 */
427 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false);
428 #endif
429 }
430
radeon_pmops_suspend(struct device * dev)431 static int radeon_pmops_suspend(struct device *dev)
432 {
433 struct drm_device *drm_dev = dev_get_drvdata(dev);
434 return radeon_suspend_kms(drm_dev, true, true, false);
435 }
436
radeon_pmops_resume(struct device * dev)437 static int radeon_pmops_resume(struct device *dev)
438 {
439 struct drm_device *drm_dev = dev_get_drvdata(dev);
440
441 /* GPU comes up enabled by the bios on resume */
442 if (radeon_is_px(drm_dev)) {
443 pm_runtime_disable(dev);
444 pm_runtime_set_active(dev);
445 pm_runtime_enable(dev);
446 }
447
448 return radeon_resume_kms(drm_dev, true, true);
449 }
450
radeon_pmops_freeze(struct device * dev)451 static int radeon_pmops_freeze(struct device *dev)
452 {
453 struct drm_device *drm_dev = dev_get_drvdata(dev);
454 return radeon_suspend_kms(drm_dev, false, true, true);
455 }
456
radeon_pmops_thaw(struct device * dev)457 static int radeon_pmops_thaw(struct device *dev)
458 {
459 struct drm_device *drm_dev = dev_get_drvdata(dev);
460 return radeon_resume_kms(drm_dev, false, true);
461 }
462
radeon_pmops_runtime_suspend(struct device * dev)463 static int radeon_pmops_runtime_suspend(struct device *dev)
464 {
465 struct pci_dev *pdev = to_pci_dev(dev);
466 struct drm_device *drm_dev = pci_get_drvdata(pdev);
467 int ret;
468
469 if (!radeon_is_px(drm_dev)) {
470 pm_runtime_forbid(dev);
471 return -EBUSY;
472 }
473
474 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
475 drm_kms_helper_poll_disable(drm_dev);
476
477 ret = radeon_suspend_kms(drm_dev, false, false, false);
478 pci_save_state(pdev);
479 pci_disable_device(pdev);
480 pci_ignore_hotplug(pdev);
481 if (radeon_is_atpx_hybrid())
482 pci_set_power_state(pdev, PCI_D3cold);
483 else if (!radeon_has_atpx_dgpu_power_cntl())
484 pci_set_power_state(pdev, PCI_D3hot);
485 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
486
487 return 0;
488 }
489
radeon_pmops_runtime_resume(struct device * dev)490 static int radeon_pmops_runtime_resume(struct device *dev)
491 {
492 struct pci_dev *pdev = to_pci_dev(dev);
493 struct drm_device *drm_dev = pci_get_drvdata(pdev);
494 int ret;
495
496 if (!radeon_is_px(drm_dev))
497 return -EINVAL;
498
499 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
500
501 if (radeon_is_atpx_hybrid() ||
502 !radeon_has_atpx_dgpu_power_cntl())
503 pci_set_power_state(pdev, PCI_D0);
504 pci_restore_state(pdev);
505 ret = pci_enable_device(pdev);
506 if (ret)
507 return ret;
508 pci_set_master(pdev);
509
510 ret = radeon_resume_kms(drm_dev, false, false);
511 drm_kms_helper_poll_enable(drm_dev);
512 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
513 return 0;
514 }
515
radeon_pmops_runtime_idle(struct device * dev)516 static int radeon_pmops_runtime_idle(struct device *dev)
517 {
518 struct drm_device *drm_dev = dev_get_drvdata(dev);
519 struct drm_crtc *crtc;
520
521 if (!radeon_is_px(drm_dev)) {
522 pm_runtime_forbid(dev);
523 return -EBUSY;
524 }
525
526 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
527 if (crtc->enabled) {
528 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
529 return -EBUSY;
530 }
531 }
532
533 pm_runtime_mark_last_busy(dev);
534 pm_runtime_autosuspend(dev);
535 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
536 return 1;
537 }
538
radeon_drm_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)539 long radeon_drm_ioctl(struct file *filp,
540 unsigned int cmd, unsigned long arg)
541 {
542 struct drm_file *file_priv = filp->private_data;
543 struct drm_device *dev;
544 long ret;
545 dev = file_priv->minor->dev;
546 ret = pm_runtime_get_sync(dev->dev);
547 if (ret < 0) {
548 pm_runtime_put_autosuspend(dev->dev);
549 return ret;
550 }
551
552 ret = drm_ioctl(filp, cmd, arg);
553
554 pm_runtime_mark_last_busy(dev->dev);
555 pm_runtime_put_autosuspend(dev->dev);
556 return ret;
557 }
558
559 #ifdef CONFIG_COMPAT
radeon_kms_compat_ioctl(struct file * filp,unsigned int cmd,unsigned long arg)560 static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
561 {
562 unsigned int nr = DRM_IOCTL_NR(cmd);
563 int ret;
564
565 if (nr < DRM_COMMAND_BASE)
566 return drm_compat_ioctl(filp, cmd, arg);
567
568 ret = radeon_drm_ioctl(filp, cmd, arg);
569
570 return ret;
571 }
572 #endif
573
574 static const struct dev_pm_ops radeon_pm_ops = {
575 .suspend = radeon_pmops_suspend,
576 .resume = radeon_pmops_resume,
577 .freeze = radeon_pmops_freeze,
578 .thaw = radeon_pmops_thaw,
579 .poweroff = radeon_pmops_freeze,
580 .restore = radeon_pmops_resume,
581 .runtime_suspend = radeon_pmops_runtime_suspend,
582 .runtime_resume = radeon_pmops_runtime_resume,
583 .runtime_idle = radeon_pmops_runtime_idle,
584 };
585
586 static const struct file_operations radeon_driver_kms_fops = {
587 .owner = THIS_MODULE,
588 .open = drm_open,
589 .release = drm_release,
590 .unlocked_ioctl = radeon_drm_ioctl,
591 .mmap = radeon_mmap,
592 .poll = drm_poll,
593 .read = drm_read,
594 #ifdef CONFIG_COMPAT
595 .compat_ioctl = radeon_kms_compat_ioctl,
596 #endif
597 };
598
599 static struct drm_driver kms_driver = {
600 .driver_features =
601 DRIVER_GEM | DRIVER_RENDER,
602 .load = radeon_driver_load_kms,
603 .open = radeon_driver_open_kms,
604 .postclose = radeon_driver_postclose_kms,
605 .lastclose = radeon_driver_lastclose_kms,
606 .unload = radeon_driver_unload_kms,
607 .irq_preinstall = radeon_driver_irq_preinstall_kms,
608 .irq_postinstall = radeon_driver_irq_postinstall_kms,
609 .irq_uninstall = radeon_driver_irq_uninstall_kms,
610 .irq_handler = radeon_driver_irq_handler_kms,
611 .ioctls = radeon_ioctls_kms,
612 .gem_free_object_unlocked = radeon_gem_object_free,
613 .gem_open_object = radeon_gem_object_open,
614 .gem_close_object = radeon_gem_object_close,
615 .dumb_create = radeon_mode_dumb_create,
616 .dumb_map_offset = radeon_mode_dumb_mmap,
617 .fops = &radeon_driver_kms_fops,
618
619 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
620 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
621 .gem_prime_export = radeon_gem_prime_export,
622 .gem_prime_pin = radeon_gem_prime_pin,
623 .gem_prime_unpin = radeon_gem_prime_unpin,
624 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
625 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
626 .gem_prime_vmap = radeon_gem_prime_vmap,
627 .gem_prime_vunmap = radeon_gem_prime_vunmap,
628
629 .name = DRIVER_NAME,
630 .desc = DRIVER_DESC,
631 .date = DRIVER_DATE,
632 .major = KMS_DRIVER_MAJOR,
633 .minor = KMS_DRIVER_MINOR,
634 .patchlevel = KMS_DRIVER_PATCHLEVEL,
635 };
636
637 static struct drm_driver *driver;
638 static struct pci_driver *pdriver;
639
640 static struct pci_driver radeon_kms_pci_driver = {
641 .name = DRIVER_NAME,
642 .id_table = pciidlist,
643 .probe = radeon_pci_probe,
644 .remove = radeon_pci_remove,
645 .shutdown = radeon_pci_shutdown,
646 .driver.pm = &radeon_pm_ops,
647 };
648
radeon_init(void)649 static int __init radeon_init(void)
650 {
651 if (vgacon_text_force() && radeon_modeset == -1) {
652 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
653 radeon_modeset = 0;
654 }
655 /* set to modesetting by default if not nomodeset */
656 if (radeon_modeset == -1)
657 radeon_modeset = 1;
658
659 if (radeon_modeset == 1) {
660 DRM_INFO("radeon kernel modesetting enabled.\n");
661 driver = &kms_driver;
662 pdriver = &radeon_kms_pci_driver;
663 driver->driver_features |= DRIVER_MODESET;
664 driver->num_ioctls = radeon_max_kms_ioctl;
665 radeon_register_atpx_handler();
666
667 } else {
668 DRM_ERROR("No UMS support in radeon module!\n");
669 return -EINVAL;
670 }
671
672 return pci_register_driver(pdriver);
673 }
674
radeon_exit(void)675 static void __exit radeon_exit(void)
676 {
677 pci_unregister_driver(pdriver);
678 radeon_unregister_atpx_handler();
679 mmu_notifier_synchronize();
680 }
681
682 module_init(radeon_init);
683 module_exit(radeon_exit);
684
685 MODULE_AUTHOR(DRIVER_AUTHOR);
686 MODULE_DESCRIPTION(DRIVER_DESC);
687 MODULE_LICENSE("GPL and additional rights");
688