1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
4 *
5 * Based on drivers/tty/serial/8250/8250_pci.c,
6 *
7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
8 */
9 #include <linux/acpi.h>
10 #include <linux/dmi.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/property.h>
16 #include <linux/serial_core.h>
17 #include <linux/serial_reg.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/tty.h>
21 #include <linux/8250_pci.h>
22 #include <linux/delay.h>
23
24 #include <asm/byteorder.h>
25
26 #include "8250.h"
27
28 #define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052
29 #define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d
30 #define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c
31 #define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8
32 #define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2
33 #define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db
34 #define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea
35
36 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
37 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
38 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
39 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
40 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
41 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
42 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
43
44 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
45 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
46
47 #define PCI_SUBDEVICE_ID_USR_2980 0x0128
48 #define PCI_SUBDEVICE_ID_USR_2981 0x0129
49
50 #define PCI_DEVICE_ID_SEALEVEL_710xC 0x1001
51 #define PCI_DEVICE_ID_SEALEVEL_720xC 0x1002
52 #define PCI_DEVICE_ID_SEALEVEL_740xC 0x1004
53 #define PCI_DEVICE_ID_SEALEVEL_780xC 0x1008
54 #define PCI_DEVICE_ID_SEALEVEL_716xC 0x1010
55
56 #define UART_EXAR_INT0 0x80
57 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
58 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
59 #define UART_EXAR_DVID 0x8d /* Device identification */
60
61 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */
62 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
63 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
64 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
65 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
66 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
67 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
68
69 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
70 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
71
72 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
73 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
74 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
75 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
76 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
77 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
78 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
79 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
80 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
81 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
82 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
83 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
84
85 #define UART_EXAR_RS485_DLY(x) ((x) << 4)
86
87 /*
88 * IOT2040 MPIO wiring semantics:
89 *
90 * MPIO Port Function
91 * ---- ---- --------
92 * 0 2 Mode bit 0
93 * 1 2 Mode bit 1
94 * 2 2 Terminate bus
95 * 3 - <reserved>
96 * 4 3 Mode bit 0
97 * 5 3 Mode bit 1
98 * 6 3 Terminate bus
99 * 7 - <reserved>
100 * 8 2 Enable
101 * 9 3 Enable
102 * 10 - Red LED
103 * 11..15 - <unused>
104 */
105
106 /* IOT2040 MPIOs 0..7 */
107 #define IOT2040_UART_MODE_RS232 0x01
108 #define IOT2040_UART_MODE_RS485 0x02
109 #define IOT2040_UART_MODE_RS422 0x03
110 #define IOT2040_UART_TERMINATE_BUS 0x04
111
112 #define IOT2040_UART1_MASK 0x0f
113 #define IOT2040_UART2_SHIFT 4
114
115 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */
116 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */
117
118 /* IOT2040 MPIOs 8..15 */
119 #define IOT2040_UARTS_ENABLE 0x03
120 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */
121
122 struct exar8250;
123
124 struct exar8250_platform {
125 int (*rs485_config)(struct uart_port *, struct serial_rs485 *);
126 int (*register_gpio)(struct pci_dev *, struct uart_8250_port *);
127 };
128
129 /**
130 * struct exar8250_board - board information
131 * @num_ports: number of serial ports
132 * @reg_shift: describes UART register mapping in PCI memory
133 * @setup: quirk run at ->probe() stage
134 * @exit: quirk run at ->remove() stage
135 */
136 struct exar8250_board {
137 unsigned int num_ports;
138 unsigned int reg_shift;
139 int (*setup)(struct exar8250 *, struct pci_dev *,
140 struct uart_8250_port *, int);
141 void (*exit)(struct pci_dev *pcidev);
142 };
143
144 struct exar8250 {
145 unsigned int nr;
146 struct exar8250_board *board;
147 void __iomem *virt;
148 int line[];
149 };
150
exar_pm(struct uart_port * port,unsigned int state,unsigned int old)151 static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old)
152 {
153 /*
154 * Exar UARTs have a SLEEP register that enables or disables each UART
155 * to enter sleep mode separately. On the XR17V35x the register
156 * is accessible to each UART at the UART_EXAR_SLEEP offset, but
157 * the UART channel may only write to the corresponding bit.
158 */
159 serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0);
160 }
161
162 /*
163 * XR17V35x UARTs have an extra fractional divisor register (DLD)
164 * Calculate divisor with extra 4-bit fractional portion
165 */
xr17v35x_get_divisor(struct uart_port * p,unsigned int baud,unsigned int * frac)166 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud,
167 unsigned int *frac)
168 {
169 unsigned int quot_16;
170
171 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud);
172 *frac = quot_16 & 0x0f;
173
174 return quot_16 >> 4;
175 }
176
xr17v35x_set_divisor(struct uart_port * p,unsigned int baud,unsigned int quot,unsigned int quot_frac)177 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud,
178 unsigned int quot, unsigned int quot_frac)
179 {
180 serial8250_do_set_divisor(p, baud, quot, quot_frac);
181
182 /* Preserve bits not related to baudrate; DLD[7:4]. */
183 quot_frac |= serial_port_in(p, 0x2) & 0xf0;
184 serial_port_out(p, 0x2, quot_frac);
185 }
186
xr17v35x_startup(struct uart_port * port)187 static int xr17v35x_startup(struct uart_port *port)
188 {
189 /*
190 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
191 * MCR [7:5] and MSR [7:0]
192 */
193 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
194
195 /*
196 * Make sure all interrups are masked until initialization is
197 * complete and the FIFOs are cleared
198 */
199 serial_port_out(port, UART_IER, 0);
200
201 return serial8250_do_startup(port);
202 }
203
exar_shutdown(struct uart_port * port)204 static void exar_shutdown(struct uart_port *port)
205 {
206 unsigned char lsr;
207 bool tx_complete = false;
208 struct uart_8250_port *up = up_to_u8250p(port);
209 struct circ_buf *xmit = &port->state->xmit;
210 int i = 0;
211
212 do {
213 lsr = serial_in(up, UART_LSR);
214 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
215 tx_complete = true;
216 else
217 tx_complete = false;
218 usleep_range(1000, 1100);
219 } while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000);
220
221 serial8250_do_shutdown(port);
222 }
223
default_setup(struct exar8250 * priv,struct pci_dev * pcidev,int idx,unsigned int offset,struct uart_8250_port * port)224 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
225 int idx, unsigned int offset,
226 struct uart_8250_port *port)
227 {
228 const struct exar8250_board *board = priv->board;
229 unsigned int bar = 0;
230 unsigned char status;
231
232 port->port.iotype = UPIO_MEM;
233 port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
234 port->port.membase = priv->virt + offset;
235 port->port.regshift = board->reg_shift;
236
237 /*
238 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled
239 * with when DLAB is set which will cause the device to incorrectly match
240 * and assign port type to PORT_16650. The EFR for this UART is found
241 * at offset 0x09. Instead check the Deice ID (DVID) register
242 * for a 2, 4 or 8 port UART.
243 */
244 status = readb(port->port.membase + UART_EXAR_DVID);
245 if (status == 0x82 || status == 0x84 || status == 0x88) {
246 port->port.type = PORT_XR17V35X;
247
248 port->port.get_divisor = xr17v35x_get_divisor;
249 port->port.set_divisor = xr17v35x_set_divisor;
250
251 port->port.startup = xr17v35x_startup;
252 } else {
253 port->port.type = PORT_XR17D15X;
254 }
255
256 port->port.pm = exar_pm;
257 port->port.shutdown = exar_shutdown;
258
259 return 0;
260 }
261
262 static int
pci_fastcom335_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)263 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
264 struct uart_8250_port *port, int idx)
265 {
266 unsigned int offset = idx * 0x200;
267 unsigned int baud = 1843200;
268 u8 __iomem *p;
269 int err;
270
271 port->port.uartclk = baud * 16;
272
273 err = default_setup(priv, pcidev, idx, offset, port);
274 if (err)
275 return err;
276
277 p = port->port.membase;
278
279 writeb(0x00, p + UART_EXAR_8XMODE);
280 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
281 writeb(32, p + UART_EXAR_TXTRG);
282 writeb(32, p + UART_EXAR_RXTRG);
283
284 /*
285 * Setup Multipurpose Input/Output pins.
286 */
287 if (idx == 0) {
288 switch (pcidev->device) {
289 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
290 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
291 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
292 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
293 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
294 break;
295 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
296 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
297 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
298 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
299 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
300 break;
301 }
302 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
303 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
304 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
305 }
306
307 return 0;
308 }
309
310 static int
pci_connect_tech_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)311 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
312 struct uart_8250_port *port, int idx)
313 {
314 unsigned int offset = idx * 0x200;
315 unsigned int baud = 1843200;
316
317 port->port.uartclk = baud * 16;
318 return default_setup(priv, pcidev, idx, offset, port);
319 }
320
321 static int
pci_xr17c154_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)322 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
323 struct uart_8250_port *port, int idx)
324 {
325 unsigned int offset = idx * 0x200;
326 unsigned int baud = 921600;
327
328 port->port.uartclk = baud * 16;
329 return default_setup(priv, pcidev, idx, offset, port);
330 }
331
setup_gpio(struct pci_dev * pcidev,u8 __iomem * p)332 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
333 {
334 /*
335 * The Commtech adapters required the MPIOs to be driven low. The Exar
336 * devices will export them as GPIOs, so we pre-configure them safely
337 * as inputs.
338 */
339
340 u8 dir = 0x00;
341
342 if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
343 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
344 // Configure GPIO as inputs for Commtech adapters
345 dir = 0xff;
346 } else {
347 // Configure GPIO as outputs for SeaLevel adapters
348 dir = 0x00;
349 }
350
351 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
352 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
353 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
354 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
355 writeb(dir, p + UART_EXAR_MPIOSEL_7_0);
356 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
357 writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
358 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
359 writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
360 writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
361 writeb(dir, p + UART_EXAR_MPIOSEL_15_8);
362 writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
363 }
364
365 static void *
__xr17v35x_register_gpio(struct pci_dev * pcidev,const struct property_entry * properties)366 __xr17v35x_register_gpio(struct pci_dev *pcidev,
367 const struct property_entry *properties)
368 {
369 struct platform_device *pdev;
370
371 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
372 if (!pdev)
373 return NULL;
374
375 pdev->dev.parent = &pcidev->dev;
376 ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev));
377
378 if (platform_device_add_properties(pdev, properties) < 0 ||
379 platform_device_add(pdev) < 0) {
380 platform_device_put(pdev);
381 return NULL;
382 }
383
384 return pdev;
385 }
386
387 static const struct property_entry exar_gpio_properties[] = {
388 PROPERTY_ENTRY_U32("exar,first-pin", 0),
389 PROPERTY_ENTRY_U32("ngpios", 16),
390 { }
391 };
392
xr17v35x_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)393 static int xr17v35x_register_gpio(struct pci_dev *pcidev,
394 struct uart_8250_port *port)
395 {
396 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
397 port->port.private_data =
398 __xr17v35x_register_gpio(pcidev, exar_gpio_properties);
399
400 return 0;
401 }
402
generic_rs485_config(struct uart_port * port,struct serial_rs485 * rs485)403 static int generic_rs485_config(struct uart_port *port,
404 struct serial_rs485 *rs485)
405 {
406 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
407 u8 __iomem *p = port->membase;
408 u8 value;
409
410 value = readb(p + UART_EXAR_FCTR);
411 if (is_rs485)
412 value |= UART_FCTR_EXAR_485;
413 else
414 value &= ~UART_FCTR_EXAR_485;
415
416 writeb(value, p + UART_EXAR_FCTR);
417
418 if (is_rs485)
419 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
420
421 port->rs485 = *rs485;
422
423 return 0;
424 }
425
426 static const struct exar8250_platform exar8250_default_platform = {
427 .register_gpio = xr17v35x_register_gpio,
428 .rs485_config = generic_rs485_config,
429 };
430
iot2040_rs485_config(struct uart_port * port,struct serial_rs485 * rs485)431 static int iot2040_rs485_config(struct uart_port *port,
432 struct serial_rs485 *rs485)
433 {
434 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
435 u8 __iomem *p = port->membase;
436 u8 mask = IOT2040_UART1_MASK;
437 u8 mode, value;
438
439 if (is_rs485) {
440 if (rs485->flags & SER_RS485_RX_DURING_TX)
441 mode = IOT2040_UART_MODE_RS422;
442 else
443 mode = IOT2040_UART_MODE_RS485;
444
445 if (rs485->flags & SER_RS485_TERMINATE_BUS)
446 mode |= IOT2040_UART_TERMINATE_BUS;
447 } else {
448 mode = IOT2040_UART_MODE_RS232;
449 }
450
451 if (port->line == 3) {
452 mask <<= IOT2040_UART2_SHIFT;
453 mode <<= IOT2040_UART2_SHIFT;
454 }
455
456 value = readb(p + UART_EXAR_MPIOLVL_7_0);
457 value &= ~mask;
458 value |= mode;
459 writeb(value, p + UART_EXAR_MPIOLVL_7_0);
460
461 return generic_rs485_config(port, rs485);
462 }
463
464 static const struct property_entry iot2040_gpio_properties[] = {
465 PROPERTY_ENTRY_U32("exar,first-pin", 10),
466 PROPERTY_ENTRY_U32("ngpios", 1),
467 { }
468 };
469
iot2040_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)470 static int iot2040_register_gpio(struct pci_dev *pcidev,
471 struct uart_8250_port *port)
472 {
473 u8 __iomem *p = port->port.membase;
474
475 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
476 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
477 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
478 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
479
480 port->port.private_data =
481 __xr17v35x_register_gpio(pcidev, iot2040_gpio_properties);
482
483 return 0;
484 }
485
486 static const struct exar8250_platform iot2040_platform = {
487 .rs485_config = iot2040_rs485_config,
488 .register_gpio = iot2040_register_gpio,
489 };
490
491 /*
492 * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device,
493 * IOT2020 doesn't have. Therefore it is sufficient to match on the common
494 * board name after the device was found.
495 */
496 static const struct dmi_system_id exar_platforms[] = {
497 {
498 .matches = {
499 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
500 },
501 .driver_data = (void *)&iot2040_platform,
502 },
503 {}
504 };
505
506 static int
pci_xr17v35x_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)507 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
508 struct uart_8250_port *port, int idx)
509 {
510 const struct exar8250_platform *platform;
511 const struct dmi_system_id *dmi_match;
512 unsigned int offset = idx * 0x400;
513 unsigned int baud = 7812500;
514 u8 __iomem *p;
515 int ret;
516
517 dmi_match = dmi_first_match(exar_platforms);
518 if (dmi_match)
519 platform = dmi_match->driver_data;
520 else
521 platform = &exar8250_default_platform;
522
523 port->port.uartclk = baud * 16;
524 port->port.rs485_config = platform->rs485_config;
525
526 /*
527 * Setup the UART clock for the devices on expansion slot to
528 * half the clock speed of the main chip (which is 125MHz)
529 */
530 if (idx >= 8)
531 port->port.uartclk /= 2;
532
533 ret = default_setup(priv, pcidev, idx, offset, port);
534 if (ret)
535 return ret;
536
537 p = port->port.membase;
538
539 writeb(0x00, p + UART_EXAR_8XMODE);
540 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
541 writeb(128, p + UART_EXAR_TXTRG);
542 writeb(128, p + UART_EXAR_RXTRG);
543
544 if (idx == 0) {
545 /* Setup Multipurpose Input/Output pins. */
546 setup_gpio(pcidev, p);
547
548 ret = platform->register_gpio(pcidev, port);
549 }
550
551 return ret;
552 }
553
pci_xr17v35x_exit(struct pci_dev * pcidev)554 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
555 {
556 struct exar8250 *priv = pci_get_drvdata(pcidev);
557 struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
558 struct platform_device *pdev = port->port.private_data;
559
560 platform_device_unregister(pdev);
561 port->port.private_data = NULL;
562 }
563
exar_misc_clear(struct exar8250 * priv)564 static inline void exar_misc_clear(struct exar8250 *priv)
565 {
566 /* Clear all PCI interrupts by reading INT0. No effect on IIR */
567 readb(priv->virt + UART_EXAR_INT0);
568
569 /* Clear INT0 for Expansion Interface slave ports, too */
570 if (priv->board->num_ports > 8)
571 readb(priv->virt + 0x2000 + UART_EXAR_INT0);
572 }
573
574 /*
575 * These Exar UARTs have an extra interrupt indicator that could fire for a
576 * few interrupts that are not presented/cleared through IIR. One of which is
577 * a wakeup interrupt when coming out of sleep. These interrupts are only
578 * cleared by reading global INT0 or INT1 registers as interrupts are
579 * associated with channel 0. The INT[3:0] registers _are_ accessible from each
580 * channel's address space, but for the sake of bus efficiency we register a
581 * dedicated handler at the PCI device level to handle them.
582 */
exar_misc_handler(int irq,void * data)583 static irqreturn_t exar_misc_handler(int irq, void *data)
584 {
585 exar_misc_clear(data);
586
587 return IRQ_HANDLED;
588 }
589
590 static int
exar_pci_probe(struct pci_dev * pcidev,const struct pci_device_id * ent)591 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
592 {
593 unsigned int nr_ports, i, bar = 0, maxnr;
594 struct exar8250_board *board;
595 struct uart_8250_port uart;
596 struct exar8250 *priv;
597 int rc;
598
599 board = (struct exar8250_board *)ent->driver_data;
600 if (!board)
601 return -EINVAL;
602
603 rc = pcim_enable_device(pcidev);
604 if (rc)
605 return rc;
606
607 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
608
609 if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO)
610 nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1);
611 else if (board->num_ports)
612 nr_ports = board->num_ports;
613 else if (pcidev->vendor == PCI_VENDOR_ID_SEALEVEL)
614 nr_ports = pcidev->device & 0xff;
615 else
616 nr_ports = pcidev->device & 0x0f;
617
618 priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
619 if (!priv)
620 return -ENOMEM;
621
622 priv->board = board;
623 priv->virt = pcim_iomap(pcidev, bar, 0);
624 if (!priv->virt)
625 return -ENOMEM;
626
627 pci_set_master(pcidev);
628
629 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
630 if (rc < 0)
631 return rc;
632
633 memset(&uart, 0, sizeof(uart));
634 uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
635 uart.port.irq = pci_irq_vector(pcidev, 0);
636 uart.port.dev = &pcidev->dev;
637
638 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
639 IRQF_SHARED, "exar_uart", priv);
640 if (rc)
641 return rc;
642
643 /* Clear interrupts */
644 exar_misc_clear(priv);
645
646 for (i = 0; i < nr_ports && i < maxnr; i++) {
647 rc = board->setup(priv, pcidev, &uart, i);
648 if (rc) {
649 dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
650 break;
651 }
652
653 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
654 uart.port.iobase, uart.port.irq, uart.port.iotype);
655
656 priv->line[i] = serial8250_register_8250_port(&uart);
657 if (priv->line[i] < 0) {
658 dev_err(&pcidev->dev,
659 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
660 uart.port.iobase, uart.port.irq,
661 uart.port.iotype, priv->line[i]);
662 break;
663 }
664 }
665 priv->nr = i;
666 pci_set_drvdata(pcidev, priv);
667 return 0;
668 }
669
exar_pci_remove(struct pci_dev * pcidev)670 static void exar_pci_remove(struct pci_dev *pcidev)
671 {
672 struct exar8250 *priv = pci_get_drvdata(pcidev);
673 unsigned int i;
674
675 for (i = 0; i < priv->nr; i++)
676 serial8250_unregister_port(priv->line[i]);
677
678 if (priv->board->exit)
679 priv->board->exit(pcidev);
680 }
681
exar_suspend(struct device * dev)682 static int __maybe_unused exar_suspend(struct device *dev)
683 {
684 struct pci_dev *pcidev = to_pci_dev(dev);
685 struct exar8250 *priv = pci_get_drvdata(pcidev);
686 unsigned int i;
687
688 for (i = 0; i < priv->nr; i++)
689 if (priv->line[i] >= 0)
690 serial8250_suspend_port(priv->line[i]);
691
692 /* Ensure that every init quirk is properly torn down */
693 if (priv->board->exit)
694 priv->board->exit(pcidev);
695
696 return 0;
697 }
698
exar_resume(struct device * dev)699 static int __maybe_unused exar_resume(struct device *dev)
700 {
701 struct exar8250 *priv = dev_get_drvdata(dev);
702 unsigned int i;
703
704 exar_misc_clear(priv);
705
706 for (i = 0; i < priv->nr; i++)
707 if (priv->line[i] >= 0)
708 serial8250_resume_port(priv->line[i]);
709
710 return 0;
711 }
712
713 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
714
715 static const struct exar8250_board pbn_fastcom335_2 = {
716 .num_ports = 2,
717 .setup = pci_fastcom335_setup,
718 };
719
720 static const struct exar8250_board pbn_fastcom335_4 = {
721 .num_ports = 4,
722 .setup = pci_fastcom335_setup,
723 };
724
725 static const struct exar8250_board pbn_fastcom335_8 = {
726 .num_ports = 8,
727 .setup = pci_fastcom335_setup,
728 };
729
730 static const struct exar8250_board pbn_connect = {
731 .setup = pci_connect_tech_setup,
732 };
733
734 static const struct exar8250_board pbn_exar_ibm_saturn = {
735 .num_ports = 1,
736 .setup = pci_xr17c154_setup,
737 };
738
739 static const struct exar8250_board pbn_exar_XR17C15x = {
740 .setup = pci_xr17c154_setup,
741 };
742
743 static const struct exar8250_board pbn_exar_XR17V35x = {
744 .setup = pci_xr17v35x_setup,
745 .exit = pci_xr17v35x_exit,
746 };
747
748 static const struct exar8250_board pbn_fastcom35x_2 = {
749 .num_ports = 2,
750 .setup = pci_xr17v35x_setup,
751 .exit = pci_xr17v35x_exit,
752 };
753
754 static const struct exar8250_board pbn_fastcom35x_4 = {
755 .num_ports = 4,
756 .setup = pci_xr17v35x_setup,
757 .exit = pci_xr17v35x_exit,
758 };
759
760 static const struct exar8250_board pbn_fastcom35x_8 = {
761 .num_ports = 8,
762 .setup = pci_xr17v35x_setup,
763 .exit = pci_xr17v35x_exit,
764 };
765
766 static const struct exar8250_board pbn_exar_XR17V4358 = {
767 .num_ports = 12,
768 .setup = pci_xr17v35x_setup,
769 .exit = pci_xr17v35x_exit,
770 };
771
772 static const struct exar8250_board pbn_exar_XR17V8358 = {
773 .num_ports = 16,
774 .setup = pci_xr17v35x_setup,
775 .exit = pci_xr17v35x_exit,
776 };
777
778 #define CONNECT_DEVICE(devid, sdevid, bd) { \
779 PCI_DEVICE_SUB( \
780 PCI_VENDOR_ID_EXAR, \
781 PCI_DEVICE_ID_EXAR_##devid, \
782 PCI_SUBVENDOR_ID_CONNECT_TECH, \
783 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \
784 (kernel_ulong_t)&bd \
785 }
786
787 #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) }
788
789 #define IBM_DEVICE(devid, sdevid, bd) { \
790 PCI_DEVICE_SUB( \
791 PCI_VENDOR_ID_EXAR, \
792 PCI_DEVICE_ID_EXAR_##devid, \
793 PCI_VENDOR_ID_IBM, \
794 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
795 (kernel_ulong_t)&bd \
796 }
797
798 #define USR_DEVICE(devid, sdevid, bd) { \
799 PCI_DEVICE_SUB( \
800 PCI_VENDOR_ID_USR, \
801 PCI_DEVICE_ID_EXAR_##devid, \
802 PCI_VENDOR_ID_EXAR, \
803 PCI_SUBDEVICE_ID_USR_##sdevid), 0, 0, \
804 (kernel_ulong_t)&bd \
805 }
806
807 static const struct pci_device_id exar_pci_tbl[] = {
808 EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x),
809 EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x),
810 EXAR_DEVICE(ACCESSIO, COM_8S, pbn_exar_XR17C15x),
811 EXAR_DEVICE(ACCESSIO, COM232_8, pbn_exar_XR17C15x),
812 EXAR_DEVICE(ACCESSIO, COM_2SM, pbn_exar_XR17C15x),
813 EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x),
814 EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x),
815
816 CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
817 CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
818 CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
819 CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
820 CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
821 CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
822 CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
823 CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
824 CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
825 CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
826 CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
827 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
828
829 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
830
831 /* USRobotics USR298x-OEM PCI Modems */
832 USR_DEVICE(XR17C152, 2980, pbn_exar_XR17C15x),
833 USR_DEVICE(XR17C152, 2981, pbn_exar_XR17C15x),
834
835 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
836 EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x),
837 EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x),
838 EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x),
839
840 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
841 EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x),
842 EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x),
843 EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x),
844 EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358),
845 EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358),
846 EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2),
847 EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4),
848 EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8),
849
850 EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2),
851 EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4),
852 EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4),
853 EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8),
854
855 EXAR_DEVICE(SEALEVEL, 710xC, pbn_exar_XR17V35x),
856 EXAR_DEVICE(SEALEVEL, 720xC, pbn_exar_XR17V35x),
857 EXAR_DEVICE(SEALEVEL, 740xC, pbn_exar_XR17V35x),
858 EXAR_DEVICE(SEALEVEL, 780xC, pbn_exar_XR17V35x),
859 EXAR_DEVICE(SEALEVEL, 716xC, pbn_exar_XR17V35x),
860 { 0, }
861 };
862 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
863
864 static struct pci_driver exar_pci_driver = {
865 .name = "exar_serial",
866 .probe = exar_pci_probe,
867 .remove = exar_pci_remove,
868 .driver = {
869 .pm = &exar_pci_pm,
870 },
871 .id_table = exar_pci_tbl,
872 };
873 module_pci_driver(exar_pci_driver);
874
875 MODULE_LICENSE("GPL");
876 MODULE_DESCRIPTION("Exar Serial Driver");
877 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
878